src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30 #include "lcra.h"
  31
  32 #include "util/hash_table.h"
  33 #include "util/u_dynarray.h"
  34 #include "util/set.h"
  35 #include "util/list.h"
  36
  37 #include "main/mtypes.h"
  38 #include "compiler/nir_types.h"
  39 #include "compiler/nir/nir.h"
  40
  41 /* Forward declare */
  42 struct midgard_block;
  43
  44 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  45  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  46  * instruction is actually a discard op. */
  47
  48 #define TARGET_GOTO 0
  49 #define TARGET_BREAK 1
  50 #define TARGET_CONTINUE 2
  51 #define TARGET_DISCARD 3
  52
  53 typedef struct midgard_branch {
  54         /* If conditional, the condition is specified in r31.w */
  55         bool conditional;
  56
  57         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  58         bool invert_conditional;
  59
  60         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  61         unsigned target_type;
  62
  63         /* The actual target */
  64         union {
  65                 int target_block;
  66                 int target_break;
  67                 int target_continue;
  68         };
  69 } midgard_branch;
  70
  71 /* Generic in-memory data type repesenting a single logical instruction, rather
  72  * than a single instruction group. This is the preferred form for code gen.
  73  * Multiple midgard_insturctions will later be combined during scheduling,
  74  * though this is not represented in this structure.  Its format bridges
  75  * the low-level binary representation with the higher level semantic meaning.
  76  *
  77  * Notably, it allows registers to be specified as block local SSA, for code
  78  * emitted before the register allocation pass.
  79  */
  80
  81 #define MIR_SRC_COUNT 3
  82 #define MIR_VEC_COMPONENTS 16
  83
  84 typedef struct midgard_instruction {
  85         /* Must be first for casting */
  86         struct list_head link;
  87
  88         unsigned type; /* ALU, load/store, texture */
  89
  90         /* Instruction arguments represented as block-local SSA
  91          * indices, rather than registers. ~0 means unused. */
  92         unsigned src[3];
  93         unsigned dest;
  94
  95         /* vec16 swizzle, unpacked, per source */
  96         unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
  97
  98         /* Special fields for an ALU instruction */
  99         midgard_reg_info registers;
 100
 101         /* I.e. (1 << alu_bit) */
 102         int unit;
 103
 104         bool has_constants;
 105         uint32_t constants[4];
 106         uint16_t inline_constant;
 107         bool has_blend_constant;
 108         bool has_inline_constant;
 109
 110         bool compact_branch;
 111         bool writeout;
 112         bool prepacked_branch;
 113
 114         /* Kind of a hack, but hint against aggressive DCE */
 115         bool dont_eliminate;
 116
 117         /* Masks in a saneish format. One bit per channel, not packed fancy.
 118          * Use this instead of the op specific ones, and switch over at emit
 119          * time */
 120
 121         uint16_t mask;
 122
 123         /* For ALU ops only: set to true to invert (bitwise NOT) the
 124          * destination of an integer-out op. Not imeplemented in hardware but
 125          * allows more optimizations */
 126
 127         bool invert;
 128
 129         /* Hint for the register allocator not to spill the destination written
 130          * from this instruction (because it is a spill/unspill node itself).
 131          * Bitmask of spilled classes */
 132
 133         unsigned no_spill;
 134
 135         /* Generic hint for intra-pass use */
 136         bool hint;
 137
 138         /* During scheduling, the backwards dependency graph
 139          * (DAG). nr_dependencies is the number of unscheduled
 140          * instructions that must still be scheduled after
 141          * (before) this instruction. dependents are which
 142          * instructions need to be scheduled before (after) this
 143          * instruction. */
 144
 145         unsigned nr_dependencies;
 146         BITSET_WORD *dependents;
 147
 148         /* For load/store ops.. force 64-bit destination */
 149         bool load_64;
 150
 151         union {
 152                 midgard_load_store_word load_store;
 153                 midgard_vector_alu alu;
 154                 midgard_texture_word texture;
 155                 midgard_branch_extended branch_extended;
 156                 uint16_t br_compact;
 157
 158                 /* General branch, rather than packed br_compact. Higher level
 159                  * than the other components */
 160                 midgard_branch branch;
 161         };
 162 } midgard_instruction;
 163
 164 typedef struct midgard_block {
 165         /* Link to next block. Must be first for mir_get_block */
 166         struct list_head link;
 167
 168         /* List of midgard_instructions emitted for the current block */
 169         struct list_head instructions;
 170
 171         /* Index of the block in source order */
 172         unsigned source_id;
 173
 174         bool is_scheduled;
 175
 176         /* List of midgard_bundles emitted (after the scheduler has run) */
 177         struct util_dynarray bundles;
 178
 179         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 180         unsigned quadword_count;
 181
 182         /* Succeeding blocks. The compiler should not necessarily rely on
 183          * source-order traversal */
 184         struct midgard_block *successors[2];
 185         unsigned nr_successors;
 186
 187         struct set *predecessors;
 188
 189         /* The successors pointer form a graph, and in the case of
 190          * complex control flow, this graph has a cycles. To aid
 191          * traversal during liveness analysis, we have a visited?
 192          * boolean for passes to use as they see fit, provided they
 193          * clean up later */
 194         bool visited;
 195
 196         /* In liveness analysis, these are live masks (per-component) for
 197          * indices for the block. Scalar compilers have the luxury of using
 198          * simple bit fields, but for us, liveness is a vector idea. */
 199         uint16_t *live_in;
 200         uint16_t *live_out;
 201 } midgard_block;
 202
 203 typedef struct midgard_bundle {
 204         /* Tag for the overall bundle */
 205         int tag;
 206
 207         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 208          * sadd, vadd, smul, vlut, branch) */
 209         int instruction_count;
 210         midgard_instruction *instructions[6];
 211
 212         /* Bundle-wide ALU configuration */
 213         int padding;
 214         int control;
 215         bool has_embedded_constants;
 216         float constants[4];
 217         bool has_blend_constant;
 218 } midgard_bundle;
 219
 220 typedef struct compiler_context {
 221         nir_shader *nir;
 222         gl_shader_stage stage;
 223
 224         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 225         bool is_blend;
 226
 227         /* Render target number for a keyed blend shader. Depends on is_blend */
 228         unsigned blend_rt;
 229
 230         /* Tracking for blend constant patching */
 231         int blend_constant_offset;
 232
 233         /* Number of bytes used for Thread Local Storage */
 234         unsigned tls_size;
 235
 236         /* Count of spills and fills for shaderdb */
 237         unsigned spills;
 238         unsigned fills;
 239
 240         /* Current NIR function */
 241         nir_function *func;
 242
 243         /* Allocated compiler temporary counter */
 244         unsigned temp_alloc;
 245
 246         /* Unordered list of midgard_blocks */
 247         int block_count;
 248         struct list_head blocks;
 249
 250         /* TODO merge with block_count? */
 251         unsigned block_source_count;
 252
 253         /* List of midgard_instructions emitted for the current block */
 254         midgard_block *current_block;
 255
 256         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 257         midgard_block *after_block;
 258
 259         /* The current "depth" of the loop, for disambiguating breaks/continues
 260          * when using nested loops */
 261         int current_loop_depth;
 262
 263         /* Total number of loops for shader-db */
 264         unsigned loop_count;
 265
 266         /* Constants which have been loaded, for later inlining */
 267         struct hash_table_u64 *ssa_constants;
 268
 269         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 270         struct hash_table_u64 *hash_to_temp;
 271         int temp_count;
 272         int max_hash;
 273
 274         /* Just the count of the max register used. Higher count => higher
 275          * register pressure */
 276         int work_registers;
 277
 278         /* Used for cont/last hinting. Increase when a tex op is added.
 279          * Decrease when a tex op is removed. */
 280         int texture_op_count;
 281
 282         /* The number of uniforms allowable for the fast path */
 283         int uniform_cutoff;
 284
 285         /* Count of instructions emitted from NIR overall, across all blocks */
 286         int instruction_count;
 287
 288         /* Alpha ref value passed in */
 289         float alpha_ref;
 290
 291         unsigned quadword_count;
 292
 293         /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
 294         unsigned sysvals[MAX_SYSVAL_COUNT];
 295         unsigned sysval_count;
 296         struct hash_table_u64 *sysval_to_id;
 297
 298         /* Bitmask of valid metadata */
 299         unsigned metadata;
 300
 301         /* Model-specific quirk set */
 302         uint32_t quirks;
 303 } compiler_context;
 304
 305 /* Per-block live_in/live_out */
 306 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 307
 308 /* Helpers for manipulating the above structures (forming the driver IR) */
 309
 310 /* Append instruction to end of current block */
 311
 312 static inline midgard_instruction *
 313 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 314 {
 315         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 316         memcpy(heap, &ins, sizeof(ins));
 317         return heap;
 318 }
 319
 320 static inline midgard_instruction *
 321 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 322 {
 323         midgard_instruction *u = mir_upload_ins(ctx, ins);
 324         list_addtail(&u->link, &ctx->current_block->instructions);
 325         return u;
 326 }
 327
 328 static inline struct midgard_instruction *
 329 mir_insert_instruction_before(struct compiler_context *ctx,
 330                               struct midgard_instruction *tag,
 331                               struct midgard_instruction ins)
 332 {
 333         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 334         list_addtail(&u->link, &tag->link);
 335         return u;
 336 }
 337
 338 static inline void
 339 mir_remove_instruction(struct midgard_instruction *ins)
 340 {
 341         list_del(&ins->link);
 342 }
 343
 344 static inline midgard_instruction*
 345 mir_prev_op(struct midgard_instruction *ins)
 346 {
 347         return list_last_entry(&(ins->link), midgard_instruction, link);
 348 }
 349
 350 static inline midgard_instruction*
 351 mir_next_op(struct midgard_instruction *ins)
 352 {
 353         return list_first_entry(&(ins->link), midgard_instruction, link);
 354 }
 355
 356 #define mir_foreach_block(ctx, v) \
 357         list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
 358
 359 #define mir_foreach_block_from(ctx, from, v) \
 360         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 361
 362 #define mir_foreach_instr(ctx, v) \
 363         list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 364
 365 #define mir_foreach_instr_safe(ctx, v) \
 366         list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 367
 368 #define mir_foreach_instr_in_block(block, v) \
 369         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 370 #define mir_foreach_instr_in_block_rev(block, v) \
 371         list_for_each_entry_rev(struct midgard_instruction, v, &block->instructions, link)
 372
 373 #define mir_foreach_instr_in_block_safe(block, v) \
 374         list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
 375
 376 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 377         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
 378
 379 #define mir_foreach_instr_in_block_from(block, v, from) \
 380         list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
 381
 382 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 383         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
 384
 385 #define mir_foreach_bundle_in_block(block, v) \
 386         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 387
 388 #define mir_foreach_bundle_in_block_rev(block, v) \
 389         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 390
 391 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 392         midgard_instruction* v; \
 393         signed i = 0; \
 394         mir_foreach_bundle_in_block_rev(block, _bundle) \
 395                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 396                                 i >= 0; \
 397                                 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
 398
 399 #define mir_foreach_instr_global(ctx, v) \
 400         mir_foreach_block(ctx, v_block) \
 401                 mir_foreach_instr_in_block(v_block, v)
 402
 403 #define mir_foreach_instr_global_safe(ctx, v) \
 404         mir_foreach_block(ctx, v_block) \
 405                 mir_foreach_instr_in_block_safe(v_block, v)
 406
 407 #define mir_foreach_successor(blk, v) \
 408         struct midgard_block *v; \
 409         struct midgard_block **_v; \
 410         for (_v = &blk->successors[0], \
 411                 v = *_v; \
 412                 v != NULL && _v < &blk->successors[2]; \
 413                 _v++, v = *_v) \
 414
 415 /* Based on set_foreach, expanded with automatic type casts */
 416
 417 #define mir_foreach_predecessor(blk, v) \
 418         struct set_entry *_entry_##v; \
 419         struct midgard_block *v; \
 420         for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
 421                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 422                 _entry_##v != NULL; \
 423                 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
 424                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 425
 426 #define mir_foreach_src(ins, v) \
 427         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 428
 429 static inline midgard_instruction *
 430 mir_last_in_block(struct midgard_block *block)
 431 {
 432         return list_last_entry(&block->instructions, struct midgard_instruction, link);
 433 }
 434
 435 static inline midgard_block *
 436 mir_get_block(compiler_context *ctx, int idx)
 437 {
 438         struct list_head *lst = &ctx->blocks;
 439
 440         while ((idx--) + 1)
 441                 lst = lst->next;
 442
 443         return (struct midgard_block *) lst;
 444 }
 445
 446 static inline midgard_block *
 447 mir_exit_block(struct compiler_context *ctx)
 448 {
 449         midgard_block *last = list_last_entry(&ctx->blocks,
 450                         struct midgard_block, link);
 451
 452         /* The last block must be empty logically but contains branch writeout
 453          * for fragment shaders */
 454
 455         assert(last->nr_successors == 0);
 456
 457         return last;
 458 }
 459
 460 static inline bool
 461 mir_is_alu_bundle(midgard_bundle *bundle)
 462 {
 463         return IS_ALU(bundle->tag);
 464 }
 465
 466 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
 467
 468 #define IS_REG (1)
 469
 470 static inline unsigned
 471 make_compiler_temp(compiler_context *ctx)
 472 {
 473         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 474 }
 475
 476 static inline unsigned
 477 make_compiler_temp_reg(compiler_context *ctx)
 478 {
 479         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
 480 }
 481
 482 static inline unsigned
 483 nir_src_index(compiler_context *ctx, nir_src *src)
 484 {
 485         if (src->is_ssa)
 486                 return (src->ssa->index << 1) | 0;
 487         else {
 488                 assert(!src->reg.indirect);
 489                 return (src->reg.reg->index << 1) | IS_REG;
 490         }
 491 }
 492
 493 static inline unsigned
 494 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
 495 {
 496         return nir_src_index(ctx, &src->src);
 497 }
 498
 499 static inline unsigned
 500 nir_dest_index(compiler_context *ctx, nir_dest *dst)
 501 {
 502         if (dst->is_ssa)
 503                 return (dst->ssa.index << 1) | 0;
 504         else {
 505                 assert(!dst->reg.indirect);
 506                 return (dst->reg.reg->index << 1) | IS_REG;
 507         }
 508 }
 509
 510
 511
 512 /* MIR manipulation */
 513
 514 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 515 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 516 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 517 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 518 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 519 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 520 bool mir_single_use(compiler_context *ctx, unsigned value);
 521 bool mir_special_index(compiler_context *ctx, unsigned idx);
 522 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 523 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 524 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 525 midgard_reg_mode mir_typesize(midgard_instruction *ins);
 526 midgard_reg_mode mir_srcsize(midgard_instruction *ins, unsigned i);
 527 unsigned mir_bytes_for_mode(midgard_reg_mode mode);
 528 midgard_reg_mode mir_mode_for_destsize(unsigned size);
 529 uint16_t mir_from_bytemask(uint16_t bytemask, midgard_reg_mode mode);
 530 uint16_t mir_to_bytemask(midgard_reg_mode mode, unsigned mask);
 531 uint16_t mir_bytemask(midgard_instruction *ins);
 532 uint16_t mir_round_bytemask_down(uint16_t mask, midgard_reg_mode mode);
 533 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 534
 535 /* MIR printing */
 536
 537 void mir_print_instruction(midgard_instruction *ins);
 538 void mir_print_bundle(midgard_bundle *ctx);
 539 void mir_print_block(midgard_block *block);
 540 void mir_print_shader(compiler_context *ctx);
 541 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 542 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 543 bool mir_nontrivial_outmod(midgard_instruction *ins);
 544
 545 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 546 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 547 void mir_flip(midgard_instruction *ins);
 548 void mir_compute_temp_count(compiler_context *ctx);
 549
 550 /* 'Intrinsic' move for aliasing */
 551
 552 static inline midgard_instruction
 553 v_mov(unsigned src, unsigned dest)
 554 {
 555         midgard_instruction ins = {
 556                 .type = TAG_ALU_4,
 557                 .mask = 0xF,
 558                 .src = { SSA_UNUSED, src, SSA_UNUSED },
 559                 .swizzle = SWIZZLE_IDENTITY,
 560                 .dest = dest,
 561                 .alu = {
 562                         .op = midgard_alu_op_imov,
 563                         .reg_mode = midgard_reg_mode_32,
 564                         .dest_override = midgard_dest_override_none,
 565                         .outmod = midgard_outmod_int_wrap
 566                 },
 567         };
 568
 569         return ins;
 570 }
 571
 572 /* Broad types of register classes so we can handle special
 573  * registers */
 574
 575 #define REG_CLASS_WORK          0
 576 #define REG_CLASS_LDST          1
 577 #define REG_CLASS_TEXR          3
 578 #define REG_CLASS_TEXW          4
 579
 580 /* Like a move, but to thread local storage! */
 581
 582 static inline midgard_instruction
 583 v_load_store_scratch(
 584                 unsigned srcdest,
 585                 unsigned index,
 586                 bool is_store,
 587                 unsigned mask)
 588 {
 589         /* We index by 32-bit vec4s */
 590         unsigned byte = (index * 4 * 4);
 591
 592         midgard_instruction ins = {
 593                 .type = TAG_LOAD_STORE_4,
 594                 .mask = mask,
 595                 .dest = ~0,
 596                 .src = { ~0, ~0, ~0 },
 597                 .swizzle = SWIZZLE_IDENTITY_4,
 598                 .load_store = {
 599                         .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
 600
 601                         /* For register spilling - to thread local storage */
 602                         .arg_1 = 0xEA,
 603                         .arg_2 = 0x1E,
 604                 },
 605
 606                 /* If we spill an unspill, RA goes into an infinite loop */
 607                 .no_spill = (1 << REG_CLASS_WORK)
 608         };
 609
 610         ins.constants[0] = byte;
 611
 612         if (is_store) {
 613                 ins.src[0] = srcdest;
 614
 615                 /* Ensure we are tightly swizzled so liveness analysis is
 616                  * correct */
 617
 618                 for (unsigned i = 0; i < 4; ++i) {
 619                         if (!(mask & (1 << i)))
 620                                 ins.swizzle[0][i] = COMPONENT_X;
 621                 }
 622         } else
 623                 ins.dest = srcdest;
 624
 625         return ins;
 626 }
 627
 628 static inline bool
 629 mir_has_arg(midgard_instruction *ins, unsigned arg)
 630 {
 631         if (!ins)
 632                 return false;
 633
 634         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
 635                 if (ins->src[i] == arg)
 636                         return true;
 637         }
 638
 639         return false;
 640 }
 641
 642 /* Scheduling */
 643
 644 void schedule_program(compiler_context *ctx);
 645
 646 void mir_ra(compiler_context *ctx);
 647 void mir_squeeze_index(compiler_context *ctx);
 648 void mir_lower_special_reads(compiler_context *ctx);
 649 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 650 void mir_compute_liveness(compiler_context *ctx);
 651 void mir_invalidate_liveness(compiler_context *ctx);
 652 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 653
 654 void mir_create_pipeline_registers(compiler_context *ctx);
 655
 656 void
 657 midgard_promote_uniforms(compiler_context *ctx, unsigned promoted_count);
 658
 659 midgard_instruction *
 660 emit_ubo_read(
 661         compiler_context *ctx,
 662         nir_instr *instr,
 663         unsigned dest,
 664         unsigned offset,
 665         nir_src *indirect_offset,
 666         unsigned index);
 667
 668 void
 669 emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override, unsigned nr_components);
 670
 671 void
 672 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 673
 674 void
 675 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 676
 677 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
 678
 679 /* Final emission */
 680
 681 void emit_binary_bundle(
 682         compiler_context *ctx,
 683         midgard_bundle *bundle,
 684         struct util_dynarray *emission,
 685         int next_tag);
 686
 687 bool
 688 nir_undef_to_zero(nir_shader *shader);
 689
 690 void midgard_nir_lod_errata(nir_shader *shader);
 691
 692 /* Optimizations */
 693
 694 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 695 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 696 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 697 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 698 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 699
 700 void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
 701 bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
 702 bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
 703 bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
 704 bool midgard_opt_csel_invert(compiler_context *ctx, midgard_block *block);
 705 bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
 706
 707 #endif