src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30
  31 #include "util/hash_table.h"
  32 #include "util/u_dynarray.h"
  33 #include "util/set.h"
  34 #include "util/list.h"
  35
  36 #include "main/mtypes.h"
  37 #include "compiler/nir_types.h"
  38 #include "compiler/nir/nir.h"
  39
  40 /* Forward declare */
  41 struct midgard_block;
  42
  43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  44  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  45  * instruction is actually a discard op. */
  46
  47 #define TARGET_GOTO 0
  48 #define TARGET_BREAK 1
  49 #define TARGET_CONTINUE 2
  50 #define TARGET_DISCARD 3
  51
  52 typedef struct midgard_branch {
  53         /* If conditional, the condition is specified in r31.w */
  54         bool conditional;
  55
  56         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  57         bool invert_conditional;
  58
  59         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  60         unsigned target_type;
  61
  62         /* The actual target */
  63         union {
  64                 int target_block;
  65                 int target_break;
  66                 int target_continue;
  67         };
  68 } midgard_branch;
  69
  70 /* Generic in-memory data type repesenting a single logical instruction, rather
  71  * than a single instruction group. This is the preferred form for code gen.
  72  * Multiple midgard_insturctions will later be combined during scheduling,
  73  * though this is not represented in this structure.  Its format bridges
  74  * the low-level binary representation with the higher level semantic meaning.
  75  *
  76  * Notably, it allows registers to be specified as block local SSA, for code
  77  * emitted before the register allocation pass.
  78  */
  79
  80 typedef struct midgard_instruction {
  81         /* Must be first for casting */
  82         struct list_head link;
  83
  84         unsigned type; /* ALU, load/store, texture */
  85
  86         /* Instruction arguments represented as block-local SSA
  87          * indices, rather than registers. ~0 means unused. */
  88         unsigned src[3];
  89         unsigned dest;
  90
  91         /* Special fields for an ALU instruction */
  92         midgard_reg_info registers;
  93
  94         /* I.e. (1 << alu_bit) */
  95         int unit;
  96
  97         /* When emitting bundle, should this instruction have a break forced
  98          * before it? Used for r31 writes which are valid only within a single
  99          * bundle and *need* to happen as early as possible... this is a hack,
 100          * TODO remove when we have a scheduler */
 101         bool precede_break;
 102
 103         bool has_constants;
 104         uint32_t constants[4];
 105         uint16_t inline_constant;
 106         bool has_blend_constant;
 107         bool has_inline_constant;
 108
 109         bool compact_branch;
 110         bool writeout;
 111         bool prepacked_branch;
 112
 113         /* Kind of a hack, but hint against aggressive DCE */
 114         bool dont_eliminate;
 115
 116         /* Masks in a saneish format. One bit per channel, not packed fancy.
 117          * Use this instead of the op specific ones, and switch over at emit
 118          * time */
 119
 120         uint16_t mask;
 121
 122         /* For ALU ops only: set to true to invert (bitwise NOT) the
 123          * destination of an integer-out op. Not imeplemented in hardware but
 124          * allows more optimizations */
 125
 126         bool invert;
 127
 128         /* Hint for the register allocator not to spill the destination written
 129          * from this instruction (because it is a spill/unspill node itself) */
 130
 131         bool no_spill;
 132
 133         /* Generic hint for intra-pass use */
 134         bool hint;
 135
 136         union {
 137                 midgard_load_store_word load_store;
 138                 midgard_vector_alu alu;
 139                 midgard_texture_word texture;
 140                 midgard_branch_extended branch_extended;
 141                 uint16_t br_compact;
 142
 143                 /* General branch, rather than packed br_compact. Higher level
 144                  * than the other components */
 145                 midgard_branch branch;
 146         };
 147 } midgard_instruction;
 148
 149 typedef struct midgard_block {
 150         /* Link to next block. Must be first for mir_get_block */
 151         struct list_head link;
 152
 153         /* List of midgard_instructions emitted for the current block */
 154         struct list_head instructions;
 155
 156         /* Index of the block in source order */
 157         unsigned source_id;
 158
 159         bool is_scheduled;
 160
 161         /* List of midgard_bundles emitted (after the scheduler has run) */
 162         struct util_dynarray bundles;
 163
 164         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 165         unsigned quadword_count;
 166
 167         /* Succeeding blocks. The compiler should not necessarily rely on
 168          * source-order traversal */
 169         struct midgard_block *successors[2];
 170         unsigned nr_successors;
 171
 172         struct set *predecessors;
 173
 174         /* The successors pointer form a graph, and in the case of
 175          * complex control flow, this graph has a cycles. To aid
 176          * traversal during liveness analysis, we have a visited?
 177          * boolean for passes to use as they see fit, provided they
 178          * clean up later */
 179         bool visited;
 180
 181         /* In liveness analysis, these are live masks (per-component) for
 182          * indices for the block. Scalar compilers have the luxury of using
 183          * simple bit fields, but for us, liveness is a vector idea. We use
 184          * 8-bit to allow finegrained tracking up to vec8. If you're
 185          * implementing vec16 on Panfrost... I'm sorry. */
 186         uint8_t *live_in;
 187         uint8_t *live_out;
 188 } midgard_block;
 189
 190 typedef struct midgard_bundle {
 191         /* Tag for the overall bundle */
 192         int tag;
 193
 194         /* Instructions contained by the bundle */
 195         int instruction_count;
 196         midgard_instruction *instructions[5];
 197
 198         /* Bundle-wide ALU configuration */
 199         int padding;
 200         int control;
 201         bool has_embedded_constants;
 202         float constants[4];
 203         bool has_blend_constant;
 204 } midgard_bundle;
 205
 206 typedef struct compiler_context {
 207         nir_shader *nir;
 208         gl_shader_stage stage;
 209
 210         /* The screen we correspond to */
 211         struct midgard_screen *screen;
 212
 213         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 214         bool is_blend;
 215
 216         /* Tracking for blend constant patching */
 217         int blend_constant_offset;
 218
 219         /* Number of bytes used for Thread Local Storage */
 220         unsigned tls_size;
 221
 222         /* Count of spills and fills for shaderdb */
 223         unsigned spills;
 224         unsigned fills;
 225
 226         /* Current NIR function */
 227         nir_function *func;
 228
 229         /* Allocated compiler temporary counter */
 230         unsigned temp_alloc;
 231
 232         /* Unordered list of midgard_blocks */
 233         int block_count;
 234         struct list_head blocks;
 235
 236         /* TODO merge with block_count? */
 237         unsigned block_source_count;
 238
 239         /* List of midgard_instructions emitted for the current block */
 240         midgard_block *current_block;
 241
 242         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 243         midgard_block *after_block;
 244
 245         /* The current "depth" of the loop, for disambiguating breaks/continues
 246          * when using nested loops */
 247         int current_loop_depth;
 248
 249         /* Total number of loops for shader-db */
 250         unsigned loop_count;
 251
 252         /* Constants which have been loaded, for later inlining */
 253         struct hash_table_u64 *ssa_constants;
 254
 255         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 256         struct hash_table_u64 *hash_to_temp;
 257         int temp_count;
 258         int max_hash;
 259
 260         /* Just the count of the max register used. Higher count => higher
 261          * register pressure */
 262         int work_registers;
 263
 264         /* Used for cont/last hinting. Increase when a tex op is added.
 265          * Decrease when a tex op is removed. */
 266         int texture_op_count;
 267
 268         /* Mapping of texture register -> SSA index for unaliasing */
 269         int texture_index[2];
 270
 271         /* The number of uniforms allowable for the fast path */
 272         int uniform_cutoff;
 273
 274         /* Count of instructions emitted from NIR overall, across all blocks */
 275         int instruction_count;
 276
 277         /* Alpha ref value passed in */
 278         float alpha_ref;
 279
 280         /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
 281         unsigned sysvals[MAX_SYSVAL_COUNT];
 282         unsigned sysval_count;
 283         struct hash_table_u64 *sysval_to_id;
 284 } compiler_context;
 285
 286 /* Helpers for manipulating the above structures (forming the driver IR) */
 287
 288 /* Append instruction to end of current block */
 289
 290 static inline midgard_instruction *
 291 mir_upload_ins(struct midgard_instruction ins)
 292 {
 293         midgard_instruction *heap = malloc(sizeof(ins));
 294         memcpy(heap, &ins, sizeof(ins));
 295         return heap;
 296 }
 297
 298 static inline midgard_instruction *
 299 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 300 {
 301         midgard_instruction *u = mir_upload_ins(ins);
 302         list_addtail(&u->link, &ctx->current_block->instructions);
 303         return u;
 304 }
 305
 306 static inline struct midgard_instruction *
 307 mir_insert_instruction_before(struct midgard_instruction *tag, struct midgard_instruction ins)
 308 {
 309         struct midgard_instruction *u = mir_upload_ins(ins);
 310         list_addtail(&u->link, &tag->link);
 311         return u;
 312 }
 313
 314 static inline void
 315 mir_remove_instruction(struct midgard_instruction *ins)
 316 {
 317         list_del(&ins->link);
 318         free(ins);
 319 }
 320
 321 static inline midgard_instruction*
 322 mir_prev_op(struct midgard_instruction *ins)
 323 {
 324         return list_last_entry(&(ins->link), midgard_instruction, link);
 325 }
 326
 327 static inline midgard_instruction*
 328 mir_next_op(struct midgard_instruction *ins)
 329 {
 330         return list_first_entry(&(ins->link), midgard_instruction, link);
 331 }
 332
 333 #define mir_foreach_block(ctx, v) \
 334         list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
 335
 336 #define mir_foreach_block_from(ctx, from, v) \
 337         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 338
 339 #define mir_foreach_instr(ctx, v) \
 340         list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 341
 342 #define mir_foreach_instr_safe(ctx, v) \
 343         list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 344
 345 #define mir_foreach_instr_in_block(block, v) \
 346         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 347 #define mir_foreach_instr_in_block_rev(block, v) \
 348         list_for_each_entry_rev(struct midgard_instruction, v, &block->instructions, link)
 349
 350 #define mir_foreach_instr_in_block_safe(block, v) \
 351         list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
 352
 353 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 354         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
 355
 356 #define mir_foreach_instr_in_block_from(block, v, from) \
 357         list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
 358
 359 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 360         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
 361
 362 #define mir_foreach_bundle_in_block(block, v) \
 363         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 364
 365 #define mir_foreach_instr_global(ctx, v) \
 366         mir_foreach_block(ctx, v_block) \
 367                 mir_foreach_instr_in_block(v_block, v)
 368
 369 #define mir_foreach_instr_global_safe(ctx, v) \
 370         mir_foreach_block(ctx, v_block) \
 371                 mir_foreach_instr_in_block_safe(v_block, v)
 372
 373 #define mir_foreach_successor(blk, v) \
 374         struct midgard_block *v; \
 375         struct midgard_block **_v; \
 376         for (_v = &blk->successors[0], \
 377                 v = *_v; \
 378                 v != NULL && _v < &blk->successors[2]; \
 379                 _v++, v = *_v) \
 380
 381 /* Based on set_foreach, expanded with automatic type casts */
 382
 383 #define mir_foreach_predecessor(blk, v) \
 384         struct set_entry *_entry_##v; \
 385         struct midgard_block *v; \
 386         for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
 387                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 388                 _entry_##v != NULL; \
 389                 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
 390                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 391
 392 #define mir_foreach_src(ins, v) \
 393         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 394
 395 static inline midgard_instruction *
 396 mir_last_in_block(struct midgard_block *block)
 397 {
 398         return list_last_entry(&block->instructions, struct midgard_instruction, link);
 399 }
 400
 401 static inline midgard_block *
 402 mir_get_block(compiler_context *ctx, int idx)
 403 {
 404         struct list_head *lst = &ctx->blocks;
 405
 406         while ((idx--) + 1)
 407                 lst = lst->next;
 408
 409         return (struct midgard_block *) lst;
 410 }
 411
 412 static inline midgard_block *
 413 mir_exit_block(struct compiler_context *ctx)
 414 {
 415         midgard_block *last = list_last_entry(&ctx->blocks,
 416                         struct midgard_block, link);
 417
 418         /* The last block must be empty (the exit block) */
 419         assert(list_empty(&last->instructions));
 420         assert(last->nr_successors == 0);
 421
 422         return last;
 423 }
 424
 425 static inline bool
 426 mir_is_alu_bundle(midgard_bundle *bundle)
 427 {
 428         return IS_ALU(bundle->tag);
 429 }
 430
 431 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
 432
 433 #define IS_REG (1)
 434
 435 static inline unsigned
 436 make_compiler_temp(compiler_context *ctx)
 437 {
 438         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 439 }
 440
 441 static inline unsigned
 442 make_compiler_temp_reg(compiler_context *ctx)
 443 {
 444         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
 445 }
 446
 447 static inline unsigned
 448 nir_src_index(compiler_context *ctx, nir_src *src)
 449 {
 450         if (src->is_ssa)
 451                 return (src->ssa->index << 1) | 0;
 452         else {
 453                 assert(!src->reg.indirect);
 454                 return (src->reg.reg->index << 1) | IS_REG;
 455         }
 456 }
 457
 458 static inline unsigned
 459 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
 460 {
 461         return nir_src_index(ctx, &src->src);
 462 }
 463
 464 static inline unsigned
 465 nir_dest_index(compiler_context *ctx, nir_dest *dst)
 466 {
 467         if (dst->is_ssa)
 468                 return (dst->ssa.index << 1) | 0;
 469         else {
 470                 assert(!dst->reg.indirect);
 471                 return (dst->reg.reg->index << 1) | IS_REG;
 472         }
 473 }
 474
 475
 476
 477 /* MIR manipulation */
 478
 479 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 480 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 481 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 482 void mir_rewrite_index_dst_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 483 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 484 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 485 void mir_rewrite_index_src_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 486 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned swizzle);
 487 bool mir_single_use(compiler_context *ctx, unsigned value);
 488 bool mir_special_index(compiler_context *ctx, unsigned idx);
 489 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 490 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 491 unsigned mir_mask_of_read_components(midgard_instruction *ins, unsigned node);
 492 unsigned mir_ubo_shift(midgard_load_store_op op);
 493
 494 /* MIR printing */
 495
 496 void mir_print_instruction(midgard_instruction *ins);
 497 void mir_print_bundle(midgard_bundle *ctx);
 498 void mir_print_block(midgard_block *block);
 499 void mir_print_shader(compiler_context *ctx);
 500 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 501 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 502 bool mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask);
 503 bool mir_nontrivial_outmod(midgard_instruction *ins);
 504
 505 /* MIR goodies */
 506
 507 static const midgard_vector_alu_src blank_alu_src = {
 508         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
 509 };
 510
 511 static const midgard_vector_alu_src blank_alu_src_xxxx = {
 512         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X),
 513 };
 514
 515 static const midgard_scalar_alu_src blank_scalar_alu_src = {
 516         .full = true
 517 };
 518
 519 /* Used for encoding the unused source of 1-op instructions */
 520 static const midgard_vector_alu_src zero_alu_src = { 0 };
 521
 522 /* 'Intrinsic' move for aliasing */
 523
 524 static inline midgard_instruction
 525 v_mov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
 526 {
 527         midgard_instruction ins = {
 528                 .type = TAG_ALU_4,
 529                 .mask = 0xF,
 530                 .src = { SSA_UNUSED, src, SSA_UNUSED },
 531                 .dest = dest,
 532                 .alu = {
 533                         .op = midgard_alu_op_imov,
 534                         .reg_mode = midgard_reg_mode_32,
 535                         .dest_override = midgard_dest_override_none,
 536                         .outmod = midgard_outmod_int_wrap,
 537                         .src1 = vector_alu_srco_unsigned(zero_alu_src),
 538                         .src2 = vector_alu_srco_unsigned(mod)
 539                 },
 540         };
 541
 542         return ins;
 543 }
 544
 545 static inline bool
 546 mir_has_arg(midgard_instruction *ins, unsigned arg)
 547 {
 548         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
 549                 if (ins->src[i] == arg)
 550                         return true;
 551         }
 552
 553         return false;
 554 }
 555
 556 /* Scheduling */
 557
 558 void schedule_program(compiler_context *ctx);
 559
 560 /* Register allocation */
 561
 562 struct ra_graph;
 563
 564 /* Broad types of register classes so we can handle special
 565  * registers */
 566
 567 #define NR_REG_CLASSES 5
 568
 569 #define REG_CLASS_WORK          0
 570 #define REG_CLASS_LDST          1
 571 #define REG_CLASS_LDST27        2
 572 #define REG_CLASS_TEXR          3
 573 #define REG_CLASS_TEXW          4
 574
 575 void mir_lower_special_reads(compiler_context *ctx);
 576 struct ra_graph* allocate_registers(compiler_context *ctx, bool *spilled);
 577 void install_registers(compiler_context *ctx, struct ra_graph *g);
 578 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 579 bool mir_has_multiple_writes(compiler_context *ctx, int src);
 580
 581 void mir_create_pipeline_registers(compiler_context *ctx);
 582
 583 void
 584 midgard_promote_uniforms(compiler_context *ctx, unsigned promoted_count);
 585
 586 midgard_instruction *
 587 emit_ubo_read(
 588         compiler_context *ctx,
 589         nir_instr *instr,
 590         unsigned dest,
 591         unsigned offset,
 592         nir_src *indirect_offset,
 593         unsigned index);
 594
 595 void
 596 emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override, unsigned nr_components);
 597
 598 void
 599 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 600
 601 void
 602 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 603
 604 bool mir_op_computes_derivatives(unsigned op);
 605
 606 /* Final emission */
 607
 608 void emit_binary_bundle(
 609         compiler_context *ctx,
 610         midgard_bundle *bundle,
 611         struct util_dynarray *emission,
 612         int next_tag);
 613
 614 /* NIR stuff. TODO: Move? Share? Something? */
 615
 616 bool
 617 nir_undef_to_zero(nir_shader *shader);
 618
 619 void
 620 nir_clamp_psiz(nir_shader *shader, float min_size, float max_size);
 621
 622 /* Optimizations */
 623
 624 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 625 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 626 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 627 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 628 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 629 void midgard_opt_post_move_eliminate(compiler_context *ctx, midgard_block *block, struct ra_graph *g);
 630
 631 void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
 632 bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
 633 bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
 634 bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
 635 bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
 636
 637 #endif