src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30
  31 #include "util/hash_table.h"
  32 #include "util/u_dynarray.h"
  33 #include "util/set.h"
  34 #include "util/list.h"
  35
  36 #include "main/mtypes.h"
  37 #include "compiler/nir_types.h"
  38 #include "compiler/nir/nir.h"
  39
  40 /* Forward declare */
  41 struct midgard_block;
  42
  43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  44  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  45  * instruction is actually a discard op. */
  46
  47 #define TARGET_GOTO 0
  48 #define TARGET_BREAK 1
  49 #define TARGET_CONTINUE 2
  50 #define TARGET_DISCARD 3
  51
  52 typedef struct midgard_branch {
  53         /* If conditional, the condition is specified in r31.w */
  54         bool conditional;
  55
  56         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  57         bool invert_conditional;
  58
  59         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  60         unsigned target_type;
  61
  62         /* The actual target */
  63         union {
  64                 int target_block;
  65                 int target_break;
  66                 int target_continue;
  67         };
  68 } midgard_branch;
  69
  70 /* Generic in-memory data type repesenting a single logical instruction, rather
  71  * than a single instruction group. This is the preferred form for code gen.
  72  * Multiple midgard_insturctions will later be combined during scheduling,
  73  * though this is not represented in this structure.  Its format bridges
  74  * the low-level binary representation with the higher level semantic meaning.
  75  *
  76  * Notably, it allows registers to be specified as block local SSA, for code
  77  * emitted before the register allocation pass.
  78  */
  79
  80 typedef struct midgard_instruction {
  81         /* Must be first for casting */
  82         struct list_head link;
  83
  84         unsigned type; /* ALU, load/store, texture */
  85
  86         /* Instruction arguments represented as block-local SSA
  87          * indices, rather than registers. ~0 means unused. */
  88         unsigned src[3];
  89         unsigned dest;
  90
  91         /* Swizzle for the conditional for a csel */
  92         unsigned csel_swizzle;
  93
  94         /* Special fields for an ALU instruction */
  95         midgard_reg_info registers;
  96
  97         /* I.e. (1 << alu_bit) */
  98         int unit;
  99
 100         /* When emitting bundle, should this instruction have a break forced
 101          * before it? Used for r31 writes which are valid only within a single
 102          * bundle and *need* to happen as early as possible... this is a hack,
 103          * TODO remove when we have a scheduler */
 104         bool precede_break;
 105
 106         bool has_constants;
 107         uint32_t constants[4];
 108         uint16_t inline_constant;
 109         bool has_blend_constant;
 110         bool has_inline_constant;
 111
 112         bool compact_branch;
 113         bool writeout;
 114         bool prepacked_branch;
 115
 116         /* Kind of a hack, but hint against aggressive DCE */
 117         bool dont_eliminate;
 118
 119         /* Masks in a saneish format. One bit per channel, not packed fancy.
 120          * Use this instead of the op specific ones, and switch over at emit
 121          * time */
 122
 123         uint16_t mask;
 124
 125         /* For ALU ops only: set to true to invert (bitwise NOT) the
 126          * destination of an integer-out op. Not imeplemented in hardware but
 127          * allows more optimizations */
 128
 129         bool invert;
 130
 131         /* Hint for the register allocator not to spill the destination written
 132          * from this instruction (because it is a spill/unspill node itself) */
 133
 134         bool no_spill;
 135
 136         /* Generic hint for intra-pass use */
 137         bool hint;
 138
 139         union {
 140                 midgard_load_store_word load_store;
 141                 midgard_vector_alu alu;
 142                 midgard_texture_word texture;
 143                 midgard_branch_extended branch_extended;
 144                 uint16_t br_compact;
 145
 146                 /* General branch, rather than packed br_compact. Higher level
 147                  * than the other components */
 148                 midgard_branch branch;
 149         };
 150 } midgard_instruction;
 151
 152 typedef struct midgard_block {
 153         /* Link to next block. Must be first for mir_get_block */
 154         struct list_head link;
 155
 156         /* List of midgard_instructions emitted for the current block */
 157         struct list_head instructions;
 158
 159         /* Index of the block in source order */
 160         unsigned source_id;
 161
 162         bool is_scheduled;
 163
 164         /* List of midgard_bundles emitted (after the scheduler has run) */
 165         struct util_dynarray bundles;
 166
 167         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 168         unsigned quadword_count;
 169
 170         /* Succeeding blocks. The compiler should not necessarily rely on
 171          * source-order traversal */
 172         struct midgard_block *successors[2];
 173         unsigned nr_successors;
 174
 175         struct set *predecessors;
 176
 177         /* The successors pointer form a graph, and in the case of
 178          * complex control flow, this graph has a cycles. To aid
 179          * traversal during liveness analysis, we have a visited?
 180          * boolean for passes to use as they see fit, provided they
 181          * clean up later */
 182         bool visited;
 183
 184         /* In liveness analysis, these are live masks (per-component) for
 185          * indices for the block. Scalar compilers have the luxury of using
 186          * simple bit fields, but for us, liveness is a vector idea. We use
 187          * 8-bit to allow finegrained tracking up to vec8. If you're
 188          * implementing vec16 on Panfrost... I'm sorry. */
 189         uint8_t *live_in;
 190         uint8_t *live_out;
 191 } midgard_block;
 192
 193 typedef struct midgard_bundle {
 194         /* Tag for the overall bundle */
 195         int tag;
 196
 197         /* Instructions contained by the bundle */
 198         int instruction_count;
 199         midgard_instruction *instructions[5];
 200
 201         /* Bundle-wide ALU configuration */
 202         int padding;
 203         int control;
 204         bool has_embedded_constants;
 205         float constants[4];
 206         bool has_blend_constant;
 207 } midgard_bundle;
 208
 209 typedef struct compiler_context {
 210         nir_shader *nir;
 211         gl_shader_stage stage;
 212
 213         /* The screen we correspond to */
 214         struct midgard_screen *screen;
 215
 216         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 217         bool is_blend;
 218
 219         /* Tracking for blend constant patching */
 220         int blend_constant_offset;
 221
 222         /* Number of bytes used for Thread Local Storage */
 223         unsigned tls_size;
 224
 225         /* Count of spills and fills for shaderdb */
 226         unsigned spills;
 227         unsigned fills;
 228
 229         /* Current NIR function */
 230         nir_function *func;
 231
 232         /* Allocated compiler temporary counter */
 233         unsigned temp_alloc;
 234
 235         /* Unordered list of midgard_blocks */
 236         int block_count;
 237         struct list_head blocks;
 238
 239         /* TODO merge with block_count? */
 240         unsigned block_source_count;
 241
 242         /* List of midgard_instructions emitted for the current block */
 243         midgard_block *current_block;
 244
 245         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 246         midgard_block *after_block;
 247
 248         /* The current "depth" of the loop, for disambiguating breaks/continues
 249          * when using nested loops */
 250         int current_loop_depth;
 251
 252         /* Total number of loops for shader-db */
 253         unsigned loop_count;
 254
 255         /* Constants which have been loaded, for later inlining */
 256         struct hash_table_u64 *ssa_constants;
 257
 258         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 259         struct hash_table_u64 *hash_to_temp;
 260         int temp_count;
 261         int max_hash;
 262
 263         /* Just the count of the max register used. Higher count => higher
 264          * register pressure */
 265         int work_registers;
 266
 267         /* Used for cont/last hinting. Increase when a tex op is added.
 268          * Decrease when a tex op is removed. */
 269         int texture_op_count;
 270
 271         /* Mapping of texture register -> SSA index for unaliasing */
 272         int texture_index[2];
 273
 274         /* The number of uniforms allowable for the fast path */
 275         int uniform_cutoff;
 276
 277         /* Count of instructions emitted from NIR overall, across all blocks */
 278         int instruction_count;
 279
 280         /* Alpha ref value passed in */
 281         float alpha_ref;
 282
 283         /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
 284         unsigned sysvals[MAX_SYSVAL_COUNT];
 285         unsigned sysval_count;
 286         struct hash_table_u64 *sysval_to_id;
 287 } compiler_context;
 288
 289 /* Helpers for manipulating the above structures (forming the driver IR) */
 290
 291 /* Append instruction to end of current block */
 292
 293 static inline midgard_instruction *
 294 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 295 {
 296         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 297         memcpy(heap, &ins, sizeof(ins));
 298         return heap;
 299 }
 300
 301 static inline midgard_instruction *
 302 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 303 {
 304         midgard_instruction *u = mir_upload_ins(ctx, ins);
 305         list_addtail(&u->link, &ctx->current_block->instructions);
 306         return u;
 307 }
 308
 309 static inline struct midgard_instruction *
 310 mir_insert_instruction_before(struct compiler_context *ctx,
 311                               struct midgard_instruction *tag,
 312                               struct midgard_instruction ins)
 313 {
 314         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 315         list_addtail(&u->link, &tag->link);
 316         return u;
 317 }
 318
 319 static inline void
 320 mir_remove_instruction(struct midgard_instruction *ins)
 321 {
 322         list_del(&ins->link);
 323 }
 324
 325 static inline midgard_instruction*
 326 mir_prev_op(struct midgard_instruction *ins)
 327 {
 328         return list_last_entry(&(ins->link), midgard_instruction, link);
 329 }
 330
 331 static inline midgard_instruction*
 332 mir_next_op(struct midgard_instruction *ins)
 333 {
 334         return list_first_entry(&(ins->link), midgard_instruction, link);
 335 }
 336
 337 #define mir_foreach_block(ctx, v) \
 338         list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
 339
 340 #define mir_foreach_block_from(ctx, from, v) \
 341         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 342
 343 #define mir_foreach_instr(ctx, v) \
 344         list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 345
 346 #define mir_foreach_instr_safe(ctx, v) \
 347         list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 348
 349 #define mir_foreach_instr_in_block(block, v) \
 350         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 351 #define mir_foreach_instr_in_block_rev(block, v) \
 352         list_for_each_entry_rev(struct midgard_instruction, v, &block->instructions, link)
 353
 354 #define mir_foreach_instr_in_block_safe(block, v) \
 355         list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
 356
 357 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 358         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
 359
 360 #define mir_foreach_instr_in_block_from(block, v, from) \
 361         list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
 362
 363 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 364         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
 365
 366 #define mir_foreach_bundle_in_block(block, v) \
 367         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 368
 369 #define mir_foreach_bundle_in_block_rev(block, v) \
 370         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 371
 372 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 373         midgard_instruction* v; \
 374         signed i = 0; \
 375         mir_foreach_bundle_in_block_rev(block, _bundle) \
 376                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 377                                 i >= 0; \
 378                                 --i, v = _bundle->instructions[i]) \
 379
 380 #define mir_foreach_instr_global(ctx, v) \
 381         mir_foreach_block(ctx, v_block) \
 382                 mir_foreach_instr_in_block(v_block, v)
 383
 384 #define mir_foreach_instr_global_safe(ctx, v) \
 385         mir_foreach_block(ctx, v_block) \
 386                 mir_foreach_instr_in_block_safe(v_block, v)
 387
 388 #define mir_foreach_successor(blk, v) \
 389         struct midgard_block *v; \
 390         struct midgard_block **_v; \
 391         for (_v = &blk->successors[0], \
 392                 v = *_v; \
 393                 v != NULL && _v < &blk->successors[2]; \
 394                 _v++, v = *_v) \
 395
 396 /* Based on set_foreach, expanded with automatic type casts */
 397
 398 #define mir_foreach_predecessor(blk, v) \
 399         struct set_entry *_entry_##v; \
 400         struct midgard_block *v; \
 401         for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
 402                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 403                 _entry_##v != NULL; \
 404                 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
 405                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 406
 407 #define mir_foreach_src(ins, v) \
 408         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 409
 410 static inline midgard_instruction *
 411 mir_last_in_block(struct midgard_block *block)
 412 {
 413         return list_last_entry(&block->instructions, struct midgard_instruction, link);
 414 }
 415
 416 static inline midgard_block *
 417 mir_get_block(compiler_context *ctx, int idx)
 418 {
 419         struct list_head *lst = &ctx->blocks;
 420
 421         while ((idx--) + 1)
 422                 lst = lst->next;
 423
 424         return (struct midgard_block *) lst;
 425 }
 426
 427 static inline midgard_block *
 428 mir_exit_block(struct compiler_context *ctx)
 429 {
 430         midgard_block *last = list_last_entry(&ctx->blocks,
 431                         struct midgard_block, link);
 432
 433         /* The last block must be empty logically but contains branch writeout
 434          * for fragment shaders */
 435
 436         assert(last->nr_successors == 0);
 437
 438         return last;
 439 }
 440
 441 static inline bool
 442 mir_is_alu_bundle(midgard_bundle *bundle)
 443 {
 444         return IS_ALU(bundle->tag);
 445 }
 446
 447 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
 448
 449 #define IS_REG (1)
 450
 451 static inline unsigned
 452 make_compiler_temp(compiler_context *ctx)
 453 {
 454         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 455 }
 456
 457 static inline unsigned
 458 make_compiler_temp_reg(compiler_context *ctx)
 459 {
 460         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
 461 }
 462
 463 static inline unsigned
 464 nir_src_index(compiler_context *ctx, nir_src *src)
 465 {
 466         if (src->is_ssa)
 467                 return (src->ssa->index << 1) | 0;
 468         else {
 469                 assert(!src->reg.indirect);
 470                 return (src->reg.reg->index << 1) | IS_REG;
 471         }
 472 }
 473
 474 static inline unsigned
 475 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
 476 {
 477         return nir_src_index(ctx, &src->src);
 478 }
 479
 480 static inline unsigned
 481 nir_dest_index(compiler_context *ctx, nir_dest *dst)
 482 {
 483         if (dst->is_ssa)
 484                 return (dst->ssa.index << 1) | 0;
 485         else {
 486                 assert(!dst->reg.indirect);
 487                 return (dst->reg.reg->index << 1) | IS_REG;
 488         }
 489 }
 490
 491
 492
 493 /* MIR manipulation */
 494
 495 unsigned mir_get_swizzle(midgard_instruction *ins, unsigned idx);
 496 void mir_set_swizzle(midgard_instruction *ins, unsigned idx, unsigned new);
 497 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 498 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 499 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 500 void mir_rewrite_index_dst_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 501 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 502 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 503 void mir_rewrite_index_src_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 504 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned swizzle);
 505 bool mir_single_use(compiler_context *ctx, unsigned value);
 506 bool mir_special_index(compiler_context *ctx, unsigned idx);
 507 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 508 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 509 unsigned mir_mask_of_read_components(midgard_instruction *ins, unsigned node);
 510 unsigned mir_ubo_shift(midgard_load_store_op op);
 511
 512 /* MIR printing */
 513
 514 void mir_print_instruction(midgard_instruction *ins);
 515 void mir_print_bundle(midgard_bundle *ctx);
 516 void mir_print_block(midgard_block *block);
 517 void mir_print_shader(compiler_context *ctx);
 518 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 519 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 520 bool mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask);
 521 bool mir_nontrivial_outmod(midgard_instruction *ins);
 522
 523 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 524 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 525
 526 /* MIR goodies */
 527
 528 static const midgard_vector_alu_src blank_alu_src = {
 529         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
 530 };
 531
 532 static const midgard_vector_alu_src blank_alu_src_xxxx = {
 533         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X),
 534 };
 535
 536 static const midgard_scalar_alu_src blank_scalar_alu_src = {
 537         .full = true
 538 };
 539
 540 /* Used for encoding the unused source of 1-op instructions */
 541 static const midgard_vector_alu_src zero_alu_src = { 0 };
 542
 543 /* 'Intrinsic' move for aliasing */
 544
 545 static inline midgard_instruction
 546 v_mov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
 547 {
 548         midgard_instruction ins = {
 549                 .type = TAG_ALU_4,
 550                 .mask = 0xF,
 551                 .src = { SSA_UNUSED, src, SSA_UNUSED },
 552                 .dest = dest,
 553                 .alu = {
 554                         .op = midgard_alu_op_imov,
 555                         .reg_mode = midgard_reg_mode_32,
 556                         .dest_override = midgard_dest_override_none,
 557                         .outmod = midgard_outmod_int_wrap,
 558                         .src1 = vector_alu_srco_unsigned(zero_alu_src),
 559                         .src2 = vector_alu_srco_unsigned(mod)
 560                 },
 561         };
 562
 563         return ins;
 564 }
 565
 566 static inline bool
 567 mir_has_arg(midgard_instruction *ins, unsigned arg)
 568 {
 569         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
 570                 if (ins->src[i] == arg)
 571                         return true;
 572         }
 573
 574         return false;
 575 }
 576
 577 /* Scheduling */
 578
 579 void schedule_program(compiler_context *ctx);
 580
 581 /* Register allocation */
 582
 583 struct ra_graph;
 584
 585 /* Broad types of register classes so we can handle special
 586  * registers */
 587
 588 #define NR_REG_CLASSES 5
 589
 590 #define REG_CLASS_WORK          0
 591 #define REG_CLASS_LDST          1
 592 #define REG_CLASS_LDST27        2
 593 #define REG_CLASS_TEXR          3
 594 #define REG_CLASS_TEXW          4
 595
 596 void mir_lower_special_reads(compiler_context *ctx);
 597 struct ra_graph* allocate_registers(compiler_context *ctx, bool *spilled);
 598 void install_registers(compiler_context *ctx, struct ra_graph *g);
 599 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 600 bool mir_has_multiple_writes(compiler_context *ctx, int src);
 601
 602 void mir_create_pipeline_registers(compiler_context *ctx);
 603
 604 void
 605 midgard_promote_uniforms(compiler_context *ctx, unsigned promoted_count);
 606
 607 midgard_instruction *
 608 emit_ubo_read(
 609         compiler_context *ctx,
 610         nir_instr *instr,
 611         unsigned dest,
 612         unsigned offset,
 613         nir_src *indirect_offset,
 614         unsigned index);
 615
 616 void
 617 emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override, unsigned nr_components);
 618
 619 void
 620 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 621
 622 void
 623 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 624
 625 bool mir_op_computes_derivatives(unsigned op);
 626
 627 /* Final emission */
 628
 629 void emit_binary_bundle(
 630         compiler_context *ctx,
 631         midgard_bundle *bundle,
 632         struct util_dynarray *emission,
 633         int next_tag);
 634
 635 /* NIR stuff. TODO: Move? Share? Something? */
 636
 637 bool
 638 nir_undef_to_zero(nir_shader *shader);
 639
 640 void
 641 nir_clamp_psiz(nir_shader *shader, float min_size, float max_size);
 642
 643 /* Optimizations */
 644
 645 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 646 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 647 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 648 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 649 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 650 void midgard_opt_post_move_eliminate(compiler_context *ctx, midgard_block *block, struct ra_graph *g);
 651
 652 void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
 653 bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
 654 bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
 655 bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
 656 bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
 657
 658 #endif