src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30
  31 #include "util/hash_table.h"
  32 #include "util/u_dynarray.h"
  33 #include "util/set.h"
  34 #include "util/list.h"
  35
  36 #include "main/mtypes.h"
  37 #include "compiler/nir_types.h"
  38 #include "compiler/nir/nir.h"
  39
  40 /* Forward declare */
  41 struct midgard_block;
  42
  43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  44  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  45  * instruction is actually a discard op. */
  46
  47 #define TARGET_GOTO 0
  48 #define TARGET_BREAK 1
  49 #define TARGET_CONTINUE 2
  50 #define TARGET_DISCARD 3
  51
  52 typedef struct midgard_branch {
  53         /* If conditional, the condition is specified in r31.w */
  54         bool conditional;
  55
  56         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  57         bool invert_conditional;
  58
  59         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  60         unsigned target_type;
  61
  62         /* The actual target */
  63         union {
  64                 int target_block;
  65                 int target_break;
  66                 int target_continue;
  67         };
  68 } midgard_branch;
  69
  70 /* Instruction arguments represented as block-local SSA indices, rather than
  71  * registers. Negative values mean unused. */
  72
  73 typedef struct {
  74         int src[3];
  75         int dest;
  76
  77         bool inline_constant;
  78 } ssa_args;
  79
  80 /* Generic in-memory data type repesenting a single logical instruction, rather
  81  * than a single instruction group. This is the preferred form for code gen.
  82  * Multiple midgard_insturctions will later be combined during scheduling,
  83  * though this is not represented in this structure.  Its format bridges
  84  * the low-level binary representation with the higher level semantic meaning.
  85  *
  86  * Notably, it allows registers to be specified as block local SSA, for code
  87  * emitted before the register allocation pass.
  88  */
  89
  90 typedef struct midgard_instruction {
  91         /* Must be first for casting */
  92         struct list_head link;
  93
  94         unsigned type; /* ALU, load/store, texture */
  95
  96         /* If the register allocator has not run yet... */
  97         ssa_args ssa_args;
  98
  99         /* Special fields for an ALU instruction */
 100         midgard_reg_info registers;
 101
 102         /* I.e. (1 << alu_bit) */
 103         int unit;
 104
 105         /* When emitting bundle, should this instruction have a break forced
 106          * before it? Used for r31 writes which are valid only within a single
 107          * bundle and *need* to happen as early as possible... this is a hack,
 108          * TODO remove when we have a scheduler */
 109         bool precede_break;
 110
 111         bool has_constants;
 112         float constants[4];
 113         uint16_t inline_constant;
 114         bool has_blend_constant;
 115
 116         bool compact_branch;
 117         bool writeout;
 118         bool prepacked_branch;
 119
 120         /* Kind of a hack, but hint against aggressive DCE */
 121         bool dont_eliminate;
 122
 123         /* Masks in a saneish format. One bit per channel, not packed fancy.
 124          * Use this instead of the op specific ones, and switch over at emit
 125          * time */
 126
 127         uint16_t mask;
 128
 129         /* For ALU ops only: set to true to invert (bitwise NOT) the
 130          * destination of an integer-out op. Not imeplemented in hardware but
 131          * allows more optimizations */
 132
 133         bool invert;
 134
 135         /* Hint for the register allocator not to spill the destination written
 136          * from this instruction (because it is a spill/unspill node itself) */
 137
 138         bool no_spill;
 139
 140         /* Generic hint for intra-pass use */
 141         bool hint;
 142
 143         union {
 144                 midgard_load_store_word load_store;
 145                 midgard_vector_alu alu;
 146                 midgard_texture_word texture;
 147                 midgard_branch_extended branch_extended;
 148                 uint16_t br_compact;
 149
 150                 /* General branch, rather than packed br_compact. Higher level
 151                  * than the other components */
 152                 midgard_branch branch;
 153         };
 154 } midgard_instruction;
 155
 156 typedef struct midgard_block {
 157         /* Link to next block. Must be first for mir_get_block */
 158         struct list_head link;
 159
 160         /* List of midgard_instructions emitted for the current block */
 161         struct list_head instructions;
 162
 163         /* Index of the block in source order */
 164         unsigned source_id;
 165
 166         bool is_scheduled;
 167
 168         /* List of midgard_bundles emitted (after the scheduler has run) */
 169         struct util_dynarray bundles;
 170
 171         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 172         unsigned quadword_count;
 173
 174         /* Succeeding blocks. The compiler should not necessarily rely on
 175          * source-order traversal */
 176         struct midgard_block *successors[2];
 177         unsigned nr_successors;
 178
 179         struct set *predecessors;
 180
 181         /* The successors pointer form a graph, and in the case of
 182          * complex control flow, this graph has a cycles. To aid
 183          * traversal during liveness analysis, we have a visited?
 184          * boolean for passes to use as they see fit, provided they
 185          * clean up later */
 186         bool visited;
 187
 188         /* In liveness analysis, these are live masks (per-component) for
 189          * indices for the block. Scalar compilers have the luxury of using
 190          * simple bit fields, but for us, liveness is a vector idea. We use
 191          * 8-bit to allow finegrained tracking up to vec8. If you're
 192          * implementing vec16 on Panfrost... I'm sorry. */
 193         uint8_t *live_in;
 194         uint8_t *live_out;
 195 } midgard_block;
 196
 197 typedef struct midgard_bundle {
 198         /* Tag for the overall bundle */
 199         int tag;
 200
 201         /* Instructions contained by the bundle */
 202         int instruction_count;
 203         midgard_instruction *instructions[5];
 204
 205         /* Bundle-wide ALU configuration */
 206         int padding;
 207         int control;
 208         bool has_embedded_constants;
 209         float constants[4];
 210         bool has_blend_constant;
 211 } midgard_bundle;
 212
 213 typedef struct compiler_context {
 214         nir_shader *nir;
 215         gl_shader_stage stage;
 216
 217         /* The screen we correspond to */
 218         struct midgard_screen *screen;
 219
 220         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 221         bool is_blend;
 222
 223         /* Tracking for blend constant patching */
 224         int blend_constant_offset;
 225
 226         /* Number of bytes used for Thread Local Storage */
 227         unsigned tls_size;
 228
 229         /* Count of spills and fills for shaderdb */
 230         unsigned spills;
 231         unsigned fills;
 232
 233         /* Current NIR function */
 234         nir_function *func;
 235
 236         /* Allocated compiler temporary counter */
 237         unsigned temp_alloc;
 238
 239         /* Unordered list of midgard_blocks */
 240         int block_count;
 241         struct list_head blocks;
 242
 243         /* TODO merge with block_count? */
 244         unsigned block_source_count;
 245
 246         /* List of midgard_instructions emitted for the current block */
 247         midgard_block *current_block;
 248
 249         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 250         midgard_block *after_block;
 251
 252         /* The current "depth" of the loop, for disambiguating breaks/continues
 253          * when using nested loops */
 254         int current_loop_depth;
 255
 256         /* Total number of loops for shader-db */
 257         unsigned loop_count;
 258
 259         /* Constants which have been loaded, for later inlining */
 260         struct hash_table_u64 *ssa_constants;
 261
 262         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 263         struct hash_table_u64 *hash_to_temp;
 264         int temp_count;
 265         int max_hash;
 266
 267         /* Just the count of the max register used. Higher count => higher
 268          * register pressure */
 269         int work_registers;
 270
 271         /* Used for cont/last hinting. Increase when a tex op is added.
 272          * Decrease when a tex op is removed. */
 273         int texture_op_count;
 274
 275         /* Mapping of texture register -> SSA index for unaliasing */
 276         int texture_index[2];
 277
 278         /* The number of uniforms allowable for the fast path */
 279         int uniform_cutoff;
 280
 281         /* Count of instructions emitted from NIR overall, across all blocks */
 282         int instruction_count;
 283
 284         /* Alpha ref value passed in */
 285         float alpha_ref;
 286
 287         /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
 288         unsigned sysvals[MAX_SYSVAL_COUNT];
 289         unsigned sysval_count;
 290         struct hash_table_u64 *sysval_to_id;
 291 } compiler_context;
 292
 293 /* Helpers for manipulating the above structures (forming the driver IR) */
 294
 295 /* Append instruction to end of current block */
 296
 297 static inline midgard_instruction *
 298 mir_upload_ins(struct midgard_instruction ins)
 299 {
 300         midgard_instruction *heap = malloc(sizeof(ins));
 301         memcpy(heap, &ins, sizeof(ins));
 302         return heap;
 303 }
 304
 305 static inline midgard_instruction *
 306 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 307 {
 308         midgard_instruction *u = mir_upload_ins(ins);
 309         list_addtail(&u->link, &ctx->current_block->instructions);
 310         return u;
 311 }
 312
 313 static inline struct midgard_instruction *
 314 mir_insert_instruction_before(struct midgard_instruction *tag, struct midgard_instruction ins)
 315 {
 316         struct midgard_instruction *u = mir_upload_ins(ins);
 317         list_addtail(&u->link, &tag->link);
 318         return u;
 319 }
 320
 321 static inline void
 322 mir_remove_instruction(struct midgard_instruction *ins)
 323 {
 324         list_del(&ins->link);
 325 }
 326
 327 static inline midgard_instruction*
 328 mir_prev_op(struct midgard_instruction *ins)
 329 {
 330         return list_last_entry(&(ins->link), midgard_instruction, link);
 331 }
 332
 333 static inline midgard_instruction*
 334 mir_next_op(struct midgard_instruction *ins)
 335 {
 336         return list_first_entry(&(ins->link), midgard_instruction, link);
 337 }
 338
 339 #define mir_foreach_block(ctx, v) \
 340         list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
 341
 342 #define mir_foreach_block_from(ctx, from, v) \
 343         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 344
 345 #define mir_foreach_instr(ctx, v) \
 346         list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 347
 348 #define mir_foreach_instr_safe(ctx, v) \
 349         list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 350
 351 #define mir_foreach_instr_in_block(block, v) \
 352         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 353 #define mir_foreach_instr_in_block_rev(block, v) \
 354         list_for_each_entry_rev(struct midgard_instruction, v, &block->instructions, link)
 355
 356 #define mir_foreach_instr_in_block_safe(block, v) \
 357         list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
 358
 359 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 360         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
 361
 362 #define mir_foreach_instr_in_block_from(block, v, from) \
 363         list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
 364
 365 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 366         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
 367
 368 #define mir_foreach_bundle_in_block(block, v) \
 369         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 370
 371 #define mir_foreach_instr_global(ctx, v) \
 372         mir_foreach_block(ctx, v_block) \
 373                 mir_foreach_instr_in_block(v_block, v)
 374
 375 #define mir_foreach_instr_global_safe(ctx, v) \
 376         mir_foreach_block(ctx, v_block) \
 377                 mir_foreach_instr_in_block_safe(v_block, v)
 378
 379 #define mir_foreach_successor(blk, v) \
 380         struct midgard_block *v; \
 381         struct midgard_block **_v; \
 382         for (_v = &blk->successors[0], \
 383                 v = *_v; \
 384                 v != NULL && _v < &blk->successors[2]; \
 385                 _v++, v = *_v) \
 386
 387 /* Based on set_foreach, expanded with automatic type casts */
 388
 389 #define mir_foreach_predecessor(blk, v) \
 390         struct set_entry *_entry_##v; \
 391         struct midgard_block *v; \
 392         for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
 393                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 394                 _entry_##v != NULL; \
 395                 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
 396                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 397
 398 #define mir_foreach_src(ins, v) \
 399         for (unsigned v = 0; v < ARRAY_SIZE(ins->ssa_args.src); ++v)
 400
 401 static inline midgard_instruction *
 402 mir_last_in_block(struct midgard_block *block)
 403 {
 404         return list_last_entry(&block->instructions, struct midgard_instruction, link);
 405 }
 406
 407 static inline midgard_block *
 408 mir_get_block(compiler_context *ctx, int idx)
 409 {
 410         struct list_head *lst = &ctx->blocks;
 411
 412         while ((idx--) + 1)
 413                 lst = lst->next;
 414
 415         return (struct midgard_block *) lst;
 416 }
 417
 418 static inline midgard_block *
 419 mir_exit_block(struct compiler_context *ctx)
 420 {
 421         midgard_block *last = list_last_entry(&ctx->blocks,
 422                         struct midgard_block, link);
 423
 424         /* The last block must be empty (the exit block) */
 425         assert(list_empty(&last->instructions));
 426         assert(last->nr_successors == 0);
 427
 428         return last;
 429 }
 430
 431 static inline bool
 432 mir_is_alu_bundle(midgard_bundle *bundle)
 433 {
 434         return IS_ALU(bundle->tag);
 435 }
 436
 437 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
 438
 439 #define IS_REG (1)
 440
 441 static inline unsigned
 442 make_compiler_temp(compiler_context *ctx)
 443 {
 444         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 445 }
 446
 447 static inline unsigned
 448 make_compiler_temp_reg(compiler_context *ctx)
 449 {
 450         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
 451 }
 452
 453 static inline unsigned
 454 nir_src_index(compiler_context *ctx, nir_src *src)
 455 {
 456         if (src->is_ssa)
 457                 return (src->ssa->index << 1) | 0;
 458         else {
 459                 assert(!src->reg.indirect);
 460                 return (src->reg.reg->index << 1) | IS_REG;
 461         }
 462 }
 463
 464 static inline unsigned
 465 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
 466 {
 467         return nir_src_index(ctx, &src->src);
 468 }
 469
 470 static inline unsigned
 471 nir_dest_index(compiler_context *ctx, nir_dest *dst)
 472 {
 473         if (dst->is_ssa)
 474                 return (dst->ssa.index << 1) | 0;
 475         else {
 476                 assert(!dst->reg.indirect);
 477                 return (dst->reg.reg->index << 1) | IS_REG;
 478         }
 479 }
 480
 481
 482
 483 /* MIR manipulation */
 484
 485 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 486 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 487 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 488 void mir_rewrite_index_dst_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 489 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 490 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 491 void mir_rewrite_index_src_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 492 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned swizzle);
 493 bool mir_single_use(compiler_context *ctx, unsigned value);
 494 bool mir_special_index(compiler_context *ctx, unsigned idx);
 495 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 496 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 497 unsigned mir_mask_of_read_components(midgard_instruction *ins, unsigned node);
 498 unsigned mir_ubo_shift(midgard_load_store_op op);
 499
 500 /* MIR printing */
 501
 502 void mir_print_instruction(midgard_instruction *ins);
 503 void mir_print_bundle(midgard_bundle *ctx);
 504 void mir_print_block(midgard_block *block);
 505 void mir_print_shader(compiler_context *ctx);
 506 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 507 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 508 bool mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask);
 509 bool mir_nontrivial_outmod(midgard_instruction *ins);
 510
 511 /* MIR goodies */
 512
 513 static const midgard_vector_alu_src blank_alu_src = {
 514         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
 515 };
 516
 517 static const midgard_vector_alu_src blank_alu_src_xxxx = {
 518         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X),
 519 };
 520
 521 static const midgard_scalar_alu_src blank_scalar_alu_src = {
 522         .full = true
 523 };
 524
 525 /* Used for encoding the unused source of 1-op instructions */
 526 static const midgard_vector_alu_src zero_alu_src = { 0 };
 527
 528 /* 'Intrinsic' move for aliasing */
 529
 530 static inline midgard_instruction
 531 v_mov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
 532 {
 533         midgard_instruction ins = {
 534                 .type = TAG_ALU_4,
 535                 .mask = 0xF,
 536                 .ssa_args = {
 537                         .src = { SSA_UNUSED_1, src, -1 },
 538                         .dest = dest,
 539                 },
 540                 .alu = {
 541                         .op = midgard_alu_op_imov,
 542                         .reg_mode = midgard_reg_mode_32,
 543                         .dest_override = midgard_dest_override_none,
 544                         .outmod = midgard_outmod_int_wrap,
 545                         .src1 = vector_alu_srco_unsigned(zero_alu_src),
 546                         .src2 = vector_alu_srco_unsigned(mod)
 547                 },
 548         };
 549
 550         return ins;
 551 }
 552
 553 static inline bool
 554 mir_has_arg(midgard_instruction *ins, unsigned arg)
 555 {
 556         for (unsigned i = 0; i < ARRAY_SIZE(ins->ssa_args.src); ++i) {
 557                 if (ins->ssa_args.src[i] == arg)
 558                         return true;
 559         }
 560
 561         return false;
 562 }
 563
 564 /* Scheduling */
 565
 566 void schedule_program(compiler_context *ctx);
 567
 568 /* Register allocation */
 569
 570 struct ra_graph;
 571
 572 /* Broad types of register classes so we can handle special
 573  * registers */
 574
 575 #define NR_REG_CLASSES 5
 576
 577 #define REG_CLASS_WORK          0
 578 #define REG_CLASS_LDST          1
 579 #define REG_CLASS_LDST27        2
 580 #define REG_CLASS_TEXR          3
 581 #define REG_CLASS_TEXW          4
 582
 583 void mir_lower_special_reads(compiler_context *ctx);
 584 struct ra_graph* allocate_registers(compiler_context *ctx, bool *spilled);
 585 void install_registers(compiler_context *ctx, struct ra_graph *g);
 586 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 587 bool mir_has_multiple_writes(compiler_context *ctx, int src);
 588
 589 void mir_create_pipeline_registers(compiler_context *ctx);
 590
 591 void
 592 midgard_promote_uniforms(compiler_context *ctx, unsigned promoted_count);
 593
 594 midgard_instruction *
 595 emit_ubo_read(
 596         compiler_context *ctx,
 597         nir_instr *instr,
 598         unsigned dest,
 599         unsigned offset,
 600         nir_src *indirect_offset,
 601         unsigned index);
 602
 603 void
 604 emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override, unsigned nr_components);
 605
 606 void
 607 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 608
 609 void
 610 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 611
 612 bool mir_op_computes_derivatives(unsigned op);
 613
 614 /* Final emission */
 615
 616 void emit_binary_bundle(
 617         compiler_context *ctx,
 618         midgard_bundle *bundle,
 619         struct util_dynarray *emission,
 620         int next_tag);
 621
 622 /* NIR stuff. TODO: Move? Share? Something? */
 623
 624 bool
 625 nir_undef_to_zero(nir_shader *shader);
 626
 627 void
 628 nir_clamp_psiz(nir_shader *shader, float min_size, float max_size);
 629
 630 /* Optimizations */
 631
 632 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 633 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 634 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 635 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 636 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 637 void midgard_opt_post_move_eliminate(compiler_context *ctx, midgard_block *block, struct ra_graph *g);
 638
 639 void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
 640 bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
 641 bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
 642 bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
 643
 644 #endif