src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30
  31 #include "util/hash_table.h"
  32 #include "util/u_dynarray.h"
  33 #include "util/set.h"
  34 #include "util/list.h"
  35
  36 #include "main/mtypes.h"
  37 #include "compiler/nir_types.h"
  38 #include "compiler/nir/nir.h"
  39
  40 /* Forward declare */
  41 struct midgard_block;
  42
  43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  44  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  45  * instruction is actually a discard op. */
  46
  47 #define TARGET_GOTO 0
  48 #define TARGET_BREAK 1
  49 #define TARGET_CONTINUE 2
  50 #define TARGET_DISCARD 3
  51
  52 typedef struct midgard_branch {
  53         /* If conditional, the condition is specified in r31.w */
  54         bool conditional;
  55
  56         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  57         bool invert_conditional;
  58
  59         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  60         unsigned target_type;
  61
  62         /* The actual target */
  63         union {
  64                 int target_block;
  65                 int target_break;
  66                 int target_continue;
  67         };
  68 } midgard_branch;
  69
  70 /* Instruction arguments represented as block-local SSA indices, rather than
  71  * registers. Negative values mean unused. */
  72
  73 typedef struct {
  74         int src[3];
  75         int dest;
  76
  77         bool inline_constant;
  78 } ssa_args;
  79
  80 /* Generic in-memory data type repesenting a single logical instruction, rather
  81  * than a single instruction group. This is the preferred form for code gen.
  82  * Multiple midgard_insturctions will later be combined during scheduling,
  83  * though this is not represented in this structure.  Its format bridges
  84  * the low-level binary representation with the higher level semantic meaning.
  85  *
  86  * Notably, it allows registers to be specified as block local SSA, for code
  87  * emitted before the register allocation pass.
  88  */
  89
  90 typedef struct midgard_instruction {
  91         /* Must be first for casting */
  92         struct list_head link;
  93
  94         unsigned type; /* ALU, load/store, texture */
  95
  96         /* If the register allocator has not run yet... */
  97         ssa_args ssa_args;
  98
  99         /* Special fields for an ALU instruction */
 100         midgard_reg_info registers;
 101
 102         /* I.e. (1 << alu_bit) */
 103         int unit;
 104
 105         /* When emitting bundle, should this instruction have a break forced
 106          * before it? Used for r31 writes which are valid only within a single
 107          * bundle and *need* to happen as early as possible... this is a hack,
 108          * TODO remove when we have a scheduler */
 109         bool precede_break;
 110
 111         bool has_constants;
 112         float constants[4];
 113         uint16_t inline_constant;
 114         bool has_blend_constant;
 115
 116         bool compact_branch;
 117         bool writeout;
 118         bool prepacked_branch;
 119
 120         /* Kind of a hack, but hint against aggressive DCE */
 121         bool dont_eliminate;
 122
 123         /* Masks in a saneish format. One bit per channel, not packed fancy.
 124          * Use this instead of the op specific ones, and switch over at emit
 125          * time */
 126
 127         uint16_t mask;
 128
 129         /* For ALU ops only: set to true to invert (bitwise NOT) the
 130          * destination of an integer-out op. Not imeplemented in hardware but
 131          * allows more optimizations */
 132
 133         bool invert;
 134
 135         /* Hint for the register allocator not to spill the destination written
 136          * from this instruction (because it is a spill/unspill node itself) */
 137
 138         bool no_spill;
 139
 140         /* Generic hint for intra-pass use */
 141         bool hint;
 142
 143         union {
 144                 midgard_load_store_word load_store;
 145                 midgard_vector_alu alu;
 146                 midgard_texture_word texture;
 147                 midgard_branch_extended branch_extended;
 148                 uint16_t br_compact;
 149
 150                 /* General branch, rather than packed br_compact. Higher level
 151                  * than the other components */
 152                 midgard_branch branch;
 153         };
 154 } midgard_instruction;
 155
 156 typedef struct midgard_block {
 157         /* Link to next block. Must be first for mir_get_block */
 158         struct list_head link;
 159
 160         /* List of midgard_instructions emitted for the current block */
 161         struct list_head instructions;
 162
 163         bool is_scheduled;
 164
 165         /* List of midgard_bundles emitted (after the scheduler has run) */
 166         struct util_dynarray bundles;
 167
 168         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 169         unsigned quadword_count;
 170
 171         /* Succeeding blocks. The compiler should not necessarily rely on
 172          * source-order traversal */
 173         struct midgard_block *successors[4];
 174         unsigned nr_successors;
 175
 176         /* The successors pointer form a graph, and in the case of
 177          * complex control flow, this graph has a cycles. To aid
 178          * traversal during liveness analysis, we have a visited?
 179          * boolean for passes to use as they see fit, provided they
 180          * clean up later */
 181         bool visited;
 182 } midgard_block;
 183
 184 typedef struct midgard_bundle {
 185         /* Tag for the overall bundle */
 186         int tag;
 187
 188         /* Instructions contained by the bundle */
 189         int instruction_count;
 190         midgard_instruction *instructions[5];
 191
 192         /* Bundle-wide ALU configuration */
 193         int padding;
 194         int control;
 195         bool has_embedded_constants;
 196         float constants[4];
 197         bool has_blend_constant;
 198 } midgard_bundle;
 199
 200 typedef struct compiler_context {
 201         nir_shader *nir;
 202         gl_shader_stage stage;
 203
 204         /* The screen we correspond to */
 205         struct midgard_screen *screen;
 206
 207         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 208         bool is_blend;
 209
 210         /* Tracking for blend constant patching */
 211         int blend_constant_offset;
 212
 213         /* Number of bytes used for Thread Local Storage */
 214         unsigned tls_size;
 215
 216         /* Count of spills and fills for shaderdb */
 217         unsigned spills;
 218         unsigned fills;
 219
 220         /* Current NIR function */
 221         nir_function *func;
 222
 223         /* Allocated compiler temporary counter */
 224         unsigned temp_alloc;
 225
 226         /* Unordered list of midgard_blocks */
 227         int block_count;
 228         struct list_head blocks;
 229
 230         /* List of midgard_instructions emitted for the current block */
 231         midgard_block *current_block;
 232
 233         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 234         midgard_block *after_block;
 235
 236         /* The current "depth" of the loop, for disambiguating breaks/continues
 237          * when using nested loops */
 238         int current_loop_depth;
 239
 240         /* Total number of loops for shader-db */
 241         unsigned loop_count;
 242
 243         /* Constants which have been loaded, for later inlining */
 244         struct hash_table_u64 *ssa_constants;
 245
 246         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 247         struct hash_table_u64 *hash_to_temp;
 248         int temp_count;
 249         int max_hash;
 250
 251         /* Just the count of the max register used. Higher count => higher
 252          * register pressure */
 253         int work_registers;
 254
 255         /* Used for cont/last hinting. Increase when a tex op is added.
 256          * Decrease when a tex op is removed. */
 257         int texture_op_count;
 258
 259         /* Mapping of texture register -> SSA index for unaliasing */
 260         int texture_index[2];
 261
 262         /* The number of uniforms allowable for the fast path */
 263         int uniform_cutoff;
 264
 265         /* Count of instructions emitted from NIR overall, across all blocks */
 266         int instruction_count;
 267
 268         /* Alpha ref value passed in */
 269         float alpha_ref;
 270
 271         /* The index corresponding to the fragment output */
 272         unsigned fragment_output;
 273
 274         /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
 275         unsigned sysvals[MAX_SYSVAL_COUNT];
 276         unsigned sysval_count;
 277         struct hash_table_u64 *sysval_to_id;
 278 } compiler_context;
 279
 280 /* Helpers for manipulating the above structures (forming the driver IR) */
 281
 282 /* Append instruction to end of current block */
 283
 284 static inline midgard_instruction *
 285 mir_upload_ins(struct midgard_instruction ins)
 286 {
 287         midgard_instruction *heap = malloc(sizeof(ins));
 288         memcpy(heap, &ins, sizeof(ins));
 289         return heap;
 290 }
 291
 292 static inline midgard_instruction *
 293 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 294 {
 295         midgard_instruction *u = mir_upload_ins(ins);
 296         list_addtail(&u->link, &ctx->current_block->instructions);
 297         return u;
 298 }
 299
 300 static inline struct midgard_instruction *
 301 mir_insert_instruction_before(struct midgard_instruction *tag, struct midgard_instruction ins)
 302 {
 303         struct midgard_instruction *u = mir_upload_ins(ins);
 304         list_addtail(&u->link, &tag->link);
 305         return u;
 306 }
 307
 308 static inline void
 309 mir_remove_instruction(struct midgard_instruction *ins)
 310 {
 311         list_del(&ins->link);
 312 }
 313
 314 static inline midgard_instruction*
 315 mir_prev_op(struct midgard_instruction *ins)
 316 {
 317         return list_last_entry(&(ins->link), midgard_instruction, link);
 318 }
 319
 320 static inline midgard_instruction*
 321 mir_next_op(struct midgard_instruction *ins)
 322 {
 323         return list_first_entry(&(ins->link), midgard_instruction, link);
 324 }
 325
 326 #define mir_foreach_block(ctx, v) \
 327         list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
 328
 329 #define mir_foreach_block_from(ctx, from, v) \
 330         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 331
 332 #define mir_foreach_instr(ctx, v) \
 333         list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 334
 335 #define mir_foreach_instr_safe(ctx, v) \
 336         list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 337
 338 #define mir_foreach_instr_in_block(block, v) \
 339         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 340
 341 #define mir_foreach_instr_in_block_safe(block, v) \
 342         list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
 343
 344 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 345         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
 346
 347 #define mir_foreach_instr_in_block_from(block, v, from) \
 348         list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
 349
 350 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 351         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
 352
 353 #define mir_foreach_bundle_in_block(block, v) \
 354         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 355
 356 #define mir_foreach_instr_global(ctx, v) \
 357         mir_foreach_block(ctx, v_block) \
 358                 mir_foreach_instr_in_block(v_block, v)
 359
 360 #define mir_foreach_instr_global_safe(ctx, v) \
 361         mir_foreach_block(ctx, v_block) \
 362                 mir_foreach_instr_in_block_safe(v_block, v)
 363
 364 static inline midgard_instruction *
 365 mir_last_in_block(struct midgard_block *block)
 366 {
 367         return list_last_entry(&block->instructions, struct midgard_instruction, link);
 368 }
 369
 370 static inline midgard_block *
 371 mir_get_block(compiler_context *ctx, int idx)
 372 {
 373         struct list_head *lst = &ctx->blocks;
 374
 375         while ((idx--) + 1)
 376                 lst = lst->next;
 377
 378         return (struct midgard_block *) lst;
 379 }
 380
 381 static inline bool
 382 mir_is_alu_bundle(midgard_bundle *bundle)
 383 {
 384         return IS_ALU(bundle->tag);
 385 }
 386
 387 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
 388
 389 #define IS_REG (1)
 390
 391 static inline unsigned
 392 make_compiler_temp(compiler_context *ctx)
 393 {
 394         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 395 }
 396
 397 static inline unsigned
 398 make_compiler_temp_reg(compiler_context *ctx)
 399 {
 400         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
 401 }
 402
 403 static inline unsigned
 404 nir_src_index(compiler_context *ctx, nir_src *src)
 405 {
 406         if (src->is_ssa)
 407                 return (src->ssa->index << 1) | 0;
 408         else {
 409                 assert(!src->reg.indirect);
 410                 return (src->reg.reg->index << 1) | IS_REG;
 411         }
 412 }
 413
 414 static inline unsigned
 415 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
 416 {
 417         return nir_src_index(ctx, &src->src);
 418 }
 419
 420 static inline unsigned
 421 nir_dest_index(compiler_context *ctx, nir_dest *dst)
 422 {
 423         if (dst->is_ssa)
 424                 return (dst->ssa.index << 1) | 0;
 425         else {
 426                 assert(!dst->reg.indirect);
 427                 return (dst->reg.reg->index << 1) | IS_REG;
 428         }
 429 }
 430
 431
 432
 433 /* MIR manipulation */
 434
 435 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 436 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 437 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 438 void mir_rewrite_index_dst_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 439 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 440 void mir_rewrite_index_src_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 441 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned swizzle);
 442 bool mir_single_use(compiler_context *ctx, unsigned value);
 443 bool mir_special_index(compiler_context *ctx, unsigned idx);
 444 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 445 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 446 unsigned mir_mask_of_read_components(midgard_instruction *ins, unsigned node);
 447
 448 /* MIR printing */
 449
 450 void mir_print_instruction(midgard_instruction *ins);
 451 void mir_print_bundle(midgard_bundle *ctx);
 452 void mir_print_block(midgard_block *block);
 453 void mir_print_shader(compiler_context *ctx);
 454 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 455 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 456 bool mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask);
 457 bool mir_nontrivial_outmod(midgard_instruction *ins);
 458
 459 /* MIR goodies */
 460
 461 static const midgard_vector_alu_src blank_alu_src = {
 462         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
 463 };
 464
 465 static const midgard_vector_alu_src blank_alu_src_xxxx = {
 466         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X),
 467 };
 468
 469 static const midgard_scalar_alu_src blank_scalar_alu_src = {
 470         .full = true
 471 };
 472
 473 /* Used for encoding the unused source of 1-op instructions */
 474 static const midgard_vector_alu_src zero_alu_src = { 0 };
 475
 476 /* 'Intrinsic' move for aliasing */
 477
 478 static inline midgard_instruction
 479 v_mov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
 480 {
 481         midgard_instruction ins = {
 482                 .type = TAG_ALU_4,
 483                 .mask = 0xF,
 484                 .ssa_args = {
 485                         .src = { SSA_UNUSED_1, src, -1 },
 486                         .dest = dest,
 487                 },
 488                 .alu = {
 489                         .op = midgard_alu_op_imov,
 490                         .reg_mode = midgard_reg_mode_32,
 491                         .dest_override = midgard_dest_override_none,
 492                         .outmod = midgard_outmod_int_wrap,
 493                         .src1 = vector_alu_srco_unsigned(zero_alu_src),
 494                         .src2 = vector_alu_srco_unsigned(mod)
 495                 },
 496         };
 497
 498         return ins;
 499 }
 500
 501 static inline bool
 502 mir_has_arg(midgard_instruction *ins, unsigned arg)
 503 {
 504         for (unsigned i = 0; i < ARRAY_SIZE(ins->ssa_args.src); ++i) {
 505                 if (ins->ssa_args.src[i] == arg)
 506                         return true;
 507         }
 508
 509         return false;
 510 }
 511
 512 /* Scheduling */
 513
 514 void schedule_program(compiler_context *ctx);
 515
 516 /* Register allocation */
 517
 518 struct ra_graph;
 519
 520 /* Broad types of register classes so we can handle special
 521  * registers */
 522
 523 #define NR_REG_CLASSES 5
 524
 525 #define REG_CLASS_WORK          0
 526 #define REG_CLASS_LDST          1
 527 #define REG_CLASS_LDST27        2
 528 #define REG_CLASS_TEXR          3
 529 #define REG_CLASS_TEXW          4
 530
 531 void mir_lower_special_reads(compiler_context *ctx);
 532 struct ra_graph* allocate_registers(compiler_context *ctx, bool *spilled);
 533 void install_registers(compiler_context *ctx, struct ra_graph *g);
 534 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 535 bool mir_has_multiple_writes(compiler_context *ctx, int src);
 536
 537 void mir_create_pipeline_registers(compiler_context *ctx);
 538
 539 void
 540 midgard_promote_uniforms(compiler_context *ctx, unsigned promoted_count);
 541
 542 midgard_instruction *
 543 emit_ubo_read(
 544         compiler_context *ctx,
 545         unsigned dest,
 546         unsigned offset,
 547         nir_src *indirect_offset,
 548         unsigned index);
 549
 550 void
 551 emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override, unsigned nr_components);
 552
 553 void
 554 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 555
 556 void
 557 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 558
 559 bool mir_op_computes_derivatives(unsigned op);
 560
 561 /* Final emission */
 562
 563 void emit_binary_bundle(
 564         compiler_context *ctx,
 565         midgard_bundle *bundle,
 566         struct util_dynarray *emission,
 567         int next_tag);
 568
 569 /* NIR stuff. TODO: Move? Share? Something? */
 570
 571 bool
 572 nir_undef_to_zero(nir_shader *shader);
 573
 574 void
 575 nir_clamp_psiz(nir_shader *shader, float min_size, float max_size);
 576
 577 /* Optimizations */
 578
 579 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 580 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 581 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 582 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 583 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 584 void midgard_opt_post_move_eliminate(compiler_context *ctx, midgard_block *block, struct ra_graph *g);
 585
 586 void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
 587 bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
 588 bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
 589 bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
 590
 591 #endif