src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30 #include "midgard_ops.h"
  31
  32 #include "util/hash_table.h"
  33 #include "util/u_dynarray.h"
  34 #include "util/set.h"
  35 #include "util/list.h"
  36
  37 #include "main/mtypes.h"
  38 #include "compiler/nir_types.h"
  39 #include "compiler/nir/nir.h"
  40 #include "panfrost/util/pan_ir.h"
  41 #include "panfrost/util/lcra.h"
  42
  43 /* Forward declare */
  44 struct midgard_block;
  45
  46 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  47  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  48  * instruction is actually a discard op. */
  49
  50 #define TARGET_GOTO 0
  51 #define TARGET_BREAK 1
  52 #define TARGET_CONTINUE 2
  53 #define TARGET_DISCARD 3
  54
  55 typedef struct midgard_branch {
  56         /* If conditional, the condition is specified in r31.w */
  57         bool conditional;
  58
  59         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  60         bool invert_conditional;
  61
  62         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  63         unsigned target_type;
  64
  65         /* The actual target */
  66         union {
  67                 int target_block;
  68                 int target_break;
  69                 int target_continue;
  70         };
  71 } midgard_branch;
  72
  73 /* Generic in-memory data type repesenting a single logical instruction, rather
  74  * than a single instruction group. This is the preferred form for code gen.
  75  * Multiple midgard_insturctions will later be combined during scheduling,
  76  * though this is not represented in this structure.  Its format bridges
  77  * the low-level binary representation with the higher level semantic meaning.
  78  *
  79  * Notably, it allows registers to be specified as block local SSA, for code
  80  * emitted before the register allocation pass.
  81  */
  82
  83 #define MIR_SRC_COUNT 4
  84 #define MIR_VEC_COMPONENTS 16
  85
  86 typedef struct midgard_instruction {
  87         /* Must be first for casting */
  88         struct list_head link;
  89
  90         unsigned type; /* ALU, load/store, texture */
  91
  92         /* Instruction arguments represented as block-local SSA
  93          * indices, rather than registers. ~0 means unused. */
  94         unsigned src[MIR_SRC_COUNT];
  95         unsigned dest;
  96
  97         /* vec16 swizzle, unpacked, per source */
  98         unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
  99
 100         /* Types! */
 101         nir_alu_type src_types[MIR_SRC_COUNT];
 102         nir_alu_type dest_type;
 103
 104         /* Packing ops have non-32-bit dest types even though they functionally
 105          * work at the 32-bit level, use this as a signal to disable copyprop.
 106          * We maybe need synthetic pack ops instead. */
 107         bool is_pack;
 108
 109         /* Modifiers, depending on type */
 110         union {
 111                 struct {
 112                         bool src_abs[MIR_SRC_COUNT];
 113                         bool src_neg[MIR_SRC_COUNT];
 114                 };
 115
 116                 struct {
 117                         bool src_shift[MIR_SRC_COUNT];
 118                 };
 119         };
 120
 121         /* Out of the union for csel (could maybe be fixed..) */
 122         bool src_invert[MIR_SRC_COUNT];
 123
 124         /* Special fields for an ALU instruction */
 125         midgard_reg_info registers;
 126
 127         /* For textures: should helpers execute this instruction (instead of
 128          * just helping with derivatives)? Should helpers terminate after? */
 129         bool helper_terminate;
 130         bool helper_execute;
 131
 132         /* I.e. (1 << alu_bit) */
 133         int unit;
 134
 135         bool has_constants;
 136         midgard_constants constants;
 137         uint16_t inline_constant;
 138         bool has_blend_constant;
 139         bool has_inline_constant;
 140
 141         bool compact_branch;
 142         bool writeout;
 143         bool writeout_depth;
 144         bool writeout_stencil;
 145         bool last_writeout;
 146
 147         /* Masks in a saneish format. One bit per channel, not packed fancy.
 148          * Use this instead of the op specific ones, and switch over at emit
 149          * time */
 150
 151         uint16_t mask;
 152
 153         /* Hint for the register allocator not to spill the destination written
 154          * from this instruction (because it is a spill/unspill node itself).
 155          * Bitmask of spilled classes */
 156
 157         unsigned no_spill;
 158
 159         /* Generic hint for intra-pass use */
 160         bool hint;
 161
 162         /* During scheduling, the backwards dependency graph
 163          * (DAG). nr_dependencies is the number of unscheduled
 164          * instructions that must still be scheduled after
 165          * (before) this instruction. dependents are which
 166          * instructions need to be scheduled before (after) this
 167          * instruction. */
 168
 169         unsigned nr_dependencies;
 170         BITSET_WORD *dependents;
 171
 172         union {
 173                 midgard_load_store_word load_store;
 174                 midgard_vector_alu alu;
 175                 midgard_texture_word texture;
 176                 midgard_branch_extended branch_extended;
 177                 uint16_t br_compact;
 178
 179                 /* General branch, rather than packed br_compact. Higher level
 180                  * than the other components */
 181                 midgard_branch branch;
 182         };
 183 } midgard_instruction;
 184
 185 typedef struct midgard_block {
 186         pan_block base;
 187
 188         bool scheduled;
 189
 190         /* List of midgard_bundles emitted (after the scheduler has run) */
 191         struct util_dynarray bundles;
 192
 193         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 194         unsigned quadword_count;
 195
 196         /* Indicates this is a fixed-function fragment epilogue block */
 197         bool epilogue;
 198
 199         /* Are helper invocations required by this block? */
 200         bool helpers_in;
 201 } midgard_block;
 202
 203 typedef struct midgard_bundle {
 204         /* Tag for the overall bundle */
 205         int tag;
 206
 207         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 208          * sadd, vadd, smul, vlut, branch) */
 209         int instruction_count;
 210         midgard_instruction *instructions[6];
 211
 212         /* Bundle-wide ALU configuration */
 213         int padding;
 214         int control;
 215         bool has_embedded_constants;
 216         midgard_constants constants;
 217         bool has_blend_constant;
 218         bool last_writeout;
 219 } midgard_bundle;
 220
 221 enum midgard_rt_id {
 222         MIDGARD_COLOR_RT0,
 223         MIDGARD_COLOR_RT1,
 224         MIDGARD_COLOR_RT2,
 225         MIDGARD_COLOR_RT3,
 226         MIDGARD_ZS_RT,
 227         MIDGARD_NUM_RTS,
 228 };
 229
 230 typedef struct compiler_context {
 231         nir_shader *nir;
 232         gl_shader_stage stage;
 233
 234         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 235         bool is_blend;
 236
 237         /* Render target number for a keyed blend shader. Depends on is_blend */
 238         unsigned blend_rt;
 239
 240         /* Tracking for blend constant patching */
 241         int blend_constant_offset;
 242
 243         /* Number of bytes used for Thread Local Storage */
 244         unsigned tls_size;
 245
 246         /* Count of spills and fills for shaderdb */
 247         unsigned spills;
 248         unsigned fills;
 249
 250         /* Current NIR function */
 251         nir_function *func;
 252
 253         /* Allocated compiler temporary counter */
 254         unsigned temp_alloc;
 255
 256         /* Unordered list of midgard_blocks */
 257         int block_count;
 258         struct list_head blocks;
 259
 260         /* TODO merge with block_count? */
 261         unsigned block_source_count;
 262
 263         /* List of midgard_instructions emitted for the current block */
 264         midgard_block *current_block;
 265
 266         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 267         midgard_block *after_block;
 268
 269         /* The current "depth" of the loop, for disambiguating breaks/continues
 270          * when using nested loops */
 271         int current_loop_depth;
 272
 273         /* Total number of loops for shader-db */
 274         unsigned loop_count;
 275
 276         /* Constants which have been loaded, for later inlining */
 277         struct hash_table_u64 *ssa_constants;
 278
 279         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 280         struct hash_table_u64 *hash_to_temp;
 281         int temp_count;
 282         int max_hash;
 283
 284         /* Set of NIR indices that were already emitted as outmods */
 285         BITSET_WORD *already_emitted;
 286
 287         /* Just the count of the max register used. Higher count => higher
 288          * register pressure */
 289         int work_registers;
 290
 291         /* The number of uniforms allowable for the fast path */
 292         int uniform_cutoff;
 293
 294         /* Count of instructions emitted from NIR overall, across all blocks */
 295         int instruction_count;
 296
 297         /* Alpha ref value passed in */
 298         float alpha_ref;
 299
 300         unsigned quadword_count;
 301
 302         /* Bitmask of valid metadata */
 303         unsigned metadata;
 304
 305         /* Model-specific quirk set */
 306         uint32_t quirks;
 307
 308         /* Writeout instructions for each render target */
 309         midgard_instruction *writeout_branch[MIDGARD_NUM_RTS];
 310
 311         struct panfrost_sysvals sysvals;
 312 } compiler_context;
 313
 314 /* Per-block live_in/live_out */
 315 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 316
 317 /* Helpers for manipulating the above structures (forming the driver IR) */
 318
 319 /* Append instruction to end of current block */
 320
 321 static inline midgard_instruction *
 322 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 323 {
 324         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 325         memcpy(heap, &ins, sizeof(ins));
 326         return heap;
 327 }
 328
 329 static inline midgard_instruction *
 330 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 331 {
 332         midgard_instruction *u = mir_upload_ins(ctx, ins);
 333         list_addtail(&u->link, &ctx->current_block->base.instructions);
 334         return u;
 335 }
 336
 337 static inline struct midgard_instruction *
 338 mir_insert_instruction_before(struct compiler_context *ctx,
 339                               struct midgard_instruction *tag,
 340                               struct midgard_instruction ins)
 341 {
 342         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 343         list_addtail(&u->link, &tag->link);
 344         return u;
 345 }
 346
 347 static inline void
 348 mir_remove_instruction(struct midgard_instruction *ins)
 349 {
 350         list_del(&ins->link);
 351 }
 352
 353 static inline midgard_instruction*
 354 mir_prev_op(struct midgard_instruction *ins)
 355 {
 356         return list_last_entry(&(ins->link), midgard_instruction, link);
 357 }
 358
 359 static inline midgard_instruction*
 360 mir_next_op(struct midgard_instruction *ins)
 361 {
 362         return list_first_entry(&(ins->link), midgard_instruction, link);
 363 }
 364
 365 #define mir_foreach_block(ctx, v) \
 366         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 367
 368 #define mir_foreach_block_from(ctx, from, v) \
 369         list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
 370
 371 #define mir_foreach_instr_in_block(block, v) \
 372         list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
 373 #define mir_foreach_instr_in_block_rev(block, v) \
 374         list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
 375
 376 #define mir_foreach_instr_in_block_safe(block, v) \
 377         list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
 378
 379 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 380         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
 381
 382 #define mir_foreach_instr_in_block_from(block, v, from) \
 383         list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
 384
 385 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 386         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
 387
 388 #define mir_foreach_bundle_in_block(block, v) \
 389         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 390
 391 #define mir_foreach_bundle_in_block_rev(block, v) \
 392         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 393
 394 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 395         midgard_instruction* v; \
 396         signed i = 0; \
 397         mir_foreach_bundle_in_block_rev(block, _bundle) \
 398                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 399                                 i >= 0; \
 400                                 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
 401
 402 #define mir_foreach_instr_global(ctx, v) \
 403         mir_foreach_block(ctx, v_block) \
 404                 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
 405
 406 #define mir_foreach_instr_global_safe(ctx, v) \
 407         mir_foreach_block(ctx, v_block) \
 408                 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
 409
 410 /* Based on set_foreach, expanded with automatic type casts */
 411
 412 #define mir_foreach_predecessor(blk, v) \
 413         struct set_entry *_entry_##v; \
 414         struct midgard_block *v; \
 415         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 416                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 417                 _entry_##v != NULL; \
 418                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 419                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 420
 421 #define mir_foreach_src(ins, v) \
 422         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 423
 424 static inline midgard_instruction *
 425 mir_last_in_block(struct midgard_block *block)
 426 {
 427         return list_last_entry(&block->base.instructions, struct midgard_instruction, link);
 428 }
 429
 430 static inline midgard_block *
 431 mir_get_block(compiler_context *ctx, int idx)
 432 {
 433         struct list_head *lst = &ctx->blocks;
 434
 435         while ((idx--) + 1)
 436                 lst = lst->next;
 437
 438         return (struct midgard_block *) lst;
 439 }
 440
 441 static inline bool
 442 mir_is_alu_bundle(midgard_bundle *bundle)
 443 {
 444         return IS_ALU(bundle->tag);
 445 }
 446
 447 static inline unsigned
 448 make_compiler_temp(compiler_context *ctx)
 449 {
 450         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 451 }
 452
 453 static inline unsigned
 454 make_compiler_temp_reg(compiler_context *ctx)
 455 {
 456         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
 457 }
 458
 459 static inline unsigned
 460 nir_ssa_index(nir_ssa_def *ssa)
 461 {
 462         return (ssa->index << 1) | 0;
 463 }
 464
 465 static inline unsigned
 466 nir_src_index(compiler_context *ctx, nir_src *src)
 467 {
 468         if (src->is_ssa)
 469                 return nir_ssa_index(src->ssa);
 470         else {
 471                 assert(!src->reg.indirect);
 472                 return (src->reg.reg->index << 1) | PAN_IS_REG;
 473         }
 474 }
 475
 476 static inline unsigned
 477 nir_dest_index(nir_dest *dst)
 478 {
 479         if (dst->is_ssa)
 480                 return (dst->ssa.index << 1) | 0;
 481         else {
 482                 assert(!dst->reg.indirect);
 483                 return (dst->reg.reg->index << 1) | PAN_IS_REG;
 484         }
 485 }
 486
 487
 488
 489 /* MIR manipulation */
 490
 491 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 492 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 493 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 494 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 495 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 496 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 497 bool mir_single_use(compiler_context *ctx, unsigned value);
 498 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 499 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 500 uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i);
 501 uint16_t mir_from_bytemask(uint16_t bytemask, unsigned bits);
 502 uint16_t mir_bytemask(midgard_instruction *ins);
 503 uint16_t mir_round_bytemask_up(uint16_t mask, unsigned bits);
 504 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 505 signed mir_upper_override(midgard_instruction *ins, unsigned inst_size);
 506 unsigned mir_components_for_type(nir_alu_type T);
 507
 508 /* MIR printing */
 509
 510 void mir_print_instruction(midgard_instruction *ins);
 511 void mir_print_bundle(midgard_bundle *ctx);
 512 void mir_print_block(midgard_block *block);
 513 void mir_print_shader(compiler_context *ctx);
 514 bool mir_nontrivial_mod(midgard_instruction *ins, unsigned i, bool check_swizzle);
 515 bool mir_nontrivial_outmod(midgard_instruction *ins);
 516
 517 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 518 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 519 void mir_flip(midgard_instruction *ins);
 520 void mir_compute_temp_count(compiler_context *ctx);
 521
 522 void mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, bool is_shared);
 523
 524 /* 'Intrinsic' move for aliasing */
 525
 526 static inline midgard_instruction
 527 v_mov(unsigned src, unsigned dest)
 528 {
 529         midgard_instruction ins = {
 530                 .type = TAG_ALU_4,
 531                 .mask = 0xF,
 532                 .src = { ~0, src, ~0, ~0 },
 533                 .src_types = { 0, nir_type_uint32 },
 534                 .swizzle = SWIZZLE_IDENTITY,
 535                 .dest = dest,
 536                 .dest_type = nir_type_uint32,
 537                 .alu = {
 538                         .op = midgard_alu_op_imov,
 539                         .reg_mode = midgard_reg_mode_32,
 540                         .outmod = midgard_outmod_int_wrap
 541                 },
 542         };
 543
 544         return ins;
 545 }
 546
 547 /* Broad types of register classes so we can handle special
 548  * registers */
 549
 550 #define REG_CLASS_WORK          0
 551 #define REG_CLASS_LDST          1
 552 #define REG_CLASS_TEXR          3
 553 #define REG_CLASS_TEXW          4
 554
 555 /* Like a move, but to thread local storage! */
 556
 557 static inline midgard_instruction
 558 v_load_store_scratch(
 559                 unsigned srcdest,
 560                 unsigned index,
 561                 bool is_store,
 562                 unsigned mask)
 563 {
 564         /* We index by 32-bit vec4s */
 565         unsigned byte = (index * 4 * 4);
 566
 567         midgard_instruction ins = {
 568                 .type = TAG_LOAD_STORE_4,
 569                 .mask = mask,
 570                 .dest_type = nir_type_uint32,
 571                 .dest = ~0,
 572                 .src = { ~0, ~0, ~0, ~0 },
 573                 .swizzle = SWIZZLE_IDENTITY_4,
 574                 .load_store = {
 575                         .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
 576
 577                         /* For register spilling - to thread local storage */
 578                         .arg_1 = 0xEA,
 579                         .arg_2 = 0x1E,
 580                 },
 581
 582                 /* If we spill an unspill, RA goes into an infinite loop */
 583                 .no_spill = (1 << REG_CLASS_WORK)
 584         };
 585
 586         ins.constants.u32[0] = byte;
 587
 588         if (is_store) {
 589                 ins.src[0] = srcdest;
 590                 ins.src_types[0] = nir_type_uint32;
 591
 592                 /* Ensure we are tightly swizzled so liveness analysis is
 593                  * correct */
 594
 595                 for (unsigned i = 0; i < 4; ++i) {
 596                         if (!(mask & (1 << i)))
 597                                 ins.swizzle[0][i] = COMPONENT_X;
 598                 }
 599         } else
 600                 ins.dest = srcdest;
 601
 602         return ins;
 603 }
 604
 605 static inline bool
 606 mir_has_arg(midgard_instruction *ins, unsigned arg)
 607 {
 608         if (!ins)
 609                 return false;
 610
 611         mir_foreach_src(ins, i) {
 612                 if (ins->src[i] == arg)
 613                         return true;
 614         }
 615
 616         return false;
 617 }
 618
 619 /* Scheduling */
 620
 621 void midgard_schedule_program(compiler_context *ctx);
 622
 623 void mir_ra(compiler_context *ctx);
 624 void mir_squeeze_index(compiler_context *ctx);
 625 void mir_lower_special_reads(compiler_context *ctx);
 626 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 627 void mir_compute_liveness(compiler_context *ctx);
 628 void mir_invalidate_liveness(compiler_context *ctx);
 629 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 630
 631 void mir_create_pipeline_registers(compiler_context *ctx);
 632 void midgard_promote_uniforms(compiler_context *ctx);
 633
 634 void
 635 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 636
 637 void
 638 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 639
 640 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
 641
 642 void mir_analyze_helper_terminate(compiler_context *ctx);
 643 void mir_analyze_helper_requirements(compiler_context *ctx);
 644
 645 /* Final emission */
 646
 647 void emit_binary_bundle(
 648         compiler_context *ctx,
 649         midgard_block *block,
 650         midgard_bundle *bundle,
 651         struct util_dynarray *emission,
 652         int next_tag);
 653
 654 bool
 655 nir_undef_to_zero(nir_shader *shader);
 656 bool nir_fuse_io_16(nir_shader *shader);
 657
 658 void midgard_nir_lod_errata(nir_shader *shader);
 659
 660 /* Optimizations */
 661
 662 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 663 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 664 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 665 bool midgard_opt_dead_code_eliminate(compiler_context *ctx);
 666 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 667
 668 #endif