src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30 #include "lcra.h"
  31
  32 #include "util/hash_table.h"
  33 #include "util/u_dynarray.h"
  34 #include "util/set.h"
  35 #include "util/list.h"
  36
  37 #include "main/mtypes.h"
  38 #include "compiler/nir_types.h"
  39 #include "compiler/nir/nir.h"
  40
  41 /* Forward declare */
  42 struct midgard_block;
  43
  44 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  45  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  46  * instruction is actually a discard op. */
  47
  48 #define TARGET_GOTO 0
  49 #define TARGET_BREAK 1
  50 #define TARGET_CONTINUE 2
  51 #define TARGET_DISCARD 3
  52
  53 typedef struct midgard_branch {
  54         /* If conditional, the condition is specified in r31.w */
  55         bool conditional;
  56
  57         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  58         bool invert_conditional;
  59
  60         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  61         unsigned target_type;
  62
  63         /* The actual target */
  64         union {
  65                 int target_block;
  66                 int target_break;
  67                 int target_continue;
  68         };
  69 } midgard_branch;
  70
  71 /* Generic in-memory data type repesenting a single logical instruction, rather
  72  * than a single instruction group. This is the preferred form for code gen.
  73  * Multiple midgard_insturctions will later be combined during scheduling,
  74  * though this is not represented in this structure.  Its format bridges
  75  * the low-level binary representation with the higher level semantic meaning.
  76  *
  77  * Notably, it allows registers to be specified as block local SSA, for code
  78  * emitted before the register allocation pass.
  79  */
  80
  81 #define MIR_SRC_COUNT 3
  82 #define MIR_VEC_COMPONENTS 16
  83
  84 typedef struct midgard_instruction {
  85         /* Must be first for casting */
  86         struct list_head link;
  87
  88         unsigned type; /* ALU, load/store, texture */
  89
  90         /* Instruction arguments represented as block-local SSA
  91          * indices, rather than registers. ~0 means unused. */
  92         unsigned src[3];
  93         unsigned dest;
  94
  95         /* vec16 swizzle, unpacked, per source */
  96         unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
  97
  98         /* Special fields for an ALU instruction */
  99         midgard_reg_info registers;
 100
 101         /* I.e. (1 << alu_bit) */
 102         int unit;
 103
 104         bool has_constants;
 105         uint32_t constants[4];
 106         uint16_t inline_constant;
 107         bool has_blend_constant;
 108         bool has_inline_constant;
 109
 110         bool compact_branch;
 111         bool writeout;
 112         bool prepacked_branch;
 113
 114         /* Kind of a hack, but hint against aggressive DCE */
 115         bool dont_eliminate;
 116
 117         /* Masks in a saneish format. One bit per channel, not packed fancy.
 118          * Use this instead of the op specific ones, and switch over at emit
 119          * time */
 120
 121         uint16_t mask;
 122
 123         /* For ALU ops only: set to true to invert (bitwise NOT) the
 124          * destination of an integer-out op. Not imeplemented in hardware but
 125          * allows more optimizations */
 126
 127         bool invert;
 128
 129         /* Hint for the register allocator not to spill the destination written
 130          * from this instruction (because it is a spill/unspill node itself).
 131          * Bitmask of spilled classes */
 132
 133         unsigned no_spill;
 134
 135         /* Generic hint for intra-pass use */
 136         bool hint;
 137
 138         /* During scheduling, the backwards dependency graph
 139          * (DAG). nr_dependencies is the number of unscheduled
 140          * instructions that must still be scheduled after
 141          * (before) this instruction. dependents are which
 142          * instructions need to be scheduled before (after) this
 143          * instruction. */
 144
 145         unsigned nr_dependencies;
 146         BITSET_WORD *dependents;
 147
 148         /* For load/store ops.. force 64-bit destination */
 149         bool load_64;
 150
 151         union {
 152                 midgard_load_store_word load_store;
 153                 midgard_vector_alu alu;
 154                 midgard_texture_word texture;
 155                 midgard_branch_extended branch_extended;
 156                 uint16_t br_compact;
 157
 158                 /* General branch, rather than packed br_compact. Higher level
 159                  * than the other components */
 160                 midgard_branch branch;
 161         };
 162 } midgard_instruction;
 163
 164 typedef struct midgard_block {
 165         /* Link to next block. Must be first for mir_get_block */
 166         struct list_head link;
 167
 168         /* List of midgard_instructions emitted for the current block */
 169         struct list_head instructions;
 170
 171         /* Index of the block in source order */
 172         unsigned source_id;
 173
 174         bool is_scheduled;
 175
 176         /* List of midgard_bundles emitted (after the scheduler has run) */
 177         struct util_dynarray bundles;
 178
 179         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 180         unsigned quadword_count;
 181
 182         /* Succeeding blocks. The compiler should not necessarily rely on
 183          * source-order traversal */
 184         struct midgard_block *successors[2];
 185         unsigned nr_successors;
 186
 187         struct set *predecessors;
 188
 189         /* The successors pointer form a graph, and in the case of
 190          * complex control flow, this graph has a cycles. To aid
 191          * traversal during liveness analysis, we have a visited?
 192          * boolean for passes to use as they see fit, provided they
 193          * clean up later */
 194         bool visited;
 195
 196         /* In liveness analysis, these are live masks (per-component) for
 197          * indices for the block. Scalar compilers have the luxury of using
 198          * simple bit fields, but for us, liveness is a vector idea. */
 199         uint16_t *live_in;
 200         uint16_t *live_out;
 201
 202         /* Indicates this is a fixed-function fragment epilogue block */
 203         bool epilogue;
 204 } midgard_block;
 205
 206 typedef struct midgard_bundle {
 207         /* Tag for the overall bundle */
 208         int tag;
 209
 210         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 211          * sadd, vadd, smul, vlut, branch) */
 212         int instruction_count;
 213         midgard_instruction *instructions[6];
 214
 215         /* Bundle-wide ALU configuration */
 216         int padding;
 217         int control;
 218         bool has_embedded_constants;
 219         float constants[4];
 220         bool has_blend_constant;
 221 } midgard_bundle;
 222
 223 typedef struct compiler_context {
 224         nir_shader *nir;
 225         gl_shader_stage stage;
 226
 227         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 228         bool is_blend;
 229
 230         /* Render target number for a keyed blend shader. Depends on is_blend */
 231         unsigned blend_rt;
 232
 233         /* Tracking for blend constant patching */
 234         int blend_constant_offset;
 235
 236         /* Number of bytes used for Thread Local Storage */
 237         unsigned tls_size;
 238
 239         /* Count of spills and fills for shaderdb */
 240         unsigned spills;
 241         unsigned fills;
 242
 243         /* Current NIR function */
 244         nir_function *func;
 245
 246         /* Allocated compiler temporary counter */
 247         unsigned temp_alloc;
 248
 249         /* Unordered list of midgard_blocks */
 250         int block_count;
 251         struct list_head blocks;
 252
 253         /* TODO merge with block_count? */
 254         unsigned block_source_count;
 255
 256         /* List of midgard_instructions emitted for the current block */
 257         midgard_block *current_block;
 258
 259         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 260         midgard_block *after_block;
 261
 262         /* The current "depth" of the loop, for disambiguating breaks/continues
 263          * when using nested loops */
 264         int current_loop_depth;
 265
 266         /* Total number of loops for shader-db */
 267         unsigned loop_count;
 268
 269         /* Constants which have been loaded, for later inlining */
 270         struct hash_table_u64 *ssa_constants;
 271
 272         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 273         struct hash_table_u64 *hash_to_temp;
 274         int temp_count;
 275         int max_hash;
 276
 277         /* Just the count of the max register used. Higher count => higher
 278          * register pressure */
 279         int work_registers;
 280
 281         /* Used for cont/last hinting. Increase when a tex op is added.
 282          * Decrease when a tex op is removed. */
 283         int texture_op_count;
 284
 285         /* The number of uniforms allowable for the fast path */
 286         int uniform_cutoff;
 287
 288         /* Count of instructions emitted from NIR overall, across all blocks */
 289         int instruction_count;
 290
 291         /* Alpha ref value passed in */
 292         float alpha_ref;
 293
 294         unsigned quadword_count;
 295
 296         /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
 297         unsigned sysvals[MAX_SYSVAL_COUNT];
 298         unsigned sysval_count;
 299         struct hash_table_u64 *sysval_to_id;
 300
 301         /* Bitmask of valid metadata */
 302         unsigned metadata;
 303
 304         /* Model-specific quirk set */
 305         uint32_t quirks;
 306 } compiler_context;
 307
 308 /* Per-block live_in/live_out */
 309 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 310
 311 /* Helpers for manipulating the above structures (forming the driver IR) */
 312
 313 /* Append instruction to end of current block */
 314
 315 static inline midgard_instruction *
 316 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 317 {
 318         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 319         memcpy(heap, &ins, sizeof(ins));
 320         return heap;
 321 }
 322
 323 static inline midgard_instruction *
 324 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 325 {
 326         midgard_instruction *u = mir_upload_ins(ctx, ins);
 327         list_addtail(&u->link, &ctx->current_block->instructions);
 328         return u;
 329 }
 330
 331 static inline struct midgard_instruction *
 332 mir_insert_instruction_before(struct compiler_context *ctx,
 333                               struct midgard_instruction *tag,
 334                               struct midgard_instruction ins)
 335 {
 336         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 337         list_addtail(&u->link, &tag->link);
 338         return u;
 339 }
 340
 341 static inline void
 342 mir_remove_instruction(struct midgard_instruction *ins)
 343 {
 344         list_del(&ins->link);
 345 }
 346
 347 static inline midgard_instruction*
 348 mir_prev_op(struct midgard_instruction *ins)
 349 {
 350         return list_last_entry(&(ins->link), midgard_instruction, link);
 351 }
 352
 353 static inline midgard_instruction*
 354 mir_next_op(struct midgard_instruction *ins)
 355 {
 356         return list_first_entry(&(ins->link), midgard_instruction, link);
 357 }
 358
 359 #define mir_foreach_block(ctx, v) \
 360         list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
 361
 362 #define mir_foreach_block_from(ctx, from, v) \
 363         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 364
 365 #define mir_foreach_instr(ctx, v) \
 366         list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 367
 368 #define mir_foreach_instr_safe(ctx, v) \
 369         list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 370
 371 #define mir_foreach_instr_in_block(block, v) \
 372         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 373 #define mir_foreach_instr_in_block_rev(block, v) \
 374         list_for_each_entry_rev(struct midgard_instruction, v, &block->instructions, link)
 375
 376 #define mir_foreach_instr_in_block_safe(block, v) \
 377         list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
 378
 379 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 380         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
 381
 382 #define mir_foreach_instr_in_block_from(block, v, from) \
 383         list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
 384
 385 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 386         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
 387
 388 #define mir_foreach_bundle_in_block(block, v) \
 389         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 390
 391 #define mir_foreach_bundle_in_block_rev(block, v) \
 392         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 393
 394 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 395         midgard_instruction* v; \
 396         signed i = 0; \
 397         mir_foreach_bundle_in_block_rev(block, _bundle) \
 398                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 399                                 i >= 0; \
 400                                 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
 401
 402 #define mir_foreach_instr_global(ctx, v) \
 403         mir_foreach_block(ctx, v_block) \
 404                 mir_foreach_instr_in_block(v_block, v)
 405
 406 #define mir_foreach_instr_global_safe(ctx, v) \
 407         mir_foreach_block(ctx, v_block) \
 408                 mir_foreach_instr_in_block_safe(v_block, v)
 409
 410 #define mir_foreach_successor(blk, v) \
 411         struct midgard_block *v; \
 412         struct midgard_block **_v; \
 413         for (_v = &blk->successors[0], \
 414                 v = *_v; \
 415                 v != NULL && _v < &blk->successors[2]; \
 416                 _v++, v = *_v) \
 417
 418 /* Based on set_foreach, expanded with automatic type casts */
 419
 420 #define mir_foreach_predecessor(blk, v) \
 421         struct set_entry *_entry_##v; \
 422         struct midgard_block *v; \
 423         for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
 424                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 425                 _entry_##v != NULL; \
 426                 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
 427                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 428
 429 #define mir_foreach_src(ins, v) \
 430         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 431
 432 static inline midgard_instruction *
 433 mir_last_in_block(struct midgard_block *block)
 434 {
 435         return list_last_entry(&block->instructions, struct midgard_instruction, link);
 436 }
 437
 438 static inline midgard_block *
 439 mir_get_block(compiler_context *ctx, int idx)
 440 {
 441         struct list_head *lst = &ctx->blocks;
 442
 443         while ((idx--) + 1)
 444                 lst = lst->next;
 445
 446         return (struct midgard_block *) lst;
 447 }
 448
 449 static inline midgard_block *
 450 mir_exit_block(struct compiler_context *ctx)
 451 {
 452         midgard_block *last = list_last_entry(&ctx->blocks,
 453                         struct midgard_block, link);
 454
 455         /* The last block must be empty logically but contains branch writeout
 456          * for fragment shaders */
 457
 458         assert(last->nr_successors == 0);
 459
 460         return last;
 461 }
 462
 463 static inline bool
 464 mir_is_alu_bundle(midgard_bundle *bundle)
 465 {
 466         return IS_ALU(bundle->tag);
 467 }
 468
 469 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
 470
 471 #define IS_REG (1)
 472
 473 static inline unsigned
 474 make_compiler_temp(compiler_context *ctx)
 475 {
 476         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 477 }
 478
 479 static inline unsigned
 480 make_compiler_temp_reg(compiler_context *ctx)
 481 {
 482         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
 483 }
 484
 485 static inline unsigned
 486 nir_src_index(compiler_context *ctx, nir_src *src)
 487 {
 488         if (src->is_ssa)
 489                 return (src->ssa->index << 1) | 0;
 490         else {
 491                 assert(!src->reg.indirect);
 492                 return (src->reg.reg->index << 1) | IS_REG;
 493         }
 494 }
 495
 496 static inline unsigned
 497 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
 498 {
 499         return nir_src_index(ctx, &src->src);
 500 }
 501
 502 static inline unsigned
 503 nir_dest_index(compiler_context *ctx, nir_dest *dst)
 504 {
 505         if (dst->is_ssa)
 506                 return (dst->ssa.index << 1) | 0;
 507         else {
 508                 assert(!dst->reg.indirect);
 509                 return (dst->reg.reg->index << 1) | IS_REG;
 510         }
 511 }
 512
 513
 514
 515 /* MIR manipulation */
 516
 517 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 518 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 519 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 520 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 521 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 522 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 523 bool mir_single_use(compiler_context *ctx, unsigned value);
 524 bool mir_special_index(compiler_context *ctx, unsigned idx);
 525 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 526 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 527 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 528 midgard_reg_mode mir_typesize(midgard_instruction *ins);
 529 midgard_reg_mode mir_srcsize(midgard_instruction *ins, unsigned i);
 530 unsigned mir_bytes_for_mode(midgard_reg_mode mode);
 531 midgard_reg_mode mir_mode_for_destsize(unsigned size);
 532 uint16_t mir_from_bytemask(uint16_t bytemask, midgard_reg_mode mode);
 533 uint16_t mir_to_bytemask(midgard_reg_mode mode, unsigned mask);
 534 uint16_t mir_bytemask(midgard_instruction *ins);
 535 uint16_t mir_round_bytemask_down(uint16_t mask, midgard_reg_mode mode);
 536 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 537
 538 /* MIR printing */
 539
 540 void mir_print_instruction(midgard_instruction *ins);
 541 void mir_print_bundle(midgard_bundle *ctx);
 542 void mir_print_block(midgard_block *block);
 543 void mir_print_shader(compiler_context *ctx);
 544 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 545 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 546 bool mir_nontrivial_outmod(midgard_instruction *ins);
 547
 548 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 549 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 550 void mir_flip(midgard_instruction *ins);
 551 void mir_compute_temp_count(compiler_context *ctx);
 552
 553 /* 'Intrinsic' move for aliasing */
 554
 555 static inline midgard_instruction
 556 v_mov(unsigned src, unsigned dest)
 557 {
 558         midgard_instruction ins = {
 559                 .type = TAG_ALU_4,
 560                 .mask = 0xF,
 561                 .src = { SSA_UNUSED, src, SSA_UNUSED },
 562                 .swizzle = SWIZZLE_IDENTITY,
 563                 .dest = dest,
 564                 .alu = {
 565                         .op = midgard_alu_op_imov,
 566                         .reg_mode = midgard_reg_mode_32,
 567                         .dest_override = midgard_dest_override_none,
 568                         .outmod = midgard_outmod_int_wrap
 569                 },
 570         };
 571
 572         return ins;
 573 }
 574
 575 /* Broad types of register classes so we can handle special
 576  * registers */
 577
 578 #define REG_CLASS_WORK          0
 579 #define REG_CLASS_LDST          1
 580 #define REG_CLASS_TEXR          3
 581 #define REG_CLASS_TEXW          4
 582
 583 /* Like a move, but to thread local storage! */
 584
 585 static inline midgard_instruction
 586 v_load_store_scratch(
 587                 unsigned srcdest,
 588                 unsigned index,
 589                 bool is_store,
 590                 unsigned mask)
 591 {
 592         /* We index by 32-bit vec4s */
 593         unsigned byte = (index * 4 * 4);
 594
 595         midgard_instruction ins = {
 596                 .type = TAG_LOAD_STORE_4,
 597                 .mask = mask,
 598                 .dest = ~0,
 599                 .src = { ~0, ~0, ~0 },
 600                 .swizzle = SWIZZLE_IDENTITY_4,
 601                 .load_store = {
 602                         .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
 603
 604                         /* For register spilling - to thread local storage */
 605                         .arg_1 = 0xEA,
 606                         .arg_2 = 0x1E,
 607                 },
 608
 609                 /* If we spill an unspill, RA goes into an infinite loop */
 610                 .no_spill = (1 << REG_CLASS_WORK)
 611         };
 612
 613         ins.constants[0] = byte;
 614
 615         if (is_store) {
 616                 ins.src[0] = srcdest;
 617
 618                 /* Ensure we are tightly swizzled so liveness analysis is
 619                  * correct */
 620
 621                 for (unsigned i = 0; i < 4; ++i) {
 622                         if (!(mask & (1 << i)))
 623                                 ins.swizzle[0][i] = COMPONENT_X;
 624                 }
 625         } else
 626                 ins.dest = srcdest;
 627
 628         return ins;
 629 }
 630
 631 static inline bool
 632 mir_has_arg(midgard_instruction *ins, unsigned arg)
 633 {
 634         if (!ins)
 635                 return false;
 636
 637         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
 638                 if (ins->src[i] == arg)
 639                         return true;
 640         }
 641
 642         return false;
 643 }
 644
 645 /* Scheduling */
 646
 647 void schedule_program(compiler_context *ctx);
 648
 649 void mir_ra(compiler_context *ctx);
 650 void mir_squeeze_index(compiler_context *ctx);
 651 void mir_lower_special_reads(compiler_context *ctx);
 652 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 653 void mir_compute_liveness(compiler_context *ctx);
 654 void mir_invalidate_liveness(compiler_context *ctx);
 655 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 656
 657 void mir_create_pipeline_registers(compiler_context *ctx);
 658
 659 void
 660 midgard_promote_uniforms(compiler_context *ctx, unsigned promoted_count);
 661
 662 midgard_instruction *
 663 emit_ubo_read(
 664         compiler_context *ctx,
 665         nir_instr *instr,
 666         unsigned dest,
 667         unsigned offset,
 668         nir_src *indirect_offset,
 669         unsigned index);
 670
 671 void
 672 emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override, unsigned nr_components);
 673
 674 void
 675 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 676
 677 void
 678 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 679
 680 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
 681
 682 /* Final emission */
 683
 684 void emit_binary_bundle(
 685         compiler_context *ctx,
 686         midgard_bundle *bundle,
 687         struct util_dynarray *emission,
 688         int next_tag);
 689
 690 bool
 691 nir_undef_to_zero(nir_shader *shader);
 692
 693 void midgard_nir_lod_errata(nir_shader *shader);
 694
 695 /* Optimizations */
 696
 697 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 698 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 699 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 700 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 701 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 702
 703 void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
 704 bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
 705 bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
 706 bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
 707 bool midgard_opt_csel_invert(compiler_context *ctx, midgard_block *block);
 708 bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
 709
 710 #endif