src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30 #include "midgard_ops.h"
  31
  32 #include "util/hash_table.h"
  33 #include "util/u_dynarray.h"
  34 #include "util/set.h"
  35 #include "util/list.h"
  36
  37 #include "main/mtypes.h"
  38 #include "compiler/nir_types.h"
  39 #include "compiler/nir/nir.h"
  40 #include "panfrost/util/pan_ir.h"
  41 #include "panfrost/util/lcra.h"
  42
  43 /* Forward declare */
  44 struct midgard_block;
  45
  46 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  47  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  48  * instruction is actually a discard op. */
  49
  50 #define TARGET_GOTO 0
  51 #define TARGET_BREAK 1
  52 #define TARGET_CONTINUE 2
  53 #define TARGET_DISCARD 3
  54 #define TARGET_TILEBUF_WAIT 4
  55
  56 typedef struct midgard_branch {
  57         /* If conditional, the condition is specified in r31.w */
  58         bool conditional;
  59
  60         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  61         bool invert_conditional;
  62
  63         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  64         unsigned target_type;
  65
  66         /* The actual target */
  67         union {
  68                 int target_block;
  69                 int target_break;
  70                 int target_continue;
  71         };
  72 } midgard_branch;
  73
  74 #define PAN_WRITEOUT_C 1
  75 #define PAN_WRITEOUT_Z 2
  76 #define PAN_WRITEOUT_S 4
  77
  78 /* Generic in-memory data type repesenting a single logical instruction, rather
  79  * than a single instruction group. This is the preferred form for code gen.
  80  * Multiple midgard_insturctions will later be combined during scheduling,
  81  * though this is not represented in this structure.  Its format bridges
  82  * the low-level binary representation with the higher level semantic meaning.
  83  *
  84  * Notably, it allows registers to be specified as block local SSA, for code
  85  * emitted before the register allocation pass.
  86  */
  87
  88 #define MIR_SRC_COUNT 4
  89 #define MIR_VEC_COMPONENTS 16
  90
  91 typedef struct midgard_instruction {
  92         /* Must be first for casting */
  93         struct list_head link;
  94
  95         unsigned type; /* ALU, load/store, texture */
  96
  97         /* Instruction arguments represented as block-local SSA
  98          * indices, rather than registers. ~0 means unused. */
  99         unsigned src[MIR_SRC_COUNT];
 100         unsigned dest;
 101
 102         /* vec16 swizzle, unpacked, per source */
 103         unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
 104
 105         /* Types! */
 106         nir_alu_type src_types[MIR_SRC_COUNT];
 107         nir_alu_type dest_type;
 108
 109         /* Packing ops have non-32-bit dest types even though they functionally
 110          * work at the 32-bit level, use this as a signal to disable copyprop.
 111          * We maybe need synthetic pack ops instead. */
 112         bool is_pack;
 113
 114         /* Modifiers, depending on type */
 115         union {
 116                 struct {
 117                         bool src_abs[MIR_SRC_COUNT];
 118                         bool src_neg[MIR_SRC_COUNT];
 119                 };
 120
 121                 struct {
 122                         bool src_shift[MIR_SRC_COUNT];
 123                 };
 124         };
 125
 126         /* Out of the union for csel (could maybe be fixed..) */
 127         bool src_invert[MIR_SRC_COUNT];
 128
 129         /* If the op supports it */
 130         enum midgard_roundmode roundmode;
 131
 132         /* For textures: should helpers execute this instruction (instead of
 133          * just helping with derivatives)? Should helpers terminate after? */
 134         bool helper_terminate;
 135         bool helper_execute;
 136
 137         /* I.e. (1 << alu_bit) */
 138         int unit;
 139
 140         bool has_constants;
 141         midgard_constants constants;
 142         uint16_t inline_constant;
 143         bool has_blend_constant;
 144         bool has_inline_constant;
 145
 146         bool compact_branch;
 147         uint8_t writeout;
 148         bool last_writeout;
 149
 150         /* Masks in a saneish format. One bit per channel, not packed fancy.
 151          * Use this instead of the op specific ones, and switch over at emit
 152          * time */
 153
 154         uint16_t mask;
 155
 156         /* Hint for the register allocator not to spill the destination written
 157          * from this instruction (because it is a spill/unspill node itself).
 158          * Bitmask of spilled classes */
 159
 160         unsigned no_spill;
 161
 162         /* Generic hint for intra-pass use */
 163         bool hint;
 164
 165         /* During scheduling, the backwards dependency graph
 166          * (DAG). nr_dependencies is the number of unscheduled
 167          * instructions that must still be scheduled after
 168          * (before) this instruction. dependents are which
 169          * instructions need to be scheduled before (after) this
 170          * instruction. */
 171
 172         unsigned nr_dependencies;
 173         BITSET_WORD *dependents;
 174
 175         /* Use this in conjunction with `type` */
 176         unsigned op;
 177
 178         /* This refers to midgard_outmod_float or midgard_outmod_int.
 179          * In case of a ALU op, use midgard_is_integer_out_op() to know which
 180          * one is used.
 181          * If it's a texture op, it's always midgard_outmod_float. */
 182         unsigned outmod;
 183
 184         union {
 185                 midgard_load_store_word load_store;
 186                 midgard_texture_word texture;
 187
 188                 midgard_branch branch;
 189         };
 190 } midgard_instruction;
 191
 192 typedef struct midgard_block {
 193         pan_block base;
 194
 195         bool scheduled;
 196
 197         /* List of midgard_bundles emitted (after the scheduler has run) */
 198         struct util_dynarray bundles;
 199
 200         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 201         unsigned quadword_count;
 202
 203         /* Indicates this is a fixed-function fragment epilogue block */
 204         bool epilogue;
 205
 206         /* Are helper invocations required by this block? */
 207         bool helpers_in;
 208 } midgard_block;
 209
 210 typedef struct midgard_bundle {
 211         /* Tag for the overall bundle */
 212         int tag;
 213
 214         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 215          * sadd, vadd, smul, vlut, branch) */
 216         int instruction_count;
 217         midgard_instruction *instructions[6];
 218
 219         /* Bundle-wide ALU configuration */
 220         int padding;
 221         int control;
 222         bool has_embedded_constants;
 223         midgard_constants constants;
 224         bool has_blend_constant;
 225         bool last_writeout;
 226 } midgard_bundle;
 227
 228 enum midgard_rt_id {
 229         MIDGARD_COLOR_RT0 = 0,
 230         MIDGARD_COLOR_RT1,
 231         MIDGARD_COLOR_RT2,
 232         MIDGARD_COLOR_RT3,
 233         MIDGARD_COLOR_RT4,
 234         MIDGARD_COLOR_RT5,
 235         MIDGARD_COLOR_RT6,
 236         MIDGARD_COLOR_RT7,
 237         MIDGARD_ZS_RT,
 238         MIDGARD_NUM_RTS,
 239 };
 240
 241 typedef struct compiler_context {
 242         nir_shader *nir;
 243         gl_shader_stage stage;
 244
 245         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 246         bool is_blend;
 247
 248         /* Render target number for a keyed blend shader. Depends on is_blend */
 249         unsigned blend_rt;
 250
 251         /* Index to precolour to r0 for an input blend colour */
 252         unsigned blend_input;
 253
 254         /* Index to precolour to r2 for a dual-source blend colour */
 255         unsigned blend_src1;
 256
 257         /* Tracking for blend constant patching */
 258         int blend_constant_offset;
 259
 260         /* Number of bytes used for Thread Local Storage */
 261         unsigned tls_size;
 262
 263         /* Count of spills and fills for shaderdb */
 264         unsigned spills;
 265         unsigned fills;
 266
 267         /* Current NIR function */
 268         nir_function *func;
 269
 270         /* Allocated compiler temporary counter */
 271         unsigned temp_alloc;
 272
 273         /* Unordered list of midgard_blocks */
 274         int block_count;
 275         struct list_head blocks;
 276
 277         /* TODO merge with block_count? */
 278         unsigned block_source_count;
 279
 280         /* List of midgard_instructions emitted for the current block */
 281         midgard_block *current_block;
 282
 283         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 284         midgard_block *after_block;
 285
 286         /* The current "depth" of the loop, for disambiguating breaks/continues
 287          * when using nested loops */
 288         int current_loop_depth;
 289
 290         /* Total number of loops for shader-db */
 291         unsigned loop_count;
 292
 293         /* Constants which have been loaded, for later inlining */
 294         struct hash_table_u64 *ssa_constants;
 295
 296         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 297         struct hash_table_u64 *hash_to_temp;
 298         int temp_count;
 299         int max_hash;
 300
 301         /* Set of NIR indices that were already emitted as outmods */
 302         BITSET_WORD *already_emitted;
 303
 304         /* Just the count of the max register used. Higher count => higher
 305          * register pressure */
 306         int work_registers;
 307
 308         /* The number of uniforms allowable for the fast path */
 309         int uniform_cutoff;
 310
 311         /* Count of instructions emitted from NIR overall, across all blocks */
 312         int instruction_count;
 313
 314         /* Alpha ref value passed in */
 315         float alpha_ref;
 316
 317         unsigned quadword_count;
 318
 319         /* Bitmask of valid metadata */
 320         unsigned metadata;
 321
 322         /* Model-specific quirk set */
 323         uint32_t quirks;
 324
 325         /* Writeout instructions for each render target */
 326         midgard_instruction *writeout_branch[MIDGARD_NUM_RTS];
 327
 328         struct panfrost_sysvals sysvals;
 329 } compiler_context;
 330
 331 /* Per-block live_in/live_out */
 332 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 333
 334 /* Helpers for manipulating the above structures (forming the driver IR) */
 335
 336 /* Append instruction to end of current block */
 337
 338 static inline midgard_instruction *
 339 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 340 {
 341         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 342         memcpy(heap, &ins, sizeof(ins));
 343         return heap;
 344 }
 345
 346 static inline midgard_instruction *
 347 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 348 {
 349         midgard_instruction *u = mir_upload_ins(ctx, ins);
 350         list_addtail(&u->link, &ctx->current_block->base.instructions);
 351         return u;
 352 }
 353
 354 static inline struct midgard_instruction *
 355 mir_insert_instruction_before(struct compiler_context *ctx,
 356                               struct midgard_instruction *tag,
 357                               struct midgard_instruction ins)
 358 {
 359         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 360         list_addtail(&u->link, &tag->link);
 361         return u;
 362 }
 363
 364 static inline void
 365 mir_remove_instruction(struct midgard_instruction *ins)
 366 {
 367         list_del(&ins->link);
 368 }
 369
 370 static inline midgard_instruction*
 371 mir_prev_op(struct midgard_instruction *ins)
 372 {
 373         return list_last_entry(&(ins->link), midgard_instruction, link);
 374 }
 375
 376 static inline midgard_instruction*
 377 mir_next_op(struct midgard_instruction *ins)
 378 {
 379         return list_first_entry(&(ins->link), midgard_instruction, link);
 380 }
 381
 382 #define mir_foreach_block(ctx, v) \
 383         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 384
 385 #define mir_foreach_block_from(ctx, from, v) \
 386         list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
 387
 388 #define mir_foreach_instr_in_block(block, v) \
 389         list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
 390 #define mir_foreach_instr_in_block_rev(block, v) \
 391         list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
 392
 393 #define mir_foreach_instr_in_block_safe(block, v) \
 394         list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
 395
 396 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 397         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
 398
 399 #define mir_foreach_instr_in_block_from(block, v, from) \
 400         list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
 401
 402 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 403         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
 404
 405 #define mir_foreach_bundle_in_block(block, v) \
 406         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 407
 408 #define mir_foreach_bundle_in_block_rev(block, v) \
 409         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 410
 411 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 412         midgard_instruction* v; \
 413         signed i = 0; \
 414         mir_foreach_bundle_in_block_rev(block, _bundle) \
 415                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 416                                 i >= 0; \
 417                                 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
 418
 419 #define mir_foreach_instr_global(ctx, v) \
 420         mir_foreach_block(ctx, v_block) \
 421                 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
 422
 423 #define mir_foreach_instr_global_safe(ctx, v) \
 424         mir_foreach_block(ctx, v_block) \
 425                 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
 426
 427 /* Based on set_foreach, expanded with automatic type casts */
 428
 429 #define mir_foreach_predecessor(blk, v) \
 430         struct set_entry *_entry_##v; \
 431         struct midgard_block *v; \
 432         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 433                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 434                 _entry_##v != NULL; \
 435                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 436                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 437
 438 #define mir_foreach_src(ins, v) \
 439         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 440
 441 static inline midgard_instruction *
 442 mir_last_in_block(struct midgard_block *block)
 443 {
 444         return list_last_entry(&block->base.instructions, struct midgard_instruction, link);
 445 }
 446
 447 static inline midgard_block *
 448 mir_get_block(compiler_context *ctx, int idx)
 449 {
 450         struct list_head *lst = &ctx->blocks;
 451
 452         while ((idx--) + 1)
 453                 lst = lst->next;
 454
 455         return (struct midgard_block *) lst;
 456 }
 457
 458 static inline bool
 459 mir_is_alu_bundle(midgard_bundle *bundle)
 460 {
 461         return IS_ALU(bundle->tag);
 462 }
 463
 464 static inline unsigned
 465 make_compiler_temp(compiler_context *ctx)
 466 {
 467         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 468 }
 469
 470 static inline unsigned
 471 make_compiler_temp_reg(compiler_context *ctx)
 472 {
 473         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
 474 }
 475
 476 static inline unsigned
 477 nir_ssa_index(nir_ssa_def *ssa)
 478 {
 479         return (ssa->index << 1) | 0;
 480 }
 481
 482 static inline unsigned
 483 nir_src_index(compiler_context *ctx, nir_src *src)
 484 {
 485         if (src->is_ssa)
 486                 return nir_ssa_index(src->ssa);
 487         else {
 488                 assert(!src->reg.indirect);
 489                 return (src->reg.reg->index << 1) | PAN_IS_REG;
 490         }
 491 }
 492
 493 static inline unsigned
 494 nir_dest_index(nir_dest *dst)
 495 {
 496         if (dst->is_ssa)
 497                 return (dst->ssa.index << 1) | 0;
 498         else {
 499                 assert(!dst->reg.indirect);
 500                 return (dst->reg.reg->index << 1) | PAN_IS_REG;
 501         }
 502 }
 503
 504
 505
 506 /* MIR manipulation */
 507
 508 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 509 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 510 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 511 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 512 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 513 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 514 bool mir_single_use(compiler_context *ctx, unsigned value);
 515 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 516 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 517 uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i);
 518 uint16_t mir_from_bytemask(uint16_t bytemask, unsigned bits);
 519 uint16_t mir_bytemask(midgard_instruction *ins);
 520 uint16_t mir_round_bytemask_up(uint16_t mask, unsigned bits);
 521 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 522 signed mir_upper_override(midgard_instruction *ins, unsigned inst_size);
 523 unsigned mir_components_for_type(nir_alu_type T);
 524 unsigned max_bitsize_for_alu(midgard_instruction *ins);
 525 midgard_reg_mode reg_mode_for_bitsize(unsigned bitsize);
 526
 527 /* MIR printing */
 528
 529 void mir_print_instruction(midgard_instruction *ins);
 530 void mir_print_bundle(midgard_bundle *ctx);
 531 void mir_print_block(midgard_block *block);
 532 void mir_print_shader(compiler_context *ctx);
 533 bool mir_nontrivial_mod(midgard_instruction *ins, unsigned i, bool check_swizzle);
 534 bool mir_nontrivial_outmod(midgard_instruction *ins);
 535
 536 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 537 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 538 void mir_flip(midgard_instruction *ins);
 539 void mir_compute_temp_count(compiler_context *ctx);
 540
 541 void mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, bool is_shared);
 542
 543 /* 'Intrinsic' move for aliasing */
 544
 545 static inline midgard_instruction
 546 v_mov(unsigned src, unsigned dest)
 547 {
 548         midgard_instruction ins = {
 549                 .type = TAG_ALU_4,
 550                 .mask = 0xF,
 551                 .src = { ~0, src, ~0, ~0 },
 552                 .src_types = { 0, nir_type_uint32 },
 553                 .swizzle = SWIZZLE_IDENTITY,
 554                 .dest = dest,
 555                 .dest_type = nir_type_uint32,
 556                 .op = midgard_alu_op_imov,
 557                 .outmod = midgard_outmod_int_wrap
 558         };
 559
 560         return ins;
 561 }
 562
 563 /* Broad types of register classes so we can handle special
 564  * registers */
 565
 566 #define REG_CLASS_WORK          0
 567 #define REG_CLASS_LDST          1
 568 #define REG_CLASS_TEXR          3
 569 #define REG_CLASS_TEXW          4
 570
 571 /* Like a move, but to thread local storage! */
 572
 573 static inline midgard_instruction
 574 v_load_store_scratch(
 575                 unsigned srcdest,
 576                 unsigned index,
 577                 bool is_store,
 578                 unsigned mask)
 579 {
 580         /* We index by 32-bit vec4s */
 581         unsigned byte = (index * 4 * 4);
 582
 583         midgard_instruction ins = {
 584                 .type = TAG_LOAD_STORE_4,
 585                 .mask = mask,
 586                 .dest_type = nir_type_uint32,
 587                 .dest = ~0,
 588                 .src = { ~0, ~0, ~0, ~0 },
 589                 .swizzle = SWIZZLE_IDENTITY_4,
 590                 .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
 591                 .load_store = {
 592                         /* For register spilling - to thread local storage */
 593                         .arg_1 = 0xEA,
 594                         .arg_2 = 0x1E,
 595                 },
 596
 597                 /* If we spill an unspill, RA goes into an infinite loop */
 598                 .no_spill = (1 << REG_CLASS_WORK)
 599         };
 600
 601         ins.constants.u32[0] = byte;
 602
 603         if (is_store) {
 604                 ins.src[0] = srcdest;
 605                 ins.src_types[0] = nir_type_uint32;
 606
 607                 /* Ensure we are tightly swizzled so liveness analysis is
 608                  * correct */
 609
 610                 for (unsigned i = 0; i < 4; ++i) {
 611                         if (!(mask & (1 << i)))
 612                                 ins.swizzle[0][i] = COMPONENT_X;
 613                 }
 614         } else
 615                 ins.dest = srcdest;
 616
 617         return ins;
 618 }
 619
 620 static inline bool
 621 mir_has_arg(midgard_instruction *ins, unsigned arg)
 622 {
 623         if (!ins)
 624                 return false;
 625
 626         mir_foreach_src(ins, i) {
 627                 if (ins->src[i] == arg)
 628                         return true;
 629         }
 630
 631         return false;
 632 }
 633
 634 /* Scheduling */
 635
 636 void midgard_schedule_program(compiler_context *ctx);
 637
 638 void mir_ra(compiler_context *ctx);
 639 void mir_squeeze_index(compiler_context *ctx);
 640 void mir_lower_special_reads(compiler_context *ctx);
 641 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 642 void mir_compute_liveness(compiler_context *ctx);
 643 void mir_invalidate_liveness(compiler_context *ctx);
 644 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 645
 646 void mir_create_pipeline_registers(compiler_context *ctx);
 647 void midgard_promote_uniforms(compiler_context *ctx);
 648
 649 void
 650 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 651
 652 void
 653 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 654
 655 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
 656
 657 void mir_analyze_helper_terminate(compiler_context *ctx);
 658 void mir_analyze_helper_requirements(compiler_context *ctx);
 659
 660 /* Final emission */
 661
 662 void emit_binary_bundle(
 663         compiler_context *ctx,
 664         midgard_block *block,
 665         midgard_bundle *bundle,
 666         struct util_dynarray *emission,
 667         int next_tag);
 668
 669 bool
 670 nir_undef_to_zero(nir_shader *shader);
 671 bool nir_fuse_io_16(nir_shader *shader);
 672
 673 void midgard_nir_lod_errata(nir_shader *shader);
 674
 675 unsigned midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx);
 676
 677 /* Optimizations */
 678
 679 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 680 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 681 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 682 bool midgard_opt_dead_code_eliminate(compiler_context *ctx);
 683 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 684
 685 #endif