2 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #ifndef _MDG_COMPILER_H
25 #define _MDG_COMPILER_H
29 #include "midgard_compile.h"
32 #include "util/hash_table.h"
33 #include "util/u_dynarray.h"
35 #include "util/list.h"
37 #include "main/mtypes.h"
38 #include "compiler/nir_types.h"
39 #include "compiler/nir/nir.h"
44 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
45 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
46 * instruction is actually a discard op. */
49 #define TARGET_BREAK 1
50 #define TARGET_CONTINUE 2
51 #define TARGET_DISCARD 3
53 typedef struct midgard_branch
{
54 /* If conditional, the condition is specified in r31.w */
57 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
58 bool invert_conditional
;
60 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
63 /* The actual target */
71 /* Generic in-memory data type repesenting a single logical instruction, rather
72 * than a single instruction group. This is the preferred form for code gen.
73 * Multiple midgard_insturctions will later be combined during scheduling,
74 * though this is not represented in this structure. Its format bridges
75 * the low-level binary representation with the higher level semantic meaning.
77 * Notably, it allows registers to be specified as block local SSA, for code
78 * emitted before the register allocation pass.
81 #define MIR_SRC_COUNT 4
82 #define MIR_VEC_COMPONENTS 16
84 typedef struct midgard_instruction
{
85 /* Must be first for casting */
86 struct list_head link
;
88 unsigned type
; /* ALU, load/store, texture */
90 /* Instruction arguments represented as block-local SSA
91 * indices, rather than registers. ~0 means unused. */
92 unsigned src
[MIR_SRC_COUNT
];
95 /* vec16 swizzle, unpacked, per source */
96 unsigned swizzle
[MIR_SRC_COUNT
][MIR_VEC_COMPONENTS
];
98 /* Special fields for an ALU instruction */
99 midgard_reg_info registers
;
101 /* I.e. (1 << alu_bit) */
105 uint32_t constants
[4];
106 uint16_t inline_constant
;
107 bool has_blend_constant
;
108 bool has_inline_constant
;
113 /* Kind of a hack, but hint against aggressive DCE */
116 /* Masks in a saneish format. One bit per channel, not packed fancy.
117 * Use this instead of the op specific ones, and switch over at emit
122 /* For ALU ops only: set to true to invert (bitwise NOT) the
123 * destination of an integer-out op. Not implemented in hardware but
124 * allows more optimizations */
128 /* Hint for the register allocator not to spill the destination written
129 * from this instruction (because it is a spill/unspill node itself).
130 * Bitmask of spilled classes */
134 /* Generic hint for intra-pass use */
137 /* During scheduling, the backwards dependency graph
138 * (DAG). nr_dependencies is the number of unscheduled
139 * instructions that must still be scheduled after
140 * (before) this instruction. dependents are which
141 * instructions need to be scheduled before (after) this
144 unsigned nr_dependencies
;
145 BITSET_WORD
*dependents
;
147 /* For load/store ops.. force 64-bit destination */
151 midgard_load_store_word load_store
;
152 midgard_vector_alu alu
;
153 midgard_texture_word texture
;
154 midgard_branch_extended branch_extended
;
157 /* General branch, rather than packed br_compact. Higher level
158 * than the other components */
159 midgard_branch branch
;
161 } midgard_instruction
;
163 typedef struct midgard_block
{
164 /* Link to next block. Must be first for mir_get_block */
165 struct list_head link
;
167 /* List of midgard_instructions emitted for the current block */
168 struct list_head instructions
;
170 /* Index of the block in source order */
175 /* List of midgard_bundles emitted (after the scheduler has run) */
176 struct util_dynarray bundles
;
178 /* Number of quadwords _actually_ emitted, as determined after scheduling */
179 unsigned quadword_count
;
181 /* Succeeding blocks. The compiler should not necessarily rely on
182 * source-order traversal */
183 struct midgard_block
*successors
[2];
184 unsigned nr_successors
;
186 struct set
*predecessors
;
188 /* The successors pointer form a graph, and in the case of
189 * complex control flow, this graph has a cycles. To aid
190 * traversal during liveness analysis, we have a visited?
191 * boolean for passes to use as they see fit, provided they
195 /* In liveness analysis, these are live masks (per-component) for
196 * indices for the block. Scalar compilers have the luxury of using
197 * simple bit fields, but for us, liveness is a vector idea. */
201 /* Indicates this is a fixed-function fragment epilogue block */
205 typedef struct midgard_bundle
{
206 /* Tag for the overall bundle */
209 /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
210 * sadd, vadd, smul, vlut, branch) */
211 int instruction_count
;
212 midgard_instruction
*instructions
[6];
214 /* Bundle-wide ALU configuration */
217 bool has_embedded_constants
;
219 bool has_blend_constant
;
222 typedef struct compiler_context
{
224 gl_shader_stage stage
;
226 /* Is internally a blend shader? Depends on stage == FRAGMENT */
229 /* Render target number for a keyed blend shader. Depends on is_blend */
232 /* Tracking for blend constant patching */
233 int blend_constant_offset
;
235 /* Number of bytes used for Thread Local Storage */
238 /* Count of spills and fills for shaderdb */
242 /* Current NIR function */
245 /* Allocated compiler temporary counter */
248 /* Unordered list of midgard_blocks */
250 struct list_head blocks
;
252 /* TODO merge with block_count? */
253 unsigned block_source_count
;
255 /* List of midgard_instructions emitted for the current block */
256 midgard_block
*current_block
;
258 /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
259 midgard_block
*after_block
;
261 /* The current "depth" of the loop, for disambiguating breaks/continues
262 * when using nested loops */
263 int current_loop_depth
;
265 /* Total number of loops for shader-db */
268 /* Constants which have been loaded, for later inlining */
269 struct hash_table_u64
*ssa_constants
;
271 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
272 struct hash_table_u64
*hash_to_temp
;
276 /* Just the count of the max register used. Higher count => higher
277 * register pressure */
280 /* Used for cont/last hinting. Increase when a tex op is added.
281 * Decrease when a tex op is removed. */
282 int texture_op_count
;
284 /* The number of uniforms allowable for the fast path */
287 /* Count of instructions emitted from NIR overall, across all blocks */
288 int instruction_count
;
290 /* Alpha ref value passed in */
293 unsigned quadword_count
;
295 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
296 unsigned sysvals
[MAX_SYSVAL_COUNT
];
297 unsigned sysval_count
;
298 struct hash_table_u64
*sysval_to_id
;
300 /* Bitmask of valid metadata */
303 /* Model-specific quirk set */
307 /* Per-block live_in/live_out */
308 #define MIDGARD_METADATA_LIVENESS (1 << 0)
310 /* Helpers for manipulating the above structures (forming the driver IR) */
312 /* Append instruction to end of current block */
314 static inline midgard_instruction
*
315 mir_upload_ins(struct compiler_context
*ctx
, struct midgard_instruction ins
)
317 midgard_instruction
*heap
= ralloc(ctx
, struct midgard_instruction
);
318 memcpy(heap
, &ins
, sizeof(ins
));
322 static inline midgard_instruction
*
323 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
325 midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
326 list_addtail(&u
->link
, &ctx
->current_block
->instructions
);
330 static inline struct midgard_instruction
*
331 mir_insert_instruction_before(struct compiler_context
*ctx
,
332 struct midgard_instruction
*tag
,
333 struct midgard_instruction ins
)
335 struct midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
336 list_addtail(&u
->link
, &tag
->link
);
341 mir_remove_instruction(struct midgard_instruction
*ins
)
343 list_del(&ins
->link
);
346 static inline midgard_instruction
*
347 mir_prev_op(struct midgard_instruction
*ins
)
349 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
352 static inline midgard_instruction
*
353 mir_next_op(struct midgard_instruction
*ins
)
355 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
358 #define mir_foreach_block(ctx, v) \
359 list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
361 #define mir_foreach_block_from(ctx, from, v) \
362 list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
364 #define mir_foreach_instr(ctx, v) \
365 list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
367 #define mir_foreach_instr_safe(ctx, v) \
368 list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
370 #define mir_foreach_instr_in_block(block, v) \
371 list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
372 #define mir_foreach_instr_in_block_rev(block, v) \
373 list_for_each_entry_rev(struct midgard_instruction, v, &block->instructions, link)
375 #define mir_foreach_instr_in_block_safe(block, v) \
376 list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
378 #define mir_foreach_instr_in_block_safe_rev(block, v) \
379 list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
381 #define mir_foreach_instr_in_block_from(block, v, from) \
382 list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
384 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
385 list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
387 #define mir_foreach_bundle_in_block(block, v) \
388 util_dynarray_foreach(&block->bundles, midgard_bundle, v)
390 #define mir_foreach_bundle_in_block_rev(block, v) \
391 util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
393 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
394 midgard_instruction* v; \
396 mir_foreach_bundle_in_block_rev(block, _bundle) \
397 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
399 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
401 #define mir_foreach_instr_global(ctx, v) \
402 mir_foreach_block(ctx, v_block) \
403 mir_foreach_instr_in_block(v_block, v)
405 #define mir_foreach_instr_global_safe(ctx, v) \
406 mir_foreach_block(ctx, v_block) \
407 mir_foreach_instr_in_block_safe(v_block, v)
409 #define mir_foreach_successor(blk, v) \
410 struct midgard_block *v; \
411 struct midgard_block **_v; \
412 for (_v = &blk->successors[0], \
414 v != NULL && _v < &blk->successors[2]; \
417 /* Based on set_foreach, expanded with automatic type casts */
419 #define mir_foreach_predecessor(blk, v) \
420 struct set_entry *_entry_##v; \
421 struct midgard_block *v; \
422 for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
423 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL); \
424 _entry_##v != NULL; \
425 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
426 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
428 #define mir_foreach_src(ins, v) \
429 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
431 static inline midgard_instruction
*
432 mir_last_in_block(struct midgard_block
*block
)
434 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
437 static inline midgard_block
*
438 mir_get_block(compiler_context
*ctx
, int idx
)
440 struct list_head
*lst
= &ctx
->blocks
;
445 return (struct midgard_block
*) lst
;
448 static inline midgard_block
*
449 mir_exit_block(struct compiler_context
*ctx
)
451 midgard_block
*last
= list_last_entry(&ctx
->blocks
,
452 struct midgard_block
, link
);
454 /* The last block must be empty logically but contains branch writeout
455 * for fragment shaders */
457 assert(last
->nr_successors
== 0);
463 mir_is_alu_bundle(midgard_bundle
*bundle
)
465 return IS_ALU(bundle
->tag
);
468 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
472 static inline unsigned
473 make_compiler_temp(compiler_context
*ctx
)
475 return (ctx
->func
->impl
->ssa_alloc
+ ctx
->temp_alloc
++) << 1;
478 static inline unsigned
479 make_compiler_temp_reg(compiler_context
*ctx
)
481 return ((ctx
->func
->impl
->reg_alloc
+ ctx
->temp_alloc
++) << 1) | IS_REG
;
484 static inline unsigned
485 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
488 return (src
->ssa
->index
<< 1) | 0;
490 assert(!src
->reg
.indirect
);
491 return (src
->reg
.reg
->index
<< 1) | IS_REG
;
495 static inline unsigned
496 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
498 return nir_src_index(ctx
, &src
->src
);
501 static inline unsigned
502 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
505 return (dst
->ssa
.index
<< 1) | 0;
507 assert(!dst
->reg
.indirect
);
508 return (dst
->reg
.reg
->index
<< 1) | IS_REG
;
514 /* MIR manipulation */
516 void mir_rewrite_index(compiler_context
*ctx
, unsigned old
, unsigned new);
517 void mir_rewrite_index_src(compiler_context
*ctx
, unsigned old
, unsigned new);
518 void mir_rewrite_index_dst(compiler_context
*ctx
, unsigned old
, unsigned new);
519 void mir_rewrite_index_dst_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
520 void mir_rewrite_index_src_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
521 void mir_rewrite_index_src_swizzle(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned *swizzle
);
522 bool mir_single_use(compiler_context
*ctx
, unsigned value
);
523 bool mir_special_index(compiler_context
*ctx
, unsigned idx
);
524 unsigned mir_use_count(compiler_context
*ctx
, unsigned value
);
525 bool mir_is_written_before(compiler_context
*ctx
, midgard_instruction
*ins
, unsigned node
);
526 uint16_t mir_bytemask_of_read_components(midgard_instruction
*ins
, unsigned node
);
527 midgard_reg_mode
mir_typesize(midgard_instruction
*ins
);
528 midgard_reg_mode
mir_srcsize(midgard_instruction
*ins
, unsigned i
);
529 unsigned mir_bytes_for_mode(midgard_reg_mode mode
);
530 midgard_reg_mode
mir_mode_for_destsize(unsigned size
);
531 uint16_t mir_from_bytemask(uint16_t bytemask
, midgard_reg_mode mode
);
532 uint16_t mir_to_bytemask(midgard_reg_mode mode
, unsigned mask
);
533 uint16_t mir_bytemask(midgard_instruction
*ins
);
534 uint16_t mir_round_bytemask_down(uint16_t mask
, midgard_reg_mode mode
);
535 void mir_set_bytemask(midgard_instruction
*ins
, uint16_t bytemask
);
536 unsigned mir_upper_override(midgard_instruction
*ins
);
540 void mir_print_instruction(midgard_instruction
*ins
);
541 void mir_print_bundle(midgard_bundle
*ctx
);
542 void mir_print_block(midgard_block
*block
);
543 void mir_print_shader(compiler_context
*ctx
);
544 bool mir_nontrivial_source2_mod(midgard_instruction
*ins
);
545 bool mir_nontrivial_source2_mod_simple(midgard_instruction
*ins
);
546 bool mir_nontrivial_outmod(midgard_instruction
*ins
);
548 void mir_insert_instruction_before_scheduled(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*tag
, midgard_instruction ins
);
549 void mir_insert_instruction_after_scheduled(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*tag
, midgard_instruction ins
);
550 void mir_flip(midgard_instruction
*ins
);
551 void mir_compute_temp_count(compiler_context
*ctx
);
553 /* 'Intrinsic' move for aliasing */
555 static inline midgard_instruction
556 v_mov(unsigned src
, unsigned dest
)
558 midgard_instruction ins
= {
561 .src
= { ~0, src
, ~0, ~0 },
562 .swizzle
= SWIZZLE_IDENTITY
,
565 .op
= midgard_alu_op_imov
,
566 .reg_mode
= midgard_reg_mode_32
,
567 .dest_override
= midgard_dest_override_none
,
568 .outmod
= midgard_outmod_int_wrap
575 /* Broad types of register classes so we can handle special
578 #define REG_CLASS_WORK 0
579 #define REG_CLASS_LDST 1
580 #define REG_CLASS_TEXR 3
581 #define REG_CLASS_TEXW 4
583 /* Like a move, but to thread local storage! */
585 static inline midgard_instruction
586 v_load_store_scratch(
592 /* We index by 32-bit vec4s */
593 unsigned byte
= (index
* 4 * 4);
595 midgard_instruction ins
= {
596 .type
= TAG_LOAD_STORE_4
,
599 .src
= { ~0, ~0, ~0, ~0 },
600 .swizzle
= SWIZZLE_IDENTITY_4
,
602 .op
= is_store
? midgard_op_st_int4
: midgard_op_ld_int4
,
604 /* For register spilling - to thread local storage */
609 /* If we spill an unspill, RA goes into an infinite loop */
610 .no_spill
= (1 << REG_CLASS_WORK
)
613 ins
.constants
[0] = byte
;
616 ins
.src
[0] = srcdest
;
618 /* Ensure we are tightly swizzled so liveness analysis is
621 for (unsigned i
= 0; i
< 4; ++i
) {
622 if (!(mask
& (1 << i
)))
623 ins
.swizzle
[0][i
] = COMPONENT_X
;
632 mir_has_arg(midgard_instruction
*ins
, unsigned arg
)
637 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
->src
); ++i
) {
638 if (ins
->src
[i
] == arg
)
647 void schedule_program(compiler_context
*ctx
);
649 void mir_ra(compiler_context
*ctx
);
650 void mir_squeeze_index(compiler_context
*ctx
);
651 void mir_lower_special_reads(compiler_context
*ctx
);
652 void mir_liveness_ins_update(uint16_t *live
, midgard_instruction
*ins
, unsigned max
);
653 void mir_compute_liveness(compiler_context
*ctx
);
654 void mir_invalidate_liveness(compiler_context
*ctx
);
655 bool mir_is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
);
657 void mir_create_pipeline_registers(compiler_context
*ctx
);
658 void midgard_promote_uniforms(compiler_context
*ctx
);
660 midgard_instruction
*
662 compiler_context
*ctx
,
666 nir_src
*indirect_offset
,
670 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
, signed dest_override
, unsigned nr_components
);
673 midgard_emit_derivatives(compiler_context
*ctx
, nir_alu_instr
*instr
);
676 midgard_lower_derivatives(compiler_context
*ctx
, midgard_block
*block
);
678 bool mir_op_computes_derivatives(gl_shader_stage stage
, unsigned op
);
682 void emit_binary_bundle(
683 compiler_context
*ctx
,
684 midgard_bundle
*bundle
,
685 struct util_dynarray
*emission
,
689 nir_undef_to_zero(nir_shader
*shader
);
691 void midgard_nir_lod_errata(nir_shader
*shader
);
695 bool midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
);
696 bool midgard_opt_combine_projection(compiler_context
*ctx
, midgard_block
*block
);
697 bool midgard_opt_varying_projection(compiler_context
*ctx
, midgard_block
*block
);
698 bool midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
);
699 bool midgard_opt_dead_move_eliminate(compiler_context
*ctx
, midgard_block
*block
);
701 void midgard_lower_invert(compiler_context
*ctx
, midgard_block
*block
);
702 bool midgard_opt_not_propagate(compiler_context
*ctx
, midgard_block
*block
);
703 bool midgard_opt_fuse_src_invert(compiler_context
*ctx
, midgard_block
*block
);
704 bool midgard_opt_fuse_dest_invert(compiler_context
*ctx
, midgard_block
*block
);
705 bool midgard_opt_csel_invert(compiler_context
*ctx
, midgard_block
*block
);
706 bool midgard_opt_promote_fmov(compiler_context
*ctx
, midgard_block
*block
);
707 bool midgard_opt_drop_cmp_invert(compiler_context
*ctx
, midgard_block
*block
);
708 bool midgard_opt_invert_branch(compiler_context
*ctx
, midgard_block
*block
);