src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30 #include "midgard_ops.h"
  31
  32 #include "util/hash_table.h"
  33 #include "util/u_dynarray.h"
  34 #include "util/set.h"
  35 #include "util/list.h"
  36
  37 #include "main/mtypes.h"
  38 #include "compiler/nir_types.h"
  39 #include "compiler/nir/nir.h"
  40 #include "panfrost/util/pan_ir.h"
  41 #include "panfrost/util/lcra.h"
  42
  43 /* Forward declare */
  44 struct midgard_block;
  45
  46 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  47  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  48  * instruction is actually a discard op. */
  49
  50 #define TARGET_GOTO 0
  51 #define TARGET_BREAK 1
  52 #define TARGET_CONTINUE 2
  53 #define TARGET_DISCARD 3
  54 #define TARGET_TILEBUF_WAIT 4
  55
  56 typedef struct midgard_branch {
  57         /* If conditional, the condition is specified in r31.w */
  58         bool conditional;
  59
  60         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  61         bool invert_conditional;
  62
  63         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  64         unsigned target_type;
  65
  66         /* The actual target */
  67         union {
  68                 int target_block;
  69                 int target_break;
  70                 int target_continue;
  71         };
  72 } midgard_branch;
  73
  74 #define PAN_WRITEOUT_C 1
  75 #define PAN_WRITEOUT_Z 2
  76 #define PAN_WRITEOUT_S 4
  77
  78 /* Generic in-memory data type repesenting a single logical instruction, rather
  79  * than a single instruction group. This is the preferred form for code gen.
  80  * Multiple midgard_insturctions will later be combined during scheduling,
  81  * though this is not represented in this structure.  Its format bridges
  82  * the low-level binary representation with the higher level semantic meaning.
  83  *
  84  * Notably, it allows registers to be specified as block local SSA, for code
  85  * emitted before the register allocation pass.
  86  */
  87
  88 #define MIR_SRC_COUNT 4
  89 #define MIR_VEC_COMPONENTS 16
  90
  91 typedef struct midgard_instruction {
  92         /* Must be first for casting */
  93         struct list_head link;
  94
  95         unsigned type; /* ALU, load/store, texture */
  96
  97         /* Instruction arguments represented as block-local SSA
  98          * indices, rather than registers. ~0 means unused. */
  99         unsigned src[MIR_SRC_COUNT];
 100         unsigned dest;
 101
 102         /* vec16 swizzle, unpacked, per source */
 103         unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
 104
 105         /* Types! */
 106         nir_alu_type src_types[MIR_SRC_COUNT];
 107         nir_alu_type dest_type;
 108
 109         /* Packing ops have non-32-bit dest types even though they functionally
 110          * work at the 32-bit level, use this as a signal to disable copyprop.
 111          * We maybe need synthetic pack ops instead. */
 112         bool is_pack;
 113
 114         /* Modifiers, depending on type */
 115         union {
 116                 struct {
 117                         bool src_abs[MIR_SRC_COUNT];
 118                         bool src_neg[MIR_SRC_COUNT];
 119                 };
 120
 121                 struct {
 122                         bool src_shift[MIR_SRC_COUNT];
 123                 };
 124         };
 125
 126         /* Out of the union for csel (could maybe be fixed..) */
 127         bool src_invert[MIR_SRC_COUNT];
 128
 129         /* If the op supports it */
 130         enum midgard_roundmode roundmode;
 131
 132         /* Special fields for an ALU instruction */
 133         midgard_reg_info registers;
 134
 135         /* For textures: should helpers execute this instruction (instead of
 136          * just helping with derivatives)? Should helpers terminate after? */
 137         bool helper_terminate;
 138         bool helper_execute;
 139
 140         /* I.e. (1 << alu_bit) */
 141         int unit;
 142
 143         bool has_constants;
 144         midgard_constants constants;
 145         uint16_t inline_constant;
 146         bool has_blend_constant;
 147         bool has_inline_constant;
 148
 149         bool compact_branch;
 150         uint8_t writeout;
 151         bool last_writeout;
 152
 153         /* Masks in a saneish format. One bit per channel, not packed fancy.
 154          * Use this instead of the op specific ones, and switch over at emit
 155          * time */
 156
 157         uint16_t mask;
 158
 159         /* Hint for the register allocator not to spill the destination written
 160          * from this instruction (because it is a spill/unspill node itself).
 161          * Bitmask of spilled classes */
 162
 163         unsigned no_spill;
 164
 165         /* Generic hint for intra-pass use */
 166         bool hint;
 167
 168         /* During scheduling, the backwards dependency graph
 169          * (DAG). nr_dependencies is the number of unscheduled
 170          * instructions that must still be scheduled after
 171          * (before) this instruction. dependents are which
 172          * instructions need to be scheduled before (after) this
 173          * instruction. */
 174
 175         unsigned nr_dependencies;
 176         BITSET_WORD *dependents;
 177
 178         union {
 179                 midgard_load_store_word load_store;
 180                 midgard_vector_alu alu;
 181                 midgard_texture_word texture;
 182                 midgard_branch_extended branch_extended;
 183                 uint16_t br_compact;
 184
 185                 /* General branch, rather than packed br_compact. Higher level
 186                  * than the other components */
 187                 midgard_branch branch;
 188         };
 189 } midgard_instruction;
 190
 191 typedef struct midgard_block {
 192         pan_block base;
 193
 194         bool scheduled;
 195
 196         /* List of midgard_bundles emitted (after the scheduler has run) */
 197         struct util_dynarray bundles;
 198
 199         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 200         unsigned quadword_count;
 201
 202         /* Indicates this is a fixed-function fragment epilogue block */
 203         bool epilogue;
 204
 205         /* Are helper invocations required by this block? */
 206         bool helpers_in;
 207 } midgard_block;
 208
 209 typedef struct midgard_bundle {
 210         /* Tag for the overall bundle */
 211         int tag;
 212
 213         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 214          * sadd, vadd, smul, vlut, branch) */
 215         int instruction_count;
 216         midgard_instruction *instructions[6];
 217
 218         /* Bundle-wide ALU configuration */
 219         int padding;
 220         int control;
 221         bool has_embedded_constants;
 222         midgard_constants constants;
 223         bool has_blend_constant;
 224         bool last_writeout;
 225 } midgard_bundle;
 226
 227 enum midgard_rt_id {
 228         MIDGARD_COLOR_RT0 = 0,
 229         MIDGARD_COLOR_RT1,
 230         MIDGARD_COLOR_RT2,
 231         MIDGARD_COLOR_RT3,
 232         MIDGARD_COLOR_RT4,
 233         MIDGARD_COLOR_RT5,
 234         MIDGARD_COLOR_RT6,
 235         MIDGARD_COLOR_RT7,
 236         MIDGARD_ZS_RT,
 237         MIDGARD_NUM_RTS,
 238 };
 239
 240 typedef struct compiler_context {
 241         nir_shader *nir;
 242         gl_shader_stage stage;
 243
 244         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 245         bool is_blend;
 246
 247         /* Render target number for a keyed blend shader. Depends on is_blend */
 248         unsigned blend_rt;
 249
 250         /* Index to precolour to r0 for an input blend colour */
 251         unsigned blend_input;
 252
 253         /* Index to precolour to r2 for a dual-source blend colour */
 254         unsigned blend_src1;
 255
 256         /* Tracking for blend constant patching */
 257         int blend_constant_offset;
 258
 259         /* Number of bytes used for Thread Local Storage */
 260         unsigned tls_size;
 261
 262         /* Count of spills and fills for shaderdb */
 263         unsigned spills;
 264         unsigned fills;
 265
 266         /* Current NIR function */
 267         nir_function *func;
 268
 269         /* Allocated compiler temporary counter */
 270         unsigned temp_alloc;
 271
 272         /* Unordered list of midgard_blocks */
 273         int block_count;
 274         struct list_head blocks;
 275
 276         /* TODO merge with block_count? */
 277         unsigned block_source_count;
 278
 279         /* List of midgard_instructions emitted for the current block */
 280         midgard_block *current_block;
 281
 282         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 283         midgard_block *after_block;
 284
 285         /* The current "depth" of the loop, for disambiguating breaks/continues
 286          * when using nested loops */
 287         int current_loop_depth;
 288
 289         /* Total number of loops for shader-db */
 290         unsigned loop_count;
 291
 292         /* Constants which have been loaded, for later inlining */
 293         struct hash_table_u64 *ssa_constants;
 294
 295         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 296         struct hash_table_u64 *hash_to_temp;
 297         int temp_count;
 298         int max_hash;
 299
 300         /* Set of NIR indices that were already emitted as outmods */
 301         BITSET_WORD *already_emitted;
 302
 303         /* Just the count of the max register used. Higher count => higher
 304          * register pressure */
 305         int work_registers;
 306
 307         /* The number of uniforms allowable for the fast path */
 308         int uniform_cutoff;
 309
 310         /* Count of instructions emitted from NIR overall, across all blocks */
 311         int instruction_count;
 312
 313         /* Alpha ref value passed in */
 314         float alpha_ref;
 315
 316         unsigned quadword_count;
 317
 318         /* Bitmask of valid metadata */
 319         unsigned metadata;
 320
 321         /* Model-specific quirk set */
 322         uint32_t quirks;
 323
 324         /* Writeout instructions for each render target */
 325         midgard_instruction *writeout_branch[MIDGARD_NUM_RTS];
 326
 327         struct panfrost_sysvals sysvals;
 328 } compiler_context;
 329
 330 /* Per-block live_in/live_out */
 331 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 332
 333 /* Helpers for manipulating the above structures (forming the driver IR) */
 334
 335 /* Append instruction to end of current block */
 336
 337 static inline midgard_instruction *
 338 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 339 {
 340         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 341         memcpy(heap, &ins, sizeof(ins));
 342         return heap;
 343 }
 344
 345 static inline midgard_instruction *
 346 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 347 {
 348         midgard_instruction *u = mir_upload_ins(ctx, ins);
 349         list_addtail(&u->link, &ctx->current_block->base.instructions);
 350         return u;
 351 }
 352
 353 static inline struct midgard_instruction *
 354 mir_insert_instruction_before(struct compiler_context *ctx,
 355                               struct midgard_instruction *tag,
 356                               struct midgard_instruction ins)
 357 {
 358         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 359         list_addtail(&u->link, &tag->link);
 360         return u;
 361 }
 362
 363 static inline void
 364 mir_remove_instruction(struct midgard_instruction *ins)
 365 {
 366         list_del(&ins->link);
 367 }
 368
 369 static inline midgard_instruction*
 370 mir_prev_op(struct midgard_instruction *ins)
 371 {
 372         return list_last_entry(&(ins->link), midgard_instruction, link);
 373 }
 374
 375 static inline midgard_instruction*
 376 mir_next_op(struct midgard_instruction *ins)
 377 {
 378         return list_first_entry(&(ins->link), midgard_instruction, link);
 379 }
 380
 381 #define mir_foreach_block(ctx, v) \
 382         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 383
 384 #define mir_foreach_block_from(ctx, from, v) \
 385         list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
 386
 387 #define mir_foreach_instr_in_block(block, v) \
 388         list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
 389 #define mir_foreach_instr_in_block_rev(block, v) \
 390         list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
 391
 392 #define mir_foreach_instr_in_block_safe(block, v) \
 393         list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
 394
 395 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 396         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
 397
 398 #define mir_foreach_instr_in_block_from(block, v, from) \
 399         list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
 400
 401 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 402         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
 403
 404 #define mir_foreach_bundle_in_block(block, v) \
 405         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 406
 407 #define mir_foreach_bundle_in_block_rev(block, v) \
 408         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 409
 410 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 411         midgard_instruction* v; \
 412         signed i = 0; \
 413         mir_foreach_bundle_in_block_rev(block, _bundle) \
 414                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 415                                 i >= 0; \
 416                                 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
 417
 418 #define mir_foreach_instr_global(ctx, v) \
 419         mir_foreach_block(ctx, v_block) \
 420                 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
 421
 422 #define mir_foreach_instr_global_safe(ctx, v) \
 423         mir_foreach_block(ctx, v_block) \
 424                 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
 425
 426 /* Based on set_foreach, expanded with automatic type casts */
 427
 428 #define mir_foreach_predecessor(blk, v) \
 429         struct set_entry *_entry_##v; \
 430         struct midgard_block *v; \
 431         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 432                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 433                 _entry_##v != NULL; \
 434                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 435                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 436
 437 #define mir_foreach_src(ins, v) \
 438         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 439
 440 static inline midgard_instruction *
 441 mir_last_in_block(struct midgard_block *block)
 442 {
 443         return list_last_entry(&block->base.instructions, struct midgard_instruction, link);
 444 }
 445
 446 static inline midgard_block *
 447 mir_get_block(compiler_context *ctx, int idx)
 448 {
 449         struct list_head *lst = &ctx->blocks;
 450
 451         while ((idx--) + 1)
 452                 lst = lst->next;
 453
 454         return (struct midgard_block *) lst;
 455 }
 456
 457 static inline bool
 458 mir_is_alu_bundle(midgard_bundle *bundle)
 459 {
 460         return IS_ALU(bundle->tag);
 461 }
 462
 463 static inline unsigned
 464 make_compiler_temp(compiler_context *ctx)
 465 {
 466         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 467 }
 468
 469 static inline unsigned
 470 make_compiler_temp_reg(compiler_context *ctx)
 471 {
 472         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
 473 }
 474
 475 static inline unsigned
 476 nir_ssa_index(nir_ssa_def *ssa)
 477 {
 478         return (ssa->index << 1) | 0;
 479 }
 480
 481 static inline unsigned
 482 nir_src_index(compiler_context *ctx, nir_src *src)
 483 {
 484         if (src->is_ssa)
 485                 return nir_ssa_index(src->ssa);
 486         else {
 487                 assert(!src->reg.indirect);
 488                 return (src->reg.reg->index << 1) | PAN_IS_REG;
 489         }
 490 }
 491
 492 static inline unsigned
 493 nir_dest_index(nir_dest *dst)
 494 {
 495         if (dst->is_ssa)
 496                 return (dst->ssa.index << 1) | 0;
 497         else {
 498                 assert(!dst->reg.indirect);
 499                 return (dst->reg.reg->index << 1) | PAN_IS_REG;
 500         }
 501 }
 502
 503
 504
 505 /* MIR manipulation */
 506
 507 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 508 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 509 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 510 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 511 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 512 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 513 bool mir_single_use(compiler_context *ctx, unsigned value);
 514 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 515 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 516 uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i);
 517 uint16_t mir_from_bytemask(uint16_t bytemask, unsigned bits);
 518 uint16_t mir_bytemask(midgard_instruction *ins);
 519 uint16_t mir_round_bytemask_up(uint16_t mask, unsigned bits);
 520 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 521 signed mir_upper_override(midgard_instruction *ins, unsigned inst_size);
 522 unsigned mir_components_for_type(nir_alu_type T);
 523
 524 /* MIR printing */
 525
 526 void mir_print_instruction(midgard_instruction *ins);
 527 void mir_print_bundle(midgard_bundle *ctx);
 528 void mir_print_block(midgard_block *block);
 529 void mir_print_shader(compiler_context *ctx);
 530 bool mir_nontrivial_mod(midgard_instruction *ins, unsigned i, bool check_swizzle);
 531 bool mir_nontrivial_outmod(midgard_instruction *ins);
 532
 533 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 534 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 535 void mir_flip(midgard_instruction *ins);
 536 void mir_compute_temp_count(compiler_context *ctx);
 537
 538 void mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, bool is_shared);
 539
 540 /* 'Intrinsic' move for aliasing */
 541
 542 static inline midgard_instruction
 543 v_mov(unsigned src, unsigned dest)
 544 {
 545         midgard_instruction ins = {
 546                 .type = TAG_ALU_4,
 547                 .mask = 0xF,
 548                 .src = { ~0, src, ~0, ~0 },
 549                 .src_types = { 0, nir_type_uint32 },
 550                 .swizzle = SWIZZLE_IDENTITY,
 551                 .dest = dest,
 552                 .dest_type = nir_type_uint32,
 553                 .alu = {
 554                         .op = midgard_alu_op_imov,
 555                         .reg_mode = midgard_reg_mode_32,
 556                         .outmod = midgard_outmod_int_wrap
 557                 },
 558         };
 559
 560         return ins;
 561 }
 562
 563 /* Broad types of register classes so we can handle special
 564  * registers */
 565
 566 #define REG_CLASS_WORK          0
 567 #define REG_CLASS_LDST          1
 568 #define REG_CLASS_TEXR          3
 569 #define REG_CLASS_TEXW          4
 570
 571 /* Like a move, but to thread local storage! */
 572
 573 static inline midgard_instruction
 574 v_load_store_scratch(
 575                 unsigned srcdest,
 576                 unsigned index,
 577                 bool is_store,
 578                 unsigned mask)
 579 {
 580         /* We index by 32-bit vec4s */
 581         unsigned byte = (index * 4 * 4);
 582
 583         midgard_instruction ins = {
 584                 .type = TAG_LOAD_STORE_4,
 585                 .mask = mask,
 586                 .dest_type = nir_type_uint32,
 587                 .dest = ~0,
 588                 .src = { ~0, ~0, ~0, ~0 },
 589                 .swizzle = SWIZZLE_IDENTITY_4,
 590                 .load_store = {
 591                         .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
 592
 593                         /* For register spilling - to thread local storage */
 594                         .arg_1 = 0xEA,
 595                         .arg_2 = 0x1E,
 596                 },
 597
 598                 /* If we spill an unspill, RA goes into an infinite loop */
 599                 .no_spill = (1 << REG_CLASS_WORK)
 600         };
 601
 602         ins.constants.u32[0] = byte;
 603
 604         if (is_store) {
 605                 ins.src[0] = srcdest;
 606                 ins.src_types[0] = nir_type_uint32;
 607
 608                 /* Ensure we are tightly swizzled so liveness analysis is
 609                  * correct */
 610
 611                 for (unsigned i = 0; i < 4; ++i) {
 612                         if (!(mask & (1 << i)))
 613                                 ins.swizzle[0][i] = COMPONENT_X;
 614                 }
 615         } else
 616                 ins.dest = srcdest;
 617
 618         return ins;
 619 }
 620
 621 static inline bool
 622 mir_has_arg(midgard_instruction *ins, unsigned arg)
 623 {
 624         if (!ins)
 625                 return false;
 626
 627         mir_foreach_src(ins, i) {
 628                 if (ins->src[i] == arg)
 629                         return true;
 630         }
 631
 632         return false;
 633 }
 634
 635 /* Scheduling */
 636
 637 void midgard_schedule_program(compiler_context *ctx);
 638
 639 void mir_ra(compiler_context *ctx);
 640 void mir_squeeze_index(compiler_context *ctx);
 641 void mir_lower_special_reads(compiler_context *ctx);
 642 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 643 void mir_compute_liveness(compiler_context *ctx);
 644 void mir_invalidate_liveness(compiler_context *ctx);
 645 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 646
 647 void mir_create_pipeline_registers(compiler_context *ctx);
 648 void midgard_promote_uniforms(compiler_context *ctx);
 649
 650 void
 651 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 652
 653 void
 654 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 655
 656 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
 657
 658 void mir_analyze_helper_terminate(compiler_context *ctx);
 659 void mir_analyze_helper_requirements(compiler_context *ctx);
 660
 661 /* Final emission */
 662
 663 void emit_binary_bundle(
 664         compiler_context *ctx,
 665         midgard_block *block,
 666         midgard_bundle *bundle,
 667         struct util_dynarray *emission,
 668         int next_tag);
 669
 670 bool
 671 nir_undef_to_zero(nir_shader *shader);
 672 bool nir_fuse_io_16(nir_shader *shader);
 673
 674 void midgard_nir_lod_errata(nir_shader *shader);
 675
 676 /* Optimizations */
 677
 678 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 679 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 680 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 681 bool midgard_opt_dead_code_eliminate(compiler_context *ctx);
 682 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 683
 684 #endif