2 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #ifndef _MDG_COMPILER_H
25 #define _MDG_COMPILER_H
29 #include "midgard_compile.h"
31 #include "util/hash_table.h"
32 #include "util/u_dynarray.h"
34 #include "util/list.h"
36 #include "main/mtypes.h"
37 #include "compiler/nir_types.h"
38 #include "compiler/nir/nir.h"
43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
44 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
45 * instruction is actually a discard op. */
48 #define TARGET_BREAK 1
49 #define TARGET_CONTINUE 2
50 #define TARGET_DISCARD 3
52 typedef struct midgard_branch
{
53 /* If conditional, the condition is specified in r31.w */
56 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
57 bool invert_conditional
;
59 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
62 /* The actual target */
70 /* Generic in-memory data type repesenting a single logical instruction, rather
71 * than a single instruction group. This is the preferred form for code gen.
72 * Multiple midgard_insturctions will later be combined during scheduling,
73 * though this is not represented in this structure. Its format bridges
74 * the low-level binary representation with the higher level semantic meaning.
76 * Notably, it allows registers to be specified as block local SSA, for code
77 * emitted before the register allocation pass.
80 typedef struct midgard_instruction
{
81 /* Must be first for casting */
82 struct list_head link
;
84 unsigned type
; /* ALU, load/store, texture */
86 /* Instruction arguments represented as block-local SSA
87 * indices, rather than registers. ~0 means unused. */
91 /* Swizzle for the conditional for a csel */
92 unsigned csel_swizzle
;
94 /* Special fields for an ALU instruction */
95 midgard_reg_info registers
;
97 /* I.e. (1 << alu_bit) */
100 /* When emitting bundle, should this instruction have a break forced
101 * before it? Used for r31 writes which are valid only within a single
102 * bundle and *need* to happen as early as possible... this is a hack,
103 * TODO remove when we have a scheduler */
107 uint32_t constants
[4];
108 uint16_t inline_constant
;
109 bool has_blend_constant
;
110 bool has_inline_constant
;
114 bool prepacked_branch
;
116 /* Kind of a hack, but hint against aggressive DCE */
119 /* Masks in a saneish format. One bit per channel, not packed fancy.
120 * Use this instead of the op specific ones, and switch over at emit
125 /* For ALU ops only: set to true to invert (bitwise NOT) the
126 * destination of an integer-out op. Not imeplemented in hardware but
127 * allows more optimizations */
131 /* Hint for the register allocator not to spill the destination written
132 * from this instruction (because it is a spill/unspill node itself) */
136 /* Generic hint for intra-pass use */
140 midgard_load_store_word load_store
;
141 midgard_vector_alu alu
;
142 midgard_texture_word texture
;
143 midgard_branch_extended branch_extended
;
146 /* General branch, rather than packed br_compact. Higher level
147 * than the other components */
148 midgard_branch branch
;
150 } midgard_instruction
;
152 typedef struct midgard_block
{
153 /* Link to next block. Must be first for mir_get_block */
154 struct list_head link
;
156 /* List of midgard_instructions emitted for the current block */
157 struct list_head instructions
;
159 /* Index of the block in source order */
164 /* List of midgard_bundles emitted (after the scheduler has run) */
165 struct util_dynarray bundles
;
167 /* Number of quadwords _actually_ emitted, as determined after scheduling */
168 unsigned quadword_count
;
170 /* Succeeding blocks. The compiler should not necessarily rely on
171 * source-order traversal */
172 struct midgard_block
*successors
[2];
173 unsigned nr_successors
;
175 struct set
*predecessors
;
177 /* The successors pointer form a graph, and in the case of
178 * complex control flow, this graph has a cycles. To aid
179 * traversal during liveness analysis, we have a visited?
180 * boolean for passes to use as they see fit, provided they
184 /* In liveness analysis, these are live masks (per-component) for
185 * indices for the block. Scalar compilers have the luxury of using
186 * simple bit fields, but for us, liveness is a vector idea. We use
187 * 8-bit to allow finegrained tracking up to vec8. If you're
188 * implementing vec16 on Panfrost... I'm sorry. */
193 typedef struct midgard_bundle
{
194 /* Tag for the overall bundle */
197 /* Instructions contained by the bundle */
198 int instruction_count
;
199 midgard_instruction
*instructions
[5];
201 /* Bundle-wide ALU configuration */
204 bool has_embedded_constants
;
206 bool has_blend_constant
;
209 typedef struct compiler_context
{
211 gl_shader_stage stage
;
213 /* The screen we correspond to */
214 struct midgard_screen
*screen
;
216 /* Is internally a blend shader? Depends on stage == FRAGMENT */
219 /* Tracking for blend constant patching */
220 int blend_constant_offset
;
222 /* Number of bytes used for Thread Local Storage */
225 /* Count of spills and fills for shaderdb */
229 /* Current NIR function */
232 /* Allocated compiler temporary counter */
235 /* Unordered list of midgard_blocks */
237 struct list_head blocks
;
239 /* TODO merge with block_count? */
240 unsigned block_source_count
;
242 /* List of midgard_instructions emitted for the current block */
243 midgard_block
*current_block
;
245 /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
246 midgard_block
*after_block
;
248 /* The current "depth" of the loop, for disambiguating breaks/continues
249 * when using nested loops */
250 int current_loop_depth
;
252 /* Total number of loops for shader-db */
255 /* Constants which have been loaded, for later inlining */
256 struct hash_table_u64
*ssa_constants
;
258 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
259 struct hash_table_u64
*hash_to_temp
;
263 /* Just the count of the max register used. Higher count => higher
264 * register pressure */
267 /* Used for cont/last hinting. Increase when a tex op is added.
268 * Decrease when a tex op is removed. */
269 int texture_op_count
;
271 /* The number of uniforms allowable for the fast path */
274 /* Count of instructions emitted from NIR overall, across all blocks */
275 int instruction_count
;
277 /* Alpha ref value passed in */
280 unsigned quadword_count
;
282 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
283 unsigned sysvals
[MAX_SYSVAL_COUNT
];
284 unsigned sysval_count
;
285 struct hash_table_u64
*sysval_to_id
;
288 /* Helpers for manipulating the above structures (forming the driver IR) */
290 /* Append instruction to end of current block */
292 static inline midgard_instruction
*
293 mir_upload_ins(struct compiler_context
*ctx
, struct midgard_instruction ins
)
295 midgard_instruction
*heap
= ralloc(ctx
, struct midgard_instruction
);
296 memcpy(heap
, &ins
, sizeof(ins
));
300 static inline midgard_instruction
*
301 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
303 midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
304 list_addtail(&u
->link
, &ctx
->current_block
->instructions
);
308 static inline struct midgard_instruction
*
309 mir_insert_instruction_before(struct compiler_context
*ctx
,
310 struct midgard_instruction
*tag
,
311 struct midgard_instruction ins
)
313 struct midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
314 list_addtail(&u
->link
, &tag
->link
);
319 mir_remove_instruction(struct midgard_instruction
*ins
)
321 list_del(&ins
->link
);
324 static inline midgard_instruction
*
325 mir_prev_op(struct midgard_instruction
*ins
)
327 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
330 static inline midgard_instruction
*
331 mir_next_op(struct midgard_instruction
*ins
)
333 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
336 #define mir_foreach_block(ctx, v) \
337 list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
339 #define mir_foreach_block_from(ctx, from, v) \
340 list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
342 #define mir_foreach_instr(ctx, v) \
343 list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
345 #define mir_foreach_instr_safe(ctx, v) \
346 list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
348 #define mir_foreach_instr_in_block(block, v) \
349 list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
350 #define mir_foreach_instr_in_block_rev(block, v) \
351 list_for_each_entry_rev(struct midgard_instruction, v, &block->instructions, link)
353 #define mir_foreach_instr_in_block_safe(block, v) \
354 list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
356 #define mir_foreach_instr_in_block_safe_rev(block, v) \
357 list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
359 #define mir_foreach_instr_in_block_from(block, v, from) \
360 list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
362 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
363 list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
365 #define mir_foreach_bundle_in_block(block, v) \
366 util_dynarray_foreach(&block->bundles, midgard_bundle, v)
368 #define mir_foreach_bundle_in_block_rev(block, v) \
369 util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
371 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
372 midgard_instruction* v; \
374 mir_foreach_bundle_in_block_rev(block, _bundle) \
375 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
377 --i, v = _bundle->instructions[i]) \
379 #define mir_foreach_instr_global(ctx, v) \
380 mir_foreach_block(ctx, v_block) \
381 mir_foreach_instr_in_block(v_block, v)
383 #define mir_foreach_instr_global_safe(ctx, v) \
384 mir_foreach_block(ctx, v_block) \
385 mir_foreach_instr_in_block_safe(v_block, v)
387 #define mir_foreach_successor(blk, v) \
388 struct midgard_block *v; \
389 struct midgard_block **_v; \
390 for (_v = &blk->successors[0], \
392 v != NULL && _v < &blk->successors[2]; \
395 /* Based on set_foreach, expanded with automatic type casts */
397 #define mir_foreach_predecessor(blk, v) \
398 struct set_entry *_entry_##v; \
399 struct midgard_block *v; \
400 for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
401 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL); \
402 _entry_##v != NULL; \
403 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
404 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
406 #define mir_foreach_src(ins, v) \
407 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
409 static inline midgard_instruction
*
410 mir_last_in_block(struct midgard_block
*block
)
412 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
415 static inline midgard_block
*
416 mir_get_block(compiler_context
*ctx
, int idx
)
418 struct list_head
*lst
= &ctx
->blocks
;
423 return (struct midgard_block
*) lst
;
426 static inline midgard_block
*
427 mir_exit_block(struct compiler_context
*ctx
)
429 midgard_block
*last
= list_last_entry(&ctx
->blocks
,
430 struct midgard_block
, link
);
432 /* The last block must be empty logically but contains branch writeout
433 * for fragment shaders */
435 assert(last
->nr_successors
== 0);
441 mir_is_alu_bundle(midgard_bundle
*bundle
)
443 return IS_ALU(bundle
->tag
);
446 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
450 static inline unsigned
451 make_compiler_temp(compiler_context
*ctx
)
453 return (ctx
->func
->impl
->ssa_alloc
+ ctx
->temp_alloc
++) << 1;
456 static inline unsigned
457 make_compiler_temp_reg(compiler_context
*ctx
)
459 return ((ctx
->func
->impl
->reg_alloc
+ ctx
->temp_alloc
++) << 1) | IS_REG
;
462 static inline unsigned
463 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
466 return (src
->ssa
->index
<< 1) | 0;
468 assert(!src
->reg
.indirect
);
469 return (src
->reg
.reg
->index
<< 1) | IS_REG
;
473 static inline unsigned
474 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
476 return nir_src_index(ctx
, &src
->src
);
479 static inline unsigned
480 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
483 return (dst
->ssa
.index
<< 1) | 0;
485 assert(!dst
->reg
.indirect
);
486 return (dst
->reg
.reg
->index
<< 1) | IS_REG
;
492 /* MIR manipulation */
494 unsigned mir_get_swizzle(midgard_instruction
*ins
, unsigned idx
);
495 void mir_set_swizzle(midgard_instruction
*ins
, unsigned idx
, unsigned new);
496 void mir_rewrite_index(compiler_context
*ctx
, unsigned old
, unsigned new);
497 void mir_rewrite_index_src(compiler_context
*ctx
, unsigned old
, unsigned new);
498 void mir_rewrite_index_dst(compiler_context
*ctx
, unsigned old
, unsigned new);
499 void mir_rewrite_index_dst_tag(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned tag
);
500 void mir_rewrite_index_dst_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
501 void mir_rewrite_index_src_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
502 void mir_rewrite_index_src_tag(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned tag
);
503 void mir_rewrite_index_src_swizzle(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned swizzle
);
504 bool mir_single_use(compiler_context
*ctx
, unsigned value
);
505 bool mir_special_index(compiler_context
*ctx
, unsigned idx
);
506 unsigned mir_use_count(compiler_context
*ctx
, unsigned value
);
507 bool mir_is_written_before(compiler_context
*ctx
, midgard_instruction
*ins
, unsigned node
);
508 unsigned mir_mask_of_read_components(midgard_instruction
*ins
, unsigned node
);
509 unsigned mir_ubo_shift(midgard_load_store_op op
);
513 void mir_print_instruction(midgard_instruction
*ins
);
514 void mir_print_bundle(midgard_bundle
*ctx
);
515 void mir_print_block(midgard_block
*block
);
516 void mir_print_shader(compiler_context
*ctx
);
517 bool mir_nontrivial_source2_mod(midgard_instruction
*ins
);
518 bool mir_nontrivial_source2_mod_simple(midgard_instruction
*ins
);
519 bool mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
);
520 bool mir_nontrivial_outmod(midgard_instruction
*ins
);
522 void mir_insert_instruction_before_scheduled(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*tag
, midgard_instruction ins
);
523 void mir_insert_instruction_after_scheduled(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*tag
, midgard_instruction ins
);
527 static const midgard_vector_alu_src blank_alu_src
= {
528 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
531 static const midgard_vector_alu_src blank_alu_src_xxxx
= {
532 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
535 static const midgard_scalar_alu_src blank_scalar_alu_src
= {
539 /* Used for encoding the unused source of 1-op instructions */
540 static const midgard_vector_alu_src zero_alu_src
= { 0 };
542 /* 'Intrinsic' move for aliasing */
544 static inline midgard_instruction
545 v_mov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
547 midgard_instruction ins
= {
550 .src
= { SSA_UNUSED
, src
, SSA_UNUSED
},
553 .op
= midgard_alu_op_imov
,
554 .reg_mode
= midgard_reg_mode_32
,
555 .dest_override
= midgard_dest_override_none
,
556 .outmod
= midgard_outmod_int_wrap
,
557 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
558 .src2
= vector_alu_srco_unsigned(mod
)
566 mir_has_arg(midgard_instruction
*ins
, unsigned arg
)
571 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
->src
); ++i
) {
572 if (ins
->src
[i
] == arg
)
581 void schedule_program(compiler_context
*ctx
);
583 /* Register allocation */
587 /* Broad types of register classes so we can handle special
590 #define NR_REG_CLASSES 5
592 #define REG_CLASS_WORK 0
593 #define REG_CLASS_LDST 1
594 #define REG_CLASS_LDST27 2
595 #define REG_CLASS_TEXR 3
596 #define REG_CLASS_TEXW 4
598 void mir_lower_special_reads(compiler_context
*ctx
);
599 struct ra_graph
* allocate_registers(compiler_context
*ctx
, bool *spilled
);
600 void install_registers(compiler_context
*ctx
, struct ra_graph
*g
);
601 bool mir_is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
);
602 bool mir_has_multiple_writes(compiler_context
*ctx
, int src
);
604 void mir_create_pipeline_registers(compiler_context
*ctx
);
607 midgard_promote_uniforms(compiler_context
*ctx
, unsigned promoted_count
);
609 midgard_instruction
*
611 compiler_context
*ctx
,
615 nir_src
*indirect_offset
,
619 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
, signed dest_override
, unsigned nr_components
);
622 midgard_emit_derivatives(compiler_context
*ctx
, nir_alu_instr
*instr
);
625 midgard_lower_derivatives(compiler_context
*ctx
, midgard_block
*block
);
627 bool mir_op_computes_derivatives(unsigned op
);
631 void emit_binary_bundle(
632 compiler_context
*ctx
,
633 midgard_bundle
*bundle
,
634 struct util_dynarray
*emission
,
637 /* NIR stuff. TODO: Move? Share? Something? */
640 nir_undef_to_zero(nir_shader
*shader
);
643 nir_clamp_psiz(nir_shader
*shader
, float min_size
, float max_size
);
647 bool midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
);
648 bool midgard_opt_combine_projection(compiler_context
*ctx
, midgard_block
*block
);
649 bool midgard_opt_varying_projection(compiler_context
*ctx
, midgard_block
*block
);
650 bool midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
);
651 bool midgard_opt_dead_move_eliminate(compiler_context
*ctx
, midgard_block
*block
);
652 void midgard_opt_post_move_eliminate(compiler_context
*ctx
, midgard_block
*block
, struct ra_graph
*g
);
654 void midgard_lower_invert(compiler_context
*ctx
, midgard_block
*block
);
655 bool midgard_opt_not_propagate(compiler_context
*ctx
, midgard_block
*block
);
656 bool midgard_opt_fuse_src_invert(compiler_context
*ctx
, midgard_block
*block
);
657 bool midgard_opt_fuse_dest_invert(compiler_context
*ctx
, midgard_block
*block
);
658 bool midgard_opt_promote_fmov(compiler_context
*ctx
, midgard_block
*block
);