src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30 #include "lcra.h"
  31
  32 #include "util/hash_table.h"
  33 #include "util/u_dynarray.h"
  34 #include "util/set.h"
  35 #include "util/list.h"
  36
  37 #include "main/mtypes.h"
  38 #include "compiler/nir_types.h"
  39 #include "compiler/nir/nir.h"
  40
  41 /* Forward declare */
  42 struct midgard_block;
  43
  44 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  45  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  46  * instruction is actually a discard op. */
  47
  48 #define TARGET_GOTO 0
  49 #define TARGET_BREAK 1
  50 #define TARGET_CONTINUE 2
  51 #define TARGET_DISCARD 3
  52
  53 typedef struct midgard_branch {
  54         /* If conditional, the condition is specified in r31.w */
  55         bool conditional;
  56
  57         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  58         bool invert_conditional;
  59
  60         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  61         unsigned target_type;
  62
  63         /* The actual target */
  64         union {
  65                 int target_block;
  66                 int target_break;
  67                 int target_continue;
  68         };
  69 } midgard_branch;
  70
  71 /* Generic in-memory data type repesenting a single logical instruction, rather
  72  * than a single instruction group. This is the preferred form for code gen.
  73  * Multiple midgard_insturctions will later be combined during scheduling,
  74  * though this is not represented in this structure.  Its format bridges
  75  * the low-level binary representation with the higher level semantic meaning.
  76  *
  77  * Notably, it allows registers to be specified as block local SSA, for code
  78  * emitted before the register allocation pass.
  79  */
  80
  81 #define MIR_SRC_COUNT 3
  82 #define MIR_VEC_COMPONENTS 16
  83
  84 typedef struct midgard_instruction {
  85         /* Must be first for casting */
  86         struct list_head link;
  87
  88         unsigned type; /* ALU, load/store, texture */
  89
  90         /* Instruction arguments represented as block-local SSA
  91          * indices, rather than registers. ~0 means unused. */
  92         unsigned src[3];
  93         unsigned dest;
  94
  95         /* vec16 swizzle, unpacked, per source */
  96         unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
  97
  98         /* Special fields for an ALU instruction */
  99         midgard_reg_info registers;
 100
 101         /* I.e. (1 << alu_bit) */
 102         int unit;
 103
 104         bool has_constants;
 105         uint32_t constants[4];
 106         uint16_t inline_constant;
 107         bool has_blend_constant;
 108         bool has_inline_constant;
 109
 110         bool compact_branch;
 111         bool writeout;
 112         bool prepacked_branch;
 113
 114         /* Kind of a hack, but hint against aggressive DCE */
 115         bool dont_eliminate;
 116
 117         /* Masks in a saneish format. One bit per channel, not packed fancy.
 118          * Use this instead of the op specific ones, and switch over at emit
 119          * time */
 120
 121         uint16_t mask;
 122
 123         /* For ALU ops only: set to true to invert (bitwise NOT) the
 124          * destination of an integer-out op. Not imeplemented in hardware but
 125          * allows more optimizations */
 126
 127         bool invert;
 128
 129         /* Hint for the register allocator not to spill the destination written
 130          * from this instruction (because it is a spill/unspill node itself) */
 131
 132         bool no_spill;
 133
 134         /* Generic hint for intra-pass use */
 135         bool hint;
 136
 137         /* During scheduling, the backwards dependency graph
 138          * (DAG). nr_dependencies is the number of unscheduled
 139          * instructions that must still be scheduled after
 140          * (before) this instruction. dependents are which
 141          * instructions need to be scheduled before (after) this
 142          * instruction. */
 143
 144         unsigned nr_dependencies;
 145         BITSET_WORD *dependents;
 146
 147         /* For load/store ops.. force 64-bit destination */
 148         bool load_64;
 149
 150         union {
 151                 midgard_load_store_word load_store;
 152                 midgard_vector_alu alu;
 153                 midgard_texture_word texture;
 154                 midgard_branch_extended branch_extended;
 155                 uint16_t br_compact;
 156
 157                 /* General branch, rather than packed br_compact. Higher level
 158                  * than the other components */
 159                 midgard_branch branch;
 160         };
 161 } midgard_instruction;
 162
 163 typedef struct midgard_block {
 164         /* Link to next block. Must be first for mir_get_block */
 165         struct list_head link;
 166
 167         /* List of midgard_instructions emitted for the current block */
 168         struct list_head instructions;
 169
 170         /* Index of the block in source order */
 171         unsigned source_id;
 172
 173         bool is_scheduled;
 174
 175         /* List of midgard_bundles emitted (after the scheduler has run) */
 176         struct util_dynarray bundles;
 177
 178         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 179         unsigned quadword_count;
 180
 181         /* Succeeding blocks. The compiler should not necessarily rely on
 182          * source-order traversal */
 183         struct midgard_block *successors[2];
 184         unsigned nr_successors;
 185
 186         struct set *predecessors;
 187
 188         /* The successors pointer form a graph, and in the case of
 189          * complex control flow, this graph has a cycles. To aid
 190          * traversal during liveness analysis, we have a visited?
 191          * boolean for passes to use as they see fit, provided they
 192          * clean up later */
 193         bool visited;
 194
 195         /* In liveness analysis, these are live masks (per-component) for
 196          * indices for the block. Scalar compilers have the luxury of using
 197          * simple bit fields, but for us, liveness is a vector idea. */
 198         uint16_t *live_in;
 199         uint16_t *live_out;
 200 } midgard_block;
 201
 202 typedef struct midgard_bundle {
 203         /* Tag for the overall bundle */
 204         int tag;
 205
 206         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 207          * sadd, vadd, smul, vlut, branch) */
 208         int instruction_count;
 209         midgard_instruction *instructions[6];
 210
 211         /* Bundle-wide ALU configuration */
 212         int padding;
 213         int control;
 214         bool has_embedded_constants;
 215         float constants[4];
 216         bool has_blend_constant;
 217 } midgard_bundle;
 218
 219 typedef struct compiler_context {
 220         nir_shader *nir;
 221         gl_shader_stage stage;
 222
 223         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 224         bool is_blend;
 225
 226         /* Tracking for blend constant patching */
 227         int blend_constant_offset;
 228
 229         /* Number of bytes used for Thread Local Storage */
 230         unsigned tls_size;
 231
 232         /* Count of spills and fills for shaderdb */
 233         unsigned spills;
 234         unsigned fills;
 235
 236         /* Current NIR function */
 237         nir_function *func;
 238
 239         /* Allocated compiler temporary counter */
 240         unsigned temp_alloc;
 241
 242         /* Unordered list of midgard_blocks */
 243         int block_count;
 244         struct list_head blocks;
 245
 246         /* TODO merge with block_count? */
 247         unsigned block_source_count;
 248
 249         /* List of midgard_instructions emitted for the current block */
 250         midgard_block *current_block;
 251
 252         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 253         midgard_block *after_block;
 254
 255         /* The current "depth" of the loop, for disambiguating breaks/continues
 256          * when using nested loops */
 257         int current_loop_depth;
 258
 259         /* Total number of loops for shader-db */
 260         unsigned loop_count;
 261
 262         /* Constants which have been loaded, for later inlining */
 263         struct hash_table_u64 *ssa_constants;
 264
 265         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 266         struct hash_table_u64 *hash_to_temp;
 267         int temp_count;
 268         int max_hash;
 269
 270         /* Just the count of the max register used. Higher count => higher
 271          * register pressure */
 272         int work_registers;
 273
 274         /* Used for cont/last hinting. Increase when a tex op is added.
 275          * Decrease when a tex op is removed. */
 276         int texture_op_count;
 277
 278         /* The number of uniforms allowable for the fast path */
 279         int uniform_cutoff;
 280
 281         /* Count of instructions emitted from NIR overall, across all blocks */
 282         int instruction_count;
 283
 284         /* Alpha ref value passed in */
 285         float alpha_ref;
 286
 287         unsigned quadword_count;
 288
 289         /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
 290         unsigned sysvals[MAX_SYSVAL_COUNT];
 291         unsigned sysval_count;
 292         struct hash_table_u64 *sysval_to_id;
 293
 294         /* Bitmask of valid metadata */
 295         unsigned metadata;
 296
 297         unsigned gpu_id;
 298 } compiler_context;
 299
 300 /* Per-block live_in/live_out */
 301 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 302
 303 /* Helpers for manipulating the above structures (forming the driver IR) */
 304
 305 /* Append instruction to end of current block */
 306
 307 static inline midgard_instruction *
 308 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 309 {
 310         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 311         memcpy(heap, &ins, sizeof(ins));
 312         return heap;
 313 }
 314
 315 static inline midgard_instruction *
 316 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 317 {
 318         midgard_instruction *u = mir_upload_ins(ctx, ins);
 319         list_addtail(&u->link, &ctx->current_block->instructions);
 320         return u;
 321 }
 322
 323 static inline struct midgard_instruction *
 324 mir_insert_instruction_before(struct compiler_context *ctx,
 325                               struct midgard_instruction *tag,
 326                               struct midgard_instruction ins)
 327 {
 328         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 329         list_addtail(&u->link, &tag->link);
 330         return u;
 331 }
 332
 333 static inline void
 334 mir_remove_instruction(struct midgard_instruction *ins)
 335 {
 336         list_del(&ins->link);
 337 }
 338
 339 static inline midgard_instruction*
 340 mir_prev_op(struct midgard_instruction *ins)
 341 {
 342         return list_last_entry(&(ins->link), midgard_instruction, link);
 343 }
 344
 345 static inline midgard_instruction*
 346 mir_next_op(struct midgard_instruction *ins)
 347 {
 348         return list_first_entry(&(ins->link), midgard_instruction, link);
 349 }
 350
 351 #define mir_foreach_block(ctx, v) \
 352         list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
 353
 354 #define mir_foreach_block_from(ctx, from, v) \
 355         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 356
 357 #define mir_foreach_instr(ctx, v) \
 358         list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 359
 360 #define mir_foreach_instr_safe(ctx, v) \
 361         list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 362
 363 #define mir_foreach_instr_in_block(block, v) \
 364         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 365 #define mir_foreach_instr_in_block_rev(block, v) \
 366         list_for_each_entry_rev(struct midgard_instruction, v, &block->instructions, link)
 367
 368 #define mir_foreach_instr_in_block_safe(block, v) \
 369         list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
 370
 371 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 372         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
 373
 374 #define mir_foreach_instr_in_block_from(block, v, from) \
 375         list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
 376
 377 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 378         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
 379
 380 #define mir_foreach_bundle_in_block(block, v) \
 381         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 382
 383 #define mir_foreach_bundle_in_block_rev(block, v) \
 384         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 385
 386 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 387         midgard_instruction* v; \
 388         signed i = 0; \
 389         mir_foreach_bundle_in_block_rev(block, _bundle) \
 390                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 391                                 i >= 0; \
 392                                 --i, v = _bundle->instructions[i]) \
 393
 394 #define mir_foreach_instr_global(ctx, v) \
 395         mir_foreach_block(ctx, v_block) \
 396                 mir_foreach_instr_in_block(v_block, v)
 397
 398 #define mir_foreach_instr_global_safe(ctx, v) \
 399         mir_foreach_block(ctx, v_block) \
 400                 mir_foreach_instr_in_block_safe(v_block, v)
 401
 402 #define mir_foreach_successor(blk, v) \
 403         struct midgard_block *v; \
 404         struct midgard_block **_v; \
 405         for (_v = &blk->successors[0], \
 406                 v = *_v; \
 407                 v != NULL && _v < &blk->successors[2]; \
 408                 _v++, v = *_v) \
 409
 410 /* Based on set_foreach, expanded with automatic type casts */
 411
 412 #define mir_foreach_predecessor(blk, v) \
 413         struct set_entry *_entry_##v; \
 414         struct midgard_block *v; \
 415         for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
 416                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 417                 _entry_##v != NULL; \
 418                 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
 419                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 420
 421 #define mir_foreach_src(ins, v) \
 422         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 423
 424 static inline midgard_instruction *
 425 mir_last_in_block(struct midgard_block *block)
 426 {
 427         return list_last_entry(&block->instructions, struct midgard_instruction, link);
 428 }
 429
 430 static inline midgard_block *
 431 mir_get_block(compiler_context *ctx, int idx)
 432 {
 433         struct list_head *lst = &ctx->blocks;
 434
 435         while ((idx--) + 1)
 436                 lst = lst->next;
 437
 438         return (struct midgard_block *) lst;
 439 }
 440
 441 static inline midgard_block *
 442 mir_exit_block(struct compiler_context *ctx)
 443 {
 444         midgard_block *last = list_last_entry(&ctx->blocks,
 445                         struct midgard_block, link);
 446
 447         /* The last block must be empty logically but contains branch writeout
 448          * for fragment shaders */
 449
 450         assert(last->nr_successors == 0);
 451
 452         return last;
 453 }
 454
 455 static inline bool
 456 mir_is_alu_bundle(midgard_bundle *bundle)
 457 {
 458         return IS_ALU(bundle->tag);
 459 }
 460
 461 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
 462
 463 #define IS_REG (1)
 464
 465 static inline unsigned
 466 make_compiler_temp(compiler_context *ctx)
 467 {
 468         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 469 }
 470
 471 static inline unsigned
 472 make_compiler_temp_reg(compiler_context *ctx)
 473 {
 474         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
 475 }
 476
 477 static inline unsigned
 478 nir_src_index(compiler_context *ctx, nir_src *src)
 479 {
 480         if (src->is_ssa)
 481                 return (src->ssa->index << 1) | 0;
 482         else {
 483                 assert(!src->reg.indirect);
 484                 return (src->reg.reg->index << 1) | IS_REG;
 485         }
 486 }
 487
 488 static inline unsigned
 489 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
 490 {
 491         return nir_src_index(ctx, &src->src);
 492 }
 493
 494 static inline unsigned
 495 nir_dest_index(compiler_context *ctx, nir_dest *dst)
 496 {
 497         if (dst->is_ssa)
 498                 return (dst->ssa.index << 1) | 0;
 499         else {
 500                 assert(!dst->reg.indirect);
 501                 return (dst->reg.reg->index << 1) | IS_REG;
 502         }
 503 }
 504
 505
 506
 507 /* MIR manipulation */
 508
 509 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 510 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 511 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 512 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 513 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 514 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 515 bool mir_single_use(compiler_context *ctx, unsigned value);
 516 bool mir_special_index(compiler_context *ctx, unsigned idx);
 517 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 518 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 519 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 520 midgard_reg_mode mir_typesize(midgard_instruction *ins);
 521 midgard_reg_mode mir_srcsize(midgard_instruction *ins, unsigned i);
 522 unsigned mir_bytes_for_mode(midgard_reg_mode mode);
 523 midgard_reg_mode mir_mode_for_destsize(unsigned size);
 524 uint16_t mir_from_bytemask(uint16_t bytemask, midgard_reg_mode mode);
 525 uint16_t mir_to_bytemask(midgard_reg_mode mode, unsigned mask);
 526 uint16_t mir_bytemask(midgard_instruction *ins);
 527 uint16_t mir_round_bytemask_down(uint16_t mask, midgard_reg_mode mode);
 528 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 529
 530 /* MIR printing */
 531
 532 void mir_print_instruction(midgard_instruction *ins);
 533 void mir_print_bundle(midgard_bundle *ctx);
 534 void mir_print_block(midgard_block *block);
 535 void mir_print_shader(compiler_context *ctx);
 536 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 537 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 538 bool mir_nontrivial_outmod(midgard_instruction *ins);
 539
 540 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 541 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 542 void mir_flip(midgard_instruction *ins);
 543 void mir_compute_temp_count(compiler_context *ctx);
 544
 545 /* 'Intrinsic' move for aliasing */
 546
 547 static inline midgard_instruction
 548 v_mov(unsigned src, unsigned dest)
 549 {
 550         midgard_instruction ins = {
 551                 .type = TAG_ALU_4,
 552                 .mask = 0xF,
 553                 .src = { SSA_UNUSED, src, SSA_UNUSED },
 554                 .swizzle = SWIZZLE_IDENTITY,
 555                 .dest = dest,
 556                 .alu = {
 557                         .op = midgard_alu_op_imov,
 558                         .reg_mode = midgard_reg_mode_32,
 559                         .dest_override = midgard_dest_override_none,
 560                         .outmod = midgard_outmod_int_wrap
 561                 },
 562         };
 563
 564         return ins;
 565 }
 566
 567 static inline bool
 568 mir_has_arg(midgard_instruction *ins, unsigned arg)
 569 {
 570         if (!ins)
 571                 return false;
 572
 573         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
 574                 if (ins->src[i] == arg)
 575                         return true;
 576         }
 577
 578         return false;
 579 }
 580
 581 /* Scheduling */
 582
 583 void schedule_program(compiler_context *ctx);
 584
 585 /* Broad types of register classes so we can handle special
 586  * registers */
 587
 588 #define REG_CLASS_WORK          0
 589 #define REG_CLASS_LDST          1
 590 #define REG_CLASS_TEXR          3
 591 #define REG_CLASS_TEXW          4
 592
 593 void mir_lower_special_reads(compiler_context *ctx);
 594 struct lcra_state* allocate_registers(compiler_context *ctx, bool *spilled);
 595 void install_registers(compiler_context *ctx, struct lcra_state *g);
 596 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 597 void mir_compute_liveness(compiler_context *ctx);
 598 void mir_invalidate_liveness(compiler_context *ctx);
 599 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 600
 601 void mir_create_pipeline_registers(compiler_context *ctx);
 602
 603 void
 604 midgard_promote_uniforms(compiler_context *ctx, unsigned promoted_count);
 605
 606 midgard_instruction *
 607 emit_ubo_read(
 608         compiler_context *ctx,
 609         nir_instr *instr,
 610         unsigned dest,
 611         unsigned offset,
 612         nir_src *indirect_offset,
 613         unsigned index);
 614
 615 void
 616 emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override, unsigned nr_components);
 617
 618 void
 619 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 620
 621 void
 622 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 623
 624 bool mir_op_computes_derivatives(unsigned op);
 625
 626 /* Final emission */
 627
 628 void emit_binary_bundle(
 629         compiler_context *ctx,
 630         midgard_bundle *bundle,
 631         struct util_dynarray *emission,
 632         int next_tag);
 633
 634 bool
 635 nir_undef_to_zero(nir_shader *shader);
 636
 637 /* Optimizations */
 638
 639 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 640 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 641 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 642 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 643 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 644
 645 void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
 646 bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
 647 bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
 648 bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
 649 bool midgard_opt_csel_invert(compiler_context *ctx, midgard_block *block);
 650 bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
 651
 652 #endif