src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30
  31 #include "util/hash_table.h"
  32 #include "util/u_dynarray.h"
  33 #include "util/set.h"
  34 #include "util/list.h"
  35
  36 #include "main/mtypes.h"
  37 #include "compiler/nir_types.h"
  38 #include "compiler/nir/nir.h"
  39
  40 /* Forward declare */
  41 struct midgard_block;
  42
  43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  44  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  45  * instruction is actually a discard op. */
  46
  47 #define TARGET_GOTO 0
  48 #define TARGET_BREAK 1
  49 #define TARGET_CONTINUE 2
  50 #define TARGET_DISCARD 3
  51
  52 typedef struct midgard_branch {
  53         /* If conditional, the condition is specified in r31.w */
  54         bool conditional;
  55
  56         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  57         bool invert_conditional;
  58
  59         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  60         unsigned target_type;
  61
  62         /* The actual target */
  63         union {
  64                 int target_block;
  65                 int target_break;
  66                 int target_continue;
  67         };
  68 } midgard_branch;
  69
  70 /* Generic in-memory data type repesenting a single logical instruction, rather
  71  * than a single instruction group. This is the preferred form for code gen.
  72  * Multiple midgard_insturctions will later be combined during scheduling,
  73  * though this is not represented in this structure.  Its format bridges
  74  * the low-level binary representation with the higher level semantic meaning.
  75  *
  76  * Notably, it allows registers to be specified as block local SSA, for code
  77  * emitted before the register allocation pass.
  78  */
  79
  80 typedef struct midgard_instruction {
  81         /* Must be first for casting */
  82         struct list_head link;
  83
  84         unsigned type; /* ALU, load/store, texture */
  85
  86         /* Instruction arguments represented as block-local SSA
  87          * indices, rather than registers. ~0 means unused. */
  88         unsigned src[3];
  89         unsigned dest;
  90
  91         /* Special fields for an ALU instruction */
  92         midgard_reg_info registers;
  93
  94         /* I.e. (1 << alu_bit) */
  95         int unit;
  96
  97         /* When emitting bundle, should this instruction have a break forced
  98          * before it? Used for r31 writes which are valid only within a single
  99          * bundle and *need* to happen as early as possible... this is a hack,
 100          * TODO remove when we have a scheduler */
 101         bool precede_break;
 102
 103         bool has_constants;
 104         uint32_t constants[4];
 105         uint16_t inline_constant;
 106         bool has_blend_constant;
 107         bool has_inline_constant;
 108
 109         bool compact_branch;
 110         bool writeout;
 111         bool prepacked_branch;
 112
 113         /* Kind of a hack, but hint against aggressive DCE */
 114         bool dont_eliminate;
 115
 116         /* Masks in a saneish format. One bit per channel, not packed fancy.
 117          * Use this instead of the op specific ones, and switch over at emit
 118          * time */
 119
 120         uint16_t mask;
 121
 122         /* For ALU ops only: set to true to invert (bitwise NOT) the
 123          * destination of an integer-out op. Not imeplemented in hardware but
 124          * allows more optimizations */
 125
 126         bool invert;
 127
 128         /* Hint for the register allocator not to spill the destination written
 129          * from this instruction (because it is a spill/unspill node itself) */
 130
 131         bool no_spill;
 132
 133         /* Generic hint for intra-pass use */
 134         bool hint;
 135
 136         union {
 137                 midgard_load_store_word load_store;
 138                 midgard_vector_alu alu;
 139                 midgard_texture_word texture;
 140                 midgard_branch_extended branch_extended;
 141                 uint16_t br_compact;
 142
 143                 /* General branch, rather than packed br_compact. Higher level
 144                  * than the other components */
 145                 midgard_branch branch;
 146         };
 147 } midgard_instruction;
 148
 149 typedef struct midgard_block {
 150         /* Link to next block. Must be first for mir_get_block */
 151         struct list_head link;
 152
 153         /* List of midgard_instructions emitted for the current block */
 154         struct list_head instructions;
 155
 156         /* Index of the block in source order */
 157         unsigned source_id;
 158
 159         bool is_scheduled;
 160
 161         /* List of midgard_bundles emitted (after the scheduler has run) */
 162         struct util_dynarray bundles;
 163
 164         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 165         unsigned quadword_count;
 166
 167         /* Succeeding blocks. The compiler should not necessarily rely on
 168          * source-order traversal */
 169         struct midgard_block *successors[2];
 170         unsigned nr_successors;
 171
 172         struct set *predecessors;
 173
 174         /* The successors pointer form a graph, and in the case of
 175          * complex control flow, this graph has a cycles. To aid
 176          * traversal during liveness analysis, we have a visited?
 177          * boolean for passes to use as they see fit, provided they
 178          * clean up later */
 179         bool visited;
 180
 181         /* In liveness analysis, these are live masks (per-component) for
 182          * indices for the block. Scalar compilers have the luxury of using
 183          * simple bit fields, but for us, liveness is a vector idea. We use
 184          * 8-bit to allow finegrained tracking up to vec8. If you're
 185          * implementing vec16 on Panfrost... I'm sorry. */
 186         uint8_t *live_in;
 187         uint8_t *live_out;
 188 } midgard_block;
 189
 190 typedef struct midgard_bundle {
 191         /* Tag for the overall bundle */
 192         int tag;
 193
 194         /* Instructions contained by the bundle */
 195         int instruction_count;
 196         midgard_instruction *instructions[5];
 197
 198         /* Bundle-wide ALU configuration */
 199         int padding;
 200         int control;
 201         bool has_embedded_constants;
 202         float constants[4];
 203         bool has_blend_constant;
 204 } midgard_bundle;
 205
 206 typedef struct compiler_context {
 207         nir_shader *nir;
 208         gl_shader_stage stage;
 209
 210         /* The screen we correspond to */
 211         struct midgard_screen *screen;
 212
 213         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 214         bool is_blend;
 215
 216         /* Tracking for blend constant patching */
 217         int blend_constant_offset;
 218
 219         /* Number of bytes used for Thread Local Storage */
 220         unsigned tls_size;
 221
 222         /* Count of spills and fills for shaderdb */
 223         unsigned spills;
 224         unsigned fills;
 225
 226         /* Current NIR function */
 227         nir_function *func;
 228
 229         /* Allocated compiler temporary counter */
 230         unsigned temp_alloc;
 231
 232         /* Unordered list of midgard_blocks */
 233         int block_count;
 234         struct list_head blocks;
 235
 236         /* TODO merge with block_count? */
 237         unsigned block_source_count;
 238
 239         /* List of midgard_instructions emitted for the current block */
 240         midgard_block *current_block;
 241
 242         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 243         midgard_block *after_block;
 244
 245         /* The current "depth" of the loop, for disambiguating breaks/continues
 246          * when using nested loops */
 247         int current_loop_depth;
 248
 249         /* Total number of loops for shader-db */
 250         unsigned loop_count;
 251
 252         /* Constants which have been loaded, for later inlining */
 253         struct hash_table_u64 *ssa_constants;
 254
 255         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 256         struct hash_table_u64 *hash_to_temp;
 257         int temp_count;
 258         int max_hash;
 259
 260         /* Just the count of the max register used. Higher count => higher
 261          * register pressure */
 262         int work_registers;
 263
 264         /* Used for cont/last hinting. Increase when a tex op is added.
 265          * Decrease when a tex op is removed. */
 266         int texture_op_count;
 267
 268         /* Mapping of texture register -> SSA index for unaliasing */
 269         int texture_index[2];
 270
 271         /* The number of uniforms allowable for the fast path */
 272         int uniform_cutoff;
 273
 274         /* Count of instructions emitted from NIR overall, across all blocks */
 275         int instruction_count;
 276
 277         /* Alpha ref value passed in */
 278         float alpha_ref;
 279
 280         /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
 281         unsigned sysvals[MAX_SYSVAL_COUNT];
 282         unsigned sysval_count;
 283         struct hash_table_u64 *sysval_to_id;
 284 } compiler_context;
 285
 286 /* Helpers for manipulating the above structures (forming the driver IR) */
 287
 288 /* Append instruction to end of current block */
 289
 290 static inline midgard_instruction *
 291 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 292 {
 293         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 294         memcpy(heap, &ins, sizeof(ins));
 295         return heap;
 296 }
 297
 298 static inline midgard_instruction *
 299 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 300 {
 301         midgard_instruction *u = mir_upload_ins(ctx, ins);
 302         list_addtail(&u->link, &ctx->current_block->instructions);
 303         return u;
 304 }
 305
 306 static inline struct midgard_instruction *
 307 mir_insert_instruction_before(struct compiler_context *ctx,
 308                               struct midgard_instruction *tag,
 309                               struct midgard_instruction ins)
 310 {
 311         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 312         list_addtail(&u->link, &tag->link);
 313         return u;
 314 }
 315
 316 static inline void
 317 mir_remove_instruction(struct midgard_instruction *ins)
 318 {
 319         list_del(&ins->link);
 320 }
 321
 322 static inline midgard_instruction*
 323 mir_prev_op(struct midgard_instruction *ins)
 324 {
 325         return list_last_entry(&(ins->link), midgard_instruction, link);
 326 }
 327
 328 static inline midgard_instruction*
 329 mir_next_op(struct midgard_instruction *ins)
 330 {
 331         return list_first_entry(&(ins->link), midgard_instruction, link);
 332 }
 333
 334 #define mir_foreach_block(ctx, v) \
 335         list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
 336
 337 #define mir_foreach_block_from(ctx, from, v) \
 338         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 339
 340 #define mir_foreach_instr(ctx, v) \
 341         list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 342
 343 #define mir_foreach_instr_safe(ctx, v) \
 344         list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 345
 346 #define mir_foreach_instr_in_block(block, v) \
 347         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 348 #define mir_foreach_instr_in_block_rev(block, v) \
 349         list_for_each_entry_rev(struct midgard_instruction, v, &block->instructions, link)
 350
 351 #define mir_foreach_instr_in_block_safe(block, v) \
 352         list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
 353
 354 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 355         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
 356
 357 #define mir_foreach_instr_in_block_from(block, v, from) \
 358         list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
 359
 360 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 361         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
 362
 363 #define mir_foreach_bundle_in_block(block, v) \
 364         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 365
 366 #define mir_foreach_bundle_in_block_rev(block, v) \
 367         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 368
 369 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 370         midgard_instruction* v; \
 371         signed i = 0; \
 372         mir_foreach_bundle_in_block_rev(block, _bundle) \
 373                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 374                                 i >= 0; \
 375                                 --i, v = _bundle->instructions[i]) \
 376
 377 #define mir_foreach_instr_global(ctx, v) \
 378         mir_foreach_block(ctx, v_block) \
 379                 mir_foreach_instr_in_block(v_block, v)
 380
 381 #define mir_foreach_instr_global_safe(ctx, v) \
 382         mir_foreach_block(ctx, v_block) \
 383                 mir_foreach_instr_in_block_safe(v_block, v)
 384
 385 #define mir_foreach_successor(blk, v) \
 386         struct midgard_block *v; \
 387         struct midgard_block **_v; \
 388         for (_v = &blk->successors[0], \
 389                 v = *_v; \
 390                 v != NULL && _v < &blk->successors[2]; \
 391                 _v++, v = *_v) \
 392
 393 /* Based on set_foreach, expanded with automatic type casts */
 394
 395 #define mir_foreach_predecessor(blk, v) \
 396         struct set_entry *_entry_##v; \
 397         struct midgard_block *v; \
 398         for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
 399                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 400                 _entry_##v != NULL; \
 401                 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
 402                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 403
 404 #define mir_foreach_src(ins, v) \
 405         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 406
 407 static inline midgard_instruction *
 408 mir_last_in_block(struct midgard_block *block)
 409 {
 410         return list_last_entry(&block->instructions, struct midgard_instruction, link);
 411 }
 412
 413 static inline midgard_block *
 414 mir_get_block(compiler_context *ctx, int idx)
 415 {
 416         struct list_head *lst = &ctx->blocks;
 417
 418         while ((idx--) + 1)
 419                 lst = lst->next;
 420
 421         return (struct midgard_block *) lst;
 422 }
 423
 424 static inline midgard_block *
 425 mir_exit_block(struct compiler_context *ctx)
 426 {
 427         midgard_block *last = list_last_entry(&ctx->blocks,
 428                         struct midgard_block, link);
 429
 430         /* The last block must be empty (the exit block) */
 431         assert(list_empty(&last->instructions));
 432         assert(last->nr_successors == 0);
 433
 434         return last;
 435 }
 436
 437 static inline bool
 438 mir_is_alu_bundle(midgard_bundle *bundle)
 439 {
 440         return IS_ALU(bundle->tag);
 441 }
 442
 443 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
 444
 445 #define IS_REG (1)
 446
 447 static inline unsigned
 448 make_compiler_temp(compiler_context *ctx)
 449 {
 450         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 451 }
 452
 453 static inline unsigned
 454 make_compiler_temp_reg(compiler_context *ctx)
 455 {
 456         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
 457 }
 458
 459 static inline unsigned
 460 nir_src_index(compiler_context *ctx, nir_src *src)
 461 {
 462         if (src->is_ssa)
 463                 return (src->ssa->index << 1) | 0;
 464         else {
 465                 assert(!src->reg.indirect);
 466                 return (src->reg.reg->index << 1) | IS_REG;
 467         }
 468 }
 469
 470 static inline unsigned
 471 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
 472 {
 473         return nir_src_index(ctx, &src->src);
 474 }
 475
 476 static inline unsigned
 477 nir_dest_index(compiler_context *ctx, nir_dest *dst)
 478 {
 479         if (dst->is_ssa)
 480                 return (dst->ssa.index << 1) | 0;
 481         else {
 482                 assert(!dst->reg.indirect);
 483                 return (dst->reg.reg->index << 1) | IS_REG;
 484         }
 485 }
 486
 487
 488
 489 /* MIR manipulation */
 490
 491 unsigned mir_get_swizzle(midgard_instruction *ins, unsigned idx);
 492 void mir_set_swizzle(midgard_instruction *ins, unsigned idx, unsigned new);
 493 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 494 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 495 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 496 void mir_rewrite_index_dst_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 497 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 498 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 499 void mir_rewrite_index_src_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 500 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned swizzle);
 501 bool mir_single_use(compiler_context *ctx, unsigned value);
 502 bool mir_special_index(compiler_context *ctx, unsigned idx);
 503 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 504 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 505 unsigned mir_mask_of_read_components(midgard_instruction *ins, unsigned node);
 506 unsigned mir_ubo_shift(midgard_load_store_op op);
 507
 508 /* MIR printing */
 509
 510 void mir_print_instruction(midgard_instruction *ins);
 511 void mir_print_bundle(midgard_bundle *ctx);
 512 void mir_print_block(midgard_block *block);
 513 void mir_print_shader(compiler_context *ctx);
 514 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 515 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 516 bool mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask);
 517 bool mir_nontrivial_outmod(midgard_instruction *ins);
 518
 519 /* MIR goodies */
 520
 521 static const midgard_vector_alu_src blank_alu_src = {
 522         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
 523 };
 524
 525 static const midgard_vector_alu_src blank_alu_src_xxxx = {
 526         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X),
 527 };
 528
 529 static const midgard_scalar_alu_src blank_scalar_alu_src = {
 530         .full = true
 531 };
 532
 533 /* Used for encoding the unused source of 1-op instructions */
 534 static const midgard_vector_alu_src zero_alu_src = { 0 };
 535
 536 /* 'Intrinsic' move for aliasing */
 537
 538 static inline midgard_instruction
 539 v_mov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
 540 {
 541         midgard_instruction ins = {
 542                 .type = TAG_ALU_4,
 543                 .mask = 0xF,
 544                 .src = { SSA_UNUSED, src, SSA_UNUSED },
 545                 .dest = dest,
 546                 .alu = {
 547                         .op = midgard_alu_op_imov,
 548                         .reg_mode = midgard_reg_mode_32,
 549                         .dest_override = midgard_dest_override_none,
 550                         .outmod = midgard_outmod_int_wrap,
 551                         .src1 = vector_alu_srco_unsigned(zero_alu_src),
 552                         .src2 = vector_alu_srco_unsigned(mod)
 553                 },
 554         };
 555
 556         return ins;
 557 }
 558
 559 static inline bool
 560 mir_has_arg(midgard_instruction *ins, unsigned arg)
 561 {
 562         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
 563                 if (ins->src[i] == arg)
 564                         return true;
 565         }
 566
 567         return false;
 568 }
 569
 570 /* Scheduling */
 571
 572 void schedule_program(compiler_context *ctx);
 573
 574 /* Register allocation */
 575
 576 struct ra_graph;
 577
 578 /* Broad types of register classes so we can handle special
 579  * registers */
 580
 581 #define NR_REG_CLASSES 5
 582
 583 #define REG_CLASS_WORK          0
 584 #define REG_CLASS_LDST          1
 585 #define REG_CLASS_LDST27        2
 586 #define REG_CLASS_TEXR          3
 587 #define REG_CLASS_TEXW          4
 588
 589 void mir_lower_special_reads(compiler_context *ctx);
 590 struct ra_graph* allocate_registers(compiler_context *ctx, bool *spilled);
 591 void install_registers(compiler_context *ctx, struct ra_graph *g);
 592 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 593 bool mir_has_multiple_writes(compiler_context *ctx, int src);
 594
 595 void mir_create_pipeline_registers(compiler_context *ctx);
 596
 597 void
 598 midgard_promote_uniforms(compiler_context *ctx, unsigned promoted_count);
 599
 600 midgard_instruction *
 601 emit_ubo_read(
 602         compiler_context *ctx,
 603         nir_instr *instr,
 604         unsigned dest,
 605         unsigned offset,
 606         nir_src *indirect_offset,
 607         unsigned index);
 608
 609 void
 610 emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override, unsigned nr_components);
 611
 612 void
 613 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 614
 615 void
 616 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 617
 618 bool mir_op_computes_derivatives(unsigned op);
 619
 620 /* Final emission */
 621
 622 void emit_binary_bundle(
 623         compiler_context *ctx,
 624         midgard_bundle *bundle,
 625         struct util_dynarray *emission,
 626         int next_tag);
 627
 628 /* NIR stuff. TODO: Move? Share? Something? */
 629
 630 bool
 631 nir_undef_to_zero(nir_shader *shader);
 632
 633 void
 634 nir_clamp_psiz(nir_shader *shader, float min_size, float max_size);
 635
 636 /* Optimizations */
 637
 638 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 639 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 640 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 641 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 642 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 643 void midgard_opt_post_move_eliminate(compiler_context *ctx, midgard_block *block, struct ra_graph *g);
 644
 645 void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
 646 bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
 647 bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
 648 bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
 649 bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
 650
 651 #endif