src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30
  31 #include "util/hash_table.h"
  32 #include "util/u_dynarray.h"
  33 #include "util/set.h"
  34 #include "util/list.h"
  35
  36 #include "main/mtypes.h"
  37 #include "compiler/nir_types.h"
  38 #include "compiler/nir/nir.h"
  39
  40 /* Forward declare */
  41 struct midgard_block;
  42
  43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  44  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  45  * instruction is actually a discard op. */
  46
  47 #define TARGET_GOTO 0
  48 #define TARGET_BREAK 1
  49 #define TARGET_CONTINUE 2
  50 #define TARGET_DISCARD 3
  51
  52 typedef struct midgard_branch {
  53         /* If conditional, the condition is specified in r31.w */
  54         bool conditional;
  55
  56         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  57         bool invert_conditional;
  58
  59         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  60         unsigned target_type;
  61
  62         /* The actual target */
  63         union {
  64                 int target_block;
  65                 int target_break;
  66                 int target_continue;
  67         };
  68 } midgard_branch;
  69
  70 /* Instruction arguments represented as block-local SSA indices, rather than
  71  * registers. Negative values mean unused. */
  72
  73 typedef struct {
  74         int src0;
  75         int src1;
  76         int dest;
  77
  78         /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
  79          * in. Only valid for ALU ops. */
  80         bool inline_constant;
  81 } ssa_args;
  82
  83 /* Generic in-memory data type repesenting a single logical instruction, rather
  84  * than a single instruction group. This is the preferred form for code gen.
  85  * Multiple midgard_insturctions will later be combined during scheduling,
  86  * though this is not represented in this structure.  Its format bridges
  87  * the low-level binary representation with the higher level semantic meaning.
  88  *
  89  * Notably, it allows registers to be specified as block local SSA, for code
  90  * emitted before the register allocation pass.
  91  */
  92
  93 typedef struct midgard_instruction {
  94         /* Must be first for casting */
  95         struct list_head link;
  96
  97         unsigned type; /* ALU, load/store, texture */
  98
  99         /* If the register allocator has not run yet... */
 100         ssa_args ssa_args;
 101
 102         /* Special fields for an ALU instruction */
 103         midgard_reg_info registers;
 104
 105         /* I.e. (1 << alu_bit) */
 106         int unit;
 107
 108         /* When emitting bundle, should this instruction have a break forced
 109          * before it? Used for r31 writes which are valid only within a single
 110          * bundle and *need* to happen as early as possible... this is a hack,
 111          * TODO remove when we have a scheduler */
 112         bool precede_break;
 113
 114         bool has_constants;
 115         float constants[4];
 116         uint16_t inline_constant;
 117         bool has_blend_constant;
 118
 119         bool compact_branch;
 120         bool writeout;
 121         bool prepacked_branch;
 122
 123         /* Masks in a saneish format. One bit per channel, not packed fancy.
 124          * Use this instead of the op specific ones, and switch over at emit
 125          * time */
 126         uint16_t mask;
 127
 128         union {
 129                 midgard_load_store_word load_store;
 130                 midgard_vector_alu alu;
 131                 midgard_texture_word texture;
 132                 midgard_branch_extended branch_extended;
 133                 uint16_t br_compact;
 134
 135                 /* General branch, rather than packed br_compact. Higher level
 136                  * than the other components */
 137                 midgard_branch branch;
 138         };
 139 } midgard_instruction;
 140
 141 typedef struct midgard_block {
 142         /* Link to next block. Must be first for mir_get_block */
 143         struct list_head link;
 144
 145         /* List of midgard_instructions emitted for the current block */
 146         struct list_head instructions;
 147
 148         bool is_scheduled;
 149
 150         /* List of midgard_bundles emitted (after the scheduler has run) */
 151         struct util_dynarray bundles;
 152
 153         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 154         unsigned quadword_count;
 155
 156         /* Successors: always one forward (the block after us), maybe
 157          * one backwards (for a backward branch). No need for a second
 158          * forward, since graph traversal would get there eventually
 159          * anyway */
 160         struct midgard_block *successors[2];
 161         unsigned nr_successors;
 162
 163         /* The successors pointer form a graph, and in the case of
 164          * complex control flow, this graph has a cycles. To aid
 165          * traversal during liveness analysis, we have a visited?
 166          * boolean for passes to use as they see fit, provided they
 167          * clean up later */
 168         bool visited;
 169 } midgard_block;
 170
 171 typedef struct midgard_bundle {
 172         /* Tag for the overall bundle */
 173         int tag;
 174
 175         /* Instructions contained by the bundle */
 176         int instruction_count;
 177         midgard_instruction *instructions[5];
 178
 179         /* Bundle-wide ALU configuration */
 180         int padding;
 181         int control;
 182         bool has_embedded_constants;
 183         float constants[4];
 184         bool has_blend_constant;
 185 } midgard_bundle;
 186
 187 typedef struct compiler_context {
 188         nir_shader *nir;
 189         gl_shader_stage stage;
 190
 191         /* The screen we correspond to */
 192         struct midgard_screen *screen;
 193
 194         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 195         bool is_blend;
 196
 197         /* Tracking for blend constant patching */
 198         int blend_constant_offset;
 199
 200         /* Number of bytes used for Thread Local Storage */
 201         unsigned tls_size;
 202
 203         /* Count of spills and fills for shaderdb */
 204         unsigned spills;
 205         unsigned fills;
 206
 207         /* Current NIR function */
 208         nir_function *func;
 209
 210         /* Allocated compiler temporary counter */
 211         unsigned temp_alloc;
 212
 213         /* Unordered list of midgard_blocks */
 214         int block_count;
 215         struct list_head blocks;
 216
 217         midgard_block *initial_block;
 218         midgard_block *previous_source_block;
 219         midgard_block *final_block;
 220
 221         /* List of midgard_instructions emitted for the current block */
 222         midgard_block *current_block;
 223
 224         /* The current "depth" of the loop, for disambiguating breaks/continues
 225          * when using nested loops */
 226         int current_loop_depth;
 227
 228         /* Total number of loops for shader-db */
 229         unsigned loop_count;
 230
 231         /* Constants which have been loaded, for later inlining */
 232         struct hash_table_u64 *ssa_constants;
 233
 234         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 235         struct hash_table_u64 *hash_to_temp;
 236         int temp_count;
 237         int max_hash;
 238
 239         /* Just the count of the max register used. Higher count => higher
 240          * register pressure */
 241         int work_registers;
 242
 243         /* Used for cont/last hinting. Increase when a tex op is added.
 244          * Decrease when a tex op is removed. */
 245         int texture_op_count;
 246
 247         /* Mapping of texture register -> SSA index for unaliasing */
 248         int texture_index[2];
 249
 250         /* The number of uniforms allowable for the fast path */
 251         int uniform_cutoff;
 252
 253         /* Count of instructions emitted from NIR overall, across all blocks */
 254         int instruction_count;
 255
 256         /* Alpha ref value passed in */
 257         float alpha_ref;
 258
 259         /* The index corresponding to the fragment output */
 260         unsigned fragment_output;
 261
 262         /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
 263         unsigned sysvals[MAX_SYSVAL_COUNT];
 264         unsigned sysval_count;
 265         struct hash_table_u64 *sysval_to_id;
 266 } compiler_context;
 267
 268 /* Helpers for manipulating the above structures (forming the driver IR) */
 269
 270 /* Append instruction to end of current block */
 271
 272 static inline midgard_instruction *
 273 mir_upload_ins(struct midgard_instruction ins)
 274 {
 275         midgard_instruction *heap = malloc(sizeof(ins));
 276         memcpy(heap, &ins, sizeof(ins));
 277         return heap;
 278 }
 279
 280 static inline void
 281 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 282 {
 283         list_addtail(&(mir_upload_ins(ins))->link, &ctx->current_block->instructions);
 284 }
 285
 286 static inline struct midgard_instruction *
 287 mir_insert_instruction_before(struct midgard_instruction *tag, struct midgard_instruction ins)
 288 {
 289         struct midgard_instruction *u = mir_upload_ins(ins);
 290         list_addtail(&u->link, &tag->link);
 291         return u;
 292 }
 293
 294 static inline void
 295 mir_remove_instruction(struct midgard_instruction *ins)
 296 {
 297         list_del(&ins->link);
 298 }
 299
 300 static inline midgard_instruction*
 301 mir_prev_op(struct midgard_instruction *ins)
 302 {
 303         return list_last_entry(&(ins->link), midgard_instruction, link);
 304 }
 305
 306 static inline midgard_instruction*
 307 mir_next_op(struct midgard_instruction *ins)
 308 {
 309         return list_first_entry(&(ins->link), midgard_instruction, link);
 310 }
 311
 312 #define mir_foreach_block(ctx, v) \
 313         list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
 314
 315 #define mir_foreach_block_from(ctx, from, v) \
 316         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 317
 318 #define mir_foreach_instr(ctx, v) \
 319         list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 320
 321 #define mir_foreach_instr_safe(ctx, v) \
 322         list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 323
 324 #define mir_foreach_instr_in_block(block, v) \
 325         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 326
 327 #define mir_foreach_instr_in_block_safe(block, v) \
 328         list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
 329
 330 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 331         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
 332
 333 #define mir_foreach_instr_in_block_from(block, v, from) \
 334         list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
 335
 336 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 337         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
 338
 339 #define mir_foreach_bundle_in_block(block, v) \
 340         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 341
 342 #define mir_foreach_instr_global(ctx, v) \
 343         mir_foreach_block(ctx, v_block) \
 344                 mir_foreach_instr_in_block(v_block, v)
 345
 346 #define mir_foreach_instr_global_safe(ctx, v) \
 347         mir_foreach_block(ctx, v_block) \
 348                 mir_foreach_instr_in_block_safe(v_block, v)
 349
 350 static inline midgard_instruction *
 351 mir_last_in_block(struct midgard_block *block)
 352 {
 353         return list_last_entry(&block->instructions, struct midgard_instruction, link);
 354 }
 355
 356 static inline midgard_block *
 357 mir_get_block(compiler_context *ctx, int idx)
 358 {
 359         struct list_head *lst = &ctx->blocks;
 360
 361         while ((idx--) + 1)
 362                 lst = lst->next;
 363
 364         return (struct midgard_block *) lst;
 365 }
 366
 367 static inline bool
 368 mir_is_alu_bundle(midgard_bundle *bundle)
 369 {
 370         return IS_ALU(bundle->tag);
 371 }
 372
 373 /* MIR manipulation */
 374
 375 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 376 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 377 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 378 void mir_rewrite_index_dst_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 379 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 380 void mir_rewrite_index_src_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 381 bool mir_single_use(compiler_context *ctx, unsigned value);
 382 bool mir_special_index(compiler_context *ctx, unsigned idx);
 383 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 384
 385 /* MIR printing */
 386
 387 void mir_print_instruction(midgard_instruction *ins);
 388 void mir_print_bundle(midgard_bundle *ctx);
 389 void mir_print_block(midgard_block *block);
 390 void mir_print_shader(compiler_context *ctx);
 391 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 392 bool mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask);
 393 bool mir_nontrivial_outmod(midgard_instruction *ins);
 394
 395 /* MIR goodies */
 396
 397 static const midgard_vector_alu_src blank_alu_src = {
 398         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
 399 };
 400
 401 static const midgard_vector_alu_src blank_alu_src_xxxx = {
 402         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X),
 403 };
 404
 405 static const midgard_scalar_alu_src blank_scalar_alu_src = {
 406         .full = true
 407 };
 408
 409 /* Used for encoding the unused source of 1-op instructions */
 410 static const midgard_vector_alu_src zero_alu_src = { 0 };
 411
 412 /* 'Intrinsic' move for aliasing */
 413
 414 static inline midgard_instruction
 415 v_mov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
 416 {
 417         midgard_instruction ins = {
 418                 .type = TAG_ALU_4,
 419                 .mask = 0xF,
 420                 .ssa_args = {
 421                         .src0 = SSA_UNUSED_1,
 422                         .src1 = src,
 423                         .dest = dest,
 424                 },
 425                 .alu = {
 426                         .op = midgard_alu_op_imov,
 427                         .reg_mode = midgard_reg_mode_32,
 428                         .dest_override = midgard_dest_override_none,
 429                         .outmod = midgard_outmod_int_wrap,
 430                         .src1 = vector_alu_srco_unsigned(zero_alu_src),
 431                         .src2 = vector_alu_srco_unsigned(mod)
 432                 },
 433         };
 434
 435         return ins;
 436 }
 437
 438 static inline bool
 439 mir_has_arg(midgard_instruction *ins, unsigned arg)
 440 {
 441         if (ins->ssa_args.src0 == arg)
 442                 return true;
 443
 444         if (ins->ssa_args.src1 == arg && !ins->ssa_args.inline_constant)
 445                 return true;
 446
 447         return false;
 448 }
 449
 450 /* Scheduling */
 451
 452 void schedule_program(compiler_context *ctx);
 453
 454 /* Register allocation */
 455
 456 struct ra_graph;
 457
 458 /* Broad types of register classes so we can handle special
 459  * registers */
 460
 461 #define NR_REG_CLASSES 5
 462
 463 #define REG_CLASS_WORK          0
 464 #define REG_CLASS_LDST          1
 465 #define REG_CLASS_LDST27        2
 466 #define REG_CLASS_TEXR          3
 467 #define REG_CLASS_TEXW          4
 468
 469 void mir_lower_special_reads(compiler_context *ctx);
 470 struct ra_graph* allocate_registers(compiler_context *ctx, bool *spilled);
 471 void install_registers(compiler_context *ctx, struct ra_graph *g);
 472 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 473 bool mir_has_multiple_writes(compiler_context *ctx, int src);
 474
 475 void mir_create_pipeline_registers(compiler_context *ctx);
 476
 477 void
 478 midgard_promote_uniforms(compiler_context *ctx, unsigned pressure);
 479
 480 void
 481 emit_ubo_read(
 482         compiler_context *ctx,
 483         unsigned dest,
 484         unsigned offset,
 485         nir_src *indirect_offset,
 486         unsigned index);
 487
 488
 489 /* Final emission */
 490
 491 void emit_binary_bundle(
 492         compiler_context *ctx,
 493         midgard_bundle *bundle,
 494         struct util_dynarray *emission,
 495         int next_tag);
 496
 497 /* NIR stuff. TODO: Move? Share? Something? */
 498
 499 bool
 500 nir_undef_to_zero(nir_shader *shader);
 501
 502 void
 503 nir_clamp_psiz(nir_shader *shader, float min_size, float max_size);
 504
 505 /* Optimizations */
 506
 507 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 508 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 509 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 510 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 511 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 512
 513 #endif