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a0640d66e8cd27dba40826a20858100aa8812a0e
[mesa.git] / src / panfrost / midgard / disassemble.c
1 /* Author(s):
2 * Connor Abbott
3 * Alyssa Rosenzweig
4 *
5 * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
6 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include <inttypes.h>
32 #include <ctype.h>
33 #include <string.h>
34 #include "midgard.h"
35 #include "midgard_ops.h"
36 #include "midgard_quirks.h"
37 #include "disassemble.h"
38 #include "helpers.h"
39 #include "util/bitscan.h"
40 #include "util/half_float.h"
41 #include "util/u_math.h"
42
43 #define DEFINE_CASE(define, str) case define: { fprintf(fp, str); break; }
44
45 static unsigned *midg_tags;
46 static bool is_instruction_int = false;
47
48 /* Stats */
49
50 static struct midgard_disasm_stats midg_stats;
51
52 /* Prints a short form of the tag for branching, the minimum needed to be
53 * legible and unambiguous */
54
55 static void
56 print_tag_short(FILE *fp, unsigned tag)
57 {
58 switch (midgard_word_types[tag]) {
59 case midgard_word_type_texture:
60 fprintf(fp, "tex/%X", tag);
61 break;
62
63 case midgard_word_type_load_store:
64 fprintf(fp, "ldst");
65 break;
66
67 case midgard_word_type_alu:
68 fprintf(fp, "alu%u/%X", midgard_word_size[tag], tag);
69 break;
70
71 default:
72 fprintf(fp, "%s%X", (tag > 0) ? "" : "unk", tag);
73 break;
74 }
75 }
76
77 static void
78 print_alu_opcode(FILE *fp, midgard_alu_op op)
79 {
80 bool int_op = false;
81
82 if (alu_opcode_props[op].name) {
83 fprintf(fp, "%s", alu_opcode_props[op].name);
84
85 int_op = midgard_is_integer_op(op);
86 } else
87 fprintf(fp, "alu_op_%02X", op);
88
89 /* For constant analysis */
90 is_instruction_int = int_op;
91 }
92
93 static void
94 print_ld_st_opcode(FILE *fp, midgard_load_store_op op)
95 {
96 if (load_store_opcode_props[op].name)
97 fprintf(fp, "%s", load_store_opcode_props[op].name);
98 else
99 fprintf(fp, "ldst_op_%02X", op);
100 }
101
102 static bool is_embedded_constant_half = false;
103 static bool is_embedded_constant_int = false;
104
105 static char
106 prefix_for_bits(unsigned bits)
107 {
108 switch (bits) {
109 case 8:
110 return 'q';
111 case 16:
112 return 'h';
113 case 64:
114 return 'd';
115 default:
116 return 0;
117 }
118 }
119
120 /* For static analysis to ensure all registers are written at least once before
121 * use along the source code path (TODO: does this break done for complex CF?)
122 */
123
124 uint16_t midg_ever_written = 0;
125
126 static void
127 print_reg(FILE *fp, unsigned reg, unsigned bits)
128 {
129 /* Perform basic static analysis for expanding constants correctly */
130
131 if (reg == 26) {
132 is_embedded_constant_int = is_instruction_int;
133 is_embedded_constant_half = (bits < 32);
134 }
135
136 unsigned uniform_reg = 23 - reg;
137 bool is_uniform = false;
138
139 /* For r8-r15, it could be a work or uniform. We distinguish based on
140 * the fact work registers are ALWAYS written before use, but uniform
141 * registers are NEVER written before use. */
142
143 if ((reg >= 8 && reg < 16) && !(midg_ever_written & (1 << reg)))
144 is_uniform = true;
145
146 /* r16-r23 are always uniform */
147
148 if (reg >= 16 && reg <= 23)
149 is_uniform = true;
150
151 /* Update the uniform count appropriately */
152
153 if (is_uniform)
154 midg_stats.uniform_count =
155 MAX2(uniform_reg + 1, midg_stats.uniform_count);
156
157 char prefix = prefix_for_bits(bits);
158
159 if (prefix)
160 putchar(prefix);
161
162 fprintf(fp, "r%u", reg);
163 }
164
165 static char *outmod_names_float[4] = {
166 "",
167 ".pos",
168 ".unk2",
169 ".sat"
170 };
171
172 static char *outmod_names_int[4] = {
173 ".isat",
174 ".usat",
175 "",
176 ".hi"
177 };
178
179 static char *srcmod_names_int[4] = {
180 "sext(",
181 "zext(",
182 "",
183 "("
184 };
185
186 static void
187 print_outmod(FILE *fp, unsigned outmod, bool is_int)
188 {
189 fprintf(fp, "%s", is_int ? outmod_names_int[outmod] :
190 outmod_names_float[outmod]);
191 }
192
193 static void
194 print_quad_word(FILE *fp, uint32_t *words, unsigned tabs)
195 {
196 unsigned i;
197
198 for (i = 0; i < 4; i++)
199 fprintf(fp, "0x%08X%s ", words[i], i == 3 ? "" : ",");
200
201 fprintf(fp, "\n");
202 }
203
204 static const char components[16] = "xyzwefghijklmnop";
205
206 /* Helper to print 4 chars of a swizzle */
207 static void
208 print_swizzle_helper(FILE *fp, unsigned swizzle, bool upper)
209 {
210 for (unsigned i = 0; i < 4; ++i) {
211 unsigned c = (swizzle >> (i * 2)) & 3;
212 c += upper*4;
213 fprintf(fp, "%c", components[c]);
214 }
215 }
216
217 /* Helper to print 8 chars of a swizzle, duplicating over */
218 static void
219 print_swizzle_helper_8(FILE *fp, unsigned swizzle, bool upper)
220 {
221 for (unsigned i = 0; i < 4; ++i) {
222 unsigned c = (swizzle >> (i * 2)) & 3;
223 c *= 2;
224 c += upper*8;
225 fprintf(fp, "%c%c", components[c], components[c+1]);
226 }
227 }
228
229 static void
230 print_swizzle_vec16(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low,
231 midgard_dest_override override)
232 {
233 fprintf(fp, ".");
234
235 if (override == midgard_dest_override_upper) {
236 if (rep_high)
237 fprintf(fp, " /* rep_high */ ");
238 if (rep_low)
239 fprintf(fp, " /* rep_low */ ");
240
241 if (!rep_high && rep_low)
242 print_swizzle_helper_8(fp, swizzle, true);
243 else
244 print_swizzle_helper_8(fp, swizzle, false);
245 } else {
246 print_swizzle_helper_8(fp, swizzle, rep_high & 1);
247 print_swizzle_helper_8(fp, swizzle, !(rep_low & 1));
248 }
249 }
250
251 static void
252 print_swizzle_vec8(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low)
253 {
254 fprintf(fp, ".");
255
256 print_swizzle_helper(fp, swizzle, rep_high & 1);
257 print_swizzle_helper(fp, swizzle, !(rep_low & 1));
258 }
259
260 static void
261 print_swizzle_vec4(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low)
262 {
263 if (rep_high)
264 fprintf(fp, " /* rep_high */ ");
265 if (rep_low)
266 fprintf(fp, " /* rep_low */ ");
267
268 if (swizzle == 0xE4) return; /* xyzw */
269
270 fprintf(fp, ".");
271 print_swizzle_helper(fp, swizzle, 0);
272 }
273 static void
274 print_swizzle_vec2(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low)
275 {
276 if (rep_high)
277 fprintf(fp, " /* rep_high */ ");
278 if (rep_low)
279 fprintf(fp, " /* rep_low */ ");
280
281 if (swizzle == 0xE4) return; /* XY */
282
283 fprintf(fp, ".");
284
285 for (unsigned i = 0; i < 4; i += 2) {
286 unsigned a = (swizzle >> (i * 2)) & 3;
287 unsigned b = (swizzle >> ((i+1) * 2)) & 3;
288
289 /* Normally we're adjacent, but if there's an issue, don't make
290 * it ambiguous */
291
292 if (a & 0x1)
293 fprintf(fp, "[%c%c]", components[a], components[b]);
294 else if (a == b)
295 fprintf(fp, "%c", components[a >> 1]);
296 else if (b == (a + 1))
297 fprintf(fp, "%c", "XY"[a >> 1]);
298 else
299 fprintf(fp, "[%c%c]", components[a], components[b]);
300 }
301 }
302
303 static int
304 bits_for_mode(midgard_reg_mode mode)
305 {
306 switch (mode) {
307 case midgard_reg_mode_8:
308 return 8;
309 case midgard_reg_mode_16:
310 return 16;
311 case midgard_reg_mode_32:
312 return 32;
313 case midgard_reg_mode_64:
314 return 64;
315 default:
316 unreachable("Invalid reg mode");
317 return 0;
318 }
319 }
320
321 static int
322 bits_for_mode_halved(midgard_reg_mode mode, bool half)
323 {
324 unsigned bits = bits_for_mode(mode);
325
326 if (half)
327 bits >>= 1;
328
329 return bits;
330 }
331
332 static void
333 print_scalar_constant(FILE *fp, unsigned src_binary,
334 const midgard_constants *consts,
335 midgard_scalar_alu *alu)
336 {
337 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
338 unsigned mod = 0;
339
340 assert(consts != NULL);
341
342 if (!midgard_is_integer_op(alu->op)) {
343 if (src->abs)
344 mod |= MIDGARD_FLOAT_MOD_ABS;
345 if (src->negate)
346 mod |= MIDGARD_FLOAT_MOD_NEG;
347 } else {
348 mod = midgard_int_normal;
349 }
350
351 fprintf(fp, "#");
352 mir_print_constant_component(fp, consts, src->component,
353 src->full ?
354 midgard_reg_mode_32 : midgard_reg_mode_16,
355 false, mod, alu->op);
356 }
357
358 static void
359 print_vector_constants(FILE *fp, unsigned src_binary,
360 const midgard_constants *consts,
361 midgard_vector_alu *alu)
362 {
363 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
364 unsigned bits = bits_for_mode_halved(alu->reg_mode, src->half);
365 unsigned max_comp = MIN2((sizeof(*consts) * 8) / bits, 8);
366 unsigned comp_mask, num_comp = 0;
367
368 assert(consts);
369
370 comp_mask = effective_writemask(alu, condense_writemask(alu->mask, bits));
371 num_comp = util_bitcount(comp_mask);
372
373 fprintf(fp, "#");
374 if (num_comp > 1)
375 fprintf(fp, "vec%d(", num_comp);
376
377 bool first = true;
378
379 for (unsigned i = 0; i < max_comp; ++i) {
380 if (!(comp_mask & (1 << i))) continue;
381
382 unsigned c = (src->swizzle >> (i * 2)) & 3;
383
384 if (first)
385 first = false;
386 else
387 fprintf(fp, ", ");
388
389 mir_print_constant_component(fp, consts, c, alu->reg_mode,
390 src->half, src->mod, alu->op);
391 }
392
393 if (num_comp > 1)
394 fprintf(fp, ")");
395 }
396
397 static void
398 print_vector_src(FILE *fp, unsigned src_binary,
399 midgard_reg_mode mode, unsigned reg,
400 midgard_dest_override override, bool is_int)
401 {
402 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
403
404 /* Modifiers change meaning depending on the op's context */
405
406 midgard_int_mod int_mod = src->mod;
407
408 if (is_int) {
409 fprintf(fp, "%s", srcmod_names_int[int_mod]);
410 } else {
411 if (src->mod & MIDGARD_FLOAT_MOD_NEG)
412 fprintf(fp, "-");
413
414 if (src->mod & MIDGARD_FLOAT_MOD_ABS)
415 fprintf(fp, "abs(");
416 }
417
418 //register
419 unsigned bits = bits_for_mode_halved(mode, src->half);
420 print_reg(fp, reg, bits);
421
422 //swizzle
423 if (bits == 16) {
424 /* When the mode of the instruction is itself 16-bit,
425 * rep_low/high work more or less as expected. But if the mode
426 * is 32-bit and we're stepping down, you only have vec4 and
427 * the meaning shifts to rep_low as higher-half and rep_high is
428 * never seen. TODO: are other modes similar? */
429
430 if (mode == midgard_reg_mode_32) {
431 fprintf(fp, ".");
432 print_swizzle_helper(fp, src->swizzle, src->rep_low);
433 assert(!src->rep_high);
434 } else {
435 print_swizzle_vec8(fp, src->swizzle, src->rep_high, src->rep_low);
436 }
437 } else if (bits == 8)
438 print_swizzle_vec16(fp, src->swizzle, src->rep_high, src->rep_low, override);
439 else if (bits == 32)
440 print_swizzle_vec4(fp, src->swizzle, src->rep_high, src->rep_low);
441 else if (bits == 64)
442 print_swizzle_vec2(fp, src->swizzle, src->rep_high, src->rep_low);
443
444 /* Since we wrapped with a function-looking thing */
445
446 if (is_int && int_mod == midgard_int_shift)
447 fprintf(fp, ") << %u", bits);
448 else if ((is_int && (int_mod != midgard_int_normal))
449 || (!is_int && src->mod & MIDGARD_FLOAT_MOD_ABS))
450 fprintf(fp, ")");
451 }
452
453 static uint16_t
454 decode_vector_imm(unsigned src2_reg, unsigned imm)
455 {
456 uint16_t ret;
457 ret = src2_reg << 11;
458 ret |= (imm & 0x7) << 8;
459 ret |= (imm >> 3) & 0xFF;
460 return ret;
461 }
462
463 static void
464 print_immediate(FILE *fp, uint16_t imm)
465 {
466 if (is_instruction_int)
467 fprintf(fp, "#%u", imm);
468 else
469 fprintf(fp, "#%g", _mesa_half_to_float(imm));
470 }
471
472 static void
473 update_dest(unsigned reg)
474 {
475 /* We should record writes as marking this as a work register. Store
476 * the max register in work_count; we'll add one at the end */
477
478 if (reg < 16) {
479 midg_stats.work_count = MAX2(reg, midg_stats.work_count);
480 midg_ever_written |= (1 << reg);
481 }
482 }
483
484 static void
485 print_dest(FILE *fp, unsigned reg, midgard_reg_mode mode, midgard_dest_override override)
486 {
487 /* Depending on the mode and override, we determine the type of
488 * destination addressed. Absent an override, we address just the
489 * type of the operation itself */
490
491 unsigned bits = bits_for_mode(mode);
492
493 if (override != midgard_dest_override_none)
494 bits /= 2;
495
496 update_dest(reg);
497 print_reg(fp, reg, bits);
498 }
499
500 static void
501 print_mask_vec16(FILE *fp, uint8_t mask, midgard_dest_override override)
502 {
503 fprintf(fp, ".");
504
505 for (unsigned i = 0; i < 8; i++) {
506 if (mask & (1 << i))
507 fprintf(fp, "%c%c",
508 components[i*2 + 0],
509 components[i*2 + 1]);
510 }
511 }
512
513 /* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
514 * it's just one bit per channel, easy peasy. For 32-bit (vec4), it's one bit
515 * per channel with one duplicate bit in the middle. For 64-bit (vec2), it's
516 * one-bit per channel with _3_ duplicate bits in the middle. Basically, just
517 * subdividing the 128-bit word in 16-bit increments. For 64-bit, we uppercase
518 * the mask to make it obvious what happened */
519
520 static void
521 print_mask(FILE *fp, uint8_t mask, unsigned bits, midgard_dest_override override)
522 {
523 if (bits == 8) {
524 print_mask_vec16(fp, mask, override);
525 return;
526 }
527
528 /* Skip 'complete' masks */
529
530 if (override == midgard_dest_override_none) {
531 if (bits >= 32 && mask == 0xFF) return;
532
533 if (bits == 16) {
534 if (mask == 0x0F)
535 return;
536 else if (mask == 0xF0) {
537 fprintf(fp, "'");
538 return;
539 }
540 }
541 }
542
543 fprintf(fp, ".");
544
545 unsigned skip = (bits / 16);
546 bool uppercase = bits > 32;
547 bool tripped = false;
548
549 /* To apply an upper destination override, we "shift" the alphabet.
550 * E.g. with an upper override on 32-bit, instead of xyzw, print efgh.
551 * For upper 16-bit, instead of xyzwefgh, print ijklmnop */
552
553 const char *alphabet = components;
554
555 if (override == midgard_dest_override_upper)
556 alphabet += (128 / bits);
557
558 for (unsigned i = 0; i < 8; i += skip) {
559 bool a = (mask & (1 << i)) != 0;
560
561 for (unsigned j = 1; j < skip; ++j) {
562 bool dupe = (mask & (1 << (i + j))) != 0;
563 tripped |= (dupe != a);
564 }
565
566 if (a) {
567 char c = alphabet[i / skip];
568
569 if (uppercase)
570 c = toupper(c);
571
572 fprintf(fp, "%c", c);
573 }
574 }
575
576 if (tripped)
577 fprintf(fp, " /* %X */", mask);
578 }
579
580 /* Prints the 4-bit masks found in texture and load/store ops, as opposed to
581 * the 8-bit masks found in (vector) ALU ops. Supports texture-style 16-bit
582 * mode as well, but not load/store-style 16-bit mode. */
583
584 static void
585 print_mask_4(FILE *fp, unsigned mask, bool upper)
586 {
587 if (mask == 0xF) {
588 if (upper)
589 fprintf(fp, "'");
590
591 return;
592 }
593
594 fprintf(fp, ".");
595
596 for (unsigned i = 0; i < 4; ++i) {
597 bool a = (mask & (1 << i)) != 0;
598 if (a)
599 fprintf(fp, "%c", components[i + (upper ? 4 : 0)]);
600 }
601 }
602
603 static void
604 print_vector_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_word,
605 const midgard_constants *consts, unsigned tabs)
606 {
607 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
608 midgard_vector_alu *alu_field = (midgard_vector_alu *) words;
609 midgard_reg_mode mode = alu_field->reg_mode;
610 unsigned override = alu_field->dest_override;
611
612 /* For now, prefix instruction names with their unit, until we
613 * understand how this works on a deeper level */
614 fprintf(fp, "%s.", name);
615
616 print_alu_opcode(fp, alu_field->op);
617
618 /* Postfix with the size to disambiguate if necessary */
619 char postfix = prefix_for_bits(bits_for_mode(mode));
620 bool size_ambiguous = override != midgard_dest_override_none;
621
622 if (size_ambiguous)
623 fprintf(fp, "%c", postfix ? postfix : 'r');
624
625 /* Print the outmod, if there is one */
626 print_outmod(fp, alu_field->outmod,
627 midgard_is_integer_out_op(alu_field->op));
628
629 fprintf(fp, " ");
630
631 /* Mask denoting status of 8-lanes */
632 uint8_t mask = alu_field->mask;
633
634 /* First, print the destination */
635 print_dest(fp, reg_info->out_reg, mode, alu_field->dest_override);
636
637 if (override != midgard_dest_override_none) {
638 bool modeable = (mode != midgard_reg_mode_8);
639 bool known = override != 0x3; /* Unused value */
640
641 if (!(modeable && known))
642 fprintf(fp, "/* do%u */ ", override);
643 }
644
645 print_mask(fp, mask, bits_for_mode(mode), override);
646
647 fprintf(fp, ", ");
648
649 bool is_int = midgard_is_integer_op(alu_field->op);
650
651 if (reg_info->src1_reg == 26)
652 print_vector_constants(fp, alu_field->src1, consts, alu_field);
653 else
654 print_vector_src(fp, alu_field->src1, mode, reg_info->src1_reg, override, is_int);
655
656 fprintf(fp, ", ");
657
658 if (reg_info->src2_imm) {
659 uint16_t imm = decode_vector_imm(reg_info->src2_reg, alu_field->src2 >> 2);
660 print_immediate(fp, imm);
661 } else if (reg_info->src2_reg == 26) {
662 print_vector_constants(fp, alu_field->src2, consts, alu_field);
663 } else {
664 print_vector_src(fp, alu_field->src2, mode,
665 reg_info->src2_reg, override, is_int);
666 }
667
668 midg_stats.instruction_count++;
669 fprintf(fp, "\n");
670 }
671
672 static void
673 print_scalar_src(FILE *fp, unsigned src_binary, unsigned reg)
674 {
675 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
676
677 if (src->negate)
678 fprintf(fp, "-");
679
680 if (src->abs)
681 fprintf(fp, "abs(");
682
683 print_reg(fp, reg, src->full ? 32 : 16);
684
685 unsigned c = src->component;
686
687 if (src->full) {
688 assert((c & 1) == 0);
689 c >>= 1;
690 }
691
692 fprintf(fp, ".%c", components[c]);
693
694 if (src->abs)
695 fprintf(fp, ")");
696
697 }
698
699 static uint16_t
700 decode_scalar_imm(unsigned src2_reg, unsigned imm)
701 {
702 uint16_t ret;
703 ret = src2_reg << 11;
704 ret |= (imm & 3) << 9;
705 ret |= (imm & 4) << 6;
706 ret |= (imm & 0x38) << 2;
707 ret |= imm >> 6;
708 return ret;
709 }
710
711 static void
712 print_scalar_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_word,
713 const midgard_constants *consts, unsigned tabs)
714 {
715 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
716 midgard_scalar_alu *alu_field = (midgard_scalar_alu *) words;
717
718 if (alu_field->unknown)
719 fprintf(fp, "scalar ALU unknown bit set\n");
720
721 fprintf(fp, "%s.", name);
722 print_alu_opcode(fp, alu_field->op);
723 print_outmod(fp, alu_field->outmod,
724 midgard_is_integer_out_op(alu_field->op));
725 fprintf(fp, " ");
726
727 bool full = alu_field->output_full;
728 update_dest(reg_info->out_reg);
729 print_reg(fp, reg_info->out_reg, full ? 32 : 16);
730 unsigned c = alu_field->output_component;
731
732 if (full) {
733 assert((c & 1) == 0);
734 c >>= 1;
735 }
736
737 fprintf(fp, ".%c, ", components[c]);
738
739 if (reg_info->src1_reg == 26)
740 print_scalar_constant(fp, alu_field->src1, consts, alu_field);
741 else
742 print_scalar_src(fp, alu_field->src1, reg_info->src1_reg);
743
744 fprintf(fp, ", ");
745
746 if (reg_info->src2_imm) {
747 uint16_t imm = decode_scalar_imm(reg_info->src2_reg,
748 alu_field->src2);
749 print_immediate(fp, imm);
750 } else if (reg_info->src2_reg == 26) {
751 print_scalar_constant(fp, alu_field->src2, consts, alu_field);
752 } else
753 print_scalar_src(fp, alu_field->src2, reg_info->src2_reg);
754
755 midg_stats.instruction_count++;
756 fprintf(fp, "\n");
757 }
758
759 static void
760 print_branch_op(FILE *fp, unsigned op)
761 {
762 switch (op) {
763 case midgard_jmp_writeout_op_branch_uncond:
764 fprintf(fp, "uncond.");
765 break;
766
767 case midgard_jmp_writeout_op_branch_cond:
768 fprintf(fp, "cond.");
769 break;
770
771 case midgard_jmp_writeout_op_writeout:
772 fprintf(fp, "write.");
773 break;
774
775 case midgard_jmp_writeout_op_tilebuffer_pending:
776 fprintf(fp, "tilebuffer.");
777 break;
778
779 case midgard_jmp_writeout_op_discard:
780 fprintf(fp, "discard.");
781 break;
782
783 default:
784 fprintf(fp, "unk%u.", op);
785 break;
786 }
787 }
788
789 static void
790 print_branch_cond(FILE *fp, int cond)
791 {
792 switch (cond) {
793 case midgard_condition_write0:
794 fprintf(fp, "write0");
795 break;
796
797 case midgard_condition_false:
798 fprintf(fp, "false");
799 break;
800
801 case midgard_condition_true:
802 fprintf(fp, "true");
803 break;
804
805 case midgard_condition_always:
806 fprintf(fp, "always");
807 break;
808
809 default:
810 fprintf(fp, "unk%X", cond);
811 break;
812 }
813 }
814
815 static bool
816 print_compact_branch_writeout_field(FILE *fp, uint16_t word)
817 {
818 midgard_jmp_writeout_op op = word & 0x7;
819 midg_stats.instruction_count++;
820
821 switch (op) {
822 case midgard_jmp_writeout_op_branch_uncond: {
823 midgard_branch_uncond br_uncond;
824 memcpy((char *) &br_uncond, (char *) &word, sizeof(br_uncond));
825 fprintf(fp, "br.uncond ");
826
827 if (br_uncond.unknown != 1)
828 fprintf(fp, "unknown:%u, ", br_uncond.unknown);
829
830 if (br_uncond.offset >= 0)
831 fprintf(fp, "+");
832
833 fprintf(fp, "%d -> ", br_uncond.offset);
834 print_tag_short(fp, br_uncond.dest_tag);
835 fprintf(fp, "\n");
836
837 return br_uncond.offset >= 0;
838 }
839
840 case midgard_jmp_writeout_op_branch_cond:
841 case midgard_jmp_writeout_op_writeout:
842 case midgard_jmp_writeout_op_discard:
843 default: {
844 midgard_branch_cond br_cond;
845 memcpy((char *) &br_cond, (char *) &word, sizeof(br_cond));
846
847 fprintf(fp, "br.");
848
849 print_branch_op(fp, br_cond.op);
850 print_branch_cond(fp, br_cond.cond);
851
852 fprintf(fp, " ");
853
854 if (br_cond.offset >= 0)
855 fprintf(fp, "+");
856
857 fprintf(fp, "%d -> ", br_cond.offset);
858 print_tag_short(fp, br_cond.dest_tag);
859 fprintf(fp, "\n");
860
861 return br_cond.offset >= 0;
862 }
863 }
864
865 return false;
866 }
867
868 static bool
869 print_extended_branch_writeout_field(FILE *fp, uint8_t *words, unsigned next)
870 {
871 midgard_branch_extended br;
872 memcpy((char *) &br, (char *) words, sizeof(br));
873
874 fprintf(fp, "brx.");
875
876 print_branch_op(fp, br.op);
877
878 /* Condition codes are a LUT in the general case, but simply repeated 8 times for single-channel conditions.. Check this. */
879
880 bool single_channel = true;
881
882 for (unsigned i = 0; i < 16; i += 2) {
883 single_channel &= (((br.cond >> i) & 0x3) == (br.cond & 0x3));
884 }
885
886 if (single_channel)
887 print_branch_cond(fp, br.cond & 0x3);
888 else
889 fprintf(fp, "lut%X", br.cond);
890
891 if (br.unknown)
892 fprintf(fp, ".unknown%u", br.unknown);
893
894 fprintf(fp, " ");
895
896 if (br.offset >= 0)
897 fprintf(fp, "+");
898
899 fprintf(fp, "%d -> ", br.offset);
900 print_tag_short(fp, br.dest_tag);
901 fprintf(fp, "\n");
902
903 unsigned I = next + br.offset * 4;
904
905 if (midg_tags[I] && midg_tags[I] != br.dest_tag) {
906 fprintf(fp, "\t/* XXX TAG ERROR: jumping to ");
907 print_tag_short(fp, br.dest_tag);
908 fprintf(fp, " but tagged ");
909 print_tag_short(fp, midg_tags[I]);
910 fprintf(fp, " */\n");
911 }
912
913 midg_tags[I] = br.dest_tag;
914
915 midg_stats.instruction_count++;
916 return br.offset >= 0;
917 }
918
919 static unsigned
920 num_alu_fields_enabled(uint32_t control_word)
921 {
922 unsigned ret = 0;
923
924 if ((control_word >> 17) & 1)
925 ret++;
926
927 if ((control_word >> 19) & 1)
928 ret++;
929
930 if ((control_word >> 21) & 1)
931 ret++;
932
933 if ((control_word >> 23) & 1)
934 ret++;
935
936 if ((control_word >> 25) & 1)
937 ret++;
938
939 return ret;
940 }
941
942 static bool
943 print_alu_word(FILE *fp, uint32_t *words, unsigned num_quad_words,
944 unsigned tabs, unsigned next)
945 {
946 uint32_t control_word = words[0];
947 uint16_t *beginning_ptr = (uint16_t *)(words + 1);
948 unsigned num_fields = num_alu_fields_enabled(control_word);
949 uint16_t *word_ptr = beginning_ptr + num_fields;
950 unsigned num_words = 2 + num_fields;
951 const midgard_constants *consts = NULL;
952 bool branch_forward = false;
953
954 if ((control_word >> 17) & 1)
955 num_words += 3;
956
957 if ((control_word >> 19) & 1)
958 num_words += 2;
959
960 if ((control_word >> 21) & 1)
961 num_words += 3;
962
963 if ((control_word >> 23) & 1)
964 num_words += 2;
965
966 if ((control_word >> 25) & 1)
967 num_words += 3;
968
969 if ((control_word >> 26) & 1)
970 num_words += 1;
971
972 if ((control_word >> 27) & 1)
973 num_words += 3;
974
975 if (num_quad_words > (num_words + 7) / 8) {
976 assert(num_quad_words == (num_words + 15) / 8);
977 //Assume that the extra quadword is constants
978 consts = (midgard_constants *)(words + (4 * num_quad_words - 4));
979 }
980
981 if ((control_word >> 16) & 1)
982 fprintf(fp, "unknown bit 16 enabled\n");
983
984 if ((control_word >> 17) & 1) {
985 print_vector_field(fp, "vmul", word_ptr, *beginning_ptr, consts, tabs);
986 beginning_ptr += 1;
987 word_ptr += 3;
988 }
989
990 if ((control_word >> 18) & 1)
991 fprintf(fp, "unknown bit 18 enabled\n");
992
993 if ((control_word >> 19) & 1) {
994 print_scalar_field(fp, "sadd", word_ptr, *beginning_ptr, consts, tabs);
995 beginning_ptr += 1;
996 word_ptr += 2;
997 }
998
999 if ((control_word >> 20) & 1)
1000 fprintf(fp, "unknown bit 20 enabled\n");
1001
1002 if ((control_word >> 21) & 1) {
1003 print_vector_field(fp, "vadd", word_ptr, *beginning_ptr, consts, tabs);
1004 beginning_ptr += 1;
1005 word_ptr += 3;
1006 }
1007
1008 if ((control_word >> 22) & 1)
1009 fprintf(fp, "unknown bit 22 enabled\n");
1010
1011 if ((control_word >> 23) & 1) {
1012 print_scalar_field(fp, "smul", word_ptr, *beginning_ptr, consts, tabs);
1013 beginning_ptr += 1;
1014 word_ptr += 2;
1015 }
1016
1017 if ((control_word >> 24) & 1)
1018 fprintf(fp, "unknown bit 24 enabled\n");
1019
1020 if ((control_word >> 25) & 1) {
1021 print_vector_field(fp, "lut", word_ptr, *beginning_ptr, consts, tabs);
1022 word_ptr += 3;
1023 }
1024
1025 if ((control_word >> 26) & 1) {
1026 branch_forward |= print_compact_branch_writeout_field(fp, *word_ptr);
1027 word_ptr += 1;
1028 }
1029
1030 if ((control_word >> 27) & 1) {
1031 branch_forward |= print_extended_branch_writeout_field(fp, (uint8_t *) word_ptr, next);
1032 word_ptr += 3;
1033 }
1034
1035 if (consts)
1036 fprintf(fp, "uconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
1037 consts->u32[0], consts->u32[1],
1038 consts->u32[2], consts->u32[3]);
1039
1040 return branch_forward;
1041 }
1042
1043 static void
1044 print_varying_parameters(FILE *fp, midgard_load_store_word *word)
1045 {
1046 midgard_varying_parameter param;
1047 unsigned v = word->varying_parameters;
1048 memcpy(&param, &v, sizeof(param));
1049
1050 if (param.is_varying) {
1051 /* If a varying, there are qualifiers */
1052 if (param.flat)
1053 fprintf(fp, ".flat");
1054
1055 if (param.interpolation != midgard_interp_default) {
1056 if (param.interpolation == midgard_interp_centroid)
1057 fprintf(fp, ".centroid");
1058 else
1059 fprintf(fp, ".interp%d", param.interpolation);
1060 }
1061
1062 if (param.modifier != midgard_varying_mod_none) {
1063 if (param.modifier == midgard_varying_mod_perspective_w)
1064 fprintf(fp, ".perspectivew");
1065 else if (param.modifier == midgard_varying_mod_perspective_z)
1066 fprintf(fp, ".perspectivez");
1067 else
1068 fprintf(fp, ".mod%d", param.modifier);
1069 }
1070 } else if (param.flat || param.interpolation || param.modifier) {
1071 fprintf(fp, " /* is_varying not set but varying metadata attached */");
1072 }
1073
1074 if (param.zero0 || param.zero1 || param.zero2)
1075 fprintf(fp, " /* zero tripped, %u %u %u */ ", param.zero0, param.zero1, param.zero2);
1076 }
1077
1078 static bool
1079 is_op_varying(unsigned op)
1080 {
1081 switch (op) {
1082 case midgard_op_st_vary_16:
1083 case midgard_op_st_vary_32:
1084 case midgard_op_st_vary_32i:
1085 case midgard_op_st_vary_32u:
1086 case midgard_op_ld_vary_16:
1087 case midgard_op_ld_vary_32:
1088 case midgard_op_ld_vary_32i:
1089 case midgard_op_ld_vary_32u:
1090 return true;
1091 }
1092
1093 return false;
1094 }
1095
1096 static bool
1097 is_op_attribute(unsigned op)
1098 {
1099 switch (op) {
1100 case midgard_op_ld_attr_16:
1101 case midgard_op_ld_attr_32:
1102 case midgard_op_ld_attr_32i:
1103 case midgard_op_ld_attr_32u:
1104 return true;
1105 }
1106
1107 return false;
1108 }
1109
1110 static void
1111 print_load_store_arg(FILE *fp, uint8_t arg, unsigned index)
1112 {
1113 /* Try to interpret as a register */
1114 midgard_ldst_register_select sel;
1115 memcpy(&sel, &arg, sizeof(arg));
1116
1117 /* If unknown is set, we're not sure what this is or how to
1118 * interpret it. But if it's zero, we get it. */
1119
1120 if (sel.unknown) {
1121 fprintf(fp, "0x%02X", arg);
1122 return;
1123 }
1124
1125 unsigned reg = REGISTER_LDST_BASE + sel.select;
1126 char comp = components[sel.component];
1127
1128 fprintf(fp, "r%u.%c", reg, comp);
1129
1130 /* Only print a shift if it's non-zero. Shifts only make sense for the
1131 * second index. For the first, we're not sure what it means yet */
1132
1133 if (index == 1) {
1134 if (sel.shift)
1135 fprintf(fp, " << %u", sel.shift);
1136 } else {
1137 fprintf(fp, " /* %X */", sel.shift);
1138 }
1139 }
1140
1141 static void
1142 update_stats(signed *stat, unsigned address)
1143 {
1144 if (*stat >= 0)
1145 *stat = MAX2(*stat, address + 1);
1146 }
1147
1148 static void
1149 print_load_store_instr(FILE *fp, uint64_t data,
1150 unsigned tabs)
1151 {
1152 midgard_load_store_word *word = (midgard_load_store_word *) &data;
1153
1154 print_ld_st_opcode(fp, word->op);
1155
1156 unsigned address = word->address;
1157
1158 if (is_op_varying(word->op)) {
1159 print_varying_parameters(fp, word);
1160
1161 /* Do some analysis: check if direct cacess */
1162
1163 if ((word->arg_2 == 0x1E) && midg_stats.varying_count >= 0)
1164 update_stats(&midg_stats.varying_count, address);
1165 else
1166 midg_stats.varying_count = -16;
1167 } else if (is_op_attribute(word->op)) {
1168 if ((word->arg_2 == 0x1E) && midg_stats.attribute_count >= 0)
1169 update_stats(&midg_stats.attribute_count, address);
1170 else
1171 midg_stats.attribute_count = -16;
1172 }
1173
1174 fprintf(fp, " r%u", word->reg + (OP_IS_STORE(word->op) ? 26 : 0));
1175 print_mask_4(fp, word->mask, false);
1176
1177 if (!OP_IS_STORE(word->op))
1178 update_dest(word->reg);
1179
1180 bool is_ubo = OP_IS_UBO_READ(word->op);
1181
1182 if (is_ubo) {
1183 /* UBOs use their own addressing scheme */
1184
1185 int lo = word->varying_parameters >> 7;
1186 int hi = word->address;
1187
1188 /* TODO: Combine fields logically */
1189 address = (hi << 3) | lo;
1190 }
1191
1192 fprintf(fp, ", %u", address);
1193
1194 print_swizzle_vec4(fp, word->swizzle, false, false);
1195
1196 fprintf(fp, ", ");
1197
1198 if (is_ubo) {
1199 fprintf(fp, "ubo%u", word->arg_1);
1200 update_stats(&midg_stats.uniform_buffer_count, word->arg_1);
1201 } else
1202 print_load_store_arg(fp, word->arg_1, 0);
1203
1204 fprintf(fp, ", ");
1205 print_load_store_arg(fp, word->arg_2, 1);
1206 fprintf(fp, " /* %X */\n", word->varying_parameters);
1207
1208 midg_stats.instruction_count++;
1209 }
1210
1211 static void
1212 print_load_store_word(FILE *fp, uint32_t *word, unsigned tabs)
1213 {
1214 midgard_load_store *load_store = (midgard_load_store *) word;
1215
1216 if (load_store->word1 != 3) {
1217 print_load_store_instr(fp, load_store->word1, tabs);
1218 }
1219
1220 if (load_store->word2 != 3) {
1221 print_load_store_instr(fp, load_store->word2, tabs);
1222 }
1223 }
1224
1225 static void
1226 print_texture_reg_select(FILE *fp, uint8_t u, unsigned base)
1227 {
1228 midgard_tex_register_select sel;
1229 memcpy(&sel, &u, sizeof(u));
1230
1231 if (!sel.full)
1232 fprintf(fp, "h");
1233
1234 fprintf(fp, "r%u", base + sel.select);
1235
1236 unsigned component = sel.component;
1237
1238 /* Use the upper half in half-reg mode */
1239 if (sel.upper) {
1240 assert(!sel.full);
1241 component += 4;
1242 }
1243
1244 fprintf(fp, ".%c", components[component]);
1245
1246 assert(sel.zero == 0);
1247 }
1248
1249 static void
1250 print_texture_format(FILE *fp, int format)
1251 {
1252 /* Act like a modifier */
1253 fprintf(fp, ".");
1254
1255 switch (format) {
1256 DEFINE_CASE(MALI_TEX_1D, "1d");
1257 DEFINE_CASE(MALI_TEX_2D, "2d");
1258 DEFINE_CASE(MALI_TEX_3D, "3d");
1259 DEFINE_CASE(MALI_TEX_CUBE, "cube");
1260
1261 default:
1262 unreachable("Bad format");
1263 }
1264 }
1265
1266 static bool
1267 midgard_op_has_helpers(unsigned op, bool gather)
1268 {
1269 if (gather)
1270 return true;
1271
1272 switch (op) {
1273 case TEXTURE_OP_NORMAL:
1274 case TEXTURE_OP_DFDX:
1275 case TEXTURE_OP_DFDY:
1276 return true;
1277 default:
1278 return false;
1279 }
1280 }
1281
1282 static void
1283 print_texture_op(FILE *fp, unsigned op, bool gather)
1284 {
1285 /* Act like a bare name, like ESSL functions */
1286
1287 if (gather) {
1288 fprintf(fp, "textureGather");
1289
1290 unsigned component = op >> 4;
1291 unsigned bottom = op & 0xF;
1292
1293 if (bottom != 0x2)
1294 fprintf(fp, "_unk%u", bottom);
1295
1296 fprintf(fp, ".%c", components[component]);
1297 return;
1298 }
1299
1300 switch (op) {
1301 DEFINE_CASE(TEXTURE_OP_NORMAL, "texture");
1302 DEFINE_CASE(TEXTURE_OP_LOD, "textureLod");
1303 DEFINE_CASE(TEXTURE_OP_TEXEL_FETCH, "texelFetch");
1304 DEFINE_CASE(TEXTURE_OP_BARRIER, "barrier");
1305 DEFINE_CASE(TEXTURE_OP_DFDX, "dFdx");
1306 DEFINE_CASE(TEXTURE_OP_DFDY, "dFdy");
1307
1308 default:
1309 fprintf(fp, "tex_%X", op);
1310 break;
1311 }
1312 }
1313
1314 static bool
1315 texture_op_takes_bias(unsigned op)
1316 {
1317 return op == TEXTURE_OP_NORMAL;
1318 }
1319
1320 static char
1321 sampler_type_name(enum mali_sampler_type t)
1322 {
1323 switch (t) {
1324 case MALI_SAMPLER_FLOAT:
1325 return 'f';
1326 case MALI_SAMPLER_UNSIGNED:
1327 return 'u';
1328 case MALI_SAMPLER_SIGNED:
1329 return 'i';
1330 default:
1331 return '?';
1332 }
1333
1334 }
1335
1336 static void
1337 print_texture_barrier(FILE *fp, uint32_t *word)
1338 {
1339 midgard_texture_barrier_word *barrier = (midgard_texture_barrier_word *) word;
1340
1341 if (barrier->type != 0x4)
1342 fprintf(fp, "/* barrier tag %X != 0x4 */ ", barrier->type);
1343
1344 if (!barrier->cont)
1345 fprintf(fp, "/* cont missing? */");
1346
1347 if (!barrier->last)
1348 fprintf(fp, "/* last missing? */");
1349
1350 if (barrier->zero1)
1351 fprintf(fp, "/* zero1 = 0x%X */ ", barrier->zero1);
1352
1353 if (barrier->zero2)
1354 fprintf(fp, "/* zero2 = 0x%X */ ", barrier->zero2);
1355
1356 if (barrier->zero3)
1357 fprintf(fp, "/* zero3 = 0x%X */ ", barrier->zero3);
1358
1359 if (barrier->zero4)
1360 fprintf(fp, "/* zero4 = 0x%X */ ", barrier->zero4);
1361
1362 if (barrier->zero5)
1363 fprintf(fp, "/* zero4 = 0x%" PRIx64 " */ ", barrier->zero5);
1364
1365 fprintf(fp, " 0x%X\n", barrier->unknown4);
1366 }
1367
1368 #undef DEFINE_CASE
1369
1370 static void
1371 print_texture_word(FILE *fp, uint32_t *word, unsigned tabs, unsigned in_reg_base, unsigned out_reg_base)
1372 {
1373 midgard_texture_word *texture = (midgard_texture_word *) word;
1374
1375 midg_stats.helper_invocations |=
1376 midgard_op_has_helpers(texture->op, texture->is_gather);
1377
1378 /* Broad category of texture operation in question */
1379 print_texture_op(fp, texture->op, texture->is_gather);
1380
1381 /* Barriers use a dramatically different code path */
1382 if (texture->op == TEXTURE_OP_BARRIER) {
1383 print_texture_barrier(fp, word);
1384 return;
1385 } else if (texture->type == 0x4)
1386 fprintf (fp, "/* nonbarrier had tag 0x4 */ ");
1387
1388 /* Specific format in question */
1389 print_texture_format(fp, texture->format);
1390
1391 /* Instruction "modifiers" parallel the ALU instructions. */
1392
1393 if (texture->shadow)
1394 fprintf(fp, ".shadow");
1395
1396 if (texture->cont)
1397 fprintf(fp, ".cont");
1398
1399 if (texture->last)
1400 fprintf(fp, ".last");
1401
1402 /* Output modifiers are always interpreted floatly */
1403 print_outmod(fp, texture->outmod, false);
1404
1405 fprintf(fp, " %sr%u", texture->out_full ? "" : "h",
1406 out_reg_base + texture->out_reg_select);
1407 print_mask_4(fp, texture->mask, texture->out_upper);
1408 assert(!(texture->out_full && texture->out_upper));
1409 fprintf(fp, ", ");
1410
1411 /* Depending on whether we read from textures directly or indirectly,
1412 * we may be able to update our analysis */
1413
1414 if (texture->texture_register) {
1415 fprintf(fp, "texture[");
1416 print_texture_reg_select(fp, texture->texture_handle, in_reg_base);
1417 fprintf(fp, "], ");
1418
1419 /* Indirect, tut tut */
1420 midg_stats.texture_count = -16;
1421 } else {
1422 fprintf(fp, "texture%u, ", texture->texture_handle);
1423 update_stats(&midg_stats.texture_count, texture->texture_handle);
1424 }
1425
1426 /* Print the type, GL style */
1427 fprintf(fp, "%csampler", sampler_type_name(texture->sampler_type));
1428
1429 if (texture->sampler_register) {
1430 fprintf(fp, "[");
1431 print_texture_reg_select(fp, texture->sampler_handle, in_reg_base);
1432 fprintf(fp, "]");
1433
1434 midg_stats.sampler_count = -16;
1435 } else {
1436 fprintf(fp, "%u", texture->sampler_handle);
1437 update_stats(&midg_stats.sampler_count, texture->sampler_handle);
1438 }
1439
1440 print_swizzle_vec4(fp, texture->swizzle, false, false);
1441 fprintf(fp, ", %sr%u", texture->in_reg_full ? "" : "h", in_reg_base + texture->in_reg_select);
1442 assert(!(texture->in_reg_full && texture->in_reg_upper));
1443
1444 /* TODO: integrate with swizzle */
1445 if (texture->in_reg_upper)
1446 fprintf(fp, "'");
1447
1448 print_swizzle_vec4(fp, texture->in_reg_swizzle, false, false);
1449
1450 /* There is *always* an offset attached. Of
1451 * course, that offset is just immediate #0 for a
1452 * GLES call that doesn't take an offset. If there
1453 * is a non-negative non-zero offset, this is
1454 * specified in immediate offset mode, with the
1455 * values in the offset_* fields as immediates. If
1456 * this is a negative offset, we instead switch to
1457 * a register offset mode, where the offset_*
1458 * fields become register triplets */
1459
1460 if (texture->offset_register) {
1461 fprintf(fp, " + ");
1462
1463 bool full = texture->offset & 1;
1464 bool select = texture->offset & 2;
1465 bool upper = texture->offset & 4;
1466
1467 fprintf(fp, "%sr%u", full ? "" : "h", in_reg_base + select);
1468 assert(!(texture->out_full && texture->out_upper));
1469
1470 /* TODO: integrate with swizzle */
1471 if (upper)
1472 fprintf(fp, "'");
1473
1474 print_swizzle_vec4(fp, texture->offset >> 3, false, false);
1475
1476 fprintf(fp, ", ");
1477 } else if (texture->offset) {
1478 /* Only select ops allow negative immediate offsets, verify */
1479
1480 signed offset_x = (texture->offset & 0xF);
1481 signed offset_y = ((texture->offset >> 4) & 0xF);
1482 signed offset_z = ((texture->offset >> 8) & 0xF);
1483
1484 bool neg_x = offset_x < 0;
1485 bool neg_y = offset_y < 0;
1486 bool neg_z = offset_z < 0;
1487 bool any_neg = neg_x || neg_y || neg_z;
1488
1489 if (any_neg && texture->op != TEXTURE_OP_TEXEL_FETCH)
1490 fprintf(fp, "/* invalid negative */ ");
1491
1492 /* Regardless, just print the immediate offset */
1493
1494 fprintf(fp, " + <%d, %d, %d>, ", offset_x, offset_y, offset_z);
1495 } else {
1496 fprintf(fp, ", ");
1497 }
1498
1499 char lod_operand = texture_op_takes_bias(texture->op) ? '+' : '=';
1500
1501 if (texture->lod_register) {
1502 fprintf(fp, "lod %c ", lod_operand);
1503 print_texture_reg_select(fp, texture->bias, in_reg_base);
1504 fprintf(fp, ", ");
1505
1506 if (texture->bias_int)
1507 fprintf(fp, " /* bias_int = 0x%X */", texture->bias_int);
1508 } else if (texture->op == TEXTURE_OP_TEXEL_FETCH) {
1509 /* For texel fetch, the int LOD is in the fractional place and
1510 * there is no fraction / possibility of bias. We *always* have
1511 * an explicit LOD, even if it's zero. */
1512
1513 if (texture->bias_int)
1514 fprintf(fp, " /* bias_int = 0x%X */ ", texture->bias_int);
1515
1516 fprintf(fp, "lod = %u, ", texture->bias);
1517 } else if (texture->bias || texture->bias_int) {
1518 signed bias_int = texture->bias_int;
1519 float bias_frac = texture->bias / 256.0f;
1520 float bias = bias_int + bias_frac;
1521
1522 bool is_bias = texture_op_takes_bias(texture->op);
1523 char sign = (bias >= 0.0) ? '+' : '-';
1524 char operand = is_bias ? sign : '=';
1525
1526 fprintf(fp, "lod %c %f, ", operand, fabsf(bias));
1527 }
1528
1529 fprintf(fp, "\n");
1530
1531 /* While not zero in general, for these simple instructions the
1532 * following unknowns are zero, so we don't include them */
1533
1534 if (texture->unknown4 ||
1535 texture->unknownA ||
1536 texture->unknown8) {
1537 fprintf(fp, "// unknown4 = 0x%x\n", texture->unknown4);
1538 fprintf(fp, "// unknownA = 0x%x\n", texture->unknownA);
1539 fprintf(fp, "// unknown8 = 0x%x\n", texture->unknown8);
1540 }
1541
1542 midg_stats.instruction_count++;
1543 }
1544
1545 struct midgard_disasm_stats
1546 disassemble_midgard(FILE *fp, uint8_t *code, size_t size, unsigned gpu_id, gl_shader_stage stage)
1547 {
1548 uint32_t *words = (uint32_t *) code;
1549 unsigned num_words = size / 4;
1550 int tabs = 0;
1551
1552 bool branch_forward = false;
1553
1554 int last_next_tag = -1;
1555
1556 unsigned i = 0;
1557
1558 midg_tags = calloc(sizeof(midg_tags[0]), num_words);
1559
1560 /* Stats for shader-db */
1561 memset(&midg_stats, 0, sizeof(midg_stats));
1562 midg_ever_written = 0;
1563
1564 while (i < num_words) {
1565 unsigned tag = words[i] & 0xF;
1566 unsigned next_tag = (words[i] >> 4) & 0xF;
1567 fprintf(fp, "\t%X -> %X\n", tag, next_tag);
1568 unsigned num_quad_words = midgard_word_size[tag];
1569
1570 if (midg_tags[i] && midg_tags[i] != tag) {
1571 fprintf(fp, "\t/* XXX: TAG ERROR branch, got ");
1572 print_tag_short(fp, tag);
1573 fprintf(fp, " expected ");
1574 print_tag_short(fp, midg_tags[i]);
1575 fprintf(fp, " */\n");
1576 }
1577
1578 midg_tags[i] = tag;
1579
1580 /* Check the tag */
1581 if (last_next_tag > 1) {
1582 if (last_next_tag != tag) {
1583 fprintf(fp, "\t/* XXX: TAG ERROR sequence, got ");
1584 print_tag_short(fp, tag);
1585 fprintf(fp, " expected ");
1586 print_tag_short(fp, last_next_tag);
1587 fprintf(fp, " */\n");
1588 }
1589 } else {
1590 /* TODO: Check ALU case */
1591 }
1592
1593 last_next_tag = next_tag;
1594
1595 switch (midgard_word_types[tag]) {
1596 case midgard_word_type_texture: {
1597 bool interpipe_aliasing =
1598 midgard_get_quirks(gpu_id) & MIDGARD_INTERPIPE_REG_ALIASING;
1599
1600 print_texture_word(fp, &words[i], tabs,
1601 interpipe_aliasing ? 0 : REG_TEX_BASE,
1602 interpipe_aliasing ? REGISTER_LDST_BASE : REG_TEX_BASE);
1603 break;
1604 }
1605
1606 case midgard_word_type_load_store:
1607 print_load_store_word(fp, &words[i], tabs);
1608 break;
1609
1610 case midgard_word_type_alu:
1611 branch_forward = print_alu_word(fp, &words[i], num_quad_words, tabs, i + 4*num_quad_words);
1612
1613 /* Reset word static analysis state */
1614 is_embedded_constant_half = false;
1615 is_embedded_constant_int = false;
1616
1617 break;
1618
1619 default:
1620 fprintf(fp, "Unknown word type %u:\n", words[i] & 0xF);
1621 num_quad_words = 1;
1622 print_quad_word(fp, &words[i], tabs);
1623 fprintf(fp, "\n");
1624 break;
1625 }
1626
1627 /* We are parsing per bundle anyway. Add before we start
1628 * breaking out so we don't miss the final bundle. */
1629
1630 midg_stats.bundle_count++;
1631 midg_stats.quadword_count += num_quad_words;
1632
1633 fprintf(fp, "\n");
1634
1635 unsigned next = (words[i] & 0xF0) >> 4;
1636
1637 if (i < num_words && next == 1 && !branch_forward)
1638 break;
1639
1640 i += 4 * num_quad_words;
1641 }
1642
1643 free(midg_tags);
1644
1645 /* We computed work_count as max_work_registers, so add one to get the
1646 * count. If no work registers are written, you still have one work
1647 * reported, which is exactly what the hardware expects */
1648
1649 midg_stats.work_count++;
1650
1651 return midg_stats;
1652 }