5 * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
6 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
35 #include "midgard_ops.h"
36 #include "midgard_quirks.h"
37 #include "disassemble.h"
39 #include "util/bitscan.h"
40 #include "util/half_float.h"
41 #include "util/u_math.h"
43 #define DEFINE_CASE(define, str) case define: { fprintf(fp, str); break; }
45 static unsigned *midg_tags
;
46 static bool is_instruction_int
= false;
50 static struct midgard_disasm_stats midg_stats
;
53 print_alu_opcode(FILE *fp
, midgard_alu_op op
)
57 if (alu_opcode_props
[op
].name
) {
58 fprintf(fp
, "%s", alu_opcode_props
[op
].name
);
60 int_op
= midgard_is_integer_op(op
);
62 fprintf(fp
, "alu_op_%02X", op
);
64 /* For constant analysis */
65 is_instruction_int
= int_op
;
69 print_ld_st_opcode(FILE *fp
, midgard_load_store_op op
)
71 if (load_store_opcode_props
[op
].name
)
72 fprintf(fp
, "%s", load_store_opcode_props
[op
].name
);
74 fprintf(fp
, "ldst_op_%02X", op
);
77 static bool is_embedded_constant_half
= false;
78 static bool is_embedded_constant_int
= false;
81 prefix_for_bits(unsigned bits
)
95 /* For static analysis to ensure all registers are written at least once before
96 * use along the source code path (TODO: does this break done for complex CF?)
99 uint16_t midg_ever_written
= 0;
102 print_reg(FILE *fp
, unsigned reg
, unsigned bits
)
104 /* Perform basic static analysis for expanding constants correctly */
107 is_embedded_constant_int
= is_instruction_int
;
108 is_embedded_constant_half
= (bits
< 32);
111 unsigned uniform_reg
= 23 - reg
;
112 bool is_uniform
= false;
114 /* For r8-r15, it could be a work or uniform. We distinguish based on
115 * the fact work registers are ALWAYS written before use, but uniform
116 * registers are NEVER written before use. */
118 if ((reg
>= 8 && reg
< 16) && !(midg_ever_written
& (1 << reg
)))
121 /* r16-r23 are always uniform */
123 if (reg
>= 16 && reg
<= 23)
126 /* Update the uniform count appropriately */
129 midg_stats
.uniform_count
=
130 MAX2(uniform_reg
+ 1, midg_stats
.uniform_count
);
132 char prefix
= prefix_for_bits(bits
);
137 fprintf(fp
, "r%u", reg
);
140 static char *outmod_names_float
[4] = {
147 static char *outmod_names_int
[4] = {
154 static char *srcmod_names_int
[4] = {
162 print_outmod(FILE *fp
, unsigned outmod
, bool is_int
)
164 fprintf(fp
, "%s", is_int
? outmod_names_int
[outmod
] :
165 outmod_names_float
[outmod
]);
169 print_quad_word(FILE *fp
, uint32_t *words
, unsigned tabs
)
173 for (i
= 0; i
< 4; i
++)
174 fprintf(fp
, "0x%08X%s ", words
[i
], i
== 3 ? "" : ",");
179 static const char components
[16] = "xyzwefghijklmnop";
181 /* Helper to print 4 chars of a swizzle */
183 print_swizzle_helper(FILE *fp
, unsigned swizzle
, unsigned offset
)
185 for (unsigned i
= 0; i
< 4; ++i
) {
186 unsigned c
= (swizzle
>> (i
* 2)) & 3;
188 fprintf(fp
, "%c", components
[c
]);
192 /* Helper to print 8 chars of a swizzle, duplicating over */
194 print_swizzle_helper_8(FILE *fp
, unsigned swizzle
, bool upper
)
196 for (unsigned i
= 0; i
< 4; ++i
) {
197 unsigned c
= (swizzle
>> (i
* 2)) & 3;
200 fprintf(fp
, "%c%c", components
[c
], components
[c
+1]);
205 print_swizzle_vec16(FILE *fp
, unsigned swizzle
, bool rep_high
, bool rep_low
,
206 midgard_dest_override override
)
210 if (override
== midgard_dest_override_upper
) {
212 fprintf(fp
, " /* rep_high */ ");
214 fprintf(fp
, " /* rep_low */ ");
216 if (!rep_high
&& rep_low
)
217 print_swizzle_helper_8(fp
, swizzle
, true);
219 print_swizzle_helper_8(fp
, swizzle
, false);
221 print_swizzle_helper_8(fp
, swizzle
, rep_high
& 1);
222 print_swizzle_helper_8(fp
, swizzle
, !(rep_low
& 1));
227 print_swizzle_vec8(FILE *fp
, unsigned swizzle
, bool rep_high
, bool rep_low
, bool half
)
231 /* TODO: Is it possible to unify half/full? */
234 print_swizzle_helper(fp
, swizzle
, (rep_low
* 8));
235 print_swizzle_helper(fp
, swizzle
, (rep_low
* 8) + !rep_high
* 4);
237 print_swizzle_helper(fp
, swizzle
, rep_high
* 4);
238 print_swizzle_helper(fp
, swizzle
, !rep_low
* 4);
243 print_swizzle_vec4(FILE *fp
, unsigned swizzle
, bool rep_high
, bool rep_low
, bool half
)
246 fprintf(fp
, " /* rep_high */ ");
248 if (!half
&& rep_low
)
249 fprintf(fp
, " /* rep_low */ ");
251 if (swizzle
== 0xE4 && !half
) return; /* xyzw */
254 print_swizzle_helper(fp
, swizzle
, rep_low
* 4);
257 print_swizzle_vec2(FILE *fp
, unsigned swizzle
, bool rep_high
, bool rep_low
, bool half
)
259 char *alphabet
= "XY";
262 alphabet
= rep_low
? "zw" : "xy";
264 fprintf(fp
, " /* rep_low */ ");
267 fprintf(fp
, " /* rep_high */ ");
269 if (swizzle
== 0xE4 && !half
) return; /* XY */
273 for (unsigned i
= 0; i
< 4; i
+= 2) {
274 unsigned a
= (swizzle
>> (i
* 2)) & 3;
275 unsigned b
= (swizzle
>> ((i
+1) * 2)) & 3;
277 /* Normally we're adjacent, but if there's an issue, don't make
281 fprintf(fp
, "%c", alphabet
[a
>> 1]);
283 fprintf(fp
, "[%c%c]", components
[a
], components
[b
]);
288 bits_for_mode(midgard_reg_mode mode
)
291 case midgard_reg_mode_8
:
293 case midgard_reg_mode_16
:
295 case midgard_reg_mode_32
:
297 case midgard_reg_mode_64
:
300 unreachable("Invalid reg mode");
306 bits_for_mode_halved(midgard_reg_mode mode
, bool half
)
308 unsigned bits
= bits_for_mode(mode
);
317 print_scalar_constant(FILE *fp
, unsigned src_binary
,
318 const midgard_constants
*consts
,
319 midgard_scalar_alu
*alu
)
321 midgard_scalar_alu_src
*src
= (midgard_scalar_alu_src
*)&src_binary
;
324 assert(consts
!= NULL
);
326 if (!midgard_is_integer_op(alu
->op
)) {
328 mod
|= MIDGARD_FLOAT_MOD_ABS
;
330 mod
|= MIDGARD_FLOAT_MOD_NEG
;
332 mod
= midgard_int_normal
;
336 mir_print_constant_component(fp
, consts
, src
->component
,
338 midgard_reg_mode_32
: midgard_reg_mode_16
,
339 false, mod
, alu
->op
);
343 print_vector_constants(FILE *fp
, unsigned src_binary
,
344 const midgard_constants
*consts
,
345 midgard_vector_alu
*alu
)
347 midgard_vector_alu_src
*src
= (midgard_vector_alu_src
*)&src_binary
;
348 unsigned bits
= bits_for_mode_halved(alu
->reg_mode
, src
->half
);
349 unsigned max_comp
= MIN2((sizeof(*consts
) * 8) / bits
, 8);
350 unsigned comp_mask
, num_comp
= 0;
354 comp_mask
= effective_writemask(alu
, condense_writemask(alu
->mask
, bits
));
355 num_comp
= util_bitcount(comp_mask
);
359 fprintf(fp
, "vec%d(", num_comp
);
363 for (unsigned i
= 0; i
< max_comp
; ++i
) {
364 if (!(comp_mask
& (1 << i
))) continue;
366 unsigned c
= (src
->swizzle
>> (i
* 2)) & 3;
373 mir_print_constant_component(fp
, consts
, c
, alu
->reg_mode
,
374 src
->half
, src
->mod
, alu
->op
);
382 print_vector_src(FILE *fp
, unsigned src_binary
,
383 midgard_reg_mode mode
, unsigned reg
,
384 midgard_dest_override override
, bool is_int
)
386 midgard_vector_alu_src
*src
= (midgard_vector_alu_src
*)&src_binary
;
388 /* Modifiers change meaning depending on the op's context */
390 midgard_int_mod int_mod
= src
->mod
;
393 fprintf(fp
, "%s", srcmod_names_int
[int_mod
]);
395 if (src
->mod
& MIDGARD_FLOAT_MOD_NEG
)
398 if (src
->mod
& MIDGARD_FLOAT_MOD_ABS
)
403 unsigned bits
= bits_for_mode_halved(mode
, src
->half
);
404 print_reg(fp
, reg
, bits
);
406 /* When the source was stepped down via `half`, rep_low means "higher
407 * half" and rep_high is never seen. When it's not native,
408 * rep_low/rep_high are for, well, replication */
410 if (mode
== midgard_reg_mode_8
) {
412 print_swizzle_vec16(fp
, src
->swizzle
, src
->rep_high
, src
->rep_low
, override
);
413 } else if (mode
== midgard_reg_mode_16
) {
414 print_swizzle_vec8(fp
, src
->swizzle
, src
->rep_high
, src
->rep_low
, src
->half
);
415 } else if (mode
== midgard_reg_mode_32
) {
416 print_swizzle_vec4(fp
, src
->swizzle
, src
->rep_high
, src
->rep_low
, src
->half
);
417 } else if (mode
== midgard_reg_mode_64
) {
418 print_swizzle_vec2(fp
, src
->swizzle
, src
->rep_high
, src
->rep_low
, src
->half
);
421 /* Since we wrapped with a function-looking thing */
423 if (is_int
&& int_mod
== midgard_int_shift
)
424 fprintf(fp
, ") << %u", bits
);
425 else if ((is_int
&& (int_mod
!= midgard_int_normal
))
426 || (!is_int
&& src
->mod
& MIDGARD_FLOAT_MOD_ABS
))
431 decode_vector_imm(unsigned src2_reg
, unsigned imm
)
434 ret
= src2_reg
<< 11;
435 ret
|= (imm
& 0x7) << 8;
436 ret
|= (imm
>> 3) & 0xFF;
441 print_immediate(FILE *fp
, uint16_t imm
)
443 if (is_instruction_int
)
444 fprintf(fp
, "#%u", imm
);
446 fprintf(fp
, "#%g", _mesa_half_to_float(imm
));
450 update_dest(unsigned reg
)
452 /* We should record writes as marking this as a work register. Store
453 * the max register in work_count; we'll add one at the end */
456 midg_stats
.work_count
= MAX2(reg
, midg_stats
.work_count
);
457 midg_ever_written
|= (1 << reg
);
462 print_dest(FILE *fp
, unsigned reg
, midgard_reg_mode mode
, midgard_dest_override override
)
464 /* Depending on the mode and override, we determine the type of
465 * destination addressed. Absent an override, we address just the
466 * type of the operation itself */
468 unsigned bits
= bits_for_mode(mode
);
470 if (override
!= midgard_dest_override_none
)
474 print_reg(fp
, reg
, bits
);
478 print_mask_vec16(FILE *fp
, uint8_t mask
, midgard_dest_override override
)
482 for (unsigned i
= 0; i
< 8; i
++) {
486 components
[i
*2 + 1]);
490 /* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
491 * it's just one bit per channel, easy peasy. For 32-bit (vec4), it's one bit
492 * per channel with one duplicate bit in the middle. For 64-bit (vec2), it's
493 * one-bit per channel with _3_ duplicate bits in the middle. Basically, just
494 * subdividing the 128-bit word in 16-bit increments. For 64-bit, we uppercase
495 * the mask to make it obvious what happened */
498 print_mask(FILE *fp
, uint8_t mask
, unsigned bits
, midgard_dest_override override
)
501 print_mask_vec16(fp
, mask
, override
);
505 /* Skip 'complete' masks */
507 if (override
== midgard_dest_override_none
)
508 if (bits
>= 32 && mask
== 0xFF) return;
512 unsigned skip
= (bits
/ 16);
513 bool uppercase
= bits
> 32;
514 bool tripped
= false;
516 /* To apply an upper destination override, we "shift" the alphabet.
517 * E.g. with an upper override on 32-bit, instead of xyzw, print efgh.
518 * For upper 16-bit, instead of xyzwefgh, print ijklmnop */
520 const char *alphabet
= components
;
522 if (override
== midgard_dest_override_upper
)
523 alphabet
+= (128 / bits
);
525 for (unsigned i
= 0; i
< 8; i
+= skip
) {
526 bool a
= (mask
& (1 << i
)) != 0;
528 for (unsigned j
= 1; j
< skip
; ++j
) {
529 bool dupe
= (mask
& (1 << (i
+ j
))) != 0;
530 tripped
|= (dupe
!= a
);
534 char c
= alphabet
[i
/ skip
];
539 fprintf(fp
, "%c", c
);
544 fprintf(fp
, " /* %X */", mask
);
547 /* Prints the 4-bit masks found in texture and load/store ops, as opposed to
548 * the 8-bit masks found in (vector) ALU ops. Supports texture-style 16-bit
549 * mode as well, but not load/store-style 16-bit mode. */
552 print_mask_4(FILE *fp
, unsigned mask
, bool upper
)
563 for (unsigned i
= 0; i
< 4; ++i
) {
564 bool a
= (mask
& (1 << i
)) != 0;
566 fprintf(fp
, "%c", components
[i
+ (upper
? 4 : 0)]);
571 print_vector_field(FILE *fp
, const char *name
, uint16_t *words
, uint16_t reg_word
,
572 const midgard_constants
*consts
, unsigned tabs
)
574 midgard_reg_info
*reg_info
= (midgard_reg_info
*)®_word
;
575 midgard_vector_alu
*alu_field
= (midgard_vector_alu
*) words
;
576 midgard_reg_mode mode
= alu_field
->reg_mode
;
577 unsigned override
= alu_field
->dest_override
;
579 /* For now, prefix instruction names with their unit, until we
580 * understand how this works on a deeper level */
581 fprintf(fp
, "%s.", name
);
583 print_alu_opcode(fp
, alu_field
->op
);
585 /* Postfix with the size to disambiguate if necessary */
586 char postfix
= prefix_for_bits(bits_for_mode(mode
));
587 bool size_ambiguous
= override
!= midgard_dest_override_none
;
590 fprintf(fp
, "%c", postfix
? postfix
: 'r');
592 /* Print the outmod, if there is one */
593 print_outmod(fp
, alu_field
->outmod
,
594 midgard_is_integer_out_op(alu_field
->op
));
598 /* Mask denoting status of 8-lanes */
599 uint8_t mask
= alu_field
->mask
;
601 /* First, print the destination */
602 print_dest(fp
, reg_info
->out_reg
, mode
, alu_field
->dest_override
);
604 if (override
!= midgard_dest_override_none
) {
605 bool modeable
= (mode
!= midgard_reg_mode_8
);
606 bool known
= override
!= 0x3; /* Unused value */
608 if (!(modeable
&& known
))
609 fprintf(fp
, "/* do%u */ ", override
);
612 print_mask(fp
, mask
, bits_for_mode(mode
), override
);
616 bool is_int
= midgard_is_integer_op(alu_field
->op
);
618 if (reg_info
->src1_reg
== 26)
619 print_vector_constants(fp
, alu_field
->src1
, consts
, alu_field
);
621 print_vector_src(fp
, alu_field
->src1
, mode
, reg_info
->src1_reg
, override
, is_int
);
625 if (reg_info
->src2_imm
) {
626 uint16_t imm
= decode_vector_imm(reg_info
->src2_reg
, alu_field
->src2
>> 2);
627 print_immediate(fp
, imm
);
628 } else if (reg_info
->src2_reg
== 26) {
629 print_vector_constants(fp
, alu_field
->src2
, consts
, alu_field
);
631 print_vector_src(fp
, alu_field
->src2
, mode
,
632 reg_info
->src2_reg
, override
, is_int
);
635 midg_stats
.instruction_count
++;
640 print_scalar_src(FILE *fp
, unsigned src_binary
, unsigned reg
)
642 midgard_scalar_alu_src
*src
= (midgard_scalar_alu_src
*)&src_binary
;
650 print_reg(fp
, reg
, src
->full
? 32 : 16);
652 unsigned c
= src
->component
;
655 assert((c
& 1) == 0);
659 fprintf(fp
, ".%c", components
[c
]);
667 decode_scalar_imm(unsigned src2_reg
, unsigned imm
)
670 ret
= src2_reg
<< 11;
671 ret
|= (imm
& 3) << 9;
672 ret
|= (imm
& 4) << 6;
673 ret
|= (imm
& 0x38) << 2;
679 print_scalar_field(FILE *fp
, const char *name
, uint16_t *words
, uint16_t reg_word
,
680 const midgard_constants
*consts
, unsigned tabs
)
682 midgard_reg_info
*reg_info
= (midgard_reg_info
*)®_word
;
683 midgard_scalar_alu
*alu_field
= (midgard_scalar_alu
*) words
;
685 if (alu_field
->unknown
)
686 fprintf(fp
, "scalar ALU unknown bit set\n");
688 fprintf(fp
, "%s.", name
);
689 print_alu_opcode(fp
, alu_field
->op
);
690 print_outmod(fp
, alu_field
->outmod
,
691 midgard_is_integer_out_op(alu_field
->op
));
694 bool full
= alu_field
->output_full
;
695 update_dest(reg_info
->out_reg
);
696 print_reg(fp
, reg_info
->out_reg
, full
? 32 : 16);
697 unsigned c
= alu_field
->output_component
;
700 assert((c
& 1) == 0);
704 fprintf(fp
, ".%c, ", components
[c
]);
706 if (reg_info
->src1_reg
== 26)
707 print_scalar_constant(fp
, alu_field
->src1
, consts
, alu_field
);
709 print_scalar_src(fp
, alu_field
->src1
, reg_info
->src1_reg
);
713 if (reg_info
->src2_imm
) {
714 uint16_t imm
= decode_scalar_imm(reg_info
->src2_reg
,
716 print_immediate(fp
, imm
);
717 } else if (reg_info
->src2_reg
== 26) {
718 print_scalar_constant(fp
, alu_field
->src2
, consts
, alu_field
);
720 print_scalar_src(fp
, alu_field
->src2
, reg_info
->src2_reg
);
722 midg_stats
.instruction_count
++;
727 print_branch_op(FILE *fp
, unsigned op
)
730 case midgard_jmp_writeout_op_branch_uncond
:
731 fprintf(fp
, "uncond.");
734 case midgard_jmp_writeout_op_branch_cond
:
735 fprintf(fp
, "cond.");
738 case midgard_jmp_writeout_op_writeout
:
739 fprintf(fp
, "write.");
742 case midgard_jmp_writeout_op_tilebuffer_pending
:
743 fprintf(fp
, "tilebuffer.");
746 case midgard_jmp_writeout_op_discard
:
747 fprintf(fp
, "discard.");
751 fprintf(fp
, "unk%u.", op
);
757 print_branch_cond(FILE *fp
, int cond
)
760 case midgard_condition_write0
:
761 fprintf(fp
, "write0");
764 case midgard_condition_false
:
765 fprintf(fp
, "false");
768 case midgard_condition_true
:
772 case midgard_condition_always
:
773 fprintf(fp
, "always");
777 fprintf(fp
, "unk%X", cond
);
783 print_compact_branch_writeout_field(FILE *fp
, uint16_t word
)
785 midgard_jmp_writeout_op op
= word
& 0x7;
786 midg_stats
.instruction_count
++;
789 case midgard_jmp_writeout_op_branch_uncond
: {
790 midgard_branch_uncond br_uncond
;
791 memcpy((char *) &br_uncond
, (char *) &word
, sizeof(br_uncond
));
792 fprintf(fp
, "br.uncond ");
794 if (br_uncond
.unknown
!= 1)
795 fprintf(fp
, "unknown:%u, ", br_uncond
.unknown
);
797 if (br_uncond
.offset
>= 0)
800 fprintf(fp
, "%d -> %s", br_uncond
.offset
,
801 midgard_tag_props
[br_uncond
.dest_tag
].name
);
804 return br_uncond
.offset
>= 0;
807 case midgard_jmp_writeout_op_branch_cond
:
808 case midgard_jmp_writeout_op_writeout
:
809 case midgard_jmp_writeout_op_discard
:
811 midgard_branch_cond br_cond
;
812 memcpy((char *) &br_cond
, (char *) &word
, sizeof(br_cond
));
816 print_branch_op(fp
, br_cond
.op
);
817 print_branch_cond(fp
, br_cond
.cond
);
821 if (br_cond
.offset
>= 0)
824 fprintf(fp
, "%d -> %s", br_cond
.offset
,
825 midgard_tag_props
[br_cond
.dest_tag
].name
);
828 return br_cond
.offset
>= 0;
836 print_extended_branch_writeout_field(FILE *fp
, uint8_t *words
, unsigned next
)
838 midgard_branch_extended br
;
839 memcpy((char *) &br
, (char *) words
, sizeof(br
));
843 print_branch_op(fp
, br
.op
);
845 /* Condition codes are a LUT in the general case, but simply repeated 8 times for single-channel conditions.. Check this. */
847 bool single_channel
= true;
849 for (unsigned i
= 0; i
< 16; i
+= 2) {
850 single_channel
&= (((br
.cond
>> i
) & 0x3) == (br
.cond
& 0x3));
854 print_branch_cond(fp
, br
.cond
& 0x3);
856 fprintf(fp
, "lut%X", br
.cond
);
859 fprintf(fp
, ".unknown%u", br
.unknown
);
866 fprintf(fp
, "%d -> %s\n", br
.offset
,
867 midgard_tag_props
[br
.dest_tag
].name
);
869 unsigned I
= next
+ br
.offset
* 4;
871 if (midg_tags
[I
] && midg_tags
[I
] != br
.dest_tag
) {
872 fprintf(fp
, "\t/* XXX TAG ERROR: jumping to %s but tagged %s \n",
873 midgard_tag_props
[br
.dest_tag
].name
,
874 midgard_tag_props
[midg_tags
[I
]].name
);
877 midg_tags
[I
] = br
.dest_tag
;
879 midg_stats
.instruction_count
++;
880 return br
.offset
>= 0;
884 num_alu_fields_enabled(uint32_t control_word
)
888 if ((control_word
>> 17) & 1)
891 if ((control_word
>> 19) & 1)
894 if ((control_word
>> 21) & 1)
897 if ((control_word
>> 23) & 1)
900 if ((control_word
>> 25) & 1)
907 print_alu_word(FILE *fp
, uint32_t *words
, unsigned num_quad_words
,
908 unsigned tabs
, unsigned next
)
910 uint32_t control_word
= words
[0];
911 uint16_t *beginning_ptr
= (uint16_t *)(words
+ 1);
912 unsigned num_fields
= num_alu_fields_enabled(control_word
);
913 uint16_t *word_ptr
= beginning_ptr
+ num_fields
;
914 unsigned num_words
= 2 + num_fields
;
915 const midgard_constants
*consts
= NULL
;
916 bool branch_forward
= false;
918 if ((control_word
>> 17) & 1)
921 if ((control_word
>> 19) & 1)
924 if ((control_word
>> 21) & 1)
927 if ((control_word
>> 23) & 1)
930 if ((control_word
>> 25) & 1)
933 if ((control_word
>> 26) & 1)
936 if ((control_word
>> 27) & 1)
939 if (num_quad_words
> (num_words
+ 7) / 8) {
940 assert(num_quad_words
== (num_words
+ 15) / 8);
941 //Assume that the extra quadword is constants
942 consts
= (midgard_constants
*)(words
+ (4 * num_quad_words
- 4));
945 if ((control_word
>> 16) & 1)
946 fprintf(fp
, "unknown bit 16 enabled\n");
948 if ((control_word
>> 17) & 1) {
949 print_vector_field(fp
, "vmul", word_ptr
, *beginning_ptr
, consts
, tabs
);
954 if ((control_word
>> 18) & 1)
955 fprintf(fp
, "unknown bit 18 enabled\n");
957 if ((control_word
>> 19) & 1) {
958 print_scalar_field(fp
, "sadd", word_ptr
, *beginning_ptr
, consts
, tabs
);
963 if ((control_word
>> 20) & 1)
964 fprintf(fp
, "unknown bit 20 enabled\n");
966 if ((control_word
>> 21) & 1) {
967 print_vector_field(fp
, "vadd", word_ptr
, *beginning_ptr
, consts
, tabs
);
972 if ((control_word
>> 22) & 1)
973 fprintf(fp
, "unknown bit 22 enabled\n");
975 if ((control_word
>> 23) & 1) {
976 print_scalar_field(fp
, "smul", word_ptr
, *beginning_ptr
, consts
, tabs
);
981 if ((control_word
>> 24) & 1)
982 fprintf(fp
, "unknown bit 24 enabled\n");
984 if ((control_word
>> 25) & 1) {
985 print_vector_field(fp
, "lut", word_ptr
, *beginning_ptr
, consts
, tabs
);
989 if ((control_word
>> 26) & 1) {
990 branch_forward
|= print_compact_branch_writeout_field(fp
, *word_ptr
);
994 if ((control_word
>> 27) & 1) {
995 branch_forward
|= print_extended_branch_writeout_field(fp
, (uint8_t *) word_ptr
, next
);
1000 fprintf(fp
, "uconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
1001 consts
->u32
[0], consts
->u32
[1],
1002 consts
->u32
[2], consts
->u32
[3]);
1004 return branch_forward
;
1008 print_varying_parameters(FILE *fp
, midgard_load_store_word
*word
)
1010 midgard_varying_parameter param
;
1011 unsigned v
= word
->varying_parameters
;
1012 memcpy(¶m
, &v
, sizeof(param
));
1014 if (param
.is_varying
) {
1015 /* If a varying, there are qualifiers */
1017 fprintf(fp
, ".flat");
1019 if (param
.interpolation
!= midgard_interp_default
) {
1020 if (param
.interpolation
== midgard_interp_centroid
)
1021 fprintf(fp
, ".centroid");
1023 fprintf(fp
, ".interp%d", param
.interpolation
);
1026 if (param
.modifier
!= midgard_varying_mod_none
) {
1027 if (param
.modifier
== midgard_varying_mod_perspective_w
)
1028 fprintf(fp
, ".perspectivew");
1029 else if (param
.modifier
== midgard_varying_mod_perspective_z
)
1030 fprintf(fp
, ".perspectivez");
1032 fprintf(fp
, ".mod%d", param
.modifier
);
1034 } else if (param
.flat
|| param
.interpolation
|| param
.modifier
) {
1035 fprintf(fp
, " /* is_varying not set but varying metadata attached */");
1038 if (param
.zero0
|| param
.zero1
|| param
.zero2
)
1039 fprintf(fp
, " /* zero tripped, %u %u %u */ ", param
.zero0
, param
.zero1
, param
.zero2
);
1043 is_op_varying(unsigned op
)
1046 case midgard_op_st_vary_16
:
1047 case midgard_op_st_vary_32
:
1048 case midgard_op_st_vary_32i
:
1049 case midgard_op_st_vary_32u
:
1050 case midgard_op_ld_vary_16
:
1051 case midgard_op_ld_vary_32
:
1052 case midgard_op_ld_vary_32i
:
1053 case midgard_op_ld_vary_32u
:
1061 is_op_attribute(unsigned op
)
1064 case midgard_op_ld_attr_16
:
1065 case midgard_op_ld_attr_32
:
1066 case midgard_op_ld_attr_32i
:
1067 case midgard_op_ld_attr_32u
:
1075 print_load_store_arg(FILE *fp
, uint8_t arg
, unsigned index
)
1077 /* Try to interpret as a register */
1078 midgard_ldst_register_select sel
;
1079 memcpy(&sel
, &arg
, sizeof(arg
));
1081 /* If unknown is set, we're not sure what this is or how to
1082 * interpret it. But if it's zero, we get it. */
1085 fprintf(fp
, "0x%02X", arg
);
1089 unsigned reg
= REGISTER_LDST_BASE
+ sel
.select
;
1090 char comp
= components
[sel
.component
];
1092 fprintf(fp
, "r%u.%c", reg
, comp
);
1094 /* Only print a shift if it's non-zero. Shifts only make sense for the
1095 * second index. For the first, we're not sure what it means yet */
1099 fprintf(fp
, " << %u", sel
.shift
);
1101 fprintf(fp
, " /* %X */", sel
.shift
);
1106 update_stats(signed *stat
, unsigned address
)
1109 *stat
= MAX2(*stat
, address
+ 1);
1113 print_load_store_instr(FILE *fp
, uint64_t data
,
1116 midgard_load_store_word
*word
= (midgard_load_store_word
*) &data
;
1118 print_ld_st_opcode(fp
, word
->op
);
1120 unsigned address
= word
->address
;
1122 if (is_op_varying(word
->op
)) {
1123 print_varying_parameters(fp
, word
);
1125 /* Do some analysis: check if direct cacess */
1127 if ((word
->arg_2
== 0x1E) && midg_stats
.varying_count
>= 0)
1128 update_stats(&midg_stats
.varying_count
, address
);
1130 midg_stats
.varying_count
= -16;
1131 } else if (is_op_attribute(word
->op
)) {
1132 if ((word
->arg_2
== 0x1E) && midg_stats
.attribute_count
>= 0)
1133 update_stats(&midg_stats
.attribute_count
, address
);
1135 midg_stats
.attribute_count
= -16;
1138 fprintf(fp
, " r%u", word
->reg
+ (OP_IS_STORE(word
->op
) ? 26 : 0));
1139 print_mask_4(fp
, word
->mask
, false);
1141 if (!OP_IS_STORE(word
->op
))
1142 update_dest(word
->reg
);
1144 bool is_ubo
= OP_IS_UBO_READ(word
->op
);
1147 /* UBOs use their own addressing scheme */
1149 int lo
= word
->varying_parameters
>> 7;
1150 int hi
= word
->address
;
1152 /* TODO: Combine fields logically */
1153 address
= (hi
<< 3) | lo
;
1156 fprintf(fp
, ", %u", address
);
1158 print_swizzle_vec4(fp
, word
->swizzle
, false, false, false);
1163 fprintf(fp
, "ubo%u", word
->arg_1
);
1164 update_stats(&midg_stats
.uniform_buffer_count
, word
->arg_1
);
1166 print_load_store_arg(fp
, word
->arg_1
, 0);
1169 print_load_store_arg(fp
, word
->arg_2
, 1);
1170 fprintf(fp
, " /* %X */\n", word
->varying_parameters
);
1172 midg_stats
.instruction_count
++;
1176 print_load_store_word(FILE *fp
, uint32_t *word
, unsigned tabs
)
1178 midgard_load_store
*load_store
= (midgard_load_store
*) word
;
1180 if (load_store
->word1
!= 3) {
1181 print_load_store_instr(fp
, load_store
->word1
, tabs
);
1184 if (load_store
->word2
!= 3) {
1185 print_load_store_instr(fp
, load_store
->word2
, tabs
);
1190 print_texture_reg_select(FILE *fp
, uint8_t u
, unsigned base
)
1192 midgard_tex_register_select sel
;
1193 memcpy(&sel
, &u
, sizeof(u
));
1198 fprintf(fp
, "r%u", base
+ sel
.select
);
1200 unsigned component
= sel
.component
;
1202 /* Use the upper half in half-reg mode */
1208 fprintf(fp
, ".%c", components
[component
]);
1210 assert(sel
.zero
== 0);
1214 print_texture_format(FILE *fp
, int format
)
1216 /* Act like a modifier */
1220 DEFINE_CASE(MALI_TEX_1D
, "1d");
1221 DEFINE_CASE(MALI_TEX_2D
, "2d");
1222 DEFINE_CASE(MALI_TEX_3D
, "3d");
1223 DEFINE_CASE(MALI_TEX_CUBE
, "cube");
1226 unreachable("Bad format");
1231 midgard_op_has_helpers(unsigned op
, bool gather
)
1237 case TEXTURE_OP_NORMAL
:
1238 case TEXTURE_OP_DFDX
:
1239 case TEXTURE_OP_DFDY
:
1247 print_texture_op(FILE *fp
, unsigned op
, bool gather
)
1249 /* Act like a bare name, like ESSL functions */
1252 fprintf(fp
, "textureGather");
1254 unsigned component
= op
>> 4;
1255 unsigned bottom
= op
& 0xF;
1258 fprintf(fp
, "_unk%u", bottom
);
1260 fprintf(fp
, ".%c", components
[component
]);
1265 DEFINE_CASE(TEXTURE_OP_NORMAL
, "texture");
1266 DEFINE_CASE(TEXTURE_OP_LOD
, "textureLod");
1267 DEFINE_CASE(TEXTURE_OP_TEXEL_FETCH
, "texelFetch");
1268 DEFINE_CASE(TEXTURE_OP_BARRIER
, "barrier");
1269 DEFINE_CASE(TEXTURE_OP_DFDX
, "dFdx");
1270 DEFINE_CASE(TEXTURE_OP_DFDY
, "dFdy");
1273 fprintf(fp
, "tex_%X", op
);
1279 texture_op_takes_bias(unsigned op
)
1281 return op
== TEXTURE_OP_NORMAL
;
1285 sampler_type_name(enum mali_sampler_type t
)
1288 case MALI_SAMPLER_FLOAT
:
1290 case MALI_SAMPLER_UNSIGNED
:
1292 case MALI_SAMPLER_SIGNED
:
1301 print_texture_barrier(FILE *fp
, uint32_t *word
)
1303 midgard_texture_barrier_word
*barrier
= (midgard_texture_barrier_word
*) word
;
1305 if (barrier
->type
!= 0x4)
1306 fprintf(fp
, "/* barrier tag %X != 0x4 */ ", barrier
->type
);
1309 fprintf(fp
, "/* cont missing? */");
1312 fprintf(fp
, "/* last missing? */");
1315 fprintf(fp
, "/* zero1 = 0x%X */ ", barrier
->zero1
);
1318 fprintf(fp
, "/* zero2 = 0x%X */ ", barrier
->zero2
);
1321 fprintf(fp
, "/* zero3 = 0x%X */ ", barrier
->zero3
);
1324 fprintf(fp
, "/* zero4 = 0x%X */ ", barrier
->zero4
);
1327 fprintf(fp
, "/* zero4 = 0x%" PRIx64
" */ ", barrier
->zero5
);
1330 /* Control barriers are always implied, so include for obviousness */
1331 fprintf(fp
, " control");
1333 if (barrier
->buffer
)
1334 fprintf(fp
, " | buffer");
1336 if (barrier
->shared
)
1337 fprintf(fp
, " | shared");
1345 print_texture_word(FILE *fp
, uint32_t *word
, unsigned tabs
, unsigned in_reg_base
, unsigned out_reg_base
)
1347 midgard_texture_word
*texture
= (midgard_texture_word
*) word
;
1349 midg_stats
.helper_invocations
|=
1350 midgard_op_has_helpers(texture
->op
, texture
->is_gather
);
1352 /* Broad category of texture operation in question */
1353 print_texture_op(fp
, texture
->op
, texture
->is_gather
);
1355 /* Barriers use a dramatically different code path */
1356 if (texture
->op
== TEXTURE_OP_BARRIER
) {
1357 print_texture_barrier(fp
, word
);
1359 } else if (texture
->type
== 0x4)
1360 fprintf (fp
, "/* nonbarrier had tag 0x4 */ ");
1362 /* Specific format in question */
1363 print_texture_format(fp
, texture
->format
);
1365 /* Instruction "modifiers" parallel the ALU instructions. */
1367 if (texture
->shadow
)
1368 fprintf(fp
, ".shadow");
1371 fprintf(fp
, ".cont");
1374 fprintf(fp
, ".last");
1376 if (texture
->barrier_buffer
)
1377 fprintf(fp
, ".barrier_buffer /* XXX */");
1379 if (texture
->barrier_shared
)
1380 fprintf(fp
, ".barrier_shared /* XXX */");
1382 /* Output modifiers are always interpreted floatly */
1383 print_outmod(fp
, texture
->outmod
, false);
1385 fprintf(fp
, " %sr%u", texture
->out_full
? "" : "h",
1386 out_reg_base
+ texture
->out_reg_select
);
1387 print_mask_4(fp
, texture
->mask
, texture
->out_upper
);
1388 assert(!(texture
->out_full
&& texture
->out_upper
));
1391 /* Depending on whether we read from textures directly or indirectly,
1392 * we may be able to update our analysis */
1394 if (texture
->texture_register
) {
1395 fprintf(fp
, "texture[");
1396 print_texture_reg_select(fp
, texture
->texture_handle
, in_reg_base
);
1399 /* Indirect, tut tut */
1400 midg_stats
.texture_count
= -16;
1402 fprintf(fp
, "texture%u, ", texture
->texture_handle
);
1403 update_stats(&midg_stats
.texture_count
, texture
->texture_handle
);
1406 /* Print the type, GL style */
1407 fprintf(fp
, "%csampler", sampler_type_name(texture
->sampler_type
));
1409 if (texture
->sampler_register
) {
1411 print_texture_reg_select(fp
, texture
->sampler_handle
, in_reg_base
);
1414 midg_stats
.sampler_count
= -16;
1416 fprintf(fp
, "%u", texture
->sampler_handle
);
1417 update_stats(&midg_stats
.sampler_count
, texture
->sampler_handle
);
1420 print_swizzle_vec4(fp
, texture
->swizzle
, false, false, false);
1421 fprintf(fp
, ", %sr%u", texture
->in_reg_full
? "" : "h", in_reg_base
+ texture
->in_reg_select
);
1422 assert(!(texture
->in_reg_full
&& texture
->in_reg_upper
));
1424 /* TODO: integrate with swizzle */
1425 if (texture
->in_reg_upper
)
1428 print_swizzle_vec4(fp
, texture
->in_reg_swizzle
, false, false, false);
1430 /* There is *always* an offset attached. Of
1431 * course, that offset is just immediate #0 for a
1432 * GLES call that doesn't take an offset. If there
1433 * is a non-negative non-zero offset, this is
1434 * specified in immediate offset mode, with the
1435 * values in the offset_* fields as immediates. If
1436 * this is a negative offset, we instead switch to
1437 * a register offset mode, where the offset_*
1438 * fields become register triplets */
1440 if (texture
->offset_register
) {
1443 bool full
= texture
->offset
& 1;
1444 bool select
= texture
->offset
& 2;
1445 bool upper
= texture
->offset
& 4;
1447 fprintf(fp
, "%sr%u", full
? "" : "h", in_reg_base
+ select
);
1448 assert(!(texture
->out_full
&& texture
->out_upper
));
1450 /* TODO: integrate with swizzle */
1454 print_swizzle_vec4(fp
, texture
->offset
>> 3, false, false, false);
1457 } else if (texture
->offset
) {
1458 /* Only select ops allow negative immediate offsets, verify */
1460 signed offset_x
= (texture
->offset
& 0xF);
1461 signed offset_y
= ((texture
->offset
>> 4) & 0xF);
1462 signed offset_z
= ((texture
->offset
>> 8) & 0xF);
1464 bool neg_x
= offset_x
< 0;
1465 bool neg_y
= offset_y
< 0;
1466 bool neg_z
= offset_z
< 0;
1467 bool any_neg
= neg_x
|| neg_y
|| neg_z
;
1469 if (any_neg
&& texture
->op
!= TEXTURE_OP_TEXEL_FETCH
)
1470 fprintf(fp
, "/* invalid negative */ ");
1472 /* Regardless, just print the immediate offset */
1474 fprintf(fp
, " + <%d, %d, %d>, ", offset_x
, offset_y
, offset_z
);
1479 char lod_operand
= texture_op_takes_bias(texture
->op
) ? '+' : '=';
1481 if (texture
->lod_register
) {
1482 fprintf(fp
, "lod %c ", lod_operand
);
1483 print_texture_reg_select(fp
, texture
->bias
, in_reg_base
);
1486 if (texture
->bias_int
)
1487 fprintf(fp
, " /* bias_int = 0x%X */", texture
->bias_int
);
1488 } else if (texture
->op
== TEXTURE_OP_TEXEL_FETCH
) {
1489 /* For texel fetch, the int LOD is in the fractional place and
1490 * there is no fraction / possibility of bias. We *always* have
1491 * an explicit LOD, even if it's zero. */
1493 if (texture
->bias_int
)
1494 fprintf(fp
, " /* bias_int = 0x%X */ ", texture
->bias_int
);
1496 fprintf(fp
, "lod = %u, ", texture
->bias
);
1497 } else if (texture
->bias
|| texture
->bias_int
) {
1498 signed bias_int
= texture
->bias_int
;
1499 float bias_frac
= texture
->bias
/ 256.0f
;
1500 float bias
= bias_int
+ bias_frac
;
1502 bool is_bias
= texture_op_takes_bias(texture
->op
);
1503 char sign
= (bias
>= 0.0) ? '+' : '-';
1504 char operand
= is_bias
? sign
: '=';
1506 fprintf(fp
, "lod %c %f, ", operand
, fabsf(bias
));
1511 /* While not zero in general, for these simple instructions the
1512 * following unknowns are zero, so we don't include them */
1514 if (texture
->unknown4
||
1515 texture
->unknown8
) {
1516 fprintf(fp
, "// unknown4 = 0x%x\n", texture
->unknown4
);
1517 fprintf(fp
, "// unknown8 = 0x%x\n", texture
->unknown8
);
1520 midg_stats
.instruction_count
++;
1523 struct midgard_disasm_stats
1524 disassemble_midgard(FILE *fp
, uint8_t *code
, size_t size
, unsigned gpu_id
, gl_shader_stage stage
)
1526 uint32_t *words
= (uint32_t *) code
;
1527 unsigned num_words
= size
/ 4;
1530 bool branch_forward
= false;
1532 int last_next_tag
= -1;
1536 midg_tags
= calloc(sizeof(midg_tags
[0]), num_words
);
1538 /* Stats for shader-db */
1539 memset(&midg_stats
, 0, sizeof(midg_stats
));
1540 midg_ever_written
= 0;
1542 while (i
< num_words
) {
1543 unsigned tag
= words
[i
] & 0xF;
1544 unsigned next_tag
= (words
[i
] >> 4) & 0xF;
1545 fprintf(fp
, "\t%X\n", tag
);
1546 unsigned num_quad_words
= midgard_tag_props
[tag
].size
;
1548 if (midg_tags
[i
] && midg_tags
[i
] != tag
) {
1549 fprintf(fp
, "\t/* XXX: TAG ERROR branch, got %s expected %s */\n",
1550 midgard_tag_props
[tag
].name
,
1551 midgard_tag_props
[midg_tags
[i
]].name
);
1556 /* Check the tag. The idea is to ensure that next_tag is
1557 * *always* recoverable from the disassembly, such that we may
1558 * safely omit printing next_tag. To show this, we first
1559 * consider that next tags are semantically off-byone -- we end
1560 * up parsing tag n during step n+1. So, we ensure after we're
1561 * done disassembling the next tag of the final bundle is BREAK
1562 * and warn otherwise. We also ensure that the next tag is
1563 * never INVALID. Beyond that, since the last tag is checked
1564 * outside the loop, we can check one tag prior. If equal to
1565 * the current tag (which is unique), we're done. Otherwise, we
1566 * print if that tag was > TAG_BREAK, which implies the tag was
1567 * not TAG_BREAK or TAG_INVALID. But we already checked for
1568 * TAG_INVALID, so it's just if the last tag was TAG_BREAK that
1569 * we're silent. So we throw in a print for break-next on at
1570 * the end of the bundle (if it's not the final bundle, which
1571 * we already check for above), disambiguating this case as
1572 * well. Hence in all cases we are unambiguous, QED. */
1574 if (next_tag
== TAG_INVALID
)
1575 fprintf(fp
, "\t/* XXX: invalid next tag */\n");
1577 if (last_next_tag
> TAG_BREAK
&& last_next_tag
!= tag
) {
1578 fprintf(fp
, "\t/* XXX: TAG ERROR sequence, got %s expexted %s */\n",
1579 midgard_tag_props
[tag
].name
,
1580 midgard_tag_props
[last_next_tag
].name
);
1583 last_next_tag
= next_tag
;
1586 case TAG_TEXTURE_4_VTX
... TAG_TEXTURE_4_BARRIER
: {
1587 bool interpipe_aliasing
=
1588 midgard_get_quirks(gpu_id
) & MIDGARD_INTERPIPE_REG_ALIASING
;
1590 print_texture_word(fp
, &words
[i
], tabs
,
1591 interpipe_aliasing
? 0 : REG_TEX_BASE
,
1592 interpipe_aliasing
? REGISTER_LDST_BASE
: REG_TEX_BASE
);
1596 case TAG_LOAD_STORE_4
:
1597 print_load_store_word(fp
, &words
[i
], tabs
);
1600 case TAG_ALU_4
... TAG_ALU_16_WRITEOUT
:
1601 branch_forward
= print_alu_word(fp
, &words
[i
], num_quad_words
, tabs
, i
+ 4*num_quad_words
);
1603 /* Reset word static analysis state */
1604 is_embedded_constant_half
= false;
1605 is_embedded_constant_int
= false;
1610 fprintf(fp
, "Unknown word type %u:\n", words
[i
] & 0xF);
1612 print_quad_word(fp
, &words
[i
], tabs
);
1617 /* We are parsing per bundle anyway. Add before we start
1618 * breaking out so we don't miss the final bundle. */
1620 midg_stats
.bundle_count
++;
1621 midg_stats
.quadword_count
+= num_quad_words
;
1623 /* Include a synthetic "break" instruction at the end of the
1624 * bundle to signify that if, absent a branch, the shader
1625 * execution will stop here. Stop disassembly at such a break
1626 * based on a heuristic */
1628 if (next_tag
== TAG_BREAK
) {
1629 if (branch_forward
) {
1630 fprintf(fp
, "break\n");
1639 i
+= 4 * num_quad_words
;
1642 if (last_next_tag
!= TAG_BREAK
) {
1643 fprintf(fp
, "/* XXX: shader ended with tag %s */\n",
1644 midgard_tag_props
[last_next_tag
].name
);
1649 /* We computed work_count as max_work_registers, so add one to get the
1650 * count. If no work registers are written, you still have one work
1651 * reported, which is exactly what the hardware expects */
1653 midg_stats
.work_count
++;