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pan/mdg: Ensure fdot is scalar out in disasm
[mesa.git] / src / panfrost / midgard / disassemble.c
1 /* Author(s):
2 * Connor Abbott
3 * Alyssa Rosenzweig
4 *
5 * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
6 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include <inttypes.h>
32 #include <ctype.h>
33 #include <string.h>
34 #include "midgard.h"
35 #include "midgard_ops.h"
36 #include "midgard_quirks.h"
37 #include "disassemble.h"
38 #include "helpers.h"
39 #include "util/bitscan.h"
40 #include "util/half_float.h"
41 #include "util/u_math.h"
42
43 #define DEFINE_CASE(define, str) case define: { fprintf(fp, str); break; }
44
45 static unsigned *midg_tags;
46 static bool is_instruction_int = false;
47
48 /* Stats */
49
50 static struct midgard_disasm_stats midg_stats;
51
52 /* Transform an expanded writemask (duplicated 8-bit format) into its condensed
53 * form (one bit per component) */
54
55 static inline unsigned
56 condense_writemask(unsigned expanded_mask,
57 unsigned bits_per_component)
58 {
59 if (bits_per_component == 8)
60 unreachable("XXX TODO: sort out how 8-bit constant encoding works");
61
62 unsigned slots_per_component = bits_per_component / 16;
63 unsigned max_comp = (16 * 8) / bits_per_component;
64 unsigned condensed_mask = 0;
65
66 for (unsigned i = 0; i < max_comp; i++) {
67 if (expanded_mask & (1 << (i * slots_per_component)))
68 condensed_mask |= (1 << i);
69 }
70
71 return condensed_mask;
72 }
73
74 static void
75 print_alu_opcode(FILE *fp, midgard_alu_op op)
76 {
77 bool int_op = false;
78
79 if (alu_opcode_props[op].name) {
80 fprintf(fp, "%s", alu_opcode_props[op].name);
81
82 int_op = midgard_is_integer_op(op);
83 } else
84 fprintf(fp, "alu_op_%02X", op);
85
86 /* For constant analysis */
87 is_instruction_int = int_op;
88 }
89
90 static void
91 print_ld_st_opcode(FILE *fp, midgard_load_store_op op)
92 {
93 if (load_store_opcode_props[op].name)
94 fprintf(fp, "%s", load_store_opcode_props[op].name);
95 else
96 fprintf(fp, "ldst_op_%02X", op);
97 }
98
99 static bool is_embedded_constant_half = false;
100 static bool is_embedded_constant_int = false;
101
102 static char
103 prefix_for_bits(unsigned bits)
104 {
105 switch (bits) {
106 case 8:
107 return 'q';
108 case 16:
109 return 'h';
110 case 64:
111 return 'd';
112 default:
113 return 0;
114 }
115 }
116
117 /* For static analysis to ensure all registers are written at least once before
118 * use along the source code path (TODO: does this break done for complex CF?)
119 */
120
121 uint16_t midg_ever_written = 0;
122
123 static void
124 print_reg(FILE *fp, unsigned reg, unsigned bits)
125 {
126 /* Perform basic static analysis for expanding constants correctly */
127
128 if (reg == 26) {
129 is_embedded_constant_int = is_instruction_int;
130 is_embedded_constant_half = (bits < 32);
131 }
132
133 unsigned uniform_reg = 23 - reg;
134 bool is_uniform = false;
135
136 /* For r8-r15, it could be a work or uniform. We distinguish based on
137 * the fact work registers are ALWAYS written before use, but uniform
138 * registers are NEVER written before use. */
139
140 if ((reg >= 8 && reg < 16) && !(midg_ever_written & (1 << reg)))
141 is_uniform = true;
142
143 /* r16-r23 are always uniform */
144
145 if (reg >= 16 && reg <= 23)
146 is_uniform = true;
147
148 /* Update the uniform count appropriately */
149
150 if (is_uniform)
151 midg_stats.uniform_count =
152 MAX2(uniform_reg + 1, midg_stats.uniform_count);
153
154 char prefix = prefix_for_bits(bits);
155
156 if (prefix)
157 fputc(prefix, fp);
158
159 fprintf(fp, "r%u", reg);
160 }
161
162 static char *outmod_names_float[4] = {
163 "",
164 ".pos",
165 ".one",
166 ".sat"
167 };
168
169 static char *outmod_names_int[4] = {
170 ".isat",
171 ".usat",
172 "",
173 ".hi"
174 };
175
176 static char *srcmod_names_int[4] = {
177 "sext(",
178 "zext(",
179 "",
180 "("
181 };
182
183 static void
184 print_outmod(FILE *fp, unsigned outmod, bool is_int)
185 {
186 fprintf(fp, "%s", is_int ? outmod_names_int[outmod] :
187 outmod_names_float[outmod]);
188 }
189
190 static void
191 print_quad_word(FILE *fp, uint32_t *words, unsigned tabs)
192 {
193 unsigned i;
194
195 for (i = 0; i < 4; i++)
196 fprintf(fp, "0x%08X%s ", words[i], i == 3 ? "" : ",");
197
198 fprintf(fp, "\n");
199 }
200
201 static const char components[16] = "xyzwefghijklmnop";
202
203 /* Helper to print 4 chars of a swizzle */
204 static void
205 print_swizzle_helper(FILE *fp, unsigned swizzle, unsigned offset)
206 {
207 for (unsigned i = 0; i < 4; ++i) {
208 unsigned c = (swizzle >> (i * 2)) & 3;
209 c += offset;
210 fprintf(fp, "%c", components[c]);
211 }
212 }
213
214 /* Helper to print 8 chars of a swizzle, duplicating over */
215 static void
216 print_swizzle_helper_8(FILE *fp, unsigned swizzle, bool upper)
217 {
218 for (unsigned i = 0; i < 4; ++i) {
219 unsigned c = (swizzle >> (i * 2)) & 3;
220 c *= 2;
221 c += upper*8;
222 fprintf(fp, "%c%c", components[c], components[c+1]);
223 }
224 }
225
226 static void
227 print_swizzle_vec16(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low,
228 midgard_dest_override override)
229 {
230 fprintf(fp, ".");
231
232 if (override == midgard_dest_override_upper) {
233 if (rep_high)
234 fprintf(fp, " /* rep_high */ ");
235 if (rep_low)
236 fprintf(fp, " /* rep_low */ ");
237
238 if (!rep_high && rep_low)
239 print_swizzle_helper_8(fp, swizzle, true);
240 else
241 print_swizzle_helper_8(fp, swizzle, false);
242 } else {
243 print_swizzle_helper_8(fp, swizzle, rep_high & 1);
244 print_swizzle_helper_8(fp, swizzle, !(rep_low & 1));
245 }
246 }
247
248 static void
249 print_swizzle_vec8(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low, bool half)
250 {
251 fprintf(fp, ".");
252
253 /* TODO: Is it possible to unify half/full? */
254
255 if (half) {
256 print_swizzle_helper(fp, swizzle, (rep_low * 8));
257 print_swizzle_helper(fp, swizzle, (rep_low * 8) + !rep_high * 4);
258 } else {
259 print_swizzle_helper(fp, swizzle, rep_high * 4);
260 print_swizzle_helper(fp, swizzle, !rep_low * 4);
261 }
262 }
263
264 static void
265 print_swizzle_vec4(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low, bool half)
266 {
267 if (rep_high)
268 fprintf(fp, " /* rep_high */ ");
269
270 if (!half && rep_low)
271 fprintf(fp, " /* rep_low */ ");
272
273 if (swizzle == 0xE4 && !half) return; /* xyzw */
274
275 fprintf(fp, ".");
276 print_swizzle_helper(fp, swizzle, rep_low * 4);
277 }
278 static void
279 print_swizzle_vec2(FILE *fp, unsigned swizzle, bool rep_high, bool rep_low, bool half)
280 {
281 char *alphabet = "XY";
282
283 if (half) {
284 alphabet = rep_low ? "zw" : "xy";
285 } else if (rep_low)
286 fprintf(fp, " /* rep_low */ ");
287
288 if (rep_high)
289 fprintf(fp, " /* rep_high */ ");
290
291 if (swizzle == 0xE4 && !half) return; /* XY */
292
293 fprintf(fp, ".");
294
295 for (unsigned i = 0; i < 4; i += 2) {
296 unsigned a = (swizzle >> (i * 2)) & 3;
297 unsigned b = (swizzle >> ((i+1) * 2)) & 3;
298
299 /* Normally we're adjacent, but if there's an issue, don't make
300 * it ambiguous */
301
302 if (b == (a + 1))
303 fprintf(fp, "%c", alphabet[a >> 1]);
304 else
305 fprintf(fp, "[%c%c]", components[a], components[b]);
306 }
307 }
308
309 static int
310 bits_for_mode(midgard_reg_mode mode)
311 {
312 switch (mode) {
313 case midgard_reg_mode_8:
314 return 8;
315 case midgard_reg_mode_16:
316 return 16;
317 case midgard_reg_mode_32:
318 return 32;
319 case midgard_reg_mode_64:
320 return 64;
321 default:
322 unreachable("Invalid reg mode");
323 return 0;
324 }
325 }
326
327 static int
328 bits_for_mode_halved(midgard_reg_mode mode, bool half)
329 {
330 unsigned bits = bits_for_mode(mode);
331
332 if (half)
333 bits >>= 1;
334
335 return bits;
336 }
337
338 static void
339 print_scalar_constant(FILE *fp, unsigned src_binary,
340 const midgard_constants *consts,
341 midgard_scalar_alu *alu)
342 {
343 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
344 unsigned mod = 0;
345
346 assert(consts != NULL);
347
348 if (!midgard_is_integer_op(alu->op)) {
349 if (src->abs)
350 mod |= MIDGARD_FLOAT_MOD_ABS;
351 if (src->negate)
352 mod |= MIDGARD_FLOAT_MOD_NEG;
353 } else {
354 mod = midgard_int_normal;
355 }
356
357 fprintf(fp, "#");
358 mir_print_constant_component(fp, consts, src->component,
359 src->full ?
360 midgard_reg_mode_32 : midgard_reg_mode_16,
361 false, mod, alu->op);
362 }
363
364 static void
365 print_vector_constants(FILE *fp, unsigned src_binary,
366 const midgard_constants *consts,
367 midgard_vector_alu *alu)
368 {
369 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
370 unsigned bits = bits_for_mode_halved(alu->reg_mode, src->half);
371 unsigned max_comp = MIN2((sizeof(*consts) * 8) / bits, 8);
372 unsigned comp_mask, num_comp = 0;
373
374 assert(consts);
375
376 comp_mask = effective_writemask(alu, condense_writemask(alu->mask, bits));
377 num_comp = util_bitcount(comp_mask);
378
379 fprintf(fp, "#");
380 if (num_comp > 1)
381 fprintf(fp, "vec%d(", num_comp);
382
383 bool first = true;
384
385 for (unsigned i = 0; i < max_comp; ++i) {
386 if (!(comp_mask & (1 << i))) continue;
387
388 unsigned c = (src->swizzle >> (i * 2)) & 3;
389
390 if (first)
391 first = false;
392 else
393 fprintf(fp, ", ");
394
395 mir_print_constant_component(fp, consts, c, alu->reg_mode,
396 src->half, src->mod, alu->op);
397 }
398
399 if (num_comp > 1)
400 fprintf(fp, ")");
401 }
402
403 static void
404 print_vector_src(FILE *fp, unsigned src_binary,
405 midgard_reg_mode mode, unsigned reg,
406 midgard_dest_override override, bool is_int)
407 {
408 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
409
410 /* Modifiers change meaning depending on the op's context */
411
412 midgard_int_mod int_mod = src->mod;
413
414 if (is_int) {
415 fprintf(fp, "%s", srcmod_names_int[int_mod]);
416 } else {
417 if (src->mod & MIDGARD_FLOAT_MOD_NEG)
418 fprintf(fp, "-");
419
420 if (src->mod & MIDGARD_FLOAT_MOD_ABS)
421 fprintf(fp, "abs(");
422 }
423
424 //register
425 unsigned bits = bits_for_mode_halved(mode, src->half);
426 print_reg(fp, reg, bits);
427
428 /* When the source was stepped down via `half`, rep_low means "higher
429 * half" and rep_high is never seen. When it's not native,
430 * rep_low/rep_high are for, well, replication */
431
432 if (mode == midgard_reg_mode_8) {
433 assert(!src->half);
434 print_swizzle_vec16(fp, src->swizzle, src->rep_high, src->rep_low, override);
435 } else if (mode == midgard_reg_mode_16) {
436 print_swizzle_vec8(fp, src->swizzle, src->rep_high, src->rep_low, src->half);
437 } else if (mode == midgard_reg_mode_32) {
438 print_swizzle_vec4(fp, src->swizzle, src->rep_high, src->rep_low, src->half);
439 } else if (mode == midgard_reg_mode_64) {
440 print_swizzle_vec2(fp, src->swizzle, src->rep_high, src->rep_low, src->half);
441 }
442
443 /* Since we wrapped with a function-looking thing */
444
445 if (is_int && int_mod == midgard_int_shift)
446 fprintf(fp, ") << %u", bits);
447 else if ((is_int && (int_mod != midgard_int_normal))
448 || (!is_int && src->mod & MIDGARD_FLOAT_MOD_ABS))
449 fprintf(fp, ")");
450 }
451
452 static uint16_t
453 decode_vector_imm(unsigned src2_reg, unsigned imm)
454 {
455 uint16_t ret;
456 ret = src2_reg << 11;
457 ret |= (imm & 0x7) << 8;
458 ret |= (imm >> 3) & 0xFF;
459 return ret;
460 }
461
462 static void
463 print_immediate(FILE *fp, uint16_t imm)
464 {
465 if (is_instruction_int)
466 fprintf(fp, "#%u", imm);
467 else
468 fprintf(fp, "#%g", _mesa_half_to_float(imm));
469 }
470
471 static void
472 update_dest(unsigned reg)
473 {
474 /* We should record writes as marking this as a work register. Store
475 * the max register in work_count; we'll add one at the end */
476
477 if (reg < 16) {
478 midg_stats.work_count = MAX2(reg, midg_stats.work_count);
479 midg_ever_written |= (1 << reg);
480 }
481 }
482
483 static void
484 print_dest(FILE *fp, unsigned reg, midgard_reg_mode mode, midgard_dest_override override)
485 {
486 /* Depending on the mode and override, we determine the type of
487 * destination addressed. Absent an override, we address just the
488 * type of the operation itself */
489
490 unsigned bits = bits_for_mode(mode);
491
492 if (override != midgard_dest_override_none)
493 bits /= 2;
494
495 update_dest(reg);
496 print_reg(fp, reg, bits);
497 }
498
499 static void
500 print_mask_vec16(FILE *fp, uint8_t mask, midgard_dest_override override)
501 {
502 fprintf(fp, ".");
503
504 for (unsigned i = 0; i < 8; i++) {
505 if (mask & (1 << i))
506 fprintf(fp, "%c%c",
507 components[i*2 + 0],
508 components[i*2 + 1]);
509 }
510 }
511
512 /* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
513 * it's just one bit per channel, easy peasy. For 32-bit (vec4), it's one bit
514 * per channel with one duplicate bit in the middle. For 64-bit (vec2), it's
515 * one-bit per channel with _3_ duplicate bits in the middle. Basically, just
516 * subdividing the 128-bit word in 16-bit increments. For 64-bit, we uppercase
517 * the mask to make it obvious what happened */
518
519 static void
520 print_mask(FILE *fp, uint8_t mask, unsigned bits, midgard_dest_override override)
521 {
522 if (bits == 8) {
523 print_mask_vec16(fp, mask, override);
524 return;
525 }
526
527 /* Skip 'complete' masks */
528
529 if (override == midgard_dest_override_none)
530 if (bits >= 32 && mask == 0xFF) return;
531
532 fprintf(fp, ".");
533
534 unsigned skip = (bits / 16);
535 bool uppercase = bits > 32;
536 bool tripped = false;
537
538 /* To apply an upper destination override, we "shift" the alphabet.
539 * E.g. with an upper override on 32-bit, instead of xyzw, print efgh.
540 * For upper 16-bit, instead of xyzwefgh, print ijklmnop */
541
542 const char *alphabet = components;
543
544 if (override == midgard_dest_override_upper)
545 alphabet += (128 / bits);
546
547 for (unsigned i = 0; i < 8; i += skip) {
548 bool a = (mask & (1 << i)) != 0;
549
550 for (unsigned j = 1; j < skip; ++j) {
551 bool dupe = (mask & (1 << (i + j))) != 0;
552 tripped |= (dupe != a);
553 }
554
555 if (a) {
556 char c = alphabet[i / skip];
557
558 if (uppercase)
559 c = toupper(c);
560
561 fprintf(fp, "%c", c);
562 }
563 }
564
565 if (tripped)
566 fprintf(fp, " /* %X */", mask);
567 }
568
569 /* Prints the 4-bit masks found in texture and load/store ops, as opposed to
570 * the 8-bit masks found in (vector) ALU ops. Supports texture-style 16-bit
571 * mode as well, but not load/store-style 16-bit mode. */
572
573 static void
574 print_mask_4(FILE *fp, unsigned mask, bool upper)
575 {
576 if (mask == 0xF) {
577 if (upper)
578 fprintf(fp, "'");
579
580 return;
581 }
582
583 fprintf(fp, ".");
584
585 for (unsigned i = 0; i < 4; ++i) {
586 bool a = (mask & (1 << i)) != 0;
587 if (a)
588 fprintf(fp, "%c", components[i + (upper ? 4 : 0)]);
589 }
590 }
591
592 static void
593 print_vector_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_word,
594 const midgard_constants *consts, unsigned tabs)
595 {
596 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
597 midgard_vector_alu *alu_field = (midgard_vector_alu *) words;
598 midgard_reg_mode mode = alu_field->reg_mode;
599 unsigned override = alu_field->dest_override;
600
601 /* For now, prefix instruction names with their unit, until we
602 * understand how this works on a deeper level */
603 fprintf(fp, "%s.", name);
604
605 print_alu_opcode(fp, alu_field->op);
606
607 /* Postfix with the size to disambiguate if necessary */
608 char postfix = prefix_for_bits(bits_for_mode(mode));
609 bool size_ambiguous = override != midgard_dest_override_none;
610
611 if (size_ambiguous)
612 fprintf(fp, "%c", postfix ? postfix : 'r');
613
614 /* Print the outmod, if there is one */
615 print_outmod(fp, alu_field->outmod,
616 midgard_is_integer_out_op(alu_field->op));
617
618 fprintf(fp, " ");
619
620 /* Mask denoting status of 8-lanes */
621 uint8_t mask = alu_field->mask;
622
623 /* First, print the destination */
624 print_dest(fp, reg_info->out_reg, mode, alu_field->dest_override);
625
626 if (override != midgard_dest_override_none) {
627 bool modeable = (mode != midgard_reg_mode_8);
628 bool known = override != 0x3; /* Unused value */
629
630 if (!(modeable && known))
631 fprintf(fp, "/* do%u */ ", override);
632 }
633
634 /* Instructions like fdot4 do *not* replicate, ensure the
635 * mask is of only a single component */
636
637 unsigned rep = GET_CHANNEL_COUNT(alu_opcode_props[alu_field->op].props);
638
639 if (rep) {
640 unsigned comp_mask = condense_writemask(mask, bits_for_mode(mode));
641 unsigned num_comp = util_bitcount(comp_mask);
642 if (num_comp != 1)
643 fprintf(fp, "/* err too many components */");
644 }
645 print_mask(fp, mask, bits_for_mode(mode), override);
646
647 fprintf(fp, ", ");
648
649 bool is_int = midgard_is_integer_op(alu_field->op);
650
651 if (reg_info->src1_reg == 26)
652 print_vector_constants(fp, alu_field->src1, consts, alu_field);
653 else
654 print_vector_src(fp, alu_field->src1, mode, reg_info->src1_reg, override, is_int);
655
656 fprintf(fp, ", ");
657
658 if (reg_info->src2_imm) {
659 uint16_t imm = decode_vector_imm(reg_info->src2_reg, alu_field->src2 >> 2);
660 print_immediate(fp, imm);
661 } else if (reg_info->src2_reg == 26) {
662 print_vector_constants(fp, alu_field->src2, consts, alu_field);
663 } else {
664 print_vector_src(fp, alu_field->src2, mode,
665 reg_info->src2_reg, override, is_int);
666 }
667
668 midg_stats.instruction_count++;
669 fprintf(fp, "\n");
670 }
671
672 static void
673 print_scalar_src(FILE *fp, unsigned src_binary, unsigned reg)
674 {
675 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
676
677 if (src->negate)
678 fprintf(fp, "-");
679
680 if (src->abs)
681 fprintf(fp, "abs(");
682
683 print_reg(fp, reg, src->full ? 32 : 16);
684
685 unsigned c = src->component;
686
687 if (src->full) {
688 assert((c & 1) == 0);
689 c >>= 1;
690 }
691
692 fprintf(fp, ".%c", components[c]);
693
694 if (src->abs)
695 fprintf(fp, ")");
696
697 }
698
699 static uint16_t
700 decode_scalar_imm(unsigned src2_reg, unsigned imm)
701 {
702 uint16_t ret;
703 ret = src2_reg << 11;
704 ret |= (imm & 3) << 9;
705 ret |= (imm & 4) << 6;
706 ret |= (imm & 0x38) << 2;
707 ret |= imm >> 6;
708 return ret;
709 }
710
711 static void
712 print_scalar_field(FILE *fp, const char *name, uint16_t *words, uint16_t reg_word,
713 const midgard_constants *consts, unsigned tabs)
714 {
715 midgard_reg_info *reg_info = (midgard_reg_info *)&reg_word;
716 midgard_scalar_alu *alu_field = (midgard_scalar_alu *) words;
717
718 if (alu_field->unknown)
719 fprintf(fp, "scalar ALU unknown bit set\n");
720
721 fprintf(fp, "%s.", name);
722 print_alu_opcode(fp, alu_field->op);
723 print_outmod(fp, alu_field->outmod,
724 midgard_is_integer_out_op(alu_field->op));
725 fprintf(fp, " ");
726
727 bool full = alu_field->output_full;
728 update_dest(reg_info->out_reg);
729 print_reg(fp, reg_info->out_reg, full ? 32 : 16);
730 unsigned c = alu_field->output_component;
731
732 if (full) {
733 assert((c & 1) == 0);
734 c >>= 1;
735 }
736
737 fprintf(fp, ".%c, ", components[c]);
738
739 if (reg_info->src1_reg == 26)
740 print_scalar_constant(fp, alu_field->src1, consts, alu_field);
741 else
742 print_scalar_src(fp, alu_field->src1, reg_info->src1_reg);
743
744 fprintf(fp, ", ");
745
746 if (reg_info->src2_imm) {
747 uint16_t imm = decode_scalar_imm(reg_info->src2_reg,
748 alu_field->src2);
749 print_immediate(fp, imm);
750 } else if (reg_info->src2_reg == 26) {
751 print_scalar_constant(fp, alu_field->src2, consts, alu_field);
752 } else
753 print_scalar_src(fp, alu_field->src2, reg_info->src2_reg);
754
755 midg_stats.instruction_count++;
756 fprintf(fp, "\n");
757 }
758
759 static void
760 print_branch_op(FILE *fp, unsigned op)
761 {
762 switch (op) {
763 case midgard_jmp_writeout_op_branch_uncond:
764 fprintf(fp, "uncond.");
765 break;
766
767 case midgard_jmp_writeout_op_branch_cond:
768 fprintf(fp, "cond.");
769 break;
770
771 case midgard_jmp_writeout_op_writeout:
772 fprintf(fp, "write.");
773 break;
774
775 case midgard_jmp_writeout_op_tilebuffer_pending:
776 fprintf(fp, "tilebuffer.");
777 break;
778
779 case midgard_jmp_writeout_op_discard:
780 fprintf(fp, "discard.");
781 break;
782
783 default:
784 fprintf(fp, "unk%u.", op);
785 break;
786 }
787 }
788
789 static void
790 print_branch_cond(FILE *fp, int cond)
791 {
792 switch (cond) {
793 case midgard_condition_write0:
794 fprintf(fp, "write0");
795 break;
796
797 case midgard_condition_false:
798 fprintf(fp, "false");
799 break;
800
801 case midgard_condition_true:
802 fprintf(fp, "true");
803 break;
804
805 case midgard_condition_always:
806 fprintf(fp, "always");
807 break;
808
809 default:
810 fprintf(fp, "unk%X", cond);
811 break;
812 }
813 }
814
815 static bool
816 print_compact_branch_writeout_field(FILE *fp, uint16_t word)
817 {
818 midgard_jmp_writeout_op op = word & 0x7;
819 midg_stats.instruction_count++;
820
821 switch (op) {
822 case midgard_jmp_writeout_op_branch_uncond: {
823 midgard_branch_uncond br_uncond;
824 memcpy((char *) &br_uncond, (char *) &word, sizeof(br_uncond));
825 fprintf(fp, "br.uncond ");
826
827 if (br_uncond.unknown != 1)
828 fprintf(fp, "unknown:%u, ", br_uncond.unknown);
829
830 if (br_uncond.offset >= 0)
831 fprintf(fp, "+");
832
833 fprintf(fp, "%d -> %s", br_uncond.offset,
834 midgard_tag_props[br_uncond.dest_tag].name);
835 fprintf(fp, "\n");
836
837 return br_uncond.offset >= 0;
838 }
839
840 case midgard_jmp_writeout_op_branch_cond:
841 case midgard_jmp_writeout_op_writeout:
842 case midgard_jmp_writeout_op_discard:
843 default: {
844 midgard_branch_cond br_cond;
845 memcpy((char *) &br_cond, (char *) &word, sizeof(br_cond));
846
847 fprintf(fp, "br.");
848
849 print_branch_op(fp, br_cond.op);
850 print_branch_cond(fp, br_cond.cond);
851
852 fprintf(fp, " ");
853
854 if (br_cond.offset >= 0)
855 fprintf(fp, "+");
856
857 fprintf(fp, "%d -> %s", br_cond.offset,
858 midgard_tag_props[br_cond.dest_tag].name);
859 fprintf(fp, "\n");
860
861 return br_cond.offset >= 0;
862 }
863 }
864
865 return false;
866 }
867
868 static bool
869 print_extended_branch_writeout_field(FILE *fp, uint8_t *words, unsigned next)
870 {
871 midgard_branch_extended br;
872 memcpy((char *) &br, (char *) words, sizeof(br));
873
874 fprintf(fp, "brx.");
875
876 print_branch_op(fp, br.op);
877
878 /* Condition codes are a LUT in the general case, but simply repeated 8 times for single-channel conditions.. Check this. */
879
880 bool single_channel = true;
881
882 for (unsigned i = 0; i < 16; i += 2) {
883 single_channel &= (((br.cond >> i) & 0x3) == (br.cond & 0x3));
884 }
885
886 if (single_channel)
887 print_branch_cond(fp, br.cond & 0x3);
888 else
889 fprintf(fp, "lut%X", br.cond);
890
891 if (br.unknown)
892 fprintf(fp, ".unknown%u", br.unknown);
893
894 fprintf(fp, " ");
895
896 if (br.offset >= 0)
897 fprintf(fp, "+");
898
899 fprintf(fp, "%d -> %s\n", br.offset,
900 midgard_tag_props[br.dest_tag].name);
901
902 unsigned I = next + br.offset * 4;
903
904 if (midg_tags[I] && midg_tags[I] != br.dest_tag) {
905 fprintf(fp, "\t/* XXX TAG ERROR: jumping to %s but tagged %s \n",
906 midgard_tag_props[br.dest_tag].name,
907 midgard_tag_props[midg_tags[I]].name);
908 }
909
910 midg_tags[I] = br.dest_tag;
911
912 midg_stats.instruction_count++;
913 return br.offset >= 0;
914 }
915
916 static unsigned
917 num_alu_fields_enabled(uint32_t control_word)
918 {
919 unsigned ret = 0;
920
921 if ((control_word >> 17) & 1)
922 ret++;
923
924 if ((control_word >> 19) & 1)
925 ret++;
926
927 if ((control_word >> 21) & 1)
928 ret++;
929
930 if ((control_word >> 23) & 1)
931 ret++;
932
933 if ((control_word >> 25) & 1)
934 ret++;
935
936 return ret;
937 }
938
939 static bool
940 print_alu_word(FILE *fp, uint32_t *words, unsigned num_quad_words,
941 unsigned tabs, unsigned next)
942 {
943 uint32_t control_word = words[0];
944 uint16_t *beginning_ptr = (uint16_t *)(words + 1);
945 unsigned num_fields = num_alu_fields_enabled(control_word);
946 uint16_t *word_ptr = beginning_ptr + num_fields;
947 unsigned num_words = 2 + num_fields;
948 const midgard_constants *consts = NULL;
949 bool branch_forward = false;
950
951 if ((control_word >> 17) & 1)
952 num_words += 3;
953
954 if ((control_word >> 19) & 1)
955 num_words += 2;
956
957 if ((control_word >> 21) & 1)
958 num_words += 3;
959
960 if ((control_word >> 23) & 1)
961 num_words += 2;
962
963 if ((control_word >> 25) & 1)
964 num_words += 3;
965
966 if ((control_word >> 26) & 1)
967 num_words += 1;
968
969 if ((control_word >> 27) & 1)
970 num_words += 3;
971
972 if (num_quad_words > (num_words + 7) / 8) {
973 assert(num_quad_words == (num_words + 15) / 8);
974 //Assume that the extra quadword is constants
975 consts = (midgard_constants *)(words + (4 * num_quad_words - 4));
976 }
977
978 if ((control_word >> 16) & 1)
979 fprintf(fp, "unknown bit 16 enabled\n");
980
981 if ((control_word >> 17) & 1) {
982 print_vector_field(fp, "vmul", word_ptr, *beginning_ptr, consts, tabs);
983 beginning_ptr += 1;
984 word_ptr += 3;
985 }
986
987 if ((control_word >> 18) & 1)
988 fprintf(fp, "unknown bit 18 enabled\n");
989
990 if ((control_word >> 19) & 1) {
991 print_scalar_field(fp, "sadd", word_ptr, *beginning_ptr, consts, tabs);
992 beginning_ptr += 1;
993 word_ptr += 2;
994 }
995
996 if ((control_word >> 20) & 1)
997 fprintf(fp, "unknown bit 20 enabled\n");
998
999 if ((control_word >> 21) & 1) {
1000 print_vector_field(fp, "vadd", word_ptr, *beginning_ptr, consts, tabs);
1001 beginning_ptr += 1;
1002 word_ptr += 3;
1003 }
1004
1005 if ((control_word >> 22) & 1)
1006 fprintf(fp, "unknown bit 22 enabled\n");
1007
1008 if ((control_word >> 23) & 1) {
1009 print_scalar_field(fp, "smul", word_ptr, *beginning_ptr, consts, tabs);
1010 beginning_ptr += 1;
1011 word_ptr += 2;
1012 }
1013
1014 if ((control_word >> 24) & 1)
1015 fprintf(fp, "unknown bit 24 enabled\n");
1016
1017 if ((control_word >> 25) & 1) {
1018 print_vector_field(fp, "lut", word_ptr, *beginning_ptr, consts, tabs);
1019 word_ptr += 3;
1020 }
1021
1022 if ((control_word >> 26) & 1) {
1023 branch_forward |= print_compact_branch_writeout_field(fp, *word_ptr);
1024 word_ptr += 1;
1025 }
1026
1027 if ((control_word >> 27) & 1) {
1028 branch_forward |= print_extended_branch_writeout_field(fp, (uint8_t *) word_ptr, next);
1029 word_ptr += 3;
1030 }
1031
1032 if (consts)
1033 fprintf(fp, "uconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
1034 consts->u32[0], consts->u32[1],
1035 consts->u32[2], consts->u32[3]);
1036
1037 return branch_forward;
1038 }
1039
1040 static void
1041 print_varying_parameters(FILE *fp, midgard_load_store_word *word)
1042 {
1043 midgard_varying_parameter param;
1044 unsigned v = word->varying_parameters;
1045 memcpy(&param, &v, sizeof(param));
1046
1047 if (param.is_varying) {
1048 /* If a varying, there are qualifiers */
1049 if (param.flat)
1050 fprintf(fp, ".flat");
1051
1052 if (param.interpolation != midgard_interp_default) {
1053 if (param.interpolation == midgard_interp_centroid)
1054 fprintf(fp, ".centroid");
1055 else
1056 fprintf(fp, ".interp%d", param.interpolation);
1057 }
1058
1059 if (param.modifier != midgard_varying_mod_none) {
1060 if (param.modifier == midgard_varying_mod_perspective_w)
1061 fprintf(fp, ".perspectivew");
1062 else if (param.modifier == midgard_varying_mod_perspective_z)
1063 fprintf(fp, ".perspectivez");
1064 else
1065 fprintf(fp, ".mod%d", param.modifier);
1066 }
1067 } else if (param.flat || param.interpolation || param.modifier) {
1068 fprintf(fp, " /* is_varying not set but varying metadata attached */");
1069 }
1070
1071 if (param.zero0 || param.zero1 || param.zero2)
1072 fprintf(fp, " /* zero tripped, %u %u %u */ ", param.zero0, param.zero1, param.zero2);
1073 }
1074
1075 static bool
1076 is_op_varying(unsigned op)
1077 {
1078 switch (op) {
1079 case midgard_op_st_vary_16:
1080 case midgard_op_st_vary_32:
1081 case midgard_op_st_vary_32i:
1082 case midgard_op_st_vary_32u:
1083 case midgard_op_ld_vary_16:
1084 case midgard_op_ld_vary_32:
1085 case midgard_op_ld_vary_32i:
1086 case midgard_op_ld_vary_32u:
1087 return true;
1088 }
1089
1090 return false;
1091 }
1092
1093 static bool
1094 is_op_attribute(unsigned op)
1095 {
1096 switch (op) {
1097 case midgard_op_ld_attr_16:
1098 case midgard_op_ld_attr_32:
1099 case midgard_op_ld_attr_32i:
1100 case midgard_op_ld_attr_32u:
1101 return true;
1102 }
1103
1104 return false;
1105 }
1106
1107 static void
1108 print_load_store_arg(FILE *fp, uint8_t arg, unsigned index)
1109 {
1110 /* Try to interpret as a register */
1111 midgard_ldst_register_select sel;
1112 memcpy(&sel, &arg, sizeof(arg));
1113
1114 /* If unknown is set, we're not sure what this is or how to
1115 * interpret it. But if it's zero, we get it. */
1116
1117 if (sel.unknown) {
1118 fprintf(fp, "0x%02X", arg);
1119 return;
1120 }
1121
1122 unsigned reg = REGISTER_LDST_BASE + sel.select;
1123 char comp = components[sel.component];
1124
1125 fprintf(fp, "r%u.%c", reg, comp);
1126
1127 /* Only print a shift if it's non-zero. Shifts only make sense for the
1128 * second index. For the first, we're not sure what it means yet */
1129
1130 if (index == 1) {
1131 if (sel.shift)
1132 fprintf(fp, " << %u", sel.shift);
1133 } else {
1134 fprintf(fp, " /* %X */", sel.shift);
1135 }
1136 }
1137
1138 static void
1139 update_stats(signed *stat, unsigned address)
1140 {
1141 if (*stat >= 0)
1142 *stat = MAX2(*stat, address + 1);
1143 }
1144
1145 static void
1146 print_load_store_instr(FILE *fp, uint64_t data,
1147 unsigned tabs)
1148 {
1149 midgard_load_store_word *word = (midgard_load_store_word *) &data;
1150
1151 print_ld_st_opcode(fp, word->op);
1152
1153 unsigned address = word->address;
1154
1155 if (is_op_varying(word->op)) {
1156 print_varying_parameters(fp, word);
1157
1158 /* Do some analysis: check if direct cacess */
1159
1160 if ((word->arg_2 == 0x1E) && midg_stats.varying_count >= 0)
1161 update_stats(&midg_stats.varying_count, address);
1162 else
1163 midg_stats.varying_count = -16;
1164 } else if (is_op_attribute(word->op)) {
1165 if ((word->arg_2 == 0x1E) && midg_stats.attribute_count >= 0)
1166 update_stats(&midg_stats.attribute_count, address);
1167 else
1168 midg_stats.attribute_count = -16;
1169 }
1170
1171 fprintf(fp, " r%u", word->reg + (OP_IS_STORE(word->op) ? 26 : 0));
1172 print_mask_4(fp, word->mask, false);
1173
1174 if (!OP_IS_STORE(word->op))
1175 update_dest(word->reg);
1176
1177 bool is_ubo = OP_IS_UBO_READ(word->op);
1178
1179 if (is_ubo) {
1180 /* UBOs use their own addressing scheme */
1181
1182 int lo = word->varying_parameters >> 7;
1183 int hi = word->address;
1184
1185 /* TODO: Combine fields logically */
1186 address = (hi << 3) | lo;
1187 }
1188
1189 fprintf(fp, ", %u", address);
1190
1191 print_swizzle_vec4(fp, word->swizzle, false, false, false);
1192
1193 fprintf(fp, ", ");
1194
1195 if (is_ubo) {
1196 fprintf(fp, "ubo%u", word->arg_1);
1197 update_stats(&midg_stats.uniform_buffer_count, word->arg_1);
1198 } else
1199 print_load_store_arg(fp, word->arg_1, 0);
1200
1201 fprintf(fp, ", ");
1202 print_load_store_arg(fp, word->arg_2, 1);
1203 fprintf(fp, " /* %X */\n", word->varying_parameters);
1204
1205 midg_stats.instruction_count++;
1206 }
1207
1208 static void
1209 print_load_store_word(FILE *fp, uint32_t *word, unsigned tabs)
1210 {
1211 midgard_load_store *load_store = (midgard_load_store *) word;
1212
1213 if (load_store->word1 != 3) {
1214 print_load_store_instr(fp, load_store->word1, tabs);
1215 }
1216
1217 if (load_store->word2 != 3) {
1218 print_load_store_instr(fp, load_store->word2, tabs);
1219 }
1220 }
1221
1222 static void
1223 print_texture_reg_select(FILE *fp, uint8_t u, unsigned base)
1224 {
1225 midgard_tex_register_select sel;
1226 memcpy(&sel, &u, sizeof(u));
1227
1228 if (!sel.full)
1229 fprintf(fp, "h");
1230
1231 fprintf(fp, "r%u", base + sel.select);
1232
1233 unsigned component = sel.component;
1234
1235 /* Use the upper half in half-reg mode */
1236 if (sel.upper) {
1237 assert(!sel.full);
1238 component += 4;
1239 }
1240
1241 fprintf(fp, ".%c", components[component]);
1242
1243 assert(sel.zero == 0);
1244 }
1245
1246 static void
1247 print_texture_format(FILE *fp, int format)
1248 {
1249 /* Act like a modifier */
1250 fprintf(fp, ".");
1251
1252 switch (format) {
1253 DEFINE_CASE(MALI_TEX_1D, "1d");
1254 DEFINE_CASE(MALI_TEX_2D, "2d");
1255 DEFINE_CASE(MALI_TEX_3D, "3d");
1256 DEFINE_CASE(MALI_TEX_CUBE, "cube");
1257
1258 default:
1259 unreachable("Bad format");
1260 }
1261 }
1262
1263 static bool
1264 midgard_op_has_helpers(unsigned op, bool gather)
1265 {
1266 if (gather)
1267 return true;
1268
1269 switch (op) {
1270 case TEXTURE_OP_NORMAL:
1271 case TEXTURE_OP_DFDX:
1272 case TEXTURE_OP_DFDY:
1273 return true;
1274 default:
1275 return false;
1276 }
1277 }
1278
1279 static void
1280 print_texture_op(FILE *fp, unsigned op, bool gather)
1281 {
1282 /* Act like a bare name, like ESSL functions */
1283
1284 if (gather) {
1285 fprintf(fp, "textureGather");
1286
1287 unsigned component = op >> 4;
1288 unsigned bottom = op & 0xF;
1289
1290 if (bottom != 0x2)
1291 fprintf(fp, "_unk%u", bottom);
1292
1293 fprintf(fp, ".%c", components[component]);
1294 return;
1295 }
1296
1297 switch (op) {
1298 DEFINE_CASE(TEXTURE_OP_NORMAL, "texture");
1299 DEFINE_CASE(TEXTURE_OP_LOD, "textureLod");
1300 DEFINE_CASE(TEXTURE_OP_TEXEL_FETCH, "texelFetch");
1301 DEFINE_CASE(TEXTURE_OP_BARRIER, "barrier");
1302 DEFINE_CASE(TEXTURE_OP_DFDX, "dFdx");
1303 DEFINE_CASE(TEXTURE_OP_DFDY, "dFdy");
1304
1305 default:
1306 fprintf(fp, "tex_%X", op);
1307 break;
1308 }
1309 }
1310
1311 static bool
1312 texture_op_takes_bias(unsigned op)
1313 {
1314 return op == TEXTURE_OP_NORMAL;
1315 }
1316
1317 static char
1318 sampler_type_name(enum mali_sampler_type t)
1319 {
1320 switch (t) {
1321 case MALI_SAMPLER_FLOAT:
1322 return 'f';
1323 case MALI_SAMPLER_UNSIGNED:
1324 return 'u';
1325 case MALI_SAMPLER_SIGNED:
1326 return 'i';
1327 default:
1328 return '?';
1329 }
1330
1331 }
1332
1333 static void
1334 print_texture_barrier(FILE *fp, uint32_t *word)
1335 {
1336 midgard_texture_barrier_word *barrier = (midgard_texture_barrier_word *) word;
1337
1338 if (barrier->type != TAG_TEXTURE_4_BARRIER)
1339 fprintf(fp, "/* barrier tag %X != tex/bar */ ", barrier->type);
1340
1341 if (!barrier->cont)
1342 fprintf(fp, "/* cont missing? */");
1343
1344 if (!barrier->last)
1345 fprintf(fp, "/* last missing? */");
1346
1347 if (barrier->zero1)
1348 fprintf(fp, "/* zero1 = 0x%X */ ", barrier->zero1);
1349
1350 if (barrier->zero2)
1351 fprintf(fp, "/* zero2 = 0x%X */ ", barrier->zero2);
1352
1353 if (barrier->zero3)
1354 fprintf(fp, "/* zero3 = 0x%X */ ", barrier->zero3);
1355
1356 if (barrier->zero4)
1357 fprintf(fp, "/* zero4 = 0x%X */ ", barrier->zero4);
1358
1359 if (barrier->zero5)
1360 fprintf(fp, "/* zero4 = 0x%" PRIx64 " */ ", barrier->zero5);
1361
1362
1363 /* Control barriers are always implied, so include for obviousness */
1364 fprintf(fp, " control");
1365
1366 if (barrier->buffer)
1367 fprintf(fp, " | buffer");
1368
1369 if (barrier->shared)
1370 fprintf(fp, " | shared");
1371
1372 if (barrier->stack)
1373 fprintf(fp, " | stack");
1374
1375 fprintf(fp, "\n");
1376 }
1377
1378 #undef DEFINE_CASE
1379
1380 static void
1381 print_texture_word(FILE *fp, uint32_t *word, unsigned tabs, unsigned in_reg_base, unsigned out_reg_base)
1382 {
1383 midgard_texture_word *texture = (midgard_texture_word *) word;
1384
1385 midg_stats.helper_invocations |=
1386 midgard_op_has_helpers(texture->op, texture->is_gather);
1387
1388 /* Broad category of texture operation in question */
1389 print_texture_op(fp, texture->op, texture->is_gather);
1390
1391 /* Barriers use a dramatically different code path */
1392 if (texture->op == TEXTURE_OP_BARRIER) {
1393 print_texture_barrier(fp, word);
1394 return;
1395 } else if (texture->type == TAG_TEXTURE_4_BARRIER)
1396 fprintf (fp, "/* nonbarrier had tex/bar tag */ ");
1397 else if (texture->type == TAG_TEXTURE_4_VTX)
1398 fprintf (fp, ".vtx");
1399
1400 /* Specific format in question */
1401 print_texture_format(fp, texture->format);
1402
1403 /* Instruction "modifiers" parallel the ALU instructions. */
1404
1405 if (texture->shadow)
1406 fprintf(fp, ".shadow");
1407
1408 if (texture->cont)
1409 fprintf(fp, ".cont");
1410
1411 if (texture->last)
1412 fprintf(fp, ".last");
1413
1414 if (texture->barrier_buffer)
1415 fprintf(fp, ".barrier_buffer /* XXX */");
1416
1417 if (texture->barrier_shared)
1418 fprintf(fp, ".barrier_shared /* XXX */");
1419
1420 /* Output modifiers are always interpreted floatly */
1421 print_outmod(fp, texture->outmod, false);
1422
1423 fprintf(fp, " %sr%u", texture->out_full ? "" : "h",
1424 out_reg_base + texture->out_reg_select);
1425 print_mask_4(fp, texture->mask, texture->out_upper);
1426 assert(!(texture->out_full && texture->out_upper));
1427 fprintf(fp, ", ");
1428
1429 /* Depending on whether we read from textures directly or indirectly,
1430 * we may be able to update our analysis */
1431
1432 if (texture->texture_register) {
1433 fprintf(fp, "texture[");
1434 print_texture_reg_select(fp, texture->texture_handle, in_reg_base);
1435 fprintf(fp, "], ");
1436
1437 /* Indirect, tut tut */
1438 midg_stats.texture_count = -16;
1439 } else {
1440 fprintf(fp, "texture%u, ", texture->texture_handle);
1441 update_stats(&midg_stats.texture_count, texture->texture_handle);
1442 }
1443
1444 /* Print the type, GL style */
1445 fprintf(fp, "%csampler", sampler_type_name(texture->sampler_type));
1446
1447 if (texture->sampler_register) {
1448 fprintf(fp, "[");
1449 print_texture_reg_select(fp, texture->sampler_handle, in_reg_base);
1450 fprintf(fp, "]");
1451
1452 midg_stats.sampler_count = -16;
1453 } else {
1454 fprintf(fp, "%u", texture->sampler_handle);
1455 update_stats(&midg_stats.sampler_count, texture->sampler_handle);
1456 }
1457
1458 print_swizzle_vec4(fp, texture->swizzle, false, false, false);
1459 fprintf(fp, ", %sr%u", texture->in_reg_full ? "" : "h", in_reg_base + texture->in_reg_select);
1460 assert(!(texture->in_reg_full && texture->in_reg_upper));
1461
1462 /* TODO: integrate with swizzle */
1463 if (texture->in_reg_upper)
1464 fprintf(fp, "'");
1465
1466 print_swizzle_vec4(fp, texture->in_reg_swizzle, false, false, false);
1467
1468 /* There is *always* an offset attached. Of
1469 * course, that offset is just immediate #0 for a
1470 * GLES call that doesn't take an offset. If there
1471 * is a non-negative non-zero offset, this is
1472 * specified in immediate offset mode, with the
1473 * values in the offset_* fields as immediates. If
1474 * this is a negative offset, we instead switch to
1475 * a register offset mode, where the offset_*
1476 * fields become register triplets */
1477
1478 if (texture->offset_register) {
1479 fprintf(fp, " + ");
1480
1481 bool full = texture->offset & 1;
1482 bool select = texture->offset & 2;
1483 bool upper = texture->offset & 4;
1484
1485 fprintf(fp, "%sr%u", full ? "" : "h", in_reg_base + select);
1486 assert(!(texture->out_full && texture->out_upper));
1487
1488 /* TODO: integrate with swizzle */
1489 if (upper)
1490 fprintf(fp, "'");
1491
1492 print_swizzle_vec4(fp, texture->offset >> 3, false, false, false);
1493
1494 fprintf(fp, ", ");
1495 } else if (texture->offset) {
1496 /* Only select ops allow negative immediate offsets, verify */
1497
1498 signed offset_x = (texture->offset & 0xF);
1499 signed offset_y = ((texture->offset >> 4) & 0xF);
1500 signed offset_z = ((texture->offset >> 8) & 0xF);
1501
1502 bool neg_x = offset_x < 0;
1503 bool neg_y = offset_y < 0;
1504 bool neg_z = offset_z < 0;
1505 bool any_neg = neg_x || neg_y || neg_z;
1506
1507 if (any_neg && texture->op != TEXTURE_OP_TEXEL_FETCH)
1508 fprintf(fp, "/* invalid negative */ ");
1509
1510 /* Regardless, just print the immediate offset */
1511
1512 fprintf(fp, " + <%d, %d, %d>, ", offset_x, offset_y, offset_z);
1513 } else {
1514 fprintf(fp, ", ");
1515 }
1516
1517 char lod_operand = texture_op_takes_bias(texture->op) ? '+' : '=';
1518
1519 if (texture->lod_register) {
1520 fprintf(fp, "lod %c ", lod_operand);
1521 print_texture_reg_select(fp, texture->bias, in_reg_base);
1522 fprintf(fp, ", ");
1523
1524 if (texture->bias_int)
1525 fprintf(fp, " /* bias_int = 0x%X */", texture->bias_int);
1526 } else if (texture->op == TEXTURE_OP_TEXEL_FETCH) {
1527 /* For texel fetch, the int LOD is in the fractional place and
1528 * there is no fraction / possibility of bias. We *always* have
1529 * an explicit LOD, even if it's zero. */
1530
1531 if (texture->bias_int)
1532 fprintf(fp, " /* bias_int = 0x%X */ ", texture->bias_int);
1533
1534 fprintf(fp, "lod = %u, ", texture->bias);
1535 } else if (texture->bias || texture->bias_int) {
1536 signed bias_int = texture->bias_int;
1537 float bias_frac = texture->bias / 256.0f;
1538 float bias = bias_int + bias_frac;
1539
1540 bool is_bias = texture_op_takes_bias(texture->op);
1541 char sign = (bias >= 0.0) ? '+' : '-';
1542 char operand = is_bias ? sign : '=';
1543
1544 fprintf(fp, "lod %c %f, ", operand, fabsf(bias));
1545 }
1546
1547 fprintf(fp, "\n");
1548
1549 /* While not zero in general, for these simple instructions the
1550 * following unknowns are zero, so we don't include them */
1551
1552 if (texture->unknown4 ||
1553 texture->unknown8) {
1554 fprintf(fp, "// unknown4 = 0x%x\n", texture->unknown4);
1555 fprintf(fp, "// unknown8 = 0x%x\n", texture->unknown8);
1556 }
1557
1558 midg_stats.instruction_count++;
1559 }
1560
1561 struct midgard_disasm_stats
1562 disassemble_midgard(FILE *fp, uint8_t *code, size_t size, unsigned gpu_id, gl_shader_stage stage)
1563 {
1564 uint32_t *words = (uint32_t *) code;
1565 unsigned num_words = size / 4;
1566 int tabs = 0;
1567
1568 bool branch_forward = false;
1569
1570 int last_next_tag = -1;
1571
1572 unsigned i = 0;
1573
1574 midg_tags = calloc(sizeof(midg_tags[0]), num_words);
1575
1576 /* Stats for shader-db */
1577 memset(&midg_stats, 0, sizeof(midg_stats));
1578 midg_ever_written = 0;
1579
1580 while (i < num_words) {
1581 unsigned tag = words[i] & 0xF;
1582 unsigned next_tag = (words[i] >> 4) & 0xF;
1583 unsigned num_quad_words = midgard_tag_props[tag].size;
1584
1585 if (midg_tags[i] && midg_tags[i] != tag) {
1586 fprintf(fp, "\t/* XXX: TAG ERROR branch, got %s expected %s */\n",
1587 midgard_tag_props[tag].name,
1588 midgard_tag_props[midg_tags[i]].name);
1589 }
1590
1591 midg_tags[i] = tag;
1592
1593 /* Check the tag. The idea is to ensure that next_tag is
1594 * *always* recoverable from the disassembly, such that we may
1595 * safely omit printing next_tag. To show this, we first
1596 * consider that next tags are semantically off-byone -- we end
1597 * up parsing tag n during step n+1. So, we ensure after we're
1598 * done disassembling the next tag of the final bundle is BREAK
1599 * and warn otherwise. We also ensure that the next tag is
1600 * never INVALID. Beyond that, since the last tag is checked
1601 * outside the loop, we can check one tag prior. If equal to
1602 * the current tag (which is unique), we're done. Otherwise, we
1603 * print if that tag was > TAG_BREAK, which implies the tag was
1604 * not TAG_BREAK or TAG_INVALID. But we already checked for
1605 * TAG_INVALID, so it's just if the last tag was TAG_BREAK that
1606 * we're silent. So we throw in a print for break-next on at
1607 * the end of the bundle (if it's not the final bundle, which
1608 * we already check for above), disambiguating this case as
1609 * well. Hence in all cases we are unambiguous, QED. */
1610
1611 if (next_tag == TAG_INVALID)
1612 fprintf(fp, "\t/* XXX: invalid next tag */\n");
1613
1614 if (last_next_tag > TAG_BREAK && last_next_tag != tag) {
1615 fprintf(fp, "\t/* XXX: TAG ERROR sequence, got %s expexted %s */\n",
1616 midgard_tag_props[tag].name,
1617 midgard_tag_props[last_next_tag].name);
1618 }
1619
1620 last_next_tag = next_tag;
1621
1622 /* Tags are unique in the following way:
1623 *
1624 * INVALID, BREAK, UNKNOWN_*: verbosely printed
1625 * TEXTURE_4_BARRIER: verified by barrier/!barrier op
1626 * TEXTURE_4_VTX: .vtx tag printed
1627 * TEXTURE_4: tetxure lack of barriers or .vtx
1628 * TAG_LOAD_STORE_4: only load/store
1629 * TAG_ALU_4/8/12/16: by number of instructions/constants
1630 * TAG_ALU_4_8/12/16_WRITEOUT: ^^ with .writeout tag
1631 */
1632
1633 switch (tag) {
1634 case TAG_TEXTURE_4_VTX ... TAG_TEXTURE_4_BARRIER: {
1635 bool interpipe_aliasing =
1636 midgard_get_quirks(gpu_id) & MIDGARD_INTERPIPE_REG_ALIASING;
1637
1638 print_texture_word(fp, &words[i], tabs,
1639 interpipe_aliasing ? 0 : REG_TEX_BASE,
1640 interpipe_aliasing ? REGISTER_LDST_BASE : REG_TEX_BASE);
1641 break;
1642 }
1643
1644 case TAG_LOAD_STORE_4:
1645 print_load_store_word(fp, &words[i], tabs);
1646 break;
1647
1648 case TAG_ALU_4 ... TAG_ALU_16_WRITEOUT:
1649 branch_forward = print_alu_word(fp, &words[i], num_quad_words, tabs, i + 4*num_quad_words);
1650
1651 /* Reset word static analysis state */
1652 is_embedded_constant_half = false;
1653 is_embedded_constant_int = false;
1654
1655 /* TODO: infer/verify me */
1656 if (tag >= TAG_ALU_4_WRITEOUT)
1657 fprintf(fp, "writeout\n");
1658
1659 break;
1660
1661 default:
1662 fprintf(fp, "Unknown word type %u:\n", words[i] & 0xF);
1663 num_quad_words = 1;
1664 print_quad_word(fp, &words[i], tabs);
1665 fprintf(fp, "\n");
1666 break;
1667 }
1668
1669 /* We are parsing per bundle anyway. Add before we start
1670 * breaking out so we don't miss the final bundle. */
1671
1672 midg_stats.bundle_count++;
1673 midg_stats.quadword_count += num_quad_words;
1674
1675 /* Include a synthetic "break" instruction at the end of the
1676 * bundle to signify that if, absent a branch, the shader
1677 * execution will stop here. Stop disassembly at such a break
1678 * based on a heuristic */
1679
1680 if (next_tag == TAG_BREAK) {
1681 if (branch_forward) {
1682 fprintf(fp, "break\n");
1683 } else {
1684 fprintf(fp, "\n");
1685 break;
1686 }
1687 }
1688
1689 fprintf(fp, "\n");
1690
1691 i += 4 * num_quad_words;
1692 }
1693
1694 if (last_next_tag != TAG_BREAK) {
1695 fprintf(fp, "/* XXX: shader ended with tag %s */\n",
1696 midgard_tag_props[last_next_tag].name);
1697 }
1698
1699 free(midg_tags);
1700
1701 /* We computed work_count as max_work_registers, so add one to get the
1702 * count. If no work registers are written, you still have one work
1703 * reported, which is exactly what the hardware expects */
1704
1705 midg_stats.work_count++;
1706
1707 return midg_stats;
1708 }