1 /* Copyright (c) 2018-2019 Alyssa Rosenzweig (alyssa@rosenzweig.io)
3 * Permission is hereby granted, free of charge, to any person obtaining a copy
4 * of this software and associated documentation files (the "Software"), to deal
5 * in the Software without restriction, including without limitation the rights
6 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
7 * copies of the Software, and to permit persons to whom the Software is
8 * furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
16 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
18 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 #ifndef __MDG_HELPERS_H
23 #define __MDG_HELPERS_H
25 #include "util/macros.h"
28 #define OP_IS_LOAD_VARY_F(op) (\
29 op == midgard_op_ld_vary_16 || \
30 op == midgard_op_ld_vary_32 \
33 #define OP_IS_PROJECTION(op) ( \
34 op == midgard_op_ldst_perspective_division_z || \
35 op == midgard_op_ldst_perspective_division_w \
38 #define OP_IS_VEC4_ONLY(op) ( \
39 OP_IS_PROJECTION(op) || \
40 op == midgard_op_ld_cubemap_coords \
43 #define OP_IS_MOVE(op) ( \
44 op == midgard_alu_op_fmov || \
45 op == midgard_alu_op_imov \
48 #define OP_IS_UBO_READ(op) ( \
49 op == midgard_op_ld_ubo_char || \
50 op == midgard_op_ld_ubo_char2 || \
51 op == midgard_op_ld_ubo_char4 || \
52 op == midgard_op_ld_ubo_short4 || \
53 op == midgard_op_ld_ubo_int4 \
56 #define OP_IS_CSEL_V(op) ( \
57 op == midgard_alu_op_icsel_v || \
58 op == midgard_alu_op_fcsel_v \
61 #define OP_IS_CSEL(op) ( \
63 op == midgard_alu_op_icsel || \
64 op == midgard_alu_op_fcsel \
67 #define OP_IS_DERIVATIVE(op) ( \
68 op == TEXTURE_OP_DFDX || \
69 op == TEXTURE_OP_DFDY \
72 #define OP_IS_UNSIGNED_CMP(op) ( \
73 op == midgard_alu_op_ult || \
74 op == midgard_alu_op_ule \
77 #define OP_IS_INTEGER_CMP(op) ( \
78 op == midgard_alu_op_ieq || \
79 op == midgard_alu_op_ine || \
80 op == midgard_alu_op_ilt || \
81 op == midgard_alu_op_ile || \
82 OP_IS_UNSIGNED_CMP(op) \
85 /* ALU control words are single bit fields with a lot of space */
87 #define ALU_ENAB_VEC_MUL (1 << 17)
88 #define ALU_ENAB_SCAL_ADD (1 << 19)
89 #define ALU_ENAB_VEC_ADD (1 << 21)
90 #define ALU_ENAB_SCAL_MUL (1 << 23)
91 #define ALU_ENAB_VEC_LUT (1 << 25)
92 #define ALU_ENAB_BR_COMPACT (1 << 26)
93 #define ALU_ENAB_BRANCH (1 << 27)
95 /* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
97 /* Denotes an opcode that takes a vector input with a fixed-number of
98 * channels, but outputs to only a single output channel, like dot products.
99 * For these, to determine the effective mask, this quirk can be set. We have
100 * an intentional off-by-one (a la MALI_POSITIVE), since 0-channel makes no
101 * sense but we need to fit 4 channels in 2-bits. Similarly, 1-channel doesn't
102 * make sense (since then why are we quirked?), so that corresponds to "no
105 #define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
106 #define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
108 /* For instructions that take a single argument, normally the first argument
109 * slot is used for the argument and the second slot is a dummy #0 constant.
110 * However, there are exceptions: instructions like fmov store their argument
111 * in the _second_ slot and store a dummy r24 in the first slot, designated by
112 * QUIRK_FLIPPED_R24 */
114 #define QUIRK_FLIPPED_R24 (1 << 2)
116 /* Is the op commutative? */
117 #define OP_COMMUTES (1 << 3)
119 /* Does the op convert types between int- and float- space (i2f/f2u/etc) */
120 #define OP_TYPE_CONVERT (1 << 4)
122 /* Vector-independant shorthands for the above; these numbers are arbitrary and
123 * not from the ISA. Convert to the above with unit_enum_to_midgard */
129 /* 4-bit type tags */
131 #define TAG_TEXTURE_4_VTX 0x2
132 #define TAG_TEXTURE_4 0x3
133 #define TAG_LOAD_STORE_4 0x5
134 #define TAG_ALU_4 0x8
135 #define TAG_ALU_8 0x9
136 #define TAG_ALU_12 0xA
137 #define TAG_ALU_16 0xB
140 quadword_size(int tag
)
144 case TAG_LOAD_STORE_4
:
146 case TAG_TEXTURE_4_VTX
:
155 unreachable("Unknown tag");
159 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
160 tag == TAG_ALU_12 || tag == TAG_ALU_16)
162 /* Special register aliases */
164 #define MAX_WORK_REGISTERS 16
166 /* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
167 #define REGISTER_UNIFORMS 24
169 #define REGISTER_UNUSED 24
170 #define REGISTER_CONSTANT 26
171 #define REGISTER_LDST_BASE 26
172 #define REGISTER_TEXTURE_BASE 28
173 #define REGISTER_SELECT 31
175 /* SSA helper aliases to mimic the registers. */
177 #define SSA_FIXED_SHIFT 24
178 #define SSA_FIXED_REGISTER(reg) (((1 + (reg)) << SSA_FIXED_SHIFT) | 1)
179 #define SSA_REG_FROM_FIXED(reg) ((((reg) & ~1) >> SSA_FIXED_SHIFT) - 1)
180 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
182 #define COMPONENT_X 0x0
183 #define COMPONENT_Y 0x1
184 #define COMPONENT_Z 0x2
185 #define COMPONENT_W 0x3
187 #define SWIZZLE_IDENTITY { \
188 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
189 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
190 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
191 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 } \
194 #define SWIZZLE_IDENTITY_4 { \
195 { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
196 { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
197 { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
198 { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
201 static inline unsigned
202 mask_of(unsigned nr_comp
)
204 return (1 << nr_comp
) - 1;
211 /* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
212 * implemented on some subset of these units (or occassionally all of them).
213 * This table encodes a bit mask of valid units for each opcode, so the
214 * scheduler can figure where to plonk the instruction. */
216 /* Shorthands for each unit */
217 #define UNIT_VMUL ALU_ENAB_VEC_MUL
218 #define UNIT_SADD ALU_ENAB_SCAL_ADD
219 #define UNIT_VADD ALU_ENAB_VEC_ADD
220 #define UNIT_SMUL ALU_ENAB_SCAL_MUL
221 #define UNIT_VLUT ALU_ENAB_VEC_LUT
223 /* Shorthands for usual combinations of units */
225 #define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
226 #define UNITS_ADD (UNIT_VADD | UNIT_SADD)
227 #define UNITS_MOST (UNITS_MUL | UNITS_ADD)
228 #define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
229 #define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
230 #define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
231 #define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
233 struct mir_op_props
{
240 struct mir_ldst_op_props
{
245 /* Lower 2-bits are a midgard_reg_mode */
246 #define GET_LDST_SIZE(c) (c & 3)
248 /* Store (so the primary register is a source, not a destination */
249 #define LDST_STORE (1 << 2)
251 /* Mask has special meaning and should not be manipulated directly */
252 #define LDST_SPECIAL_MASK (1 << 3)
254 /* Non-store operation has side effects and should not be eliminated even if
256 #define LDST_SIDE_FX (1 << 4)
258 /* This file is common, so don't define the tables themselves. #include
259 * midgard_op.h if you need that, or edit midgard_ops.c directly */
261 /* Duplicate bits to convert a per-component to duplicated 8-bit format,
262 * which is used for vector units */
264 static inline unsigned
265 expand_writemask(unsigned mask
, unsigned channels
)
268 unsigned factor
= 8 / channels
;
269 unsigned expanded
= (1 << factor
) - 1;
271 for (unsigned i
= 0; i
< channels
; ++i
)
273 o
|= (expanded
<< (factor
* i
));
278 /* Coerce structs to integer */
280 static inline unsigned
281 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
284 memcpy(&u
, &src
, sizeof(src
));
288 static inline midgard_vector_alu_src
289 vector_alu_from_unsigned(unsigned u
)
291 midgard_vector_alu_src s
;
292 memcpy(&s
, &u
, sizeof(s
));
297 mir_compose_swizzle(unsigned *left
, unsigned *right
, unsigned *final_out
)
301 for (unsigned c
= 0; c
< 16; ++c
)
302 out
[c
] = right
[left
[c
]];
304 memcpy(final_out
, out
, sizeof(out
));
307 /* Checks for an xyzw.. swizzle, given a mask */
310 mir_is_simple_swizzle(unsigned *swizzle
, unsigned mask
)
312 for (unsigned i
= 0; i
< 16; ++i
) {
313 if (!(mask
& (1 << i
))) continue;
322 /* Packs a load/store argument */
324 static inline uint8_t
325 midgard_ldst_reg(unsigned reg
, unsigned component
)
327 assert((reg
== REGISTER_LDST_BASE
) || (reg
== REGISTER_LDST_BASE
+ 1));
329 midgard_ldst_register_select sel
= {
330 .component
= component
,
335 memcpy(&packed
, &sel
, sizeof(packed
));