src/panfrost/midgard/helpers.h

   1 /* Copyright (c) 2018-2019 Alyssa Rosenzweig (alyssa@rosenzweig.io)
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a copy
   4  * of this software and associated documentation files (the "Software"), to deal
   5  * in the Software without restriction, including without limitation the rights
   6  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   7  * copies of the Software, and to permit persons to whom the Software is
   8  * furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  16  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  18  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  19  * THE SOFTWARE.
  20  */
  21
  22 #ifndef __MDG_HELPERS_H
  23 #define __MDG_HELPERS_H
  24
  25 #include "util/macros.h"
  26 #include <string.h>
  27
  28 #define OP_IS_LOAD_VARY_F(op) (\
  29                 op == midgard_op_ld_vary_16 || \
  30                 op == midgard_op_ld_vary_32 \
  31         )
  32
  33 #define OP_IS_PROJECTION(op) ( \
  34                 op == midgard_op_ldst_perspective_division_z || \
  35                 op == midgard_op_ldst_perspective_division_w \
  36         )
  37
  38 #define OP_IS_VEC4_ONLY(op) ( \
  39                 OP_IS_PROJECTION(op) || \
  40                 op == midgard_op_ld_cubemap_coords \
  41         )
  42
  43 #define OP_IS_MOVE(op) ( \
  44                 op == midgard_alu_op_fmov || \
  45                 op == midgard_alu_op_imov \
  46         )
  47
  48 #define OP_IS_UBO_READ(op) ( \
  49                 op == midgard_op_ld_ubo_char  || \
  50                 op == midgard_op_ld_ubo_char2  || \
  51                 op == midgard_op_ld_ubo_char4  || \
  52                 op == midgard_op_ld_ubo_short4  || \
  53                 op == midgard_op_ld_ubo_int4 \
  54         )
  55
  56 #define OP_IS_CSEL_V(op) ( \
  57                 op == midgard_alu_op_icsel_v || \
  58                 op == midgard_alu_op_fcsel_v \
  59         )
  60
  61 #define OP_IS_CSEL(op) ( \
  62                 OP_IS_CSEL_V(op) || \
  63                 op == midgard_alu_op_icsel || \
  64                 op == midgard_alu_op_fcsel \
  65         )
  66
  67 #define OP_IS_DERIVATIVE(op) ( \
  68                 op == TEXTURE_OP_DFDX || \
  69                 op == TEXTURE_OP_DFDY \
  70         )
  71
  72 #define OP_IS_UNSIGNED_CMP(op) ( \
  73                 op == midgard_alu_op_ult || \
  74                 op == midgard_alu_op_ule \
  75         )
  76
  77 #define OP_IS_INTEGER_CMP(op) ( \
  78                 op == midgard_alu_op_ieq || \
  79                 op == midgard_alu_op_ine || \
  80                 op == midgard_alu_op_ilt || \
  81                 op == midgard_alu_op_ile || \
  82                 OP_IS_UNSIGNED_CMP(op) \
  83         )
  84
  85 /* ALU control words are single bit fields with a lot of space */
  86
  87 #define ALU_ENAB_VEC_MUL  (1 << 17)
  88 #define ALU_ENAB_SCAL_ADD  (1 << 19)
  89 #define ALU_ENAB_VEC_ADD  (1 << 21)
  90 #define ALU_ENAB_SCAL_MUL  (1 << 23)
  91 #define ALU_ENAB_VEC_LUT  (1 << 25)
  92 #define ALU_ENAB_BR_COMPACT (1 << 26)
  93 #define ALU_ENAB_BRANCH   (1 << 27)
  94
  95 /* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
  96
  97 /* Denotes an opcode that takes a vector input with a fixed-number of
  98  * channels, but outputs to only a single output channel, like dot products.
  99  * For these, to determine the effective mask, this quirk can be set. We have
 100  * an intentional off-by-one (a la MALI_POSITIVE), since 0-channel makes no
 101  * sense but we need to fit 4 channels in 2-bits. Similarly, 1-channel doesn't
 102  * make sense (since then why are we quirked?), so that corresponds to "no
 103  * count set" */
 104
 105 #define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
 106 #define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
 107
 108 /* For instructions that take a single argument, normally the first argument
 109  * slot is used for the argument and the second slot is a dummy #0 constant.
 110  * However, there are exceptions: instructions like fmov store their argument
 111  * in the _second_ slot and store a dummy r24 in the first slot, designated by
 112  * QUIRK_FLIPPED_R24 */
 113
 114 #define QUIRK_FLIPPED_R24 (1 << 2)
 115
 116 /* Is the op commutative? */
 117 #define OP_COMMUTES (1 << 3)
 118
 119 /* Does the op convert types between int- and float- space (i2f/f2u/etc) */
 120 #define OP_TYPE_CONVERT (1 << 4)
 121
 122 /* Vector-independant shorthands for the above; these numbers are arbitrary and
 123  * not from the ISA. Convert to the above with unit_enum_to_midgard */
 124
 125 #define UNIT_MUL 0
 126 #define UNIT_ADD 1
 127 #define UNIT_LUT 2
 128
 129 /* 4-bit type tags */
 130
 131 #define TAG_TEXTURE_4_VTX 0x2
 132 #define TAG_TEXTURE_4 0x3
 133 #define TAG_LOAD_STORE_4 0x5
 134 #define TAG_ALU_4 0x8
 135 #define TAG_ALU_8 0x9
 136 #define TAG_ALU_12 0xA
 137 #define TAG_ALU_16 0xB
 138
 139 #define IS_ALU(tag) (tag >= TAG_ALU_4)
 140
 141 /* Special register aliases */
 142
 143 #define MAX_WORK_REGISTERS 16
 144
 145 /* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
 146 #define REGISTER_UNIFORMS 24
 147
 148 #define REGISTER_UNUSED 24
 149 #define REGISTER_CONSTANT 26
 150 #define REGISTER_LDST_BASE 26
 151 #define REGISTER_TEXTURE_BASE 28
 152 #define REGISTER_SELECT 31
 153
 154 /* SSA helper aliases to mimic the registers. */
 155
 156 #define SSA_FIXED_SHIFT 24
 157 #define SSA_FIXED_REGISTER(reg) (((1 + (reg)) << SSA_FIXED_SHIFT) | 1)
 158 #define SSA_REG_FROM_FIXED(reg) ((((reg) & ~1) >> SSA_FIXED_SHIFT) - 1)
 159 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
 160
 161 #define COMPONENT_X 0x0
 162 #define COMPONENT_Y 0x1
 163 #define COMPONENT_Z 0x2
 164 #define COMPONENT_W 0x3
 165
 166 #define SWIZZLE_IDENTITY { \
 167         { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
 168         { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
 169         { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, \
 170         { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 } \
 171 }
 172
 173 #define SWIZZLE_IDENTITY_4 { \
 174         { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0 }, \
 175         { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0 }, \
 176         { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0 }, \
 177         { 0, 1, 2, 3, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0 }, \
 178 }
 179
 180 static inline unsigned
 181 mask_of(unsigned nr_comp)
 182 {
 183         return (1 << nr_comp) - 1;
 184 }
 185
 186 /* See ISA notes */
 187
 188 #define LDST_NOP (3)
 189
 190 /* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
 191  * implemented on some subset of these units (or occassionally all of them).
 192  * This table encodes a bit mask of valid units for each opcode, so the
 193  * scheduler can figure where to plonk the instruction. */
 194
 195 /* Shorthands for each unit */
 196 #define UNIT_VMUL ALU_ENAB_VEC_MUL
 197 #define UNIT_SADD ALU_ENAB_SCAL_ADD
 198 #define UNIT_VADD ALU_ENAB_VEC_ADD
 199 #define UNIT_SMUL ALU_ENAB_SCAL_MUL
 200 #define UNIT_VLUT ALU_ENAB_VEC_LUT
 201
 202 /* Shorthands for usual combinations of units */
 203
 204 #define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
 205 #define UNITS_ADD (UNIT_VADD | UNIT_SADD)
 206 #define UNITS_MOST (UNITS_MUL | UNITS_ADD)
 207 #define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
 208 #define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
 209 #define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
 210 #define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
 211
 212 struct mir_op_props {
 213         const char *name;
 214         unsigned props;
 215 };
 216
 217 /* For load/store */
 218
 219 struct mir_ldst_op_props {
 220         const char *name;
 221         unsigned props;
 222 };
 223
 224 /* Lower 2-bits are a midgard_reg_mode */
 225 #define GET_LDST_SIZE(c) (c & 3)
 226
 227 /* Store (so the primary register is a source, not a destination */
 228 #define LDST_STORE (1 << 2)
 229
 230 /* Mask has special meaning and should not be manipulated directly */
 231 #define LDST_SPECIAL_MASK (1 << 3)
 232
 233 /* Non-store operation has side effects and should not be eliminated even if
 234  * its mask is 0 */
 235 #define LDST_SIDE_FX (1 << 4)
 236
 237 /* This file is common, so don't define the tables themselves. #include
 238  * midgard_op.h if you need that, or edit midgard_ops.c directly */
 239
 240 /* Duplicate bits to convert a per-component to duplicated 8-bit format,
 241  * which is used for vector units */
 242
 243 static inline unsigned
 244 expand_writemask(unsigned mask, unsigned channels)
 245 {
 246         unsigned o = 0;
 247         unsigned factor = 8 / channels;
 248         unsigned expanded = (1 << factor) - 1;
 249
 250         for (unsigned i = 0; i < channels; ++i)
 251                 if (mask & (1 << i))
 252                         o |= (expanded << (factor * i));
 253
 254         return o;
 255 }
 256
 257 /* Coerce structs to integer */
 258
 259 static inline unsigned
 260 vector_alu_srco_unsigned(midgard_vector_alu_src src)
 261 {
 262         unsigned u;
 263         memcpy(&u, &src, sizeof(src));
 264         return u;
 265 }
 266
 267 static inline midgard_vector_alu_src
 268 vector_alu_from_unsigned(unsigned u)
 269 {
 270         midgard_vector_alu_src s;
 271         memcpy(&s, &u, sizeof(s));
 272         return s;
 273 }
 274
 275 static inline void
 276 mir_compose_swizzle(unsigned *left, unsigned *right, unsigned *final_out)
 277 {
 278         unsigned out[16];
 279
 280         for (unsigned c = 0; c < 16; ++c)
 281                 out[c] = right[left[c]];
 282
 283         memcpy(final_out, out, sizeof(out));
 284 }
 285
 286 /* Checks for an xyzw.. swizzle, given a mask */
 287
 288 static inline bool
 289 mir_is_simple_swizzle(unsigned *swizzle, unsigned mask)
 290 {
 291         for (unsigned i = 0; i < 16; ++i) {
 292                 if (!(mask & (1 << i))) continue;
 293
 294                 if (swizzle[i] != i)
 295                         return false;
 296         }
 297
 298         return true;
 299 }
 300
 301 /* Packs a load/store argument */
 302
 303 static inline uint8_t
 304 midgard_ldst_reg(unsigned reg, unsigned component)
 305 {
 306         assert((reg == REGISTER_LDST_BASE) || (reg == REGISTER_LDST_BASE + 1));
 307
 308         midgard_ldst_register_select sel = {
 309                 .component = component,
 310                 .select = reg - 26
 311         };
 312
 313         uint8_t packed;
 314         memcpy(&packed, &sel, sizeof(packed));
 315
 316         return packed;
 317 }
 318
 319 static inline bool
 320 midgard_is_branch_unit(unsigned unit)
 321 {
 322         return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
 323 }
 324
 325 #endif