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pan/mdg: Track ALU src types
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) \
118 i.src[0] = ssa; \
119 else \
120 i.dest = ssa; \
121 \
122 return i; \
123 }
124
125 #define M_LOAD(name) M_LOAD_STORE(name, false)
126 #define M_STORE(name) M_LOAD_STORE(name, true)
127
128 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
129 * the corresponding Midgard source */
130
131 static midgard_vector_alu_src
132 vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
133 bool half, bool sext)
134 {
135 /* Figure out how many components there are so we can adjust.
136 * Specifically we want to broadcast the last channel so things like
137 * ball2/3 work.
138 */
139
140 if (broadcast_count && src) {
141 uint8_t last_component = src->swizzle[broadcast_count - 1];
142
143 for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) {
144 src->swizzle[c] = last_component;
145 }
146 }
147
148 midgard_vector_alu_src alu_src = {
149 .rep_low = 0,
150 .rep_high = 0,
151 .half = half
152 };
153
154 if (is_int) {
155 alu_src.mod = midgard_int_normal;
156
157 /* Sign/zero-extend if needed */
158
159 if (half) {
160 alu_src.mod = sext ?
161 midgard_int_sign_extend
162 : midgard_int_zero_extend;
163 }
164
165 /* These should have been lowered away */
166 if (src)
167 assert(!(src->abs || src->negate));
168 } else {
169 if (src)
170 alu_src.mod = (src->abs << 0) | (src->negate << 1);
171 }
172
173 return alu_src;
174 }
175
176 M_LOAD(ld_attr_32);
177 M_LOAD(ld_vary_32);
178 M_LOAD(ld_ubo_int4);
179 M_LOAD(ld_int4);
180 M_STORE(st_int4);
181 M_LOAD(ld_color_buffer_32u);
182 M_STORE(st_vary_32);
183 M_LOAD(ld_cubemap_coords);
184 M_LOAD(ld_compute_id);
185
186 static midgard_instruction
187 v_branch(bool conditional, bool invert)
188 {
189 midgard_instruction ins = {
190 .type = TAG_ALU_4,
191 .unit = ALU_ENAB_BRANCH,
192 .compact_branch = true,
193 .branch = {
194 .conditional = conditional,
195 .invert_conditional = invert
196 },
197 .dest = ~0,
198 .src = { ~0, ~0, ~0, ~0 },
199 };
200
201 return ins;
202 }
203
204 static midgard_branch_extended
205 midgard_create_branch_extended( midgard_condition cond,
206 midgard_jmp_writeout_op op,
207 unsigned dest_tag,
208 signed quadword_offset)
209 {
210 /* The condition code is actually a LUT describing a function to
211 * combine multiple condition codes. However, we only support a single
212 * condition code at the moment, so we just duplicate over a bunch of
213 * times. */
214
215 uint16_t duplicated_cond =
216 (cond << 14) |
217 (cond << 12) |
218 (cond << 10) |
219 (cond << 8) |
220 (cond << 6) |
221 (cond << 4) |
222 (cond << 2) |
223 (cond << 0);
224
225 midgard_branch_extended branch = {
226 .op = op,
227 .dest_tag = dest_tag,
228 .offset = quadword_offset,
229 .cond = duplicated_cond
230 };
231
232 return branch;
233 }
234
235 static void
236 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
237 {
238 ins->has_constants = true;
239 memcpy(&ins->constants, constants, 16);
240 }
241
242 static int
243 glsl_type_size(const struct glsl_type *type, bool bindless)
244 {
245 return glsl_count_attribute_slots(type, false);
246 }
247
248 /* Lower fdot2 to a vector multiplication followed by channel addition */
249 static void
250 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
251 {
252 if (alu->op != nir_op_fdot2)
253 return;
254
255 b->cursor = nir_before_instr(&alu->instr);
256
257 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
258 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
259
260 nir_ssa_def *product = nir_fmul(b, src0, src1);
261
262 nir_ssa_def *sum = nir_fadd(b,
263 nir_channel(b, product, 0),
264 nir_channel(b, product, 1));
265
266 /* Replace the fdot2 with this sum */
267 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
268 }
269
270 static bool
271 midgard_nir_lower_fdot2(nir_shader *shader)
272 {
273 bool progress = false;
274
275 nir_foreach_function(function, shader) {
276 if (!function->impl) continue;
277
278 nir_builder _b;
279 nir_builder *b = &_b;
280 nir_builder_init(b, function->impl);
281
282 nir_foreach_block(block, function->impl) {
283 nir_foreach_instr_safe(instr, block) {
284 if (instr->type != nir_instr_type_alu) continue;
285
286 nir_alu_instr *alu = nir_instr_as_alu(instr);
287 midgard_nir_lower_fdot2_body(b, alu);
288
289 progress |= true;
290 }
291 }
292
293 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
294
295 }
296
297 return progress;
298 }
299
300 /* Midgard can't write depth and stencil separately. It has to happen in a
301 * single store operation containing both. Let's add a panfrost specific
302 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
303 * one.
304 */
305 static bool
306 midgard_nir_lower_zs_store(nir_shader *nir)
307 {
308 if (nir->info.stage != MESA_SHADER_FRAGMENT)
309 return false;
310
311 nir_variable *z_var = NULL, *s_var = NULL;
312
313 nir_foreach_variable(var, &nir->outputs) {
314 if (var->data.location == FRAG_RESULT_DEPTH)
315 z_var = var;
316 else if (var->data.location == FRAG_RESULT_STENCIL)
317 s_var = var;
318 }
319
320 if (!z_var && !s_var)
321 return false;
322
323 bool progress = false;
324
325 nir_foreach_function(function, nir) {
326 if (!function->impl) continue;
327
328 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
329
330 nir_foreach_block(block, function->impl) {
331 nir_foreach_instr_safe(instr, block) {
332 if (instr->type != nir_instr_type_intrinsic)
333 continue;
334
335 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
336 if (intr->intrinsic != nir_intrinsic_store_output)
337 continue;
338
339 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
340 assert(!z_store);
341 z_store = intr;
342 last_store = intr;
343 }
344
345 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
346 assert(!s_store);
347 s_store = intr;
348 last_store = intr;
349 }
350 }
351 }
352
353 if (!z_store && !s_store) continue;
354
355 nir_builder b;
356 nir_builder_init(&b, function->impl);
357
358 b.cursor = nir_before_instr(&last_store->instr);
359
360 nir_ssa_def *zs_store_src;
361
362 if (z_store && s_store) {
363 nir_ssa_def *srcs[2] = {
364 nir_ssa_for_src(&b, z_store->src[0], 1),
365 nir_ssa_for_src(&b, s_store->src[0], 1),
366 };
367
368 zs_store_src = nir_vec(&b, srcs, 2);
369 } else {
370 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
371 }
372
373 nir_intrinsic_instr *zs_store;
374
375 zs_store = nir_intrinsic_instr_create(b.shader,
376 nir_intrinsic_store_zs_output_pan);
377 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
378 zs_store->num_components = z_store && s_store ? 2 : 1;
379 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
380
381 /* Replace the Z and S store by a ZS store */
382 nir_builder_instr_insert(&b, &zs_store->instr);
383
384 if (z_store)
385 nir_instr_remove(&z_store->instr);
386
387 if (s_store)
388 nir_instr_remove(&s_store->instr);
389
390 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
391 progress = true;
392 }
393
394 return progress;
395 }
396
397 /* Flushes undefined values to zero */
398
399 static void
400 optimise_nir(nir_shader *nir, unsigned quirks)
401 {
402 bool progress;
403 unsigned lower_flrp =
404 (nir->options->lower_flrp16 ? 16 : 0) |
405 (nir->options->lower_flrp32 ? 32 : 0) |
406 (nir->options->lower_flrp64 ? 64 : 0);
407
408 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
409 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
410
411 nir_lower_tex_options lower_tex_options = {
412 .lower_txs_lod = true,
413 .lower_txp = ~0,
414 .lower_tex_without_implicit_lod =
415 (quirks & MIDGARD_EXPLICIT_LOD),
416
417 /* TODO: we have native gradient.. */
418 .lower_txd = true,
419 };
420
421 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
422
423 /* Must lower fdot2 after tex is lowered */
424 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
425
426 /* T720 is broken. */
427
428 if (quirks & MIDGARD_BROKEN_LOD)
429 NIR_PASS_V(nir, midgard_nir_lod_errata);
430
431 do {
432 progress = false;
433
434 NIR_PASS(progress, nir, nir_lower_var_copies);
435 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
436
437 NIR_PASS(progress, nir, nir_copy_prop);
438 NIR_PASS(progress, nir, nir_opt_remove_phis);
439 NIR_PASS(progress, nir, nir_opt_dce);
440 NIR_PASS(progress, nir, nir_opt_dead_cf);
441 NIR_PASS(progress, nir, nir_opt_cse);
442 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
443 NIR_PASS(progress, nir, nir_opt_algebraic);
444 NIR_PASS(progress, nir, nir_opt_constant_folding);
445
446 if (lower_flrp != 0) {
447 bool lower_flrp_progress = false;
448 NIR_PASS(lower_flrp_progress,
449 nir,
450 nir_lower_flrp,
451 lower_flrp,
452 false /* always_precise */,
453 nir->options->lower_ffma);
454 if (lower_flrp_progress) {
455 NIR_PASS(progress, nir,
456 nir_opt_constant_folding);
457 progress = true;
458 }
459
460 /* Nothing should rematerialize any flrps, so we only
461 * need to do this lowering once.
462 */
463 lower_flrp = 0;
464 }
465
466 NIR_PASS(progress, nir, nir_opt_undef);
467 NIR_PASS(progress, nir, nir_undef_to_zero);
468
469 NIR_PASS(progress, nir, nir_opt_loop_unroll,
470 nir_var_shader_in |
471 nir_var_shader_out |
472 nir_var_function_temp);
473
474 NIR_PASS(progress, nir, nir_opt_vectorize);
475 } while (progress);
476
477 /* Must be run at the end to prevent creation of fsin/fcos ops */
478 NIR_PASS(progress, nir, midgard_nir_scale_trig);
479
480 do {
481 progress = false;
482
483 NIR_PASS(progress, nir, nir_opt_dce);
484 NIR_PASS(progress, nir, nir_opt_algebraic);
485 NIR_PASS(progress, nir, nir_opt_constant_folding);
486 NIR_PASS(progress, nir, nir_copy_prop);
487 } while (progress);
488
489 NIR_PASS(progress, nir, nir_opt_algebraic_late);
490
491 /* We implement booleans as 32-bit 0/~0 */
492 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
493
494 /* Now that booleans are lowered, we can run out late opts */
495 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
496
497 /* Lower mods for float ops only. Integer ops don't support modifiers
498 * (saturate doesn't make sense on integers, neg/abs require dedicated
499 * instructions) */
500
501 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
502 NIR_PASS(progress, nir, nir_copy_prop);
503 NIR_PASS(progress, nir, nir_opt_dce);
504
505 /* Take us out of SSA */
506 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
507 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
508
509 /* We are a vector architecture; write combine where possible */
510 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
511 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
512
513 NIR_PASS(progress, nir, nir_opt_dce);
514 }
515
516 /* Do not actually emit a load; instead, cache the constant for inlining */
517
518 static void
519 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
520 {
521 nir_ssa_def def = instr->def;
522
523 midgard_constants *consts = rzalloc(NULL, midgard_constants);
524
525 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
526
527 #define RAW_CONST_COPY(bits) \
528 nir_const_value_to_array(consts->u##bits, instr->value, \
529 instr->def.num_components, u##bits)
530
531 switch (instr->def.bit_size) {
532 case 64:
533 RAW_CONST_COPY(64);
534 break;
535 case 32:
536 RAW_CONST_COPY(32);
537 break;
538 case 16:
539 RAW_CONST_COPY(16);
540 break;
541 case 8:
542 RAW_CONST_COPY(8);
543 break;
544 default:
545 unreachable("Invalid bit_size for load_const instruction\n");
546 }
547
548 /* Shifted for SSA, +1 for off-by-one */
549 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
550 }
551
552 /* Normally constants are embedded implicitly, but for I/O and such we have to
553 * explicitly emit a move with the constant source */
554
555 static void
556 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
557 {
558 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
559
560 if (constant_value) {
561 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
562 attach_constants(ctx, &ins, constant_value, node + 1);
563 emit_mir_instruction(ctx, ins);
564 }
565 }
566
567 static bool
568 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
569 {
570 unsigned comp = src->swizzle[0];
571
572 for (unsigned c = 1; c < nr_components; ++c) {
573 if (src->swizzle[c] != comp)
574 return true;
575 }
576
577 return false;
578 }
579
580 #define ALU_CASE(nir, _op) \
581 case nir_op_##nir: \
582 op = midgard_alu_op_##_op; \
583 assert(src_bitsize == dst_bitsize); \
584 break;
585
586 #define ALU_CASE_BCAST(nir, _op, count) \
587 case nir_op_##nir: \
588 op = midgard_alu_op_##_op; \
589 broadcast_swizzle = count; \
590 assert(src_bitsize == dst_bitsize); \
591 break;
592 static bool
593 nir_is_fzero_constant(nir_src src)
594 {
595 if (!nir_src_is_const(src))
596 return false;
597
598 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
599 if (nir_src_comp_as_float(src, c) != 0.0)
600 return false;
601 }
602
603 return true;
604 }
605
606 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
607 * special treatment override this anyway. */
608
609 static midgard_reg_mode
610 reg_mode_for_nir(nir_alu_instr *instr)
611 {
612 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
613
614 switch (src_bitsize) {
615 case 8:
616 return midgard_reg_mode_8;
617 case 16:
618 return midgard_reg_mode_16;
619 case 32:
620 return midgard_reg_mode_32;
621 case 64:
622 return midgard_reg_mode_64;
623 default:
624 unreachable("Invalid bit size");
625 }
626 }
627
628 static void
629 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to)
630 {
631 unsigned bits = nir_src_bit_size(instr->src[i].src);
632
633 ins->src[to] = nir_src_index(NULL, &instr->src[i].src);
634 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
635 }
636
637 static void
638 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
639 {
640 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
641 * is handled elsewhere */
642
643 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
644 midgard_emit_derivatives(ctx, instr);
645 return;
646 }
647
648 bool is_ssa = instr->dest.dest.is_ssa;
649
650 unsigned dest = nir_dest_index(&instr->dest.dest);
651 unsigned nr_components = nir_dest_num_components(instr->dest.dest);
652 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
653
654 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
655 * supported. A few do not and are commented for now. Also, there are a
656 * number of NIR ops which Midgard does not support and need to be
657 * lowered, also TODO. This switch block emits the opcode and calling
658 * convention of the Midgard instruction; actual packing is done in
659 * emit_alu below */
660
661 unsigned op;
662
663 /* Number of components valid to check for the instruction (the rest
664 * will be forced to the last), or 0 to use as-is. Relevant as
665 * ball-type instructions have a channel count in NIR but are all vec4
666 * in Midgard */
667
668 unsigned broadcast_swizzle = 0;
669
670 /* What register mode should we operate in? */
671 midgard_reg_mode reg_mode =
672 reg_mode_for_nir(instr);
673
674 /* Do we need a destination override? Used for inline
675 * type conversion */
676
677 midgard_dest_override dest_override =
678 midgard_dest_override_none;
679
680 /* Should we use a smaller respective source and sign-extend? */
681
682 bool half_1 = false, sext_1 = false;
683 bool half_2 = false, sext_2 = false;
684
685 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
686 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
687
688 switch (instr->op) {
689 ALU_CASE(fadd, fadd);
690 ALU_CASE(fmul, fmul);
691 ALU_CASE(fmin, fmin);
692 ALU_CASE(fmax, fmax);
693 ALU_CASE(imin, imin);
694 ALU_CASE(imax, imax);
695 ALU_CASE(umin, umin);
696 ALU_CASE(umax, umax);
697 ALU_CASE(ffloor, ffloor);
698 ALU_CASE(fround_even, froundeven);
699 ALU_CASE(ftrunc, ftrunc);
700 ALU_CASE(fceil, fceil);
701 ALU_CASE(fdot3, fdot3);
702 ALU_CASE(fdot4, fdot4);
703 ALU_CASE(iadd, iadd);
704 ALU_CASE(isub, isub);
705 ALU_CASE(imul, imul);
706
707 /* Zero shoved as second-arg */
708 ALU_CASE(iabs, iabsdiff);
709
710 ALU_CASE(mov, imov);
711
712 ALU_CASE(feq32, feq);
713 ALU_CASE(fne32, fne);
714 ALU_CASE(flt32, flt);
715 ALU_CASE(ieq32, ieq);
716 ALU_CASE(ine32, ine);
717 ALU_CASE(ilt32, ilt);
718 ALU_CASE(ult32, ult);
719
720 /* We don't have a native b2f32 instruction. Instead, like many
721 * GPUs, we exploit booleans as 0/~0 for false/true, and
722 * correspondingly AND
723 * by 1.0 to do the type conversion. For the moment, prime us
724 * to emit:
725 *
726 * iand [whatever], #0
727 *
728 * At the end of emit_alu (as MIR), we'll fix-up the constant
729 */
730
731 ALU_CASE(b2f32, iand);
732 ALU_CASE(b2i32, iand);
733
734 /* Likewise, we don't have a dedicated f2b32 instruction, but
735 * we can do a "not equal to 0.0" test. */
736
737 ALU_CASE(f2b32, fne);
738 ALU_CASE(i2b32, ine);
739
740 ALU_CASE(frcp, frcp);
741 ALU_CASE(frsq, frsqrt);
742 ALU_CASE(fsqrt, fsqrt);
743 ALU_CASE(fexp2, fexp2);
744 ALU_CASE(flog2, flog2);
745
746 ALU_CASE(f2i64, f2i_rtz);
747 ALU_CASE(f2u64, f2u_rtz);
748 ALU_CASE(i2f64, i2f_rtz);
749 ALU_CASE(u2f64, u2f_rtz);
750
751 ALU_CASE(f2i32, f2i_rtz);
752 ALU_CASE(f2u32, f2u_rtz);
753 ALU_CASE(i2f32, i2f_rtz);
754 ALU_CASE(u2f32, u2f_rtz);
755
756 ALU_CASE(f2i16, f2i_rtz);
757 ALU_CASE(f2u16, f2u_rtz);
758 ALU_CASE(i2f16, i2f_rtz);
759 ALU_CASE(u2f16, u2f_rtz);
760
761 ALU_CASE(fsin, fsin);
762 ALU_CASE(fcos, fcos);
763
764 /* We'll set invert */
765 ALU_CASE(inot, imov);
766 ALU_CASE(iand, iand);
767 ALU_CASE(ior, ior);
768 ALU_CASE(ixor, ixor);
769 ALU_CASE(ishl, ishl);
770 ALU_CASE(ishr, iasr);
771 ALU_CASE(ushr, ilsr);
772
773 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
774 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
775 ALU_CASE(b32all_fequal4, fball_eq);
776
777 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
778 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
779 ALU_CASE(b32any_fnequal4, fbany_neq);
780
781 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
782 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
783 ALU_CASE(b32all_iequal4, iball_eq);
784
785 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
786 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
787 ALU_CASE(b32any_inequal4, ibany_neq);
788
789 /* Source mods will be shoved in later */
790 ALU_CASE(fabs, fmov);
791 ALU_CASE(fneg, fmov);
792 ALU_CASE(fsat, fmov);
793
794 /* For size conversion, we use a move. Ideally though we would squash
795 * these ops together; maybe that has to happen after in NIR as part of
796 * propagation...? An earlier algebraic pass ensured we step down by
797 * only / exactly one size. If stepping down, we use a dest override to
798 * reduce the size; if stepping up, we use a larger-sized move with a
799 * half source and a sign/zero-extension modifier */
800
801 case nir_op_i2i8:
802 case nir_op_i2i16:
803 case nir_op_i2i32:
804 case nir_op_i2i64:
805 /* If we end up upscale, we'll need a sign-extend on the
806 * operand (the second argument) */
807
808 sext_2 = true;
809 /* fallthrough */
810 case nir_op_u2u8:
811 case nir_op_u2u16:
812 case nir_op_u2u32:
813 case nir_op_u2u64:
814 case nir_op_f2f16:
815 case nir_op_f2f32:
816 case nir_op_f2f64: {
817 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
818 instr->op == nir_op_f2f64)
819 op = midgard_alu_op_fmov;
820 else
821 op = midgard_alu_op_imov;
822
823 if (dst_bitsize == (src_bitsize * 2)) {
824 /* Converting up */
825 half_2 = true;
826
827 /* Use a greater register mode */
828 reg_mode++;
829 } else if (src_bitsize == (dst_bitsize * 2)) {
830 /* Converting down */
831 dest_override = midgard_dest_override_lower;
832 }
833
834 break;
835 }
836
837 /* For greater-or-equal, we lower to less-or-equal and flip the
838 * arguments */
839
840 case nir_op_fge:
841 case nir_op_fge32:
842 case nir_op_ige32:
843 case nir_op_uge32: {
844 op =
845 instr->op == nir_op_fge ? midgard_alu_op_fle :
846 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
847 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
848 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
849 0;
850
851 /* Swap via temporary */
852 nir_alu_src temp = instr->src[1];
853 instr->src[1] = instr->src[0];
854 instr->src[0] = temp;
855
856 break;
857 }
858
859 case nir_op_b32csel: {
860 /* Midgard features both fcsel and icsel, depending on
861 * the type of the arguments/output. However, as long
862 * as we're careful we can _always_ use icsel and
863 * _never_ need fcsel, since the latter does additional
864 * floating-point-specific processing whereas the
865 * former just moves bits on the wire. It's not obvious
866 * why these are separate opcodes, save for the ability
867 * to do things like sat/pos/abs/neg for free */
868
869 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
870 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
871
872 /* The condition is the first argument; move the other
873 * arguments up one to be a binary instruction for
874 * Midgard with the condition last */
875
876 nir_alu_src temp = instr->src[2];
877
878 instr->src[2] = instr->src[0];
879 instr->src[0] = instr->src[1];
880 instr->src[1] = temp;
881
882 break;
883 }
884
885 default:
886 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
887 assert(0);
888 return;
889 }
890
891 /* Midgard can perform certain modifiers on output of an ALU op */
892 unsigned outmod;
893
894 if (midgard_is_integer_out_op(op)) {
895 outmod = midgard_outmod_int_wrap;
896 } else {
897 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
898 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
899 }
900
901 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
902
903 if (instr->op == nir_op_fmax) {
904 if (nir_is_fzero_constant(instr->src[0].src)) {
905 op = midgard_alu_op_fmov;
906 nr_inputs = 1;
907 outmod = midgard_outmod_pos;
908 instr->src[0] = instr->src[1];
909 } else if (nir_is_fzero_constant(instr->src[1].src)) {
910 op = midgard_alu_op_fmov;
911 nr_inputs = 1;
912 outmod = midgard_outmod_pos;
913 }
914 }
915
916 /* Fetch unit, quirks, etc information */
917 unsigned opcode_props = alu_opcode_props[op].props;
918 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
919
920 midgard_instruction ins = {
921 .type = TAG_ALU_4,
922 .dest = dest,
923 };
924
925 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
926 ins.src[i] = ~0;
927
928 if (quirk_flipped_r24) {
929 ins.src[0] = ~0;
930 mir_copy_src(&ins, instr, 0, 1);
931 } else {
932 for (unsigned i = 0; i < nr_inputs; ++i)
933 mir_copy_src(&ins, instr, i, quirk_flipped_r24 ? 1 : i);
934 }
935
936 nir_alu_src *nirmods[3] = { NULL };
937
938 if (nr_inputs >= 2) {
939 nirmods[0] = &instr->src[0];
940 nirmods[1] = &instr->src[1];
941 } else if (nr_inputs == 1) {
942 nirmods[quirk_flipped_r24] = &instr->src[0];
943 } else {
944 assert(0);
945 }
946
947 if (nr_inputs == 3)
948 nirmods[2] = &instr->src[2];
949
950 /* These were lowered to a move, so apply the corresponding mod */
951
952 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
953 nir_alu_src *s = nirmods[quirk_flipped_r24];
954
955 if (instr->op == nir_op_fneg)
956 s->negate = !s->negate;
957
958 if (instr->op == nir_op_fabs)
959 s->abs = !s->abs;
960 }
961
962 bool is_int = midgard_is_integer_op(op);
963
964 ins.mask = mask_of(nr_components);
965
966 midgard_vector_alu alu = {
967 .op = op,
968 .reg_mode = reg_mode,
969 .dest_override = dest_override,
970 .outmod = outmod,
971
972 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)),
973 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)),
974 };
975
976 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
977
978 if (!is_ssa)
979 ins.mask &= instr->dest.write_mask;
980
981 for (unsigned m = 0; m < 3; ++m) {
982 if (!nirmods[m])
983 continue;
984
985 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c)
986 ins.swizzle[m][c] = nirmods[m]->swizzle[c];
987
988 /* Replicate. TODO: remove when vec16 lands */
989 for (unsigned c = NIR_MAX_VEC_COMPONENTS; c < MIR_VEC_COMPONENTS; ++c)
990 ins.swizzle[m][c] = nirmods[m]->swizzle[NIR_MAX_VEC_COMPONENTS - 1];
991 }
992
993 if (nr_inputs == 3) {
994 /* Conditions can't have mods */
995 assert(!nirmods[2]->abs);
996 assert(!nirmods[2]->negate);
997 }
998
999 ins.alu = alu;
1000
1001 /* Late fixup for emulated instructions */
1002
1003 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1004 /* Presently, our second argument is an inline #0 constant.
1005 * Switch over to an embedded 1.0 constant (that can't fit
1006 * inline, since we're 32-bit, not 16-bit like the inline
1007 * constants) */
1008
1009 ins.has_inline_constant = false;
1010 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1011 ins.has_constants = true;
1012
1013 if (instr->op == nir_op_b2f32)
1014 ins.constants.f32[0] = 1.0f;
1015 else
1016 ins.constants.i32[0] = 1;
1017
1018 for (unsigned c = 0; c < 16; ++c)
1019 ins.swizzle[1][c] = 0;
1020 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1021 /* Lots of instructions need a 0 plonked in */
1022 ins.has_inline_constant = false;
1023 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1024 ins.has_constants = true;
1025 ins.constants.u32[0] = 0;
1026
1027 for (unsigned c = 0; c < 16; ++c)
1028 ins.swizzle[1][c] = 0;
1029 } else if (instr->op == nir_op_inot) {
1030 ins.invert = true;
1031 }
1032
1033 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1034 /* To avoid duplicating the lookup tables (probably), true LUT
1035 * instructions can only operate as if they were scalars. Lower
1036 * them here by changing the component. */
1037
1038 unsigned orig_mask = ins.mask;
1039
1040 for (int i = 0; i < nr_components; ++i) {
1041 /* Mask the associated component, dropping the
1042 * instruction if needed */
1043
1044 ins.mask = 1 << i;
1045 ins.mask &= orig_mask;
1046
1047 if (!ins.mask)
1048 continue;
1049
1050 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1051 ins.swizzle[0][j] = nirmods[0]->swizzle[i]; /* Pull from the correct component */
1052
1053 emit_mir_instruction(ctx, ins);
1054 }
1055 } else {
1056 emit_mir_instruction(ctx, ins);
1057 }
1058 }
1059
1060 #undef ALU_CASE
1061
1062 static void
1063 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1064 {
1065 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1066 unsigned nir_mask = 0;
1067 unsigned dsize = 0;
1068
1069 if (is_read) {
1070 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1071 dsize = nir_dest_bit_size(intr->dest);
1072 } else {
1073 nir_mask = nir_intrinsic_write_mask(intr);
1074 dsize = 32;
1075 }
1076
1077 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1078 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1079 mir_set_bytemask(ins, bytemask);
1080
1081 if (dsize == 64)
1082 ins->load_64 = true;
1083 }
1084
1085 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1086 * optimized) versions of UBO #0 */
1087
1088 static midgard_instruction *
1089 emit_ubo_read(
1090 compiler_context *ctx,
1091 nir_instr *instr,
1092 unsigned dest,
1093 unsigned offset,
1094 nir_src *indirect_offset,
1095 unsigned indirect_shift,
1096 unsigned index)
1097 {
1098 /* TODO: half-floats */
1099
1100 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1101 ins.constants.u32[0] = offset;
1102
1103 if (instr->type == nir_instr_type_intrinsic)
1104 mir_set_intr_mask(instr, &ins, true);
1105
1106 if (indirect_offset) {
1107 ins.src[2] = nir_src_index(ctx, indirect_offset);
1108 ins.load_store.arg_2 = (indirect_shift << 5);
1109 } else {
1110 ins.load_store.arg_2 = 0x1E;
1111 }
1112
1113 ins.load_store.arg_1 = index;
1114
1115 return emit_mir_instruction(ctx, ins);
1116 }
1117
1118 /* Globals are like UBOs if you squint. And shared memory is like globals if
1119 * you squint even harder */
1120
1121 static void
1122 emit_global(
1123 compiler_context *ctx,
1124 nir_instr *instr,
1125 bool is_read,
1126 unsigned srcdest,
1127 nir_src *offset,
1128 bool is_shared)
1129 {
1130 /* TODO: types */
1131
1132 midgard_instruction ins;
1133
1134 if (is_read)
1135 ins = m_ld_int4(srcdest, 0);
1136 else
1137 ins = m_st_int4(srcdest, 0);
1138
1139 mir_set_offset(ctx, &ins, offset, is_shared);
1140 mir_set_intr_mask(instr, &ins, is_read);
1141
1142 emit_mir_instruction(ctx, ins);
1143 }
1144
1145 static void
1146 emit_varying_read(
1147 compiler_context *ctx,
1148 unsigned dest, unsigned offset,
1149 unsigned nr_comp, unsigned component,
1150 nir_src *indirect_offset, nir_alu_type type, bool flat)
1151 {
1152 /* XXX: Half-floats? */
1153 /* TODO: swizzle, mask */
1154
1155 midgard_instruction ins = m_ld_vary_32(dest, offset);
1156 ins.mask = mask_of(nr_comp);
1157
1158 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1159 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1160
1161 midgard_varying_parameter p = {
1162 .is_varying = 1,
1163 .interpolation = midgard_interp_default,
1164 .flat = flat,
1165 };
1166
1167 unsigned u;
1168 memcpy(&u, &p, sizeof(p));
1169 ins.load_store.varying_parameters = u;
1170
1171 if (indirect_offset)
1172 ins.src[2] = nir_src_index(ctx, indirect_offset);
1173 else
1174 ins.load_store.arg_2 = 0x1E;
1175
1176 ins.load_store.arg_1 = 0x9E;
1177
1178 /* Use the type appropriate load */
1179 switch (type) {
1180 case nir_type_uint:
1181 case nir_type_bool:
1182 ins.load_store.op = midgard_op_ld_vary_32u;
1183 break;
1184 case nir_type_int:
1185 ins.load_store.op = midgard_op_ld_vary_32i;
1186 break;
1187 case nir_type_float:
1188 ins.load_store.op = midgard_op_ld_vary_32;
1189 break;
1190 default:
1191 unreachable("Attempted to load unknown type");
1192 break;
1193 }
1194
1195 emit_mir_instruction(ctx, ins);
1196 }
1197
1198 static void
1199 emit_attr_read(
1200 compiler_context *ctx,
1201 unsigned dest, unsigned offset,
1202 unsigned nr_comp, nir_alu_type t)
1203 {
1204 midgard_instruction ins = m_ld_attr_32(dest, offset);
1205 ins.load_store.arg_1 = 0x1E;
1206 ins.load_store.arg_2 = 0x1E;
1207 ins.mask = mask_of(nr_comp);
1208
1209 /* Use the type appropriate load */
1210 switch (t) {
1211 case nir_type_uint:
1212 case nir_type_bool:
1213 ins.load_store.op = midgard_op_ld_attr_32u;
1214 break;
1215 case nir_type_int:
1216 ins.load_store.op = midgard_op_ld_attr_32i;
1217 break;
1218 case nir_type_float:
1219 ins.load_store.op = midgard_op_ld_attr_32;
1220 break;
1221 default:
1222 unreachable("Attempted to load unknown type");
1223 break;
1224 }
1225
1226 emit_mir_instruction(ctx, ins);
1227 }
1228
1229 static void
1230 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1231 unsigned nr_components, unsigned offset)
1232 {
1233 nir_dest nir_dest;
1234
1235 /* Figure out which uniform this is */
1236 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1237 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1238
1239 unsigned dest = nir_dest_index(&nir_dest);
1240
1241 /* Sysvals are prefix uniforms */
1242 unsigned uniform = ((uintptr_t) val) - 1;
1243
1244 /* Emit the read itself -- this is never indirect */
1245 midgard_instruction *ins =
1246 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1247
1248 ins->mask = mask_of(nr_components);
1249 }
1250
1251 static unsigned
1252 compute_builtin_arg(nir_op op)
1253 {
1254 switch (op) {
1255 case nir_intrinsic_load_work_group_id:
1256 return 0x14;
1257 case nir_intrinsic_load_local_invocation_id:
1258 return 0x10;
1259 default:
1260 unreachable("Invalid compute paramater loaded");
1261 }
1262 }
1263
1264 static void
1265 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1266 {
1267 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1268
1269 midgard_instruction *br = ctx->writeout_branch[rt];
1270
1271 assert(!br);
1272
1273 emit_explicit_constant(ctx, src, src);
1274
1275 struct midgard_instruction ins =
1276 v_branch(false, false);
1277
1278 ins.writeout = true;
1279
1280 /* Add dependencies */
1281 ins.src[0] = src;
1282 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1283 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1284
1285 /* Emit the branch */
1286 br = emit_mir_instruction(ctx, ins);
1287 schedule_barrier(ctx);
1288 ctx->writeout_branch[rt] = br;
1289
1290 /* Push our current location = current block count - 1 = where we'll
1291 * jump to. Maybe a bit too clever for my own good */
1292
1293 br->branch.target_block = ctx->block_count - 1;
1294 }
1295
1296 static void
1297 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1298 {
1299 unsigned reg = nir_dest_index(&instr->dest);
1300 midgard_instruction ins = m_ld_compute_id(reg, 0);
1301 ins.mask = mask_of(3);
1302 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1303 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1304 emit_mir_instruction(ctx, ins);
1305 }
1306
1307 static unsigned
1308 vertex_builtin_arg(nir_op op)
1309 {
1310 switch (op) {
1311 case nir_intrinsic_load_vertex_id:
1312 return PAN_VERTEX_ID;
1313 case nir_intrinsic_load_instance_id:
1314 return PAN_INSTANCE_ID;
1315 default:
1316 unreachable("Invalid vertex builtin");
1317 }
1318 }
1319
1320 static void
1321 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1322 {
1323 unsigned reg = nir_dest_index(&instr->dest);
1324 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1325 }
1326
1327 static void
1328 emit_control_barrier(compiler_context *ctx)
1329 {
1330 midgard_instruction ins = {
1331 .type = TAG_TEXTURE_4,
1332 .src = { ~0, ~0, ~0, ~0 },
1333 .texture = {
1334 .op = TEXTURE_OP_BARRIER,
1335
1336 /* TODO: optimize */
1337 .barrier_buffer = 1,
1338 .barrier_shared = 1
1339 }
1340 };
1341
1342 emit_mir_instruction(ctx, ins);
1343 }
1344
1345 static const nir_variable *
1346 search_var(struct exec_list *vars, unsigned driver_loc)
1347 {
1348 nir_foreach_variable(var, vars) {
1349 if (var->data.driver_location == driver_loc)
1350 return var;
1351 }
1352
1353 return NULL;
1354 }
1355
1356 static void
1357 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1358 {
1359 unsigned offset = 0, reg;
1360
1361 switch (instr->intrinsic) {
1362 case nir_intrinsic_discard_if:
1363 case nir_intrinsic_discard: {
1364 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1365 struct midgard_instruction discard = v_branch(conditional, false);
1366 discard.branch.target_type = TARGET_DISCARD;
1367
1368 if (conditional)
1369 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1370
1371 emit_mir_instruction(ctx, discard);
1372 schedule_barrier(ctx);
1373
1374 break;
1375 }
1376
1377 case nir_intrinsic_load_uniform:
1378 case nir_intrinsic_load_ubo:
1379 case nir_intrinsic_load_global:
1380 case nir_intrinsic_load_shared:
1381 case nir_intrinsic_load_input:
1382 case nir_intrinsic_load_interpolated_input: {
1383 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1384 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1385 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1386 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1387 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1388 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1389
1390 /* Get the base type of the intrinsic */
1391 /* TODO: Infer type? Does it matter? */
1392 nir_alu_type t =
1393 (is_ubo || is_global || is_shared) ? nir_type_uint :
1394 (is_interp) ? nir_type_float :
1395 nir_intrinsic_type(instr);
1396
1397 t = nir_alu_type_get_base_type(t);
1398
1399 if (!(is_ubo || is_global)) {
1400 offset = nir_intrinsic_base(instr);
1401 }
1402
1403 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1404
1405 nir_src *src_offset = nir_get_io_offset_src(instr);
1406
1407 bool direct = nir_src_is_const(*src_offset);
1408 nir_src *indirect_offset = direct ? NULL : src_offset;
1409
1410 if (direct)
1411 offset += nir_src_as_uint(*src_offset);
1412
1413 /* We may need to apply a fractional offset */
1414 int component = (is_flat || is_interp) ?
1415 nir_intrinsic_component(instr) : 0;
1416 reg = nir_dest_index(&instr->dest);
1417
1418 if (is_uniform && !ctx->is_blend) {
1419 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1420 } else if (is_ubo) {
1421 nir_src index = instr->src[0];
1422
1423 /* TODO: Is indirect block number possible? */
1424 assert(nir_src_is_const(index));
1425
1426 uint32_t uindex = nir_src_as_uint(index) + 1;
1427 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1428 } else if (is_global || is_shared) {
1429 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1430 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1431 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1432 } else if (ctx->is_blend) {
1433 /* For blend shaders, load the input color, which is
1434 * preloaded to r0 */
1435
1436 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1437 emit_mir_instruction(ctx, move);
1438 schedule_barrier(ctx);
1439 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1440 emit_attr_read(ctx, reg, offset, nr_comp, t);
1441 } else {
1442 DBG("Unknown load\n");
1443 assert(0);
1444 }
1445
1446 break;
1447 }
1448
1449 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1450 case nir_intrinsic_load_barycentric_pixel:
1451 case nir_intrinsic_load_barycentric_centroid:
1452 break;
1453
1454 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1455
1456 case nir_intrinsic_load_raw_output_pan:
1457 case nir_intrinsic_load_output_u8_as_fp16_pan:
1458 reg = nir_dest_index(&instr->dest);
1459 assert(ctx->is_blend);
1460
1461 /* T720 and below use different blend opcodes with slightly
1462 * different semantics than T760 and up */
1463
1464 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1465 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1466
1467 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1468 ld.load_store.op = old_blend ?
1469 midgard_op_ld_color_buffer_u8_as_fp16_old :
1470 midgard_op_ld_color_buffer_u8_as_fp16;
1471
1472 if (old_blend) {
1473 ld.load_store.address = 1;
1474 ld.load_store.arg_2 = 0x1E;
1475 }
1476
1477 for (unsigned c = 2; c < 16; ++c)
1478 ld.swizzle[0][c] = 0;
1479 }
1480
1481 emit_mir_instruction(ctx, ld);
1482 break;
1483
1484 case nir_intrinsic_load_blend_const_color_rgba: {
1485 assert(ctx->is_blend);
1486 reg = nir_dest_index(&instr->dest);
1487
1488 /* Blend constants are embedded directly in the shader and
1489 * patched in, so we use some magic routing */
1490
1491 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1492 ins.has_constants = true;
1493 ins.has_blend_constant = true;
1494 emit_mir_instruction(ctx, ins);
1495 break;
1496 }
1497
1498 case nir_intrinsic_store_zs_output_pan: {
1499 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1500 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1501 MIDGARD_ZS_RT);
1502
1503 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1504
1505 if (!nir_intrinsic_component(instr))
1506 br->writeout_depth = true;
1507 if (nir_intrinsic_component(instr) ||
1508 instr->num_components)
1509 br->writeout_stencil = true;
1510 assert(br->writeout_depth | br->writeout_stencil);
1511 break;
1512 }
1513
1514 case nir_intrinsic_store_output:
1515 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1516
1517 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1518
1519 reg = nir_src_index(ctx, &instr->src[0]);
1520
1521 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1522 const nir_variable *var;
1523 enum midgard_rt_id rt;
1524
1525 var = search_var(&ctx->nir->outputs,
1526 nir_intrinsic_base(instr));
1527 assert(var);
1528 if (var->data.location == FRAG_RESULT_COLOR)
1529 rt = MIDGARD_COLOR_RT0;
1530 else if (var->data.location >= FRAG_RESULT_DATA0)
1531 rt = MIDGARD_COLOR_RT0 + var->data.location -
1532 FRAG_RESULT_DATA0;
1533 else
1534 assert(0);
1535
1536 emit_fragment_store(ctx, reg, rt);
1537 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1538 /* We should have been vectorized, though we don't
1539 * currently check that st_vary is emitted only once
1540 * per slot (this is relevant, since there's not a mask
1541 * parameter available on the store [set to 0 by the
1542 * blob]). We do respect the component by adjusting the
1543 * swizzle. If this is a constant source, we'll need to
1544 * emit that explicitly. */
1545
1546 emit_explicit_constant(ctx, reg, reg);
1547
1548 unsigned dst_component = nir_intrinsic_component(instr);
1549 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1550
1551 midgard_instruction st = m_st_vary_32(reg, offset);
1552 st.load_store.arg_1 = 0x9E;
1553 st.load_store.arg_2 = 0x1E;
1554
1555 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1556 case nir_type_uint:
1557 case nir_type_bool:
1558 st.load_store.op = midgard_op_st_vary_32u;
1559 break;
1560 case nir_type_int:
1561 st.load_store.op = midgard_op_st_vary_32i;
1562 break;
1563 case nir_type_float:
1564 st.load_store.op = midgard_op_st_vary_32;
1565 break;
1566 default:
1567 unreachable("Attempted to store unknown type");
1568 break;
1569 }
1570
1571 /* nir_intrinsic_component(store_intr) encodes the
1572 * destination component start. Source component offset
1573 * adjustment is taken care of in
1574 * install_registers_instr(), when offset_swizzle() is
1575 * called.
1576 */
1577 unsigned src_component = COMPONENT_X;
1578
1579 assert(nr_comp > 0);
1580 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1581 st.swizzle[0][i] = src_component;
1582 if (i >= dst_component && i < dst_component + nr_comp - 1)
1583 src_component++;
1584 }
1585
1586 emit_mir_instruction(ctx, st);
1587 } else {
1588 DBG("Unknown store\n");
1589 assert(0);
1590 }
1591
1592 break;
1593
1594 /* Special case of store_output for lowered blend shaders */
1595 case nir_intrinsic_store_raw_output_pan:
1596 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1597 reg = nir_src_index(ctx, &instr->src[0]);
1598
1599 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1600 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1601 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1602 * of:
1603 *
1604 * imov r0.xyzw, r0.xxxx
1605 */
1606
1607 unsigned expanded = make_compiler_temp(ctx);
1608
1609 midgard_instruction splatter = v_mov(reg, expanded);
1610
1611 for (unsigned c = 0; c < 16; ++c)
1612 splatter.swizzle[1][c] = 0;
1613
1614 emit_mir_instruction(ctx, splatter);
1615 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1616 } else
1617 emit_fragment_store(ctx, reg, ctx->blend_rt);
1618
1619 break;
1620
1621 case nir_intrinsic_store_global:
1622 case nir_intrinsic_store_shared:
1623 reg = nir_src_index(ctx, &instr->src[0]);
1624 emit_explicit_constant(ctx, reg, reg);
1625
1626 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1627 break;
1628
1629 case nir_intrinsic_load_ssbo_address:
1630 emit_sysval_read(ctx, &instr->instr, 1, 0);
1631 break;
1632
1633 case nir_intrinsic_get_buffer_size:
1634 emit_sysval_read(ctx, &instr->instr, 1, 8);
1635 break;
1636
1637 case nir_intrinsic_load_viewport_scale:
1638 case nir_intrinsic_load_viewport_offset:
1639 case nir_intrinsic_load_num_work_groups:
1640 case nir_intrinsic_load_sampler_lod_parameters_pan:
1641 emit_sysval_read(ctx, &instr->instr, 3, 0);
1642 break;
1643
1644 case nir_intrinsic_load_work_group_id:
1645 case nir_intrinsic_load_local_invocation_id:
1646 emit_compute_builtin(ctx, instr);
1647 break;
1648
1649 case nir_intrinsic_load_vertex_id:
1650 case nir_intrinsic_load_instance_id:
1651 emit_vertex_builtin(ctx, instr);
1652 break;
1653
1654 case nir_intrinsic_memory_barrier_buffer:
1655 case nir_intrinsic_memory_barrier_shared:
1656 break;
1657
1658 case nir_intrinsic_control_barrier:
1659 schedule_barrier(ctx);
1660 emit_control_barrier(ctx);
1661 schedule_barrier(ctx);
1662 break;
1663
1664 default:
1665 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1666 assert(0);
1667 break;
1668 }
1669 }
1670
1671 static unsigned
1672 midgard_tex_format(enum glsl_sampler_dim dim)
1673 {
1674 switch (dim) {
1675 case GLSL_SAMPLER_DIM_1D:
1676 case GLSL_SAMPLER_DIM_BUF:
1677 return MALI_TEX_1D;
1678
1679 case GLSL_SAMPLER_DIM_2D:
1680 case GLSL_SAMPLER_DIM_EXTERNAL:
1681 case GLSL_SAMPLER_DIM_RECT:
1682 return MALI_TEX_2D;
1683
1684 case GLSL_SAMPLER_DIM_3D:
1685 return MALI_TEX_3D;
1686
1687 case GLSL_SAMPLER_DIM_CUBE:
1688 return MALI_TEX_CUBE;
1689
1690 default:
1691 DBG("Unknown sampler dim type\n");
1692 assert(0);
1693 return 0;
1694 }
1695 }
1696
1697 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1698 * was successful */
1699
1700 static bool
1701 pan_attach_constant_bias(
1702 compiler_context *ctx,
1703 nir_src lod,
1704 midgard_texture_word *word)
1705 {
1706 /* To attach as constant, it has to *be* constant */
1707
1708 if (!nir_src_is_const(lod))
1709 return false;
1710
1711 float f = nir_src_as_float(lod);
1712
1713 /* Break into fixed-point */
1714 signed lod_int = f;
1715 float lod_frac = f - lod_int;
1716
1717 /* Carry over negative fractions */
1718 if (lod_frac < 0.0) {
1719 lod_int--;
1720 lod_frac += 1.0;
1721 }
1722
1723 /* Encode */
1724 word->bias = float_to_ubyte(lod_frac);
1725 word->bias_int = lod_int;
1726
1727 return true;
1728 }
1729
1730 static enum mali_sampler_type
1731 midgard_sampler_type(nir_alu_type t) {
1732 switch (nir_alu_type_get_base_type(t))
1733 {
1734 case nir_type_float:
1735 return MALI_SAMPLER_FLOAT;
1736 case nir_type_int:
1737 return MALI_SAMPLER_SIGNED;
1738 case nir_type_uint:
1739 return MALI_SAMPLER_UNSIGNED;
1740 default:
1741 unreachable("Unknown sampler type");
1742 }
1743 }
1744
1745 static void
1746 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1747 unsigned midgard_texop)
1748 {
1749 /* TODO */
1750 //assert (!instr->sampler);
1751
1752 int texture_index = instr->texture_index;
1753 int sampler_index = texture_index;
1754
1755 /* No helper to build texture words -- we do it all here */
1756 midgard_instruction ins = {
1757 .type = TAG_TEXTURE_4,
1758 .mask = 0xF,
1759 .dest = nir_dest_index(&instr->dest),
1760 .src = { ~0, ~0, ~0, ~0 },
1761 .swizzle = SWIZZLE_IDENTITY_4,
1762 .texture = {
1763 .op = midgard_texop,
1764 .format = midgard_tex_format(instr->sampler_dim),
1765 .texture_handle = texture_index,
1766 .sampler_handle = sampler_index,
1767
1768 /* TODO: half */
1769 .in_reg_full = 1,
1770 .out_full = 1,
1771
1772 .sampler_type = midgard_sampler_type(instr->dest_type),
1773 .shadow = instr->is_shadow,
1774 }
1775 };
1776
1777 /* We may need a temporary for the coordinate */
1778
1779 bool needs_temp_coord =
1780 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1781 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1782 (instr->is_shadow);
1783
1784 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1785
1786 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1787 int index = nir_src_index(ctx, &instr->src[i].src);
1788 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1789
1790 switch (instr->src[i].src_type) {
1791 case nir_tex_src_coord: {
1792 emit_explicit_constant(ctx, index, index);
1793
1794 unsigned coord_mask = mask_of(instr->coord_components);
1795
1796 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1797
1798 if (flip_zw)
1799 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1800
1801 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1802 /* texelFetch is undefined on samplerCube */
1803 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1804
1805 /* For cubemaps, we use a special ld/st op to
1806 * select the face and copy the xy into the
1807 * texture register */
1808
1809 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1810 ld.src[1] = index;
1811 ld.mask = 0x3; /* xy */
1812 ld.load_store.arg_1 = 0x20;
1813 ld.swizzle[1][3] = COMPONENT_X;
1814 emit_mir_instruction(ctx, ld);
1815
1816 /* xyzw -> xyxx */
1817 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1818 ins.swizzle[1][3] = COMPONENT_X;
1819 } else if (needs_temp_coord) {
1820 /* mov coord_temp, coords */
1821 midgard_instruction mov = v_mov(index, coords);
1822 mov.mask = coord_mask;
1823
1824 if (flip_zw)
1825 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1826
1827 emit_mir_instruction(ctx, mov);
1828 } else {
1829 coords = index;
1830 }
1831
1832 ins.src[1] = coords;
1833
1834 /* Texelfetch coordinates uses all four elements
1835 * (xyz/index) regardless of texture dimensionality,
1836 * which means it's necessary to zero the unused
1837 * components to keep everything happy */
1838
1839 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1840 /* mov index.zw, #0, or generalized */
1841 midgard_instruction mov =
1842 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1843 mov.has_constants = true;
1844 mov.mask = coord_mask ^ 0xF;
1845 emit_mir_instruction(ctx, mov);
1846 }
1847
1848 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1849 /* Array component in w but NIR wants it in z,
1850 * but if we have a temp coord we already fixed
1851 * that up */
1852
1853 if (nr_components == 3) {
1854 ins.swizzle[1][2] = COMPONENT_Z;
1855 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1856 } else if (nr_components == 2) {
1857 ins.swizzle[1][2] =
1858 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1859 ins.swizzle[1][3] = COMPONENT_X;
1860 } else
1861 unreachable("Invalid texture 2D components");
1862 }
1863
1864 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1865 /* We zeroed */
1866 ins.swizzle[1][2] = COMPONENT_Z;
1867 ins.swizzle[1][3] = COMPONENT_W;
1868 }
1869
1870 break;
1871 }
1872
1873 case nir_tex_src_bias:
1874 case nir_tex_src_lod: {
1875 /* Try as a constant if we can */
1876
1877 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1878 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1879 break;
1880
1881 ins.texture.lod_register = true;
1882 ins.src[2] = index;
1883
1884 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1885 ins.swizzle[2][c] = COMPONENT_X;
1886
1887 emit_explicit_constant(ctx, index, index);
1888
1889 break;
1890 };
1891
1892 case nir_tex_src_offset: {
1893 ins.texture.offset_register = true;
1894 ins.src[3] = index;
1895
1896 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1897 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1898
1899 emit_explicit_constant(ctx, index, index);
1900 break;
1901 };
1902
1903 case nir_tex_src_comparator: {
1904 unsigned comp = COMPONENT_Z;
1905
1906 /* mov coord_temp.foo, coords */
1907 midgard_instruction mov = v_mov(index, coords);
1908 mov.mask = 1 << comp;
1909
1910 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1911 mov.swizzle[1][i] = COMPONENT_X;
1912
1913 emit_mir_instruction(ctx, mov);
1914 break;
1915 }
1916
1917 default: {
1918 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1919 assert(0);
1920 }
1921 }
1922 }
1923
1924 emit_mir_instruction(ctx, ins);
1925
1926 /* Used for .cont and .last hinting */
1927 ctx->texture_op_count++;
1928 }
1929
1930 static void
1931 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1932 {
1933 switch (instr->op) {
1934 case nir_texop_tex:
1935 case nir_texop_txb:
1936 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1937 break;
1938 case nir_texop_txl:
1939 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1940 break;
1941 case nir_texop_txf:
1942 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1943 break;
1944 case nir_texop_txs:
1945 emit_sysval_read(ctx, &instr->instr, 4, 0);
1946 break;
1947 default: {
1948 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1949 assert(0);
1950 }
1951 }
1952 }
1953
1954 static void
1955 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1956 {
1957 switch (instr->type) {
1958 case nir_jump_break: {
1959 /* Emit a branch out of the loop */
1960 struct midgard_instruction br = v_branch(false, false);
1961 br.branch.target_type = TARGET_BREAK;
1962 br.branch.target_break = ctx->current_loop_depth;
1963 emit_mir_instruction(ctx, br);
1964 break;
1965 }
1966
1967 default:
1968 DBG("Unknown jump type %d\n", instr->type);
1969 break;
1970 }
1971 }
1972
1973 static void
1974 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1975 {
1976 switch (instr->type) {
1977 case nir_instr_type_load_const:
1978 emit_load_const(ctx, nir_instr_as_load_const(instr));
1979 break;
1980
1981 case nir_instr_type_intrinsic:
1982 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1983 break;
1984
1985 case nir_instr_type_alu:
1986 emit_alu(ctx, nir_instr_as_alu(instr));
1987 break;
1988
1989 case nir_instr_type_tex:
1990 emit_tex(ctx, nir_instr_as_tex(instr));
1991 break;
1992
1993 case nir_instr_type_jump:
1994 emit_jump(ctx, nir_instr_as_jump(instr));
1995 break;
1996
1997 case nir_instr_type_ssa_undef:
1998 /* Spurious */
1999 break;
2000
2001 default:
2002 DBG("Unhandled instruction type\n");
2003 break;
2004 }
2005 }
2006
2007
2008 /* ALU instructions can inline or embed constants, which decreases register
2009 * pressure and saves space. */
2010
2011 #define CONDITIONAL_ATTACH(idx) { \
2012 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2013 \
2014 if (entry) { \
2015 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2016 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2017 } \
2018 }
2019
2020 static void
2021 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2022 {
2023 mir_foreach_instr_in_block(block, alu) {
2024 /* Other instructions cannot inline constants */
2025 if (alu->type != TAG_ALU_4) continue;
2026 if (alu->compact_branch) continue;
2027
2028 /* If there is already a constant here, we can do nothing */
2029 if (alu->has_constants) continue;
2030
2031 CONDITIONAL_ATTACH(0);
2032
2033 if (!alu->has_constants) {
2034 CONDITIONAL_ATTACH(1)
2035 } else if (!alu->inline_constant) {
2036 /* Corner case: _two_ vec4 constants, for instance with a
2037 * csel. For this case, we can only use a constant
2038 * register for one, we'll have to emit a move for the
2039 * other. */
2040
2041 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2042 unsigned scratch = make_compiler_temp(ctx);
2043
2044 if (entry) {
2045 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2046 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2047
2048 /* Set the source */
2049 alu->src[1] = scratch;
2050
2051 /* Inject us -before- the last instruction which set r31 */
2052 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2053 }
2054 }
2055 }
2056 }
2057
2058 /* Being a little silly with the names, but returns the op that is the bitwise
2059 * inverse of the op with the argument switched. I.e. (f and g are
2060 * contrapositives):
2061 *
2062 * f(a, b) = ~g(b, a)
2063 *
2064 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
2065 *
2066 * f(a, b) = ~g(b, a)
2067 * ~f(a, b) = g(b, a)
2068 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
2069 * f(a, b) = h(a, b)
2070 *
2071 * Thus we define this function in pairs.
2072 */
2073
2074 static inline midgard_alu_op
2075 mir_contrapositive(midgard_alu_op op)
2076 {
2077 switch (op) {
2078 case midgard_alu_op_flt:
2079 return midgard_alu_op_fle;
2080 case midgard_alu_op_fle:
2081 return midgard_alu_op_flt;
2082
2083 case midgard_alu_op_ilt:
2084 return midgard_alu_op_ile;
2085 case midgard_alu_op_ile:
2086 return midgard_alu_op_ilt;
2087
2088 default:
2089 unreachable("No known contrapositive");
2090 }
2091 }
2092
2093 /* Midgard supports two types of constants, embedded constants (128-bit) and
2094 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2095 * constants can be demoted to inline constants, for space savings and
2096 * sometimes a performance boost */
2097
2098 static void
2099 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2100 {
2101 mir_foreach_instr_in_block(block, ins) {
2102 if (!ins->has_constants) continue;
2103 if (ins->has_inline_constant) continue;
2104
2105 /* Blend constants must not be inlined by definition */
2106 if (ins->has_blend_constant) continue;
2107
2108 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2109 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2110 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2111
2112 if (!(is_16 || is_32))
2113 continue;
2114
2115 /* src1 cannot be an inline constant due to encoding
2116 * restrictions. So, if possible we try to flip the arguments
2117 * in that case */
2118
2119 int op = ins->alu.op;
2120
2121 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2122 bool flip = alu_opcode_props[op].props & OP_COMMUTES;
2123
2124 switch (op) {
2125 /* Conditionals can be inverted */
2126 case midgard_alu_op_flt:
2127 case midgard_alu_op_ilt:
2128 case midgard_alu_op_fle:
2129 case midgard_alu_op_ile:
2130 ins->alu.op = mir_contrapositive(ins->alu.op);
2131 ins->invert = true;
2132 flip = true;
2133 break;
2134
2135 case midgard_alu_op_fcsel:
2136 case midgard_alu_op_icsel:
2137 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
2138 default:
2139 break;
2140 }
2141
2142 if (flip)
2143 mir_flip(ins);
2144 }
2145
2146 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2147 /* Extract the source information */
2148
2149 midgard_vector_alu_src *src;
2150 int q = ins->alu.src2;
2151 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2152 src = m;
2153
2154 /* Component is from the swizzle. Take a nonzero component */
2155 assert(ins->mask);
2156 unsigned first_comp = ffs(ins->mask) - 1;
2157 unsigned component = ins->swizzle[1][first_comp];
2158
2159 /* Scale constant appropriately, if we can legally */
2160 uint16_t scaled_constant = 0;
2161
2162 if (is_16) {
2163 scaled_constant = ins->constants.u16[component];
2164 } else if (midgard_is_integer_op(op)) {
2165 scaled_constant = ins->constants.u32[component];
2166
2167 /* Constant overflow after resize */
2168 if (scaled_constant != ins->constants.u32[component])
2169 continue;
2170 } else {
2171 float original = ins->constants.f32[component];
2172 scaled_constant = _mesa_float_to_half(original);
2173
2174 /* Check for loss of precision. If this is
2175 * mediump, we don't care, but for a highp
2176 * shader, we need to pay attention. NIR
2177 * doesn't yet tell us which mode we're in!
2178 * Practically this prevents most constants
2179 * from being inlined, sadly. */
2180
2181 float fp32 = _mesa_half_to_float(scaled_constant);
2182
2183 if (fp32 != original)
2184 continue;
2185 }
2186
2187 /* We don't know how to handle these with a constant */
2188
2189 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2190 DBG("Bailing inline constant...\n");
2191 continue;
2192 }
2193
2194 /* Make sure that the constant is not itself a vector
2195 * by checking if all accessed values are the same. */
2196
2197 const midgard_constants *cons = &ins->constants;
2198 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2199
2200 bool is_vector = false;
2201 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2202
2203 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2204 /* We only care if this component is actually used */
2205 if (!(mask & (1 << c)))
2206 continue;
2207
2208 uint32_t test = is_16 ?
2209 cons->u16[ins->swizzle[1][c]] :
2210 cons->u32[ins->swizzle[1][c]];
2211
2212 if (test != value) {
2213 is_vector = true;
2214 break;
2215 }
2216 }
2217
2218 if (is_vector)
2219 continue;
2220
2221 /* Get rid of the embedded constant */
2222 ins->has_constants = false;
2223 ins->src[1] = ~0;
2224 ins->has_inline_constant = true;
2225 ins->inline_constant = scaled_constant;
2226 }
2227 }
2228 }
2229
2230 /* Dead code elimination for branches at the end of a block - only one branch
2231 * per block is legal semantically */
2232
2233 static void
2234 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2235 {
2236 bool branched = false;
2237
2238 mir_foreach_instr_in_block_safe(block, ins) {
2239 if (!midgard_is_branch_unit(ins->unit)) continue;
2240
2241 if (branched)
2242 mir_remove_instruction(ins);
2243
2244 branched = true;
2245 }
2246 }
2247
2248 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2249 * the move can be propagated away entirely */
2250
2251 static bool
2252 mir_compose_float_outmod(midgard_outmod_float *outmod, midgard_outmod_float comp)
2253 {
2254 /* Nothing to do */
2255 if (comp == midgard_outmod_none)
2256 return true;
2257
2258 if (*outmod == midgard_outmod_none) {
2259 *outmod = comp;
2260 return true;
2261 }
2262
2263 /* TODO: Compose rules */
2264 return false;
2265 }
2266
2267 static bool
2268 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
2269 {
2270 bool progress = false;
2271
2272 mir_foreach_instr_in_block_safe(block, ins) {
2273 if (ins->type != TAG_ALU_4) continue;
2274 if (ins->alu.op != midgard_alu_op_fmov) continue;
2275 if (ins->alu.outmod != midgard_outmod_pos) continue;
2276
2277 /* TODO: Registers? */
2278 unsigned src = ins->src[1];
2279 if (src & PAN_IS_REG) continue;
2280
2281 /* There might be a source modifier, too */
2282 if (mir_nontrivial_source2_mod(ins)) continue;
2283
2284 /* Backpropagate the modifier */
2285 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
2286 if (v->type != TAG_ALU_4) continue;
2287 if (v->dest != src) continue;
2288
2289 /* Can we even take a float outmod? */
2290 if (midgard_is_integer_out_op(v->alu.op)) continue;
2291
2292 midgard_outmod_float temp = v->alu.outmod;
2293 progress |= mir_compose_float_outmod(&temp, ins->alu.outmod);
2294
2295 /* Throw in the towel.. */
2296 if (!progress) break;
2297
2298 /* Otherwise, transfer the modifier */
2299 v->alu.outmod = temp;
2300 ins->alu.outmod = midgard_outmod_none;
2301
2302 break;
2303 }
2304 }
2305
2306 return progress;
2307 }
2308
2309 static unsigned
2310 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2311 {
2312 /* Loop to ourselves */
2313 midgard_instruction *br = ctx->writeout_branch[rt];
2314 struct midgard_instruction ins = v_branch(false, false);
2315 ins.writeout = true;
2316 ins.writeout_depth = br->writeout_depth;
2317 ins.writeout_stencil = br->writeout_stencil;
2318 ins.branch.target_block = ctx->block_count - 1;
2319 ins.constants.u32[0] = br->constants.u32[0];
2320 emit_mir_instruction(ctx, ins);
2321
2322 ctx->current_block->epilogue = true;
2323 schedule_barrier(ctx);
2324 return ins.branch.target_block;
2325 }
2326
2327 static midgard_block *
2328 emit_block(compiler_context *ctx, nir_block *block)
2329 {
2330 midgard_block *this_block = ctx->after_block;
2331 ctx->after_block = NULL;
2332
2333 if (!this_block)
2334 this_block = create_empty_block(ctx);
2335
2336 list_addtail(&this_block->base.link, &ctx->blocks);
2337
2338 this_block->scheduled = false;
2339 ++ctx->block_count;
2340
2341 /* Set up current block */
2342 list_inithead(&this_block->base.instructions);
2343 ctx->current_block = this_block;
2344
2345 nir_foreach_instr(instr, block) {
2346 emit_instr(ctx, instr);
2347 ++ctx->instruction_count;
2348 }
2349
2350 return this_block;
2351 }
2352
2353 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2354
2355 static void
2356 emit_if(struct compiler_context *ctx, nir_if *nif)
2357 {
2358 midgard_block *before_block = ctx->current_block;
2359
2360 /* Speculatively emit the branch, but we can't fill it in until later */
2361 EMIT(branch, true, true);
2362 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2363 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2364
2365 /* Emit the two subblocks. */
2366 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2367 midgard_block *end_then_block = ctx->current_block;
2368
2369 /* Emit a jump from the end of the then block to the end of the else */
2370 EMIT(branch, false, false);
2371 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2372
2373 /* Emit second block, and check if it's empty */
2374
2375 int else_idx = ctx->block_count;
2376 int count_in = ctx->instruction_count;
2377 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2378 midgard_block *end_else_block = ctx->current_block;
2379 int after_else_idx = ctx->block_count;
2380
2381 /* Now that we have the subblocks emitted, fix up the branches */
2382
2383 assert(then_block);
2384 assert(else_block);
2385
2386 if (ctx->instruction_count == count_in) {
2387 /* The else block is empty, so don't emit an exit jump */
2388 mir_remove_instruction(then_exit);
2389 then_branch->branch.target_block = after_else_idx;
2390 } else {
2391 then_branch->branch.target_block = else_idx;
2392 then_exit->branch.target_block = after_else_idx;
2393 }
2394
2395 /* Wire up the successors */
2396
2397 ctx->after_block = create_empty_block(ctx);
2398
2399 pan_block_add_successor(&before_block->base, &then_block->base);
2400 pan_block_add_successor(&before_block->base, &else_block->base);
2401
2402 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2403 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2404 }
2405
2406 static void
2407 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2408 {
2409 /* Remember where we are */
2410 midgard_block *start_block = ctx->current_block;
2411
2412 /* Allocate a loop number, growing the current inner loop depth */
2413 int loop_idx = ++ctx->current_loop_depth;
2414
2415 /* Get index from before the body so we can loop back later */
2416 int start_idx = ctx->block_count;
2417
2418 /* Emit the body itself */
2419 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2420
2421 /* Branch back to loop back */
2422 struct midgard_instruction br_back = v_branch(false, false);
2423 br_back.branch.target_block = start_idx;
2424 emit_mir_instruction(ctx, br_back);
2425
2426 /* Mark down that branch in the graph. */
2427 pan_block_add_successor(&start_block->base, &loop_block->base);
2428 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2429
2430 /* Find the index of the block about to follow us (note: we don't add
2431 * one; blocks are 0-indexed so we get a fencepost problem) */
2432 int break_block_idx = ctx->block_count;
2433
2434 /* Fix up the break statements we emitted to point to the right place,
2435 * now that we can allocate a block number for them */
2436 ctx->after_block = create_empty_block(ctx);
2437
2438 mir_foreach_block_from(ctx, start_block, _block) {
2439 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2440 if (ins->type != TAG_ALU_4) continue;
2441 if (!ins->compact_branch) continue;
2442
2443 /* We found a branch -- check the type to see if we need to do anything */
2444 if (ins->branch.target_type != TARGET_BREAK) continue;
2445
2446 /* It's a break! Check if it's our break */
2447 if (ins->branch.target_break != loop_idx) continue;
2448
2449 /* Okay, cool, we're breaking out of this loop.
2450 * Rewrite from a break to a goto */
2451
2452 ins->branch.target_type = TARGET_GOTO;
2453 ins->branch.target_block = break_block_idx;
2454
2455 pan_block_add_successor(_block, &ctx->after_block->base);
2456 }
2457 }
2458
2459 /* Now that we've finished emitting the loop, free up the depth again
2460 * so we play nice with recursion amid nested loops */
2461 --ctx->current_loop_depth;
2462
2463 /* Dump loop stats */
2464 ++ctx->loop_count;
2465 }
2466
2467 static midgard_block *
2468 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2469 {
2470 midgard_block *start_block = NULL;
2471
2472 foreach_list_typed(nir_cf_node, node, node, list) {
2473 switch (node->type) {
2474 case nir_cf_node_block: {
2475 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2476
2477 if (!start_block)
2478 start_block = block;
2479
2480 break;
2481 }
2482
2483 case nir_cf_node_if:
2484 emit_if(ctx, nir_cf_node_as_if(node));
2485 break;
2486
2487 case nir_cf_node_loop:
2488 emit_loop(ctx, nir_cf_node_as_loop(node));
2489 break;
2490
2491 case nir_cf_node_function:
2492 assert(0);
2493 break;
2494 }
2495 }
2496
2497 return start_block;
2498 }
2499
2500 /* Due to lookahead, we need to report the first tag executed in the command
2501 * stream and in branch targets. An initial block might be empty, so iterate
2502 * until we find one that 'works' */
2503
2504 static unsigned
2505 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2506 {
2507 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2508
2509 mir_foreach_block_from(ctx, initial_block, _v) {
2510 midgard_block *v = (midgard_block *) _v;
2511 if (v->quadword_count) {
2512 midgard_bundle *initial_bundle =
2513 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2514
2515 return initial_bundle->tag;
2516 }
2517 }
2518
2519 /* Default to a tag 1 which will break from the shader, in case we jump
2520 * to the exit block (i.e. `return` in a compute shader) */
2521
2522 return 1;
2523 }
2524
2525 /* For each fragment writeout instruction, generate a writeout loop to
2526 * associate with it */
2527
2528 static void
2529 mir_add_writeout_loops(compiler_context *ctx)
2530 {
2531 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2532 midgard_instruction *br = ctx->writeout_branch[rt];
2533 if (!br) continue;
2534
2535 unsigned popped = br->branch.target_block;
2536 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2537 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2538
2539 /* If we have more RTs, we'll need to restore back after our
2540 * loop terminates */
2541
2542 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2543 midgard_instruction uncond = v_branch(false, false);
2544 uncond.branch.target_block = popped;
2545 emit_mir_instruction(ctx, uncond);
2546 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2547 schedule_barrier(ctx);
2548 } else {
2549 /* We're last, so we can terminate here */
2550 br->last_writeout = true;
2551 }
2552 }
2553 }
2554
2555 int
2556 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2557 {
2558 struct util_dynarray *compiled = &program->compiled;
2559
2560 midgard_debug = debug_get_option_midgard_debug();
2561
2562 /* TODO: Bound against what? */
2563 compiler_context *ctx = rzalloc(NULL, compiler_context);
2564
2565 ctx->nir = nir;
2566 ctx->stage = nir->info.stage;
2567 ctx->is_blend = is_blend;
2568 ctx->alpha_ref = program->alpha_ref;
2569 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2570 ctx->quirks = midgard_get_quirks(gpu_id);
2571
2572 /* Start off with a safe cutoff, allowing usage of all 16 work
2573 * registers. Later, we'll promote uniform reads to uniform registers
2574 * if we determine it is beneficial to do so */
2575 ctx->uniform_cutoff = 8;
2576
2577 /* Initialize at a global (not block) level hash tables */
2578
2579 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2580 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2581
2582 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2583 * (so we don't accidentally duplicate the epilogue since mesa/st has
2584 * messed with our I/O quite a bit already) */
2585
2586 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2587
2588 if (ctx->stage == MESA_SHADER_VERTEX) {
2589 NIR_PASS_V(nir, nir_lower_viewport_transform);
2590 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2591 }
2592
2593 NIR_PASS_V(nir, nir_lower_var_copies);
2594 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2595 NIR_PASS_V(nir, nir_split_var_copies);
2596 NIR_PASS_V(nir, nir_lower_var_copies);
2597 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2598 NIR_PASS_V(nir, nir_lower_var_copies);
2599 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2600
2601 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2602 NIR_PASS_V(nir, nir_lower_ssbo);
2603 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2604
2605 /* Optimisation passes */
2606
2607 optimise_nir(nir, ctx->quirks);
2608
2609 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2610 nir_print_shader(nir, stdout);
2611 }
2612
2613 /* Assign sysvals and counts, now that we're sure
2614 * (post-optimisation) */
2615
2616 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2617 program->sysval_count = ctx->sysvals.sysval_count;
2618 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2619
2620 nir_foreach_function(func, nir) {
2621 if (!func->impl)
2622 continue;
2623
2624 list_inithead(&ctx->blocks);
2625 ctx->block_count = 0;
2626 ctx->func = func;
2627
2628 emit_cf_list(ctx, &func->impl->body);
2629 break; /* TODO: Multi-function shaders */
2630 }
2631
2632 util_dynarray_init(compiled, NULL);
2633
2634 /* Per-block lowering before opts */
2635
2636 mir_foreach_block(ctx, _block) {
2637 midgard_block *block = (midgard_block *) _block;
2638 inline_alu_constants(ctx, block);
2639 midgard_opt_promote_fmov(ctx, block);
2640 embedded_to_inline_constant(ctx, block);
2641 }
2642 /* MIR-level optimizations */
2643
2644 bool progress = false;
2645
2646 do {
2647 progress = false;
2648
2649 mir_foreach_block(ctx, _block) {
2650 midgard_block *block = (midgard_block *) _block;
2651 progress |= midgard_opt_pos_propagate(ctx, block);
2652 progress |= midgard_opt_copy_prop(ctx, block);
2653 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2654 progress |= midgard_opt_combine_projection(ctx, block);
2655 progress |= midgard_opt_varying_projection(ctx, block);
2656 progress |= midgard_opt_not_propagate(ctx, block);
2657 progress |= midgard_opt_fuse_src_invert(ctx, block);
2658 progress |= midgard_opt_fuse_dest_invert(ctx, block);
2659 progress |= midgard_opt_csel_invert(ctx, block);
2660 progress |= midgard_opt_drop_cmp_invert(ctx, block);
2661 progress |= midgard_opt_invert_branch(ctx, block);
2662 }
2663 } while (progress);
2664
2665 mir_foreach_block(ctx, _block) {
2666 midgard_block *block = (midgard_block *) _block;
2667 midgard_lower_invert(ctx, block);
2668 midgard_lower_derivatives(ctx, block);
2669 }
2670
2671 /* Nested control-flow can result in dead branches at the end of the
2672 * block. This messes with our analysis and is just dead code, so cull
2673 * them */
2674 mir_foreach_block(ctx, _block) {
2675 midgard_block *block = (midgard_block *) _block;
2676 midgard_opt_cull_dead_branch(ctx, block);
2677 }
2678
2679 /* Ensure we were lowered */
2680 mir_foreach_instr_global(ctx, ins) {
2681 assert(!ins->invert);
2682 }
2683
2684 if (ctx->stage == MESA_SHADER_FRAGMENT)
2685 mir_add_writeout_loops(ctx);
2686
2687 /* Schedule! */
2688 midgard_schedule_program(ctx);
2689 mir_ra(ctx);
2690
2691 /* Now that all the bundles are scheduled and we can calculate block
2692 * sizes, emit actual branch instructions rather than placeholders */
2693
2694 int br_block_idx = 0;
2695
2696 mir_foreach_block(ctx, _block) {
2697 midgard_block *block = (midgard_block *) _block;
2698 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2699 for (int c = 0; c < bundle->instruction_count; ++c) {
2700 midgard_instruction *ins = bundle->instructions[c];
2701
2702 if (!midgard_is_branch_unit(ins->unit)) continue;
2703
2704 /* Parse some basic branch info */
2705 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2706 bool is_conditional = ins->branch.conditional;
2707 bool is_inverted = ins->branch.invert_conditional;
2708 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2709 bool is_writeout = ins->writeout;
2710
2711 /* Determine the block we're jumping to */
2712 int target_number = ins->branch.target_block;
2713
2714 /* Report the destination tag */
2715 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2716
2717 /* Count up the number of quadwords we're
2718 * jumping over = number of quadwords until
2719 * (br_block_idx, target_number) */
2720
2721 int quadword_offset = 0;
2722
2723 if (is_discard) {
2724 /* Ignored */
2725 } else if (target_number > br_block_idx) {
2726 /* Jump forward */
2727
2728 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2729 midgard_block *blk = mir_get_block(ctx, idx);
2730 assert(blk);
2731
2732 quadword_offset += blk->quadword_count;
2733 }
2734 } else {
2735 /* Jump backwards */
2736
2737 for (int idx = br_block_idx; idx >= target_number; --idx) {
2738 midgard_block *blk = mir_get_block(ctx, idx);
2739 assert(blk);
2740
2741 quadword_offset -= blk->quadword_count;
2742 }
2743 }
2744
2745 /* Unconditional extended branches (far jumps)
2746 * have issues, so we always use a conditional
2747 * branch, setting the condition to always for
2748 * unconditional. For compact unconditional
2749 * branches, cond isn't used so it doesn't
2750 * matter what we pick. */
2751
2752 midgard_condition cond =
2753 !is_conditional ? midgard_condition_always :
2754 is_inverted ? midgard_condition_false :
2755 midgard_condition_true;
2756
2757 midgard_jmp_writeout_op op =
2758 is_discard ? midgard_jmp_writeout_op_discard :
2759 is_writeout ? midgard_jmp_writeout_op_writeout :
2760 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2761 midgard_jmp_writeout_op_branch_cond;
2762
2763 if (!is_compact) {
2764 midgard_branch_extended branch =
2765 midgard_create_branch_extended(
2766 cond, op,
2767 dest_tag,
2768 quadword_offset);
2769
2770 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2771 } else if (is_conditional || is_discard) {
2772 midgard_branch_cond branch = {
2773 .op = op,
2774 .dest_tag = dest_tag,
2775 .offset = quadword_offset,
2776 .cond = cond
2777 };
2778
2779 assert(branch.offset == quadword_offset);
2780
2781 memcpy(&ins->br_compact, &branch, sizeof(branch));
2782 } else {
2783 assert(op == midgard_jmp_writeout_op_branch_uncond);
2784
2785 midgard_branch_uncond branch = {
2786 .op = op,
2787 .dest_tag = dest_tag,
2788 .offset = quadword_offset,
2789 .unknown = 1
2790 };
2791
2792 assert(branch.offset == quadword_offset);
2793
2794 memcpy(&ins->br_compact, &branch, sizeof(branch));
2795 }
2796 }
2797 }
2798
2799 ++br_block_idx;
2800 }
2801
2802 /* Emit flat binary from the instruction arrays. Iterate each block in
2803 * sequence. Save instruction boundaries such that lookahead tags can
2804 * be assigned easily */
2805
2806 /* Cache _all_ bundles in source order for lookahead across failed branches */
2807
2808 int bundle_count = 0;
2809 mir_foreach_block(ctx, _block) {
2810 midgard_block *block = (midgard_block *) _block;
2811 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2812 }
2813 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2814 int bundle_idx = 0;
2815 mir_foreach_block(ctx, _block) {
2816 midgard_block *block = (midgard_block *) _block;
2817 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2818 source_order_bundles[bundle_idx++] = bundle;
2819 }
2820 }
2821
2822 int current_bundle = 0;
2823
2824 /* Midgard prefetches instruction types, so during emission we
2825 * need to lookahead. Unless this is the last instruction, in
2826 * which we return 1. */
2827
2828 mir_foreach_block(ctx, _block) {
2829 midgard_block *block = (midgard_block *) _block;
2830 mir_foreach_bundle_in_block(block, bundle) {
2831 int lookahead = 1;
2832
2833 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2834 lookahead = source_order_bundles[current_bundle + 1]->tag;
2835
2836 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2837 ++current_bundle;
2838 }
2839
2840 /* TODO: Free deeper */
2841 //util_dynarray_fini(&block->instructions);
2842 }
2843
2844 free(source_order_bundles);
2845
2846 /* Report the very first tag executed */
2847 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2848
2849 /* Deal with off-by-one related to the fencepost problem */
2850 program->work_register_count = ctx->work_registers + 1;
2851 program->uniform_cutoff = ctx->uniform_cutoff;
2852
2853 program->blend_patch_offset = ctx->blend_constant_offset;
2854 program->tls_size = ctx->tls_size;
2855
2856 if (midgard_debug & MIDGARD_DBG_SHADERS)
2857 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2858
2859 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2860 unsigned nr_bundles = 0, nr_ins = 0;
2861
2862 /* Count instructions and bundles */
2863
2864 mir_foreach_block(ctx, _block) {
2865 midgard_block *block = (midgard_block *) _block;
2866 nr_bundles += util_dynarray_num_elements(
2867 &block->bundles, midgard_bundle);
2868
2869 mir_foreach_bundle_in_block(block, bun)
2870 nr_ins += bun->instruction_count;
2871 }
2872
2873 /* Calculate thread count. There are certain cutoffs by
2874 * register count for thread count */
2875
2876 unsigned nr_registers = program->work_register_count;
2877
2878 unsigned nr_threads =
2879 (nr_registers <= 4) ? 4 :
2880 (nr_registers <= 8) ? 2 :
2881 1;
2882
2883 /* Dump stats */
2884
2885 fprintf(stderr, "shader%d - %s shader: "
2886 "%u inst, %u bundles, %u quadwords, "
2887 "%u registers, %u threads, %u loops, "
2888 "%u:%u spills:fills\n",
2889 SHADER_DB_COUNT++,
2890 gl_shader_stage_name(ctx->stage),
2891 nr_ins, nr_bundles, ctx->quadword_count,
2892 nr_registers, nr_threads,
2893 ctx->loop_count,
2894 ctx->spills, ctx->fills);
2895 }
2896
2897 ralloc_free(ctx);
2898
2899 return 0;
2900 }