2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
63 unsigned SHADER_DB_COUNT
= 0;
65 int midgard_debug
= 0;
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 midgard_is_branch_unit(unsigned unit
)
75 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
79 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
81 block
->successors
[block
->nr_successors
++] = successor
;
82 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
85 /* Helpers to generate midgard_instruction's using macro magic, since every
86 * driver seems to do it that way */
88 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
90 #define M_LOAD_STORE(name, rname, uname) \
91 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
92 midgard_instruction i = { \
93 .type = TAG_LOAD_STORE_4, \
101 .op = midgard_op_##name, \
102 .swizzle = SWIZZLE_XYZW, \
110 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
111 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
113 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
114 * the corresponding Midgard source */
116 static midgard_vector_alu_src
117 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
118 bool half
, bool sext
)
120 if (!src
) return blank_alu_src
;
122 /* Figure out how many components there are so we can adjust the
123 * swizzle. Specifically we want to broadcast the last channel so
124 * things like ball2/3 work
127 if (broadcast_count
) {
128 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
130 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
131 src
->swizzle
[c
] = last_component
;
135 midgard_vector_alu_src alu_src
= {
139 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
143 alu_src
.mod
= midgard_int_normal
;
145 /* Sign/zero-extend if needed */
149 midgard_int_sign_extend
150 : midgard_int_zero_extend
;
153 /* These should have been lowered away */
154 assert(!(src
->abs
|| src
->negate
));
156 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
162 /* load/store instructions have both 32-bit and 16-bit variants, depending on
163 * whether we are using vectors composed of highp or mediump. At the moment, we
164 * don't support half-floats -- this requires changes in other parts of the
165 * compiler -- therefore the 16-bit versions are commented out. */
167 //M_LOAD(ld_attr_16);
169 //M_LOAD(ld_vary_16);
171 //M_LOAD(ld_uniform_16);
172 M_LOAD(ld_uniform_32
);
173 M_LOAD(ld_color_buffer_8
);
174 //M_STORE(st_vary_16);
176 M_LOAD(st_cubemap_coords
);
178 static midgard_instruction
179 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
181 midgard_branch_cond branch
= {
189 memcpy(&compact
, &branch
, sizeof(branch
));
191 midgard_instruction ins
= {
193 .unit
= ALU_ENAB_BR_COMPACT
,
194 .prepacked_branch
= true,
195 .compact_branch
= true,
196 .br_compact
= compact
199 if (op
== midgard_jmp_writeout_op_writeout
)
205 static midgard_instruction
206 v_branch(bool conditional
, bool invert
)
208 midgard_instruction ins
= {
210 .unit
= ALU_ENAB_BRANCH
,
211 .compact_branch
= true,
213 .conditional
= conditional
,
214 .invert_conditional
= invert
221 static midgard_branch_extended
222 midgard_create_branch_extended( midgard_condition cond
,
223 midgard_jmp_writeout_op op
,
225 signed quadword_offset
)
227 /* For unclear reasons, the condition code is repeated 8 times */
228 uint16_t duplicated_cond
=
238 midgard_branch_extended branch
= {
240 .dest_tag
= dest_tag
,
241 .offset
= quadword_offset
,
242 .cond
= duplicated_cond
249 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
251 ins
->has_constants
= true;
252 memcpy(&ins
->constants
, constants
, 16);
256 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
258 return glsl_count_attribute_slots(type
, false);
261 /* Lower fdot2 to a vector multiplication followed by channel addition */
263 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
265 if (alu
->op
!= nir_op_fdot2
)
268 b
->cursor
= nir_before_instr(&alu
->instr
);
270 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
271 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
273 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
275 nir_ssa_def
*sum
= nir_fadd(b
,
276 nir_channel(b
, product
, 0),
277 nir_channel(b
, product
, 1));
279 /* Replace the fdot2 with this sum */
280 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
284 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
286 switch (instr
->intrinsic
) {
287 case nir_intrinsic_load_viewport_scale
:
288 return PAN_SYSVAL_VIEWPORT_SCALE
;
289 case nir_intrinsic_load_viewport_offset
:
290 return PAN_SYSVAL_VIEWPORT_OFFSET
;
297 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
300 return (dst
->ssa
.index
<< 1) | 0;
302 assert(!dst
->reg
.indirect
);
303 return (dst
->reg
.reg
->index
<< 1) | IS_REG
;
308 make_compiler_temp(compiler_context
*ctx
)
310 return ctx
->func
->impl
->ssa_alloc
+ ctx
->func
->impl
->reg_alloc
+ ctx
->temp_alloc
++;
313 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
316 nir_intrinsic_instr
*intr
;
317 nir_dest
*dst
= NULL
;
321 switch (instr
->type
) {
322 case nir_instr_type_intrinsic
:
323 intr
= nir_instr_as_intrinsic(instr
);
324 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
327 case nir_instr_type_tex
:
328 tex
= nir_instr_as_tex(instr
);
329 if (tex
->op
!= nir_texop_txs
)
332 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
333 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
334 nir_tex_instr_dest_size(tex
) -
335 (tex
->is_array
? 1 : 0),
344 *dest
= nir_dest_index(ctx
, dst
);
350 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
354 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
358 /* We have a sysval load; check if it's already been assigned */
360 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
363 /* It hasn't -- so assign it now! */
365 unsigned id
= ctx
->sysval_count
++;
366 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
367 ctx
->sysvals
[id
] = sysval
;
371 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
373 ctx
->sysval_count
= 0;
375 nir_foreach_function(function
, shader
) {
376 if (!function
->impl
) continue;
378 nir_foreach_block(block
, function
->impl
) {
379 nir_foreach_instr_safe(instr
, block
) {
380 midgard_nir_assign_sysval_body(ctx
, instr
);
387 midgard_nir_lower_fdot2(nir_shader
*shader
)
389 bool progress
= false;
391 nir_foreach_function(function
, shader
) {
392 if (!function
->impl
) continue;
395 nir_builder
*b
= &_b
;
396 nir_builder_init(b
, function
->impl
);
398 nir_foreach_block(block
, function
->impl
) {
399 nir_foreach_instr_safe(instr
, block
) {
400 if (instr
->type
!= nir_instr_type_alu
) continue;
402 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
403 midgard_nir_lower_fdot2_body(b
, alu
);
409 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
416 /* Flushes undefined values to zero */
419 optimise_nir(nir_shader
*nir
)
422 unsigned lower_flrp
=
423 (nir
->options
->lower_flrp16
? 16 : 0) |
424 (nir
->options
->lower_flrp32
? 32 : 0) |
425 (nir
->options
->lower_flrp64
? 64 : 0);
427 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
428 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
429 NIR_PASS(progress
, nir
, nir_lower_idiv
);
431 nir_lower_tex_options lower_tex_1st_pass_options
= {
436 nir_lower_tex_options lower_tex_2nd_pass_options
= {
437 .lower_txs_lod
= true,
440 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_1st_pass_options
);
441 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_2nd_pass_options
);
446 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
447 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
449 NIR_PASS(progress
, nir
, nir_copy_prop
);
450 NIR_PASS(progress
, nir
, nir_opt_dce
);
451 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
452 NIR_PASS(progress
, nir
, nir_opt_cse
);
453 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
454 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
455 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
457 if (lower_flrp
!= 0) {
458 bool lower_flrp_progress
= false;
459 NIR_PASS(lower_flrp_progress
,
463 false /* always_precise */,
464 nir
->options
->lower_ffma
);
465 if (lower_flrp_progress
) {
466 NIR_PASS(progress
, nir
,
467 nir_opt_constant_folding
);
471 /* Nothing should rematerialize any flrps, so we only
472 * need to do this lowering once.
477 NIR_PASS(progress
, nir
, nir_opt_undef
);
478 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
480 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
483 nir_var_function_temp
);
485 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
488 /* Must be run at the end to prevent creation of fsin/fcos ops */
489 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
494 NIR_PASS(progress
, nir
, nir_opt_dce
);
495 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
496 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
497 NIR_PASS(progress
, nir
, nir_copy_prop
);
500 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
502 /* We implement booleans as 32-bit 0/~0 */
503 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
505 /* Now that booleans are lowered, we can run out late opts */
506 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
508 /* Lower mods for float ops only. Integer ops don't support modifiers
509 * (saturate doesn't make sense on integers, neg/abs require dedicated
512 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
513 NIR_PASS(progress
, nir
, nir_copy_prop
);
514 NIR_PASS(progress
, nir
, nir_opt_dce
);
516 /* Take us out of SSA */
517 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
518 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
520 /* We are a vector architecture; write combine where possible */
521 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
522 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
524 NIR_PASS(progress
, nir
, nir_opt_dce
);
527 /* Do not actually emit a load; instead, cache the constant for inlining */
530 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
532 nir_ssa_def def
= instr
->def
;
534 float *v
= rzalloc_array(NULL
, float, 4);
535 nir_const_load_to_arr(v
, instr
, f32
);
537 /* Shifted for SSA, +1 for off-by-one */
538 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, v
);
541 /* Normally constants are embedded implicitly, but for I/O and such we have to
542 * explicitly emit a move with the constant source */
545 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
547 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
549 if (constant_value
) {
550 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, to
);
551 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
552 emit_mir_instruction(ctx
, ins
);
557 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
560 return (src
->ssa
->index
<< 1) | 0;
562 assert(!src
->reg
.indirect
);
563 return (src
->reg
.reg
->index
<< 1) | IS_REG
;
568 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
570 return nir_src_index(ctx
, &src
->src
);
574 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
576 unsigned comp
= src
->swizzle
[0];
578 for (unsigned c
= 1; c
< nr_components
; ++c
) {
579 if (src
->swizzle
[c
] != comp
)
586 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
587 * output of a conditional test) into that register */
590 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
592 int condition
= nir_src_index(ctx
, src
);
594 /* Source to swizzle the desired component into w */
596 const midgard_vector_alu_src alu_src
= {
597 .swizzle
= SWIZZLE(component
, component
, component
, component
),
600 /* There is no boolean move instruction. Instead, we simulate a move by
601 * ANDing the condition with itself to get it into r31.w */
603 midgard_instruction ins
= {
606 /* We need to set the conditional as close as possible */
607 .precede_break
= true,
608 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
609 .mask
= 1 << COMPONENT_W
,
614 .dest
= SSA_FIXED_REGISTER(31),
618 .op
= midgard_alu_op_iand
,
619 .outmod
= midgard_outmod_int_wrap
,
620 .reg_mode
= midgard_reg_mode_32
,
621 .dest_override
= midgard_dest_override_none
,
622 .src1
= vector_alu_srco_unsigned(alu_src
),
623 .src2
= vector_alu_srco_unsigned(alu_src
)
627 emit_mir_instruction(ctx
, ins
);
630 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
634 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
636 int condition
= nir_src_index(ctx
, &src
->src
);
638 /* Source to swizzle the desired component into w */
640 const midgard_vector_alu_src alu_src
= {
641 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
644 /* There is no boolean move instruction. Instead, we simulate a move by
645 * ANDing the condition with itself to get it into r31.w */
647 midgard_instruction ins
= {
649 .precede_break
= true,
650 .mask
= mask_of(nr_comp
),
654 .dest
= SSA_FIXED_REGISTER(31),
657 .op
= midgard_alu_op_iand
,
658 .outmod
= midgard_outmod_int_wrap
,
659 .reg_mode
= midgard_reg_mode_32
,
660 .dest_override
= midgard_dest_override_none
,
661 .src1
= vector_alu_srco_unsigned(alu_src
),
662 .src2
= vector_alu_srco_unsigned(alu_src
)
666 emit_mir_instruction(ctx
, ins
);
671 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
672 * pinning to eliminate this move in all known cases */
675 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
677 int offset
= nir_src_index(ctx
, src
);
679 midgard_instruction ins
= {
681 .mask
= 1 << COMPONENT_W
,
683 .src0
= SSA_UNUSED_1
,
685 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
688 .op
= midgard_alu_op_imov
,
689 .outmod
= midgard_outmod_int_wrap
,
690 .reg_mode
= midgard_reg_mode_32
,
691 .dest_override
= midgard_dest_override_none
,
692 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
693 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
697 emit_mir_instruction(ctx
, ins
);
700 #define ALU_CASE(nir, _op) \
702 op = midgard_alu_op_##_op; \
703 assert(src_bitsize == dst_bitsize); \
706 #define ALU_CASE_BCAST(nir, _op, count) \
708 op = midgard_alu_op_##_op; \
709 broadcast_swizzle = count; \
710 assert(src_bitsize == dst_bitsize); \
713 nir_is_fzero_constant(nir_src src
)
715 if (!nir_src_is_const(src
))
718 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
719 if (nir_src_comp_as_float(src
, c
) != 0.0)
726 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
727 * special treatment override this anyway. */
729 static midgard_reg_mode
730 reg_mode_for_nir(nir_alu_instr
*instr
)
732 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
734 switch (src_bitsize
) {
736 return midgard_reg_mode_8
;
738 return midgard_reg_mode_16
;
740 return midgard_reg_mode_32
;
742 return midgard_reg_mode_64
;
744 unreachable("Invalid bit size");
749 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
751 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
753 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
754 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
755 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
757 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
758 * supported. A few do not and are commented for now. Also, there are a
759 * number of NIR ops which Midgard does not support and need to be
760 * lowered, also TODO. This switch block emits the opcode and calling
761 * convention of the Midgard instruction; actual packing is done in
766 /* Number of components valid to check for the instruction (the rest
767 * will be forced to the last), or 0 to use as-is. Relevant as
768 * ball-type instructions have a channel count in NIR but are all vec4
771 unsigned broadcast_swizzle
= 0;
773 /* What register mode should we operate in? */
774 midgard_reg_mode reg_mode
=
775 reg_mode_for_nir(instr
);
777 /* Do we need a destination override? Used for inline
780 midgard_dest_override dest_override
=
781 midgard_dest_override_none
;
783 /* Should we use a smaller respective source and sign-extend? */
785 bool half_1
= false, sext_1
= false;
786 bool half_2
= false, sext_2
= false;
788 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
789 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
792 ALU_CASE(fadd
, fadd
);
793 ALU_CASE(fmul
, fmul
);
794 ALU_CASE(fmin
, fmin
);
795 ALU_CASE(fmax
, fmax
);
796 ALU_CASE(imin
, imin
);
797 ALU_CASE(imax
, imax
);
798 ALU_CASE(umin
, umin
);
799 ALU_CASE(umax
, umax
);
800 ALU_CASE(ffloor
, ffloor
);
801 ALU_CASE(fround_even
, froundeven
);
802 ALU_CASE(ftrunc
, ftrunc
);
803 ALU_CASE(fceil
, fceil
);
804 ALU_CASE(fdot3
, fdot3
);
805 ALU_CASE(fdot4
, fdot4
);
806 ALU_CASE(iadd
, iadd
);
807 ALU_CASE(isub
, isub
);
808 ALU_CASE(imul
, imul
);
810 /* Zero shoved as second-arg */
811 ALU_CASE(iabs
, iabsdiff
);
815 ALU_CASE(feq32
, feq
);
816 ALU_CASE(fne32
, fne
);
817 ALU_CASE(flt32
, flt
);
818 ALU_CASE(ieq32
, ieq
);
819 ALU_CASE(ine32
, ine
);
820 ALU_CASE(ilt32
, ilt
);
821 ALU_CASE(ult32
, ult
);
823 /* We don't have a native b2f32 instruction. Instead, like many
824 * GPUs, we exploit booleans as 0/~0 for false/true, and
825 * correspondingly AND
826 * by 1.0 to do the type conversion. For the moment, prime us
829 * iand [whatever], #0
831 * At the end of emit_alu (as MIR), we'll fix-up the constant
834 ALU_CASE(b2f32
, iand
);
835 ALU_CASE(b2i32
, iand
);
837 /* Likewise, we don't have a dedicated f2b32 instruction, but
838 * we can do a "not equal to 0.0" test. */
840 ALU_CASE(f2b32
, fne
);
841 ALU_CASE(i2b32
, ine
);
843 ALU_CASE(frcp
, frcp
);
844 ALU_CASE(frsq
, frsqrt
);
845 ALU_CASE(fsqrt
, fsqrt
);
846 ALU_CASE(fexp2
, fexp2
);
847 ALU_CASE(flog2
, flog2
);
849 ALU_CASE(f2i32
, f2i_rtz
);
850 ALU_CASE(f2u32
, f2u_rtz
);
851 ALU_CASE(i2f32
, i2f_rtz
);
852 ALU_CASE(u2f32
, u2f_rtz
);
854 ALU_CASE(f2i16
, f2i_rtz
);
855 ALU_CASE(f2u16
, f2u_rtz
);
856 ALU_CASE(i2f16
, i2f_rtz
);
857 ALU_CASE(u2f16
, u2f_rtz
);
859 ALU_CASE(fsin
, fsin
);
860 ALU_CASE(fcos
, fcos
);
862 /* Second op implicit #0 */
863 ALU_CASE(inot
, inor
);
864 ALU_CASE(iand
, iand
);
866 ALU_CASE(ixor
, ixor
);
867 ALU_CASE(ishl
, ishl
);
868 ALU_CASE(ishr
, iasr
);
869 ALU_CASE(ushr
, ilsr
);
871 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
872 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
873 ALU_CASE(b32all_fequal4
, fball_eq
);
875 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
876 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
877 ALU_CASE(b32any_fnequal4
, fbany_neq
);
879 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
880 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
881 ALU_CASE(b32all_iequal4
, iball_eq
);
883 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
884 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
885 ALU_CASE(b32any_inequal4
, ibany_neq
);
887 /* Source mods will be shoved in later */
888 ALU_CASE(fabs
, fmov
);
889 ALU_CASE(fneg
, fmov
);
890 ALU_CASE(fsat
, fmov
);
892 /* For size conversion, we use a move. Ideally though we would squash
893 * these ops together; maybe that has to happen after in NIR as part of
894 * propagation...? An earlier algebraic pass ensured we step down by
895 * only / exactly one size. If stepping down, we use a dest override to
896 * reduce the size; if stepping up, we use a larger-sized move with a
897 * half source and a sign/zero-extension modifier */
902 /* If we end up upscale, we'll need a sign-extend on the
903 * operand (the second argument) */
909 op
= midgard_alu_op_imov
;
911 if (dst_bitsize
== (src_bitsize
* 2)) {
915 /* Use a greater register mode */
917 } else if (src_bitsize
== (dst_bitsize
* 2)) {
918 /* Converting down */
919 dest_override
= midgard_dest_override_lower
;
926 assert(src_bitsize
== 32);
928 op
= midgard_alu_op_fmov
;
929 dest_override
= midgard_dest_override_lower
;
934 assert(src_bitsize
== 16);
936 op
= midgard_alu_op_fmov
;
943 /* For greater-or-equal, we lower to less-or-equal and flip the
951 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
952 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
953 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
954 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
957 /* Swap via temporary */
958 nir_alu_src temp
= instr
->src
[1];
959 instr
->src
[1] = instr
->src
[0];
960 instr
->src
[0] = temp
;
965 case nir_op_b32csel
: {
966 /* Midgard features both fcsel and icsel, depending on
967 * the type of the arguments/output. However, as long
968 * as we're careful we can _always_ use icsel and
969 * _never_ need fcsel, since the latter does additional
970 * floating-point-specific processing whereas the
971 * former just moves bits on the wire. It's not obvious
972 * why these are separate opcodes, save for the ability
973 * to do things like sat/pos/abs/neg for free */
975 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
976 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
978 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
981 /* Emit the condition into r31 */
984 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
986 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
988 /* The condition is the first argument; move the other
989 * arguments up one to be a binary instruction for
992 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
997 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1002 /* Midgard can perform certain modifiers on output of an ALU op */
1005 if (midgard_is_integer_out_op(op
)) {
1006 outmod
= midgard_outmod_int_wrap
;
1008 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
1009 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
1012 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
1014 if (instr
->op
== nir_op_fmax
) {
1015 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
1016 op
= midgard_alu_op_fmov
;
1018 outmod
= midgard_outmod_pos
;
1019 instr
->src
[0] = instr
->src
[1];
1020 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1021 op
= midgard_alu_op_fmov
;
1023 outmod
= midgard_outmod_pos
;
1027 /* Fetch unit, quirks, etc information */
1028 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1029 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1031 /* src0 will always exist afaik, but src1 will not for 1-argument
1032 * instructions. The latter can only be fetched if the instruction
1033 * needs it, or else we may segfault. */
1035 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1036 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1038 /* Rather than use the instruction generation helpers, we do it
1039 * ourselves here to avoid the mess */
1041 midgard_instruction ins
= {
1044 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1045 .src1
= quirk_flipped_r24
? src0
: src1
,
1050 nir_alu_src
*nirmods
[2] = { NULL
};
1052 if (nr_inputs
== 2) {
1053 nirmods
[0] = &instr
->src
[0];
1054 nirmods
[1] = &instr
->src
[1];
1055 } else if (nr_inputs
== 1) {
1056 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1061 /* These were lowered to a move, so apply the corresponding mod */
1063 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1064 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
1066 if (instr
->op
== nir_op_fneg
)
1067 s
->negate
= !s
->negate
;
1069 if (instr
->op
== nir_op_fabs
)
1073 bool is_int
= midgard_is_integer_op(op
);
1075 ins
.mask
= mask_of(nr_components
);
1077 midgard_vector_alu alu
= {
1079 .reg_mode
= reg_mode
,
1080 .dest_override
= dest_override
,
1083 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1084 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1087 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1090 ins
.mask
&= instr
->dest
.write_mask
;
1094 /* Late fixup for emulated instructions */
1096 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1097 /* Presently, our second argument is an inline #0 constant.
1098 * Switch over to an embedded 1.0 constant (that can't fit
1099 * inline, since we're 32-bit, not 16-bit like the inline
1102 ins
.ssa_args
.inline_constant
= false;
1103 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1104 ins
.has_constants
= true;
1106 if (instr
->op
== nir_op_b2f32
) {
1107 ins
.constants
[0] = 1.0f
;
1109 /* Type pun it into place */
1111 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1114 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1115 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1116 /* Lots of instructions need a 0 plonked in */
1117 ins
.ssa_args
.inline_constant
= false;
1118 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1119 ins
.has_constants
= true;
1120 ins
.constants
[0] = 0.0f
;
1121 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1122 } else if (instr
->op
== nir_op_inot
) {
1123 /* ~b = ~(b & b), so duplicate the source */
1124 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
1125 ins
.alu
.src2
= ins
.alu
.src1
;
1128 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1129 /* To avoid duplicating the lookup tables (probably), true LUT
1130 * instructions can only operate as if they were scalars. Lower
1131 * them here by changing the component. */
1133 uint8_t original_swizzle
[4];
1134 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1135 unsigned orig_mask
= ins
.mask
;
1137 for (int i
= 0; i
< nr_components
; ++i
) {
1138 /* Mask the associated component, dropping the
1139 * instruction if needed */
1142 ins
.mask
&= orig_mask
;
1147 for (int j
= 0; j
< 4; ++j
)
1148 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1150 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, false));
1151 emit_mir_instruction(ctx
, ins
);
1154 emit_mir_instruction(ctx
, ins
);
1160 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1161 * optimized) versions of UBO #0 */
1165 compiler_context
*ctx
,
1168 nir_src
*indirect_offset
,
1171 /* TODO: half-floats */
1173 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
1175 /* TODO: Don't split */
1176 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1177 ins
.load_store
.address
= offset
>> 3;
1179 if (indirect_offset
) {
1180 emit_indirect_offset(ctx
, indirect_offset
);
1181 ins
.load_store
.unknown
= 0x8700 | index
; /* xxx: what is this? */
1183 ins
.load_store
.unknown
= 0x1E00 | index
; /* xxx: what is this? */
1186 emit_mir_instruction(ctx
, ins
);
1191 compiler_context
*ctx
,
1192 unsigned dest
, unsigned offset
,
1193 unsigned nr_comp
, unsigned component
,
1194 nir_src
*indirect_offset
, nir_alu_type type
)
1196 /* XXX: Half-floats? */
1197 /* TODO: swizzle, mask */
1199 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1200 ins
.mask
= mask_of(nr_comp
);
1201 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1203 midgard_varying_parameter p
= {
1205 .interpolation
= midgard_interp_default
,
1206 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1210 memcpy(&u
, &p
, sizeof(p
));
1211 ins
.load_store
.varying_parameters
= u
;
1213 if (indirect_offset
) {
1214 /* We need to add in the dynamic index, moved to r27.w */
1215 emit_indirect_offset(ctx
, indirect_offset
);
1216 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1218 /* Just a direct load */
1219 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1222 /* Use the type appropriate load */
1226 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1229 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1231 case nir_type_float
:
1232 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1235 unreachable("Attempted to load unknown type");
1239 emit_mir_instruction(ctx
, ins
);
1243 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
)
1247 /* Figure out which uniform this is */
1248 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1249 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1251 /* Sysvals are prefix uniforms */
1252 unsigned uniform
= ((uintptr_t) val
) - 1;
1254 /* Emit the read itself -- this is never indirect */
1255 emit_ubo_read(ctx
, dest
, uniform
, NULL
, 0);
1259 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1261 unsigned offset
= 0, reg
;
1263 switch (instr
->intrinsic
) {
1264 case nir_intrinsic_discard_if
:
1265 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1269 case nir_intrinsic_discard
: {
1270 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1271 struct midgard_instruction discard
= v_branch(conditional
, false);
1272 discard
.branch
.target_type
= TARGET_DISCARD
;
1273 emit_mir_instruction(ctx
, discard
);
1277 case nir_intrinsic_load_uniform
:
1278 case nir_intrinsic_load_ubo
:
1279 case nir_intrinsic_load_input
: {
1280 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1281 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1283 /* Get the base type of the intrinsic */
1284 /* TODO: Infer type? Does it matter? */
1286 is_ubo
? nir_type_uint
: nir_intrinsic_type(instr
);
1287 t
= nir_alu_type_get_base_type(t
);
1290 offset
= nir_intrinsic_base(instr
);
1293 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1295 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1297 bool direct
= nir_src_is_const(*src_offset
);
1300 offset
+= nir_src_as_uint(*src_offset
);
1302 /* We may need to apply a fractional offset */
1303 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1304 nir_intrinsic_component(instr
) : 0;
1305 reg
= nir_dest_index(ctx
, &instr
->dest
);
1307 if (is_uniform
&& !ctx
->is_blend
) {
1308 emit_ubo_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
, 0);
1309 } else if (is_ubo
) {
1310 nir_src index
= instr
->src
[0];
1312 /* We don't yet support indirect UBOs. For indirect
1313 * block numbers (if that's possible), we don't know
1314 * enough about the hardware yet. For indirect sources,
1315 * we know what we need but we need to add some NIR
1316 * support for lowering correctly with respect to
1319 assert(nir_src_is_const(index
));
1320 assert(nir_src_is_const(*src_offset
));
1322 /* TODO: Alignment */
1323 assert((offset
& 0xF) == 0);
1325 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1326 emit_ubo_read(ctx
, reg
, offset
/ 16, NULL
, uindex
);
1327 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1328 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
, t
);
1329 } else if (ctx
->is_blend
) {
1330 /* For blend shaders, load the input color, which is
1331 * preloaded to r0 */
1333 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), blank_alu_src
, reg
);
1334 emit_mir_instruction(ctx
, move
);
1335 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1336 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1337 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1338 ins
.mask
= mask_of(nr_comp
);
1340 /* Use the type appropriate load */
1344 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1347 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1349 case nir_type_float
:
1350 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1353 unreachable("Attempted to load unknown type");
1357 emit_mir_instruction(ctx
, ins
);
1359 DBG("Unknown load\n");
1366 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1368 case nir_intrinsic_load_raw_output_pan
:
1369 reg
= nir_dest_index(ctx
, &instr
->dest
);
1370 assert(ctx
->is_blend
);
1372 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1373 emit_mir_instruction(ctx
, ins
);
1376 case nir_intrinsic_load_blend_const_color_rgba
: {
1377 assert(ctx
->is_blend
);
1378 reg
= nir_dest_index(ctx
, &instr
->dest
);
1380 /* Blend constants are embedded directly in the shader and
1381 * patched in, so we use some magic routing */
1383 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1384 ins
.has_constants
= true;
1385 ins
.has_blend_constant
= true;
1386 emit_mir_instruction(ctx
, ins
);
1390 case nir_intrinsic_store_output
:
1391 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1393 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1395 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1397 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1398 /* gl_FragColor is not emitted with load/store
1399 * instructions. Instead, it gets plonked into
1400 * r0 at the end of the shader and we do the
1401 * framebuffer writeout dance. TODO: Defer
1404 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1405 emit_mir_instruction(ctx
, move
);
1407 /* Save the index we're writing to for later reference
1408 * in the epilogue */
1410 ctx
->fragment_output
= reg
;
1411 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1412 /* We should have been vectorized, though we don't
1413 * currently check that st_vary is emitted only once
1414 * per slot (this is relevant, since there's not a mask
1415 * parameter available on the store [set to 0 by the
1416 * blob]). We do respect the component by adjusting the
1417 * swizzle. If this is a constant source, we'll need to
1418 * emit that explicitly. */
1420 emit_explicit_constant(ctx
, reg
, reg
);
1422 unsigned component
= nir_intrinsic_component(instr
);
1424 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1425 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1426 st
.load_store
.swizzle
= SWIZZLE_XYZW
<< (2*component
);
1427 emit_mir_instruction(ctx
, st
);
1429 DBG("Unknown store\n");
1435 /* Special case of store_output for lowered blend shaders */
1436 case nir_intrinsic_store_raw_output_pan
:
1437 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1438 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1440 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1441 emit_mir_instruction(ctx
, move
);
1442 ctx
->fragment_output
= reg
;
1446 case nir_intrinsic_load_alpha_ref_float
:
1447 assert(instr
->dest
.is_ssa
);
1449 float ref_value
= ctx
->alpha_ref
;
1451 float *v
= ralloc_array(NULL
, float, 4);
1452 memcpy(v
, &ref_value
, sizeof(float));
1453 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1456 case nir_intrinsic_load_viewport_scale
:
1457 case nir_intrinsic_load_viewport_offset
:
1458 emit_sysval_read(ctx
, &instr
->instr
);
1462 printf ("Unhandled intrinsic\n");
1469 midgard_tex_format(enum glsl_sampler_dim dim
)
1472 case GLSL_SAMPLER_DIM_1D
:
1473 case GLSL_SAMPLER_DIM_BUF
:
1476 case GLSL_SAMPLER_DIM_2D
:
1477 case GLSL_SAMPLER_DIM_EXTERNAL
:
1480 case GLSL_SAMPLER_DIM_3D
:
1483 case GLSL_SAMPLER_DIM_CUBE
:
1484 return MALI_TEX_CUBE
;
1487 DBG("Unknown sampler dim type\n");
1493 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1497 pan_attach_constant_bias(
1498 compiler_context
*ctx
,
1500 midgard_texture_word
*word
)
1502 /* To attach as constant, it has to *be* constant */
1504 if (!nir_src_is_const(lod
))
1507 float f
= nir_src_as_float(lod
);
1509 /* Break into fixed-point */
1511 float lod_frac
= f
- lod_int
;
1513 /* Carry over negative fractions */
1514 if (lod_frac
< 0.0) {
1520 word
->bias
= float_to_ubyte(lod_frac
);
1521 word
->bias_int
= lod_int
;
1526 static enum mali_sampler_type
1527 midgard_sampler_type(nir_alu_type t
) {
1528 switch (nir_alu_type_get_base_type(t
))
1530 case nir_type_float
:
1531 return MALI_SAMPLER_FLOAT
;
1533 return MALI_SAMPLER_SIGNED
;
1535 return MALI_SAMPLER_UNSIGNED
;
1537 unreachable("Unknown sampler type");
1542 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1543 unsigned midgard_texop
)
1546 //assert (!instr->sampler);
1547 //assert (!instr->texture_array_size);
1549 int texture_index
= instr
->texture_index
;
1550 int sampler_index
= texture_index
;
1552 /* No helper to build texture words -- we do it all here */
1553 midgard_instruction ins
= {
1554 .type
= TAG_TEXTURE_4
,
1557 .dest
= nir_dest_index(ctx
, &instr
->dest
),
1562 .op
= midgard_texop
,
1563 .format
= midgard_tex_format(instr
->sampler_dim
),
1564 .texture_handle
= texture_index
,
1565 .sampler_handle
= sampler_index
,
1566 .swizzle
= SWIZZLE_XYZW
,
1567 .in_reg_swizzle
= SWIZZLE_XYZW
,
1573 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1577 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1578 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1579 midgard_vector_alu_src alu_src
= blank_alu_src
;
1581 switch (instr
->src
[i
].src_type
) {
1582 case nir_tex_src_coord
: {
1583 emit_explicit_constant(ctx
, index
, index
);
1585 /* Texelfetch coordinates uses all four elements
1586 * (xyz/index) regardless of texture dimensionality,
1587 * which means it's necessary to zero the unused
1588 * components to keep everything happy */
1590 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1591 unsigned old_index
= index
;
1593 index
= make_compiler_temp(ctx
);
1595 /* mov index, old_index */
1596 midgard_instruction mov
= v_mov(old_index
, blank_alu_src
, index
);
1598 emit_mir_instruction(ctx
, mov
);
1600 /* mov index.zw, #0 */
1601 mov
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
),
1602 blank_alu_src
, index
);
1603 mov
.has_constants
= true;
1604 mov
.mask
= (1 << COMPONENT_Z
) | (1 << COMPONENT_W
);
1605 emit_mir_instruction(ctx
, mov
);
1608 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1609 /* texelFetch is undefined on samplerCube */
1610 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1612 /* For cubemaps, we use a special ld/st op to
1613 * select the face and copy the xy into the
1614 * texture register */
1616 unsigned temp
= make_compiler_temp(ctx
);
1618 midgard_instruction st
= m_st_cubemap_coords(temp
, 0);
1619 st
.ssa_args
.src0
= index
;
1620 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1621 st
.mask
= 0x3; /* xy */
1622 st
.load_store
.swizzle
= alu_src
.swizzle
;
1623 emit_mir_instruction(ctx
, st
);
1625 ins
.ssa_args
.src0
= temp
;
1627 ins
.ssa_args
.src0
= index
;
1630 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1631 /* Array component in w but NIR wants it in z */
1632 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYZZ
;
1638 case nir_tex_src_bias
:
1639 case nir_tex_src_lod
: {
1640 /* Try as a constant if we can */
1642 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1643 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1646 ins
.texture
.lod_register
= true;
1647 ins
.ssa_args
.src1
= index
;
1648 emit_explicit_constant(ctx
, index
, index
);
1654 unreachable("Unknown texture source type\n");
1658 emit_mir_instruction(ctx
, ins
);
1660 /* Used for .cont and .last hinting */
1661 ctx
->texture_op_count
++;
1665 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1667 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1668 * generic tex in some cases (which confuses the hardware) */
1670 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1672 if (is_vertex
&& instr
->op
== nir_texop_tex
)
1673 instr
->op
= nir_texop_txl
;
1675 switch (instr
->op
) {
1678 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1681 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1684 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1687 emit_sysval_read(ctx
, &instr
->instr
);
1690 unreachable("Unhanlded texture op");
1695 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1697 switch (instr
->type
) {
1698 case nir_jump_break
: {
1699 /* Emit a branch out of the loop */
1700 struct midgard_instruction br
= v_branch(false, false);
1701 br
.branch
.target_type
= TARGET_BREAK
;
1702 br
.branch
.target_break
= ctx
->current_loop_depth
;
1703 emit_mir_instruction(ctx
, br
);
1708 DBG("Unknown jump type %d\n", instr
->type
);
1714 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1716 switch (instr
->type
) {
1717 case nir_instr_type_load_const
:
1718 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1721 case nir_instr_type_intrinsic
:
1722 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1725 case nir_instr_type_alu
:
1726 emit_alu(ctx
, nir_instr_as_alu(instr
));
1729 case nir_instr_type_tex
:
1730 emit_tex(ctx
, nir_instr_as_tex(instr
));
1733 case nir_instr_type_jump
:
1734 emit_jump(ctx
, nir_instr_as_jump(instr
));
1737 case nir_instr_type_ssa_undef
:
1742 DBG("Unhandled instruction type\n");
1748 /* ALU instructions can inline or embed constants, which decreases register
1749 * pressure and saves space. */
1751 #define CONDITIONAL_ATTACH(src) { \
1752 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1755 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1756 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1761 inline_alu_constants(compiler_context
*ctx
)
1763 mir_foreach_instr(ctx
, alu
) {
1764 /* Other instructions cannot inline constants */
1765 if (alu
->type
!= TAG_ALU_4
) continue;
1767 /* If there is already a constant here, we can do nothing */
1768 if (alu
->has_constants
) continue;
1770 /* It makes no sense to inline constants on a branch */
1771 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
1773 CONDITIONAL_ATTACH(src0
);
1775 if (!alu
->has_constants
) {
1776 CONDITIONAL_ATTACH(src1
)
1777 } else if (!alu
->inline_constant
) {
1778 /* Corner case: _two_ vec4 constants, for instance with a
1779 * csel. For this case, we can only use a constant
1780 * register for one, we'll have to emit a move for the
1781 * other. Note, if both arguments are constants, then
1782 * necessarily neither argument depends on the value of
1783 * any particular register. As the destination register
1784 * will be wiped, that means we can spill the constant
1785 * to the destination register.
1788 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
1789 unsigned scratch
= alu
->ssa_args
.dest
;
1792 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1793 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
1795 /* Force a break XXX Defer r31 writes */
1796 ins
.unit
= UNIT_VLUT
;
1798 /* Set the source */
1799 alu
->ssa_args
.src1
= scratch
;
1801 /* Inject us -before- the last instruction which set r31 */
1802 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1808 /* Midgard supports two types of constants, embedded constants (128-bit) and
1809 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1810 * constants can be demoted to inline constants, for space savings and
1811 * sometimes a performance boost */
1814 embedded_to_inline_constant(compiler_context
*ctx
)
1816 mir_foreach_instr(ctx
, ins
) {
1817 if (!ins
->has_constants
) continue;
1819 if (ins
->ssa_args
.inline_constant
) continue;
1821 /* Blend constants must not be inlined by definition */
1822 if (ins
->has_blend_constant
) continue;
1824 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
1825 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
1826 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
1828 if (!(is_16
|| is_32
))
1831 /* src1 cannot be an inline constant due to encoding
1832 * restrictions. So, if possible we try to flip the arguments
1835 int op
= ins
->alu
.op
;
1837 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1839 /* These ops require an operational change to flip
1840 * their arguments TODO */
1841 case midgard_alu_op_flt
:
1842 case midgard_alu_op_fle
:
1843 case midgard_alu_op_ilt
:
1844 case midgard_alu_op_ile
:
1845 case midgard_alu_op_fcsel
:
1846 case midgard_alu_op_icsel
:
1847 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
1852 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
1853 /* Flip the SSA numbers */
1854 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
1855 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1857 /* And flip the modifiers */
1861 src_temp
= ins
->alu
.src2
;
1862 ins
->alu
.src2
= ins
->alu
.src1
;
1863 ins
->alu
.src1
= src_temp
;
1867 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1868 /* Extract the source information */
1870 midgard_vector_alu_src
*src
;
1871 int q
= ins
->alu
.src2
;
1872 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1875 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1876 int component
= src
->swizzle
& 3;
1878 /* Scale constant appropriately, if we can legally */
1879 uint16_t scaled_constant
= 0;
1881 if (midgard_is_integer_op(op
) || is_16
) {
1882 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
1883 scaled_constant
= (uint16_t) iconstants
[component
];
1885 /* Constant overflow after resize */
1886 if (scaled_constant
!= iconstants
[component
])
1889 float original
= (float) ins
->constants
[component
];
1890 scaled_constant
= _mesa_float_to_half(original
);
1892 /* Check for loss of precision. If this is
1893 * mediump, we don't care, but for a highp
1894 * shader, we need to pay attention. NIR
1895 * doesn't yet tell us which mode we're in!
1896 * Practically this prevents most constants
1897 * from being inlined, sadly. */
1899 float fp32
= _mesa_half_to_float(scaled_constant
);
1901 if (fp32
!= original
)
1905 /* We don't know how to handle these with a constant */
1907 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
1908 if (mir_nontrivial_raw_mod(*src
, is_int
) || src
->half
|| src
->rep_low
|| src
->rep_high
) {
1909 DBG("Bailing inline constant...\n");
1913 /* Make sure that the constant is not itself a
1914 * vector by checking if all accessed values
1915 * (by the swizzle) are the same. */
1917 uint32_t *cons
= (uint32_t *) ins
->constants
;
1918 uint32_t value
= cons
[component
];
1920 bool is_vector
= false;
1921 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
1923 for (int c
= 1; c
< 4; ++c
) {
1924 /* We only care if this component is actually used */
1925 if (!(mask
& (1 << c
)))
1928 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
1930 if (test
!= value
) {
1939 /* Get rid of the embedded constant */
1940 ins
->has_constants
= false;
1941 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
1942 ins
->ssa_args
.inline_constant
= true;
1943 ins
->inline_constant
= scaled_constant
;
1948 /* Dead code elimination for branches at the end of a block - only one branch
1949 * per block is legal semantically */
1952 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
1954 bool branched
= false;
1956 mir_foreach_instr_in_block_safe(block
, ins
) {
1957 if (!midgard_is_branch_unit(ins
->unit
)) continue;
1959 /* We ignore prepacked branches since the fragment epilogue is
1960 * just generally special */
1961 if (ins
->prepacked_branch
) continue;
1963 /* Discards are similarly special and may not correspond to the
1966 if (ins
->branch
.target_type
== TARGET_DISCARD
) continue;
1969 /* We already branched, so this is dead */
1970 mir_remove_instruction(ins
);
1977 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
1978 * the move can be propagated away entirely */
1981 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
1984 if (comp
== midgard_outmod_none
)
1987 if (*outmod
== midgard_outmod_none
) {
1992 /* TODO: Compose rules */
1997 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
1999 bool progress
= false;
2001 mir_foreach_instr_in_block_safe(block
, ins
) {
2002 if (ins
->type
!= TAG_ALU_4
) continue;
2003 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2004 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2006 /* TODO: Registers? */
2007 unsigned src
= ins
->ssa_args
.src1
;
2008 if (src
& IS_REG
) continue;
2009 assert(!mir_has_multiple_writes(ctx
, src
));
2011 /* There might be a source modifier, too */
2012 if (mir_nontrivial_source2_mod(ins
)) continue;
2014 /* Backpropagate the modifier */
2015 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2016 if (v
->type
!= TAG_ALU_4
) continue;
2017 if (v
->ssa_args
.dest
!= src
) continue;
2019 /* Can we even take a float outmod? */
2020 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2022 midgard_outmod_float temp
= v
->alu
.outmod
;
2023 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2025 /* Throw in the towel.. */
2026 if (!progress
) break;
2028 /* Otherwise, transfer the modifier */
2029 v
->alu
.outmod
= temp
;
2030 ins
->alu
.outmod
= midgard_outmod_none
;
2040 emit_fragment_epilogue(compiler_context
*ctx
)
2042 emit_explicit_constant(ctx
, ctx
->fragment_output
, SSA_FIXED_REGISTER(0));
2044 /* Perform the actual fragment writeout. We have two writeout/branch
2045 * instructions, forming a loop until writeout is successful as per the
2046 * docs. TODO: gl_FragDepth */
2048 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2049 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2052 static midgard_block
*
2053 emit_block(compiler_context
*ctx
, nir_block
*block
)
2055 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
2056 list_addtail(&this_block
->link
, &ctx
->blocks
);
2058 this_block
->is_scheduled
= false;
2061 ctx
->texture_index
[0] = -1;
2062 ctx
->texture_index
[1] = -1;
2064 /* Add us as a successor to the block we are following */
2065 if (ctx
->current_block
)
2066 midgard_block_add_successor(ctx
->current_block
, this_block
);
2068 /* Set up current block */
2069 list_inithead(&this_block
->instructions
);
2070 ctx
->current_block
= this_block
;
2072 nir_foreach_instr(instr
, block
) {
2073 emit_instr(ctx
, instr
);
2074 ++ctx
->instruction_count
;
2077 inline_alu_constants(ctx
);
2078 embedded_to_inline_constant(ctx
);
2080 /* Append fragment shader epilogue (value writeout) */
2081 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2082 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2083 emit_fragment_epilogue(ctx
);
2087 if (block
== nir_start_block(ctx
->func
->impl
))
2088 ctx
->initial_block
= this_block
;
2090 if (block
== nir_impl_last_block(ctx
->func
->impl
))
2091 ctx
->final_block
= this_block
;
2093 /* Allow the next control flow to access us retroactively, for
2095 ctx
->current_block
= this_block
;
2097 /* Document the fallthrough chain */
2098 ctx
->previous_source_block
= this_block
;
2103 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2106 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2108 /* Conditional branches expect the condition in r31.w; emit a move for
2109 * that in the _previous_ block (which is the current block). */
2110 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2112 /* Speculatively emit the branch, but we can't fill it in until later */
2113 EMIT(branch
, true, true);
2114 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2116 /* Emit the two subblocks */
2117 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2119 /* Emit a jump from the end of the then block to the end of the else */
2120 EMIT(branch
, false, false);
2121 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2123 /* Emit second block, and check if it's empty */
2125 int else_idx
= ctx
->block_count
;
2126 int count_in
= ctx
->instruction_count
;
2127 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2128 int after_else_idx
= ctx
->block_count
;
2130 /* Now that we have the subblocks emitted, fix up the branches */
2135 if (ctx
->instruction_count
== count_in
) {
2136 /* The else block is empty, so don't emit an exit jump */
2137 mir_remove_instruction(then_exit
);
2138 then_branch
->branch
.target_block
= after_else_idx
;
2140 then_branch
->branch
.target_block
= else_idx
;
2141 then_exit
->branch
.target_block
= after_else_idx
;
2146 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2148 /* Remember where we are */
2149 midgard_block
*start_block
= ctx
->current_block
;
2151 /* Allocate a loop number, growing the current inner loop depth */
2152 int loop_idx
= ++ctx
->current_loop_depth
;
2154 /* Get index from before the body so we can loop back later */
2155 int start_idx
= ctx
->block_count
;
2157 /* Emit the body itself */
2158 emit_cf_list(ctx
, &nloop
->body
);
2160 /* Branch back to loop back */
2161 struct midgard_instruction br_back
= v_branch(false, false);
2162 br_back
.branch
.target_block
= start_idx
;
2163 emit_mir_instruction(ctx
, br_back
);
2165 /* Mark down that branch in the graph. Note that we're really branching
2166 * to the block *after* we started in. TODO: Why doesn't the branch
2167 * itself have an off-by-one then...? */
2168 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
2170 /* Find the index of the block about to follow us (note: we don't add
2171 * one; blocks are 0-indexed so we get a fencepost problem) */
2172 int break_block_idx
= ctx
->block_count
;
2174 /* Fix up the break statements we emitted to point to the right place,
2175 * now that we can allocate a block number for them */
2177 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2178 mir_foreach_instr_in_block(block
, ins
) {
2179 if (ins
->type
!= TAG_ALU_4
) continue;
2180 if (!ins
->compact_branch
) continue;
2181 if (ins
->prepacked_branch
) continue;
2183 /* We found a branch -- check the type to see if we need to do anything */
2184 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2186 /* It's a break! Check if it's our break */
2187 if (ins
->branch
.target_break
!= loop_idx
) continue;
2189 /* Okay, cool, we're breaking out of this loop.
2190 * Rewrite from a break to a goto */
2192 ins
->branch
.target_type
= TARGET_GOTO
;
2193 ins
->branch
.target_block
= break_block_idx
;
2197 /* Now that we've finished emitting the loop, free up the depth again
2198 * so we play nice with recursion amid nested loops */
2199 --ctx
->current_loop_depth
;
2201 /* Dump loop stats */
2205 static midgard_block
*
2206 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2208 midgard_block
*start_block
= NULL
;
2210 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2211 switch (node
->type
) {
2212 case nir_cf_node_block
: {
2213 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2216 start_block
= block
;
2221 case nir_cf_node_if
:
2222 emit_if(ctx
, nir_cf_node_as_if(node
));
2225 case nir_cf_node_loop
:
2226 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2229 case nir_cf_node_function
:
2238 /* Due to lookahead, we need to report the first tag executed in the command
2239 * stream and in branch targets. An initial block might be empty, so iterate
2240 * until we find one that 'works' */
2243 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2245 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2247 unsigned first_tag
= 0;
2250 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
2252 if (initial_bundle
) {
2253 first_tag
= initial_bundle
->tag
;
2257 /* Initial block is empty, try the next block */
2258 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
2259 } while(initial_block
!= NULL
);
2266 midgard_compile_shader_nir(struct midgard_screen
*screen
, nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2268 struct util_dynarray
*compiled
= &program
->compiled
;
2270 midgard_debug
= debug_get_option_midgard_debug();
2272 compiler_context ictx
= {
2275 .stage
= nir
->info
.stage
,
2278 .is_blend
= is_blend
,
2279 .blend_constant_offset
= 0,
2281 .alpha_ref
= program
->alpha_ref
2284 compiler_context
*ctx
= &ictx
;
2286 /* Start off with a safe cutoff, allowing usage of all 16 work
2287 * registers. Later, we'll promote uniform reads to uniform registers
2288 * if we determine it is beneficial to do so */
2289 ctx
->uniform_cutoff
= 8;
2291 /* Initialize at a global (not block) level hash tables */
2293 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2294 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2295 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2297 /* Record the varying mapping for the command stream's bookkeeping */
2299 struct exec_list
*varyings
=
2300 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2302 unsigned max_varying
= 0;
2303 nir_foreach_variable(var
, varyings
) {
2304 unsigned loc
= var
->data
.driver_location
;
2305 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2307 for (int c
= 0; c
< sz
; ++c
) {
2308 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2309 max_varying
= MAX2(max_varying
, loc
+ c
);
2313 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2314 * (so we don't accidentally duplicate the epilogue since mesa/st has
2315 * messed with our I/O quite a bit already) */
2317 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2319 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2320 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2321 NIR_PASS_V(nir
, nir_clamp_psiz
, 1.0, 1024.0);
2324 NIR_PASS_V(nir
, nir_lower_var_copies
);
2325 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2326 NIR_PASS_V(nir
, nir_split_var_copies
);
2327 NIR_PASS_V(nir
, nir_lower_var_copies
);
2328 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2329 NIR_PASS_V(nir
, nir_lower_var_copies
);
2330 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2332 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2334 /* Optimisation passes */
2338 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2339 nir_print_shader(nir
, stdout
);
2342 /* Assign sysvals and counts, now that we're sure
2343 * (post-optimisation) */
2345 midgard_nir_assign_sysvals(ctx
, nir
);
2347 program
->uniform_count
= nir
->num_uniforms
;
2348 program
->sysval_count
= ctx
->sysval_count
;
2349 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2351 nir_foreach_function(func
, nir
) {
2355 list_inithead(&ctx
->blocks
);
2356 ctx
->block_count
= 0;
2359 emit_cf_list(ctx
, &func
->impl
->body
);
2360 emit_block(ctx
, func
->impl
->end_block
);
2362 break; /* TODO: Multi-function shaders */
2365 util_dynarray_init(compiled
, NULL
);
2367 /* MIR-level optimizations */
2369 bool progress
= false;
2374 mir_foreach_block(ctx
, block
) {
2375 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2376 progress
|= midgard_opt_copy_prop(ctx
, block
);
2377 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2378 progress
|= midgard_opt_combine_projection(ctx
, block
);
2379 progress
|= midgard_opt_varying_projection(ctx
, block
);
2383 /* Nested control-flow can result in dead branches at the end of the
2384 * block. This messes with our analysis and is just dead code, so cull
2386 mir_foreach_block(ctx
, block
) {
2387 midgard_opt_cull_dead_branch(ctx
, block
);
2391 schedule_program(ctx
);
2393 /* Now that all the bundles are scheduled and we can calculate block
2394 * sizes, emit actual branch instructions rather than placeholders */
2396 int br_block_idx
= 0;
2398 mir_foreach_block(ctx
, block
) {
2399 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2400 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2401 midgard_instruction
*ins
= bundle
->instructions
[c
];
2403 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2405 if (ins
->prepacked_branch
) continue;
2407 /* Parse some basic branch info */
2408 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2409 bool is_conditional
= ins
->branch
.conditional
;
2410 bool is_inverted
= ins
->branch
.invert_conditional
;
2411 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2413 /* Determine the block we're jumping to */
2414 int target_number
= ins
->branch
.target_block
;
2416 /* Report the destination tag */
2417 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2419 /* Count up the number of quadwords we're
2420 * jumping over = number of quadwords until
2421 * (br_block_idx, target_number) */
2423 int quadword_offset
= 0;
2426 /* Jump to the end of the shader. We
2427 * need to include not only the
2428 * following blocks, but also the
2429 * contents of our current block (since
2430 * discard can come in the middle of
2433 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
2435 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
2436 quadword_offset
+= quadword_size(bun
->tag
);
2439 mir_foreach_block_from(ctx
, blk
, b
) {
2440 quadword_offset
+= b
->quadword_count
;
2443 } else if (target_number
> br_block_idx
) {
2446 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2447 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2450 quadword_offset
+= blk
->quadword_count
;
2453 /* Jump backwards */
2455 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2456 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2459 quadword_offset
-= blk
->quadword_count
;
2463 /* Unconditional extended branches (far jumps)
2464 * have issues, so we always use a conditional
2465 * branch, setting the condition to always for
2466 * unconditional. For compact unconditional
2467 * branches, cond isn't used so it doesn't
2468 * matter what we pick. */
2470 midgard_condition cond
=
2471 !is_conditional
? midgard_condition_always
:
2472 is_inverted
? midgard_condition_false
:
2473 midgard_condition_true
;
2475 midgard_jmp_writeout_op op
=
2476 is_discard
? midgard_jmp_writeout_op_discard
:
2477 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2478 midgard_jmp_writeout_op_branch_cond
;
2481 midgard_branch_extended branch
=
2482 midgard_create_branch_extended(
2487 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2488 } else if (is_conditional
|| is_discard
) {
2489 midgard_branch_cond branch
= {
2491 .dest_tag
= dest_tag
,
2492 .offset
= quadword_offset
,
2496 assert(branch
.offset
== quadword_offset
);
2498 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2500 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2502 midgard_branch_uncond branch
= {
2504 .dest_tag
= dest_tag
,
2505 .offset
= quadword_offset
,
2509 assert(branch
.offset
== quadword_offset
);
2511 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2519 /* Emit flat binary from the instruction arrays. Iterate each block in
2520 * sequence. Save instruction boundaries such that lookahead tags can
2521 * be assigned easily */
2523 /* Cache _all_ bundles in source order for lookahead across failed branches */
2525 int bundle_count
= 0;
2526 mir_foreach_block(ctx
, block
) {
2527 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2529 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2531 mir_foreach_block(ctx
, block
) {
2532 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2533 source_order_bundles
[bundle_idx
++] = bundle
;
2537 int current_bundle
= 0;
2539 /* Midgard prefetches instruction types, so during emission we
2540 * need to lookahead. Unless this is the last instruction, in
2541 * which we return 1. Or if this is the second to last and the
2542 * last is an ALU, then it's also 1... */
2544 mir_foreach_block(ctx
, block
) {
2545 mir_foreach_bundle_in_block(block
, bundle
) {
2548 if (current_bundle
+ 1 < bundle_count
) {
2549 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2551 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2558 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2562 /* TODO: Free deeper */
2563 //util_dynarray_fini(&block->instructions);
2566 free(source_order_bundles
);
2568 /* Report the very first tag executed */
2569 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2571 /* Deal with off-by-one related to the fencepost problem */
2572 program
->work_register_count
= ctx
->work_registers
+ 1;
2573 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2575 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2576 program
->tls_size
= ctx
->tls_size
;
2578 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2579 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);
2581 if (midgard_debug
& MIDGARD_DBG_SHADERDB
) {
2582 unsigned nr_bundles
= 0, nr_ins
= 0, nr_quadwords
= 0;
2584 /* Count instructions and bundles */
2586 mir_foreach_instr_global(ctx
, ins
) {
2590 mir_foreach_block(ctx
, block
) {
2591 nr_bundles
+= util_dynarray_num_elements(
2592 &block
->bundles
, midgard_bundle
);
2594 nr_quadwords
+= block
->quadword_count
;
2597 /* Calculate thread count. There are certain cutoffs by
2598 * register count for thread count */
2600 unsigned nr_registers
= program
->work_register_count
;
2602 unsigned nr_threads
=
2603 (nr_registers
<= 4) ? 4 :
2604 (nr_registers
<= 8) ? 2 :
2609 fprintf(stderr
, "shader%d - %s shader: "
2610 "%u inst, %u bundles, %u quadwords, "
2611 "%u registers, %u threads, %u loops, "
2612 "%d:%d spills:fills\n",
2614 gl_shader_stage_name(ctx
->stage
),
2615 nr_ins
, nr_bundles
, nr_quadwords
,
2616 nr_registers
, nr_threads
,
2618 ctx
->spills
, ctx
->fills
);