2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
63 unsigned SHADER_DB_COUNT
= 0;
65 int midgard_debug
= 0;
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 midgard_is_branch_unit(unsigned unit
)
75 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
79 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
81 block
->successors
[block
->nr_successors
++] = successor
;
82 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
85 /* Helpers to generate midgard_instruction's using macro magic, since every
86 * driver seems to do it that way */
88 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
90 #define M_LOAD_STORE(name, rname, uname) \
91 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
92 midgard_instruction i = { \
93 .type = TAG_LOAD_STORE_4, \
101 .op = midgard_op_##name, \
102 .swizzle = SWIZZLE_XYZW, \
110 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
111 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
113 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
114 * the corresponding Midgard source */
116 static midgard_vector_alu_src
117 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
118 bool half
, bool sext
)
120 if (!src
) return blank_alu_src
;
122 /* Figure out how many components there are so we can adjust the
123 * swizzle. Specifically we want to broadcast the last channel so
124 * things like ball2/3 work
127 if (broadcast_count
) {
128 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
130 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
131 src
->swizzle
[c
] = last_component
;
135 midgard_vector_alu_src alu_src
= {
139 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
143 alu_src
.mod
= midgard_int_normal
;
145 /* Sign/zero-extend if needed */
149 midgard_int_sign_extend
150 : midgard_int_zero_extend
;
153 /* These should have been lowered away */
154 assert(!(src
->abs
|| src
->negate
));
156 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
162 /* load/store instructions have both 32-bit and 16-bit variants, depending on
163 * whether we are using vectors composed of highp or mediump. At the moment, we
164 * don't support half-floats -- this requires changes in other parts of the
165 * compiler -- therefore the 16-bit versions are commented out. */
167 //M_LOAD(ld_attr_16);
169 //M_LOAD(ld_vary_16);
171 //M_LOAD(ld_uniform_16);
172 M_LOAD(ld_uniform_32
);
173 M_LOAD(ld_color_buffer_8
);
174 //M_STORE(st_vary_16);
176 M_LOAD(st_cubemap_coords
);
178 static midgard_instruction
179 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
181 midgard_branch_cond branch
= {
189 memcpy(&compact
, &branch
, sizeof(branch
));
191 midgard_instruction ins
= {
193 .unit
= ALU_ENAB_BR_COMPACT
,
194 .prepacked_branch
= true,
195 .compact_branch
= true,
196 .br_compact
= compact
,
204 if (op
== midgard_jmp_writeout_op_writeout
)
210 static midgard_instruction
211 v_branch(bool conditional
, bool invert
)
213 midgard_instruction ins
= {
215 .unit
= ALU_ENAB_BRANCH
,
216 .compact_branch
= true,
218 .conditional
= conditional
,
219 .invert_conditional
= invert
231 static midgard_branch_extended
232 midgard_create_branch_extended( midgard_condition cond
,
233 midgard_jmp_writeout_op op
,
235 signed quadword_offset
)
237 /* The condition code is actually a LUT describing a function to
238 * combine multiple condition codes. However, we only support a single
239 * condition code at the moment, so we just duplicate over a bunch of
242 uint16_t duplicated_cond
=
252 midgard_branch_extended branch
= {
254 .dest_tag
= dest_tag
,
255 .offset
= quadword_offset
,
256 .cond
= duplicated_cond
263 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
265 ins
->has_constants
= true;
266 memcpy(&ins
->constants
, constants
, 16);
270 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
272 return glsl_count_attribute_slots(type
, false);
275 /* Lower fdot2 to a vector multiplication followed by channel addition */
277 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
279 if (alu
->op
!= nir_op_fdot2
)
282 b
->cursor
= nir_before_instr(&alu
->instr
);
284 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
285 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
287 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
289 nir_ssa_def
*sum
= nir_fadd(b
,
290 nir_channel(b
, product
, 0),
291 nir_channel(b
, product
, 1));
293 /* Replace the fdot2 with this sum */
294 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
298 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
300 switch (instr
->intrinsic
) {
301 case nir_intrinsic_load_viewport_scale
:
302 return PAN_SYSVAL_VIEWPORT_SCALE
;
303 case nir_intrinsic_load_viewport_offset
:
304 return PAN_SYSVAL_VIEWPORT_OFFSET
;
310 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
313 nir_intrinsic_instr
*intr
;
314 nir_dest
*dst
= NULL
;
318 switch (instr
->type
) {
319 case nir_instr_type_intrinsic
:
320 intr
= nir_instr_as_intrinsic(instr
);
321 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
324 case nir_instr_type_tex
:
325 tex
= nir_instr_as_tex(instr
);
326 if (tex
->op
!= nir_texop_txs
)
329 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
330 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
331 nir_tex_instr_dest_size(tex
) -
332 (tex
->is_array
? 1 : 0),
341 *dest
= nir_dest_index(ctx
, dst
);
347 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
351 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
355 /* We have a sysval load; check if it's already been assigned */
357 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
360 /* It hasn't -- so assign it now! */
362 unsigned id
= ctx
->sysval_count
++;
363 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
364 ctx
->sysvals
[id
] = sysval
;
368 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
370 ctx
->sysval_count
= 0;
372 nir_foreach_function(function
, shader
) {
373 if (!function
->impl
) continue;
375 nir_foreach_block(block
, function
->impl
) {
376 nir_foreach_instr_safe(instr
, block
) {
377 midgard_nir_assign_sysval_body(ctx
, instr
);
384 midgard_nir_lower_fdot2(nir_shader
*shader
)
386 bool progress
= false;
388 nir_foreach_function(function
, shader
) {
389 if (!function
->impl
) continue;
392 nir_builder
*b
= &_b
;
393 nir_builder_init(b
, function
->impl
);
395 nir_foreach_block(block
, function
->impl
) {
396 nir_foreach_instr_safe(instr
, block
) {
397 if (instr
->type
!= nir_instr_type_alu
) continue;
399 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
400 midgard_nir_lower_fdot2_body(b
, alu
);
406 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
413 /* Flushes undefined values to zero */
416 optimise_nir(nir_shader
*nir
)
419 unsigned lower_flrp
=
420 (nir
->options
->lower_flrp16
? 16 : 0) |
421 (nir
->options
->lower_flrp32
? 32 : 0) |
422 (nir
->options
->lower_flrp64
? 64 : 0);
424 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
425 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
426 NIR_PASS(progress
, nir
, nir_lower_idiv
);
428 nir_lower_tex_options lower_tex_1st_pass_options
= {
433 nir_lower_tex_options lower_tex_2nd_pass_options
= {
434 .lower_txs_lod
= true,
437 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_1st_pass_options
);
438 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_2nd_pass_options
);
443 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
444 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
446 NIR_PASS(progress
, nir
, nir_copy_prop
);
447 NIR_PASS(progress
, nir
, nir_opt_dce
);
448 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
449 NIR_PASS(progress
, nir
, nir_opt_cse
);
450 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
451 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
452 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
454 if (lower_flrp
!= 0) {
455 bool lower_flrp_progress
= false;
456 NIR_PASS(lower_flrp_progress
,
460 false /* always_precise */,
461 nir
->options
->lower_ffma
);
462 if (lower_flrp_progress
) {
463 NIR_PASS(progress
, nir
,
464 nir_opt_constant_folding
);
468 /* Nothing should rematerialize any flrps, so we only
469 * need to do this lowering once.
474 NIR_PASS(progress
, nir
, nir_opt_undef
);
475 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
477 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
480 nir_var_function_temp
);
482 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
485 /* Must be run at the end to prevent creation of fsin/fcos ops */
486 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
491 NIR_PASS(progress
, nir
, nir_opt_dce
);
492 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
493 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
494 NIR_PASS(progress
, nir
, nir_copy_prop
);
497 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
499 /* We implement booleans as 32-bit 0/~0 */
500 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
502 /* Now that booleans are lowered, we can run out late opts */
503 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
505 /* Lower mods for float ops only. Integer ops don't support modifiers
506 * (saturate doesn't make sense on integers, neg/abs require dedicated
509 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
510 NIR_PASS(progress
, nir
, nir_copy_prop
);
511 NIR_PASS(progress
, nir
, nir_opt_dce
);
513 /* Take us out of SSA */
514 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
515 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
517 /* We are a vector architecture; write combine where possible */
518 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
519 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
521 NIR_PASS(progress
, nir
, nir_opt_dce
);
524 /* Do not actually emit a load; instead, cache the constant for inlining */
527 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
529 nir_ssa_def def
= instr
->def
;
531 float *v
= rzalloc_array(NULL
, float, 4);
532 nir_const_load_to_arr(v
, instr
, f32
);
534 /* Shifted for SSA, +1 for off-by-one */
535 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, v
);
538 /* Normally constants are embedded implicitly, but for I/O and such we have to
539 * explicitly emit a move with the constant source */
542 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
544 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
546 if (constant_value
) {
547 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, to
);
548 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
549 emit_mir_instruction(ctx
, ins
);
554 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
556 unsigned comp
= src
->swizzle
[0];
558 for (unsigned c
= 1; c
< nr_components
; ++c
) {
559 if (src
->swizzle
[c
] != comp
)
566 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
567 * output of a conditional test) into that register */
570 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
572 int condition
= nir_src_index(ctx
, src
);
574 /* Source to swizzle the desired component into w */
576 const midgard_vector_alu_src alu_src
= {
577 .swizzle
= SWIZZLE(component
, component
, component
, component
),
580 /* There is no boolean move instruction. Instead, we simulate a move by
581 * ANDing the condition with itself to get it into r31.w */
583 midgard_instruction ins
= {
586 /* We need to set the conditional as close as possible */
587 .precede_break
= true,
588 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
589 .mask
= 1 << COMPONENT_W
,
594 .dest
= SSA_FIXED_REGISTER(31),
598 .op
= midgard_alu_op_iand
,
599 .outmod
= midgard_outmod_int_wrap
,
600 .reg_mode
= midgard_reg_mode_32
,
601 .dest_override
= midgard_dest_override_none
,
602 .src1
= vector_alu_srco_unsigned(alu_src
),
603 .src2
= vector_alu_srco_unsigned(alu_src
)
607 emit_mir_instruction(ctx
, ins
);
610 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
614 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
616 int condition
= nir_src_index(ctx
, &src
->src
);
618 /* Source to swizzle the desired component into w */
620 const midgard_vector_alu_src alu_src
= {
621 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
624 /* There is no boolean move instruction. Instead, we simulate a move by
625 * ANDing the condition with itself to get it into r31.w */
627 midgard_instruction ins
= {
629 .precede_break
= true,
630 .mask
= mask_of(nr_comp
),
634 .dest
= SSA_FIXED_REGISTER(31),
637 .op
= midgard_alu_op_iand
,
638 .outmod
= midgard_outmod_int_wrap
,
639 .reg_mode
= midgard_reg_mode_32
,
640 .dest_override
= midgard_dest_override_none
,
641 .src1
= vector_alu_srco_unsigned(alu_src
),
642 .src2
= vector_alu_srco_unsigned(alu_src
)
646 emit_mir_instruction(ctx
, ins
);
651 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
652 * pinning to eliminate this move in all known cases */
655 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
657 int offset
= nir_src_index(ctx
, src
);
659 midgard_instruction ins
= {
661 .mask
= 1 << COMPONENT_W
,
663 .src0
= SSA_UNUSED_1
,
665 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
668 .op
= midgard_alu_op_imov
,
669 .outmod
= midgard_outmod_int_wrap
,
670 .reg_mode
= midgard_reg_mode_32
,
671 .dest_override
= midgard_dest_override_none
,
672 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
673 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
677 emit_mir_instruction(ctx
, ins
);
680 #define ALU_CASE(nir, _op) \
682 op = midgard_alu_op_##_op; \
683 assert(src_bitsize == dst_bitsize); \
686 #define ALU_CASE_BCAST(nir, _op, count) \
688 op = midgard_alu_op_##_op; \
689 broadcast_swizzle = count; \
690 assert(src_bitsize == dst_bitsize); \
693 nir_is_fzero_constant(nir_src src
)
695 if (!nir_src_is_const(src
))
698 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
699 if (nir_src_comp_as_float(src
, c
) != 0.0)
706 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
707 * special treatment override this anyway. */
709 static midgard_reg_mode
710 reg_mode_for_nir(nir_alu_instr
*instr
)
712 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
714 switch (src_bitsize
) {
716 return midgard_reg_mode_8
;
718 return midgard_reg_mode_16
;
720 return midgard_reg_mode_32
;
722 return midgard_reg_mode_64
;
724 unreachable("Invalid bit size");
729 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
731 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
732 * is handled elsewhere */
734 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
735 midgard_emit_derivatives(ctx
, instr
);
739 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
741 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
742 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
743 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
745 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
746 * supported. A few do not and are commented for now. Also, there are a
747 * number of NIR ops which Midgard does not support and need to be
748 * lowered, also TODO. This switch block emits the opcode and calling
749 * convention of the Midgard instruction; actual packing is done in
754 /* Number of components valid to check for the instruction (the rest
755 * will be forced to the last), or 0 to use as-is. Relevant as
756 * ball-type instructions have a channel count in NIR but are all vec4
759 unsigned broadcast_swizzle
= 0;
761 /* What register mode should we operate in? */
762 midgard_reg_mode reg_mode
=
763 reg_mode_for_nir(instr
);
765 /* Do we need a destination override? Used for inline
768 midgard_dest_override dest_override
=
769 midgard_dest_override_none
;
771 /* Should we use a smaller respective source and sign-extend? */
773 bool half_1
= false, sext_1
= false;
774 bool half_2
= false, sext_2
= false;
776 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
777 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
780 ALU_CASE(fadd
, fadd
);
781 ALU_CASE(fmul
, fmul
);
782 ALU_CASE(fmin
, fmin
);
783 ALU_CASE(fmax
, fmax
);
784 ALU_CASE(imin
, imin
);
785 ALU_CASE(imax
, imax
);
786 ALU_CASE(umin
, umin
);
787 ALU_CASE(umax
, umax
);
788 ALU_CASE(ffloor
, ffloor
);
789 ALU_CASE(fround_even
, froundeven
);
790 ALU_CASE(ftrunc
, ftrunc
);
791 ALU_CASE(fceil
, fceil
);
792 ALU_CASE(fdot3
, fdot3
);
793 ALU_CASE(fdot4
, fdot4
);
794 ALU_CASE(iadd
, iadd
);
795 ALU_CASE(isub
, isub
);
796 ALU_CASE(imul
, imul
);
798 /* Zero shoved as second-arg */
799 ALU_CASE(iabs
, iabsdiff
);
803 ALU_CASE(feq32
, feq
);
804 ALU_CASE(fne32
, fne
);
805 ALU_CASE(flt32
, flt
);
806 ALU_CASE(ieq32
, ieq
);
807 ALU_CASE(ine32
, ine
);
808 ALU_CASE(ilt32
, ilt
);
809 ALU_CASE(ult32
, ult
);
811 /* We don't have a native b2f32 instruction. Instead, like many
812 * GPUs, we exploit booleans as 0/~0 for false/true, and
813 * correspondingly AND
814 * by 1.0 to do the type conversion. For the moment, prime us
817 * iand [whatever], #0
819 * At the end of emit_alu (as MIR), we'll fix-up the constant
822 ALU_CASE(b2f32
, iand
);
823 ALU_CASE(b2i32
, iand
);
825 /* Likewise, we don't have a dedicated f2b32 instruction, but
826 * we can do a "not equal to 0.0" test. */
828 ALU_CASE(f2b32
, fne
);
829 ALU_CASE(i2b32
, ine
);
831 ALU_CASE(frcp
, frcp
);
832 ALU_CASE(frsq
, frsqrt
);
833 ALU_CASE(fsqrt
, fsqrt
);
834 ALU_CASE(fexp2
, fexp2
);
835 ALU_CASE(flog2
, flog2
);
837 ALU_CASE(f2i32
, f2i_rtz
);
838 ALU_CASE(f2u32
, f2u_rtz
);
839 ALU_CASE(i2f32
, i2f_rtz
);
840 ALU_CASE(u2f32
, u2f_rtz
);
842 ALU_CASE(f2i16
, f2i_rtz
);
843 ALU_CASE(f2u16
, f2u_rtz
);
844 ALU_CASE(i2f16
, i2f_rtz
);
845 ALU_CASE(u2f16
, u2f_rtz
);
847 ALU_CASE(fsin
, fsin
);
848 ALU_CASE(fcos
, fcos
);
850 /* We'll set invert */
851 ALU_CASE(inot
, imov
);
852 ALU_CASE(iand
, iand
);
854 ALU_CASE(ixor
, ixor
);
855 ALU_CASE(ishl
, ishl
);
856 ALU_CASE(ishr
, iasr
);
857 ALU_CASE(ushr
, ilsr
);
859 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
860 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
861 ALU_CASE(b32all_fequal4
, fball_eq
);
863 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
864 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
865 ALU_CASE(b32any_fnequal4
, fbany_neq
);
867 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
868 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
869 ALU_CASE(b32all_iequal4
, iball_eq
);
871 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
872 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
873 ALU_CASE(b32any_inequal4
, ibany_neq
);
875 /* Source mods will be shoved in later */
876 ALU_CASE(fabs
, fmov
);
877 ALU_CASE(fneg
, fmov
);
878 ALU_CASE(fsat
, fmov
);
880 /* For size conversion, we use a move. Ideally though we would squash
881 * these ops together; maybe that has to happen after in NIR as part of
882 * propagation...? An earlier algebraic pass ensured we step down by
883 * only / exactly one size. If stepping down, we use a dest override to
884 * reduce the size; if stepping up, we use a larger-sized move with a
885 * half source and a sign/zero-extension modifier */
890 /* If we end up upscale, we'll need a sign-extend on the
891 * operand (the second argument) */
897 op
= midgard_alu_op_imov
;
899 if (dst_bitsize
== (src_bitsize
* 2)) {
903 /* Use a greater register mode */
905 } else if (src_bitsize
== (dst_bitsize
* 2)) {
906 /* Converting down */
907 dest_override
= midgard_dest_override_lower
;
914 assert(src_bitsize
== 32);
916 op
= midgard_alu_op_fmov
;
917 dest_override
= midgard_dest_override_lower
;
922 assert(src_bitsize
== 16);
924 op
= midgard_alu_op_fmov
;
931 /* For greater-or-equal, we lower to less-or-equal and flip the
939 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
940 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
941 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
942 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
945 /* Swap via temporary */
946 nir_alu_src temp
= instr
->src
[1];
947 instr
->src
[1] = instr
->src
[0];
948 instr
->src
[0] = temp
;
953 case nir_op_b32csel
: {
954 /* Midgard features both fcsel and icsel, depending on
955 * the type of the arguments/output. However, as long
956 * as we're careful we can _always_ use icsel and
957 * _never_ need fcsel, since the latter does additional
958 * floating-point-specific processing whereas the
959 * former just moves bits on the wire. It's not obvious
960 * why these are separate opcodes, save for the ability
961 * to do things like sat/pos/abs/neg for free */
963 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
964 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
966 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
969 /* Emit the condition into r31 */
972 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
974 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
976 /* The condition is the first argument; move the other
977 * arguments up one to be a binary instruction for
980 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
985 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
990 /* Midgard can perform certain modifiers on output of an ALU op */
993 if (midgard_is_integer_out_op(op
)) {
994 outmod
= midgard_outmod_int_wrap
;
996 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
997 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
1000 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
1002 if (instr
->op
== nir_op_fmax
) {
1003 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
1004 op
= midgard_alu_op_fmov
;
1006 outmod
= midgard_outmod_pos
;
1007 instr
->src
[0] = instr
->src
[1];
1008 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1009 op
= midgard_alu_op_fmov
;
1011 outmod
= midgard_outmod_pos
;
1015 /* Fetch unit, quirks, etc information */
1016 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1017 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1019 /* src0 will always exist afaik, but src1 will not for 1-argument
1020 * instructions. The latter can only be fetched if the instruction
1021 * needs it, or else we may segfault. */
1023 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1024 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1026 /* Rather than use the instruction generation helpers, we do it
1027 * ourselves here to avoid the mess */
1029 midgard_instruction ins
= {
1032 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1033 .src1
= quirk_flipped_r24
? src0
: src1
,
1038 nir_alu_src
*nirmods
[2] = { NULL
};
1040 if (nr_inputs
== 2) {
1041 nirmods
[0] = &instr
->src
[0];
1042 nirmods
[1] = &instr
->src
[1];
1043 } else if (nr_inputs
== 1) {
1044 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1049 /* These were lowered to a move, so apply the corresponding mod */
1051 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1052 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
1054 if (instr
->op
== nir_op_fneg
)
1055 s
->negate
= !s
->negate
;
1057 if (instr
->op
== nir_op_fabs
)
1061 bool is_int
= midgard_is_integer_op(op
);
1063 ins
.mask
= mask_of(nr_components
);
1065 midgard_vector_alu alu
= {
1067 .reg_mode
= reg_mode
,
1068 .dest_override
= dest_override
,
1071 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1072 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1075 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1078 ins
.mask
&= instr
->dest
.write_mask
;
1082 /* Late fixup for emulated instructions */
1084 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1085 /* Presently, our second argument is an inline #0 constant.
1086 * Switch over to an embedded 1.0 constant (that can't fit
1087 * inline, since we're 32-bit, not 16-bit like the inline
1090 ins
.ssa_args
.inline_constant
= false;
1091 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1092 ins
.has_constants
= true;
1094 if (instr
->op
== nir_op_b2f32
) {
1095 ins
.constants
[0] = 1.0f
;
1097 /* Type pun it into place */
1099 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1102 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1103 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1104 /* Lots of instructions need a 0 plonked in */
1105 ins
.ssa_args
.inline_constant
= false;
1106 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1107 ins
.has_constants
= true;
1108 ins
.constants
[0] = 0.0f
;
1109 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1110 } else if (instr
->op
== nir_op_inot
) {
1114 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1115 /* To avoid duplicating the lookup tables (probably), true LUT
1116 * instructions can only operate as if they were scalars. Lower
1117 * them here by changing the component. */
1119 uint8_t original_swizzle
[4];
1120 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1121 unsigned orig_mask
= ins
.mask
;
1123 for (int i
= 0; i
< nr_components
; ++i
) {
1124 /* Mask the associated component, dropping the
1125 * instruction if needed */
1128 ins
.mask
&= orig_mask
;
1133 for (int j
= 0; j
< 4; ++j
)
1134 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1136 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, false));
1137 emit_mir_instruction(ctx
, ins
);
1140 emit_mir_instruction(ctx
, ins
);
1146 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1147 * optimized) versions of UBO #0 */
1151 compiler_context
*ctx
,
1154 nir_src
*indirect_offset
,
1157 /* TODO: half-floats */
1159 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
1161 /* TODO: Don't split */
1162 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1163 ins
.load_store
.address
= offset
>> 3;
1165 if (indirect_offset
) {
1166 emit_indirect_offset(ctx
, indirect_offset
);
1167 ins
.load_store
.unknown
= 0x8700 | index
; /* xxx: what is this? */
1169 ins
.load_store
.unknown
= 0x1E00 | index
; /* xxx: what is this? */
1172 emit_mir_instruction(ctx
, ins
);
1177 compiler_context
*ctx
,
1178 unsigned dest
, unsigned offset
,
1179 unsigned nr_comp
, unsigned component
,
1180 nir_src
*indirect_offset
, nir_alu_type type
)
1182 /* XXX: Half-floats? */
1183 /* TODO: swizzle, mask */
1185 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1186 ins
.mask
= mask_of(nr_comp
);
1187 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1189 midgard_varying_parameter p
= {
1191 .interpolation
= midgard_interp_default
,
1192 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1196 memcpy(&u
, &p
, sizeof(p
));
1197 ins
.load_store
.varying_parameters
= u
;
1199 if (indirect_offset
) {
1200 /* We need to add in the dynamic index, moved to r27.w */
1201 emit_indirect_offset(ctx
, indirect_offset
);
1202 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1204 /* Just a direct load */
1205 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1208 /* Use the type appropriate load */
1212 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1215 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1217 case nir_type_float
:
1218 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1221 unreachable("Attempted to load unknown type");
1225 emit_mir_instruction(ctx
, ins
);
1229 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
)
1233 /* Figure out which uniform this is */
1234 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1235 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1237 /* Sysvals are prefix uniforms */
1238 unsigned uniform
= ((uintptr_t) val
) - 1;
1240 /* Emit the read itself -- this is never indirect */
1241 emit_ubo_read(ctx
, dest
, uniform
, NULL
, 0);
1245 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1247 unsigned offset
= 0, reg
;
1249 switch (instr
->intrinsic
) {
1250 case nir_intrinsic_discard_if
:
1251 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1255 case nir_intrinsic_discard
: {
1256 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1257 struct midgard_instruction discard
= v_branch(conditional
, false);
1258 discard
.branch
.target_type
= TARGET_DISCARD
;
1259 emit_mir_instruction(ctx
, discard
);
1263 case nir_intrinsic_load_uniform
:
1264 case nir_intrinsic_load_ubo
:
1265 case nir_intrinsic_load_input
: {
1266 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1267 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1269 /* Get the base type of the intrinsic */
1270 /* TODO: Infer type? Does it matter? */
1272 is_ubo
? nir_type_uint
: nir_intrinsic_type(instr
);
1273 t
= nir_alu_type_get_base_type(t
);
1276 offset
= nir_intrinsic_base(instr
);
1279 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1281 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1283 bool direct
= nir_src_is_const(*src_offset
);
1286 offset
+= nir_src_as_uint(*src_offset
);
1288 /* We may need to apply a fractional offset */
1289 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1290 nir_intrinsic_component(instr
) : 0;
1291 reg
= nir_dest_index(ctx
, &instr
->dest
);
1293 if (is_uniform
&& !ctx
->is_blend
) {
1294 emit_ubo_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
, 0);
1295 } else if (is_ubo
) {
1296 nir_src index
= instr
->src
[0];
1298 /* We don't yet support indirect UBOs. For indirect
1299 * block numbers (if that's possible), we don't know
1300 * enough about the hardware yet. For indirect sources,
1301 * we know what we need but we need to add some NIR
1302 * support for lowering correctly with respect to
1305 assert(nir_src_is_const(index
));
1306 assert(nir_src_is_const(*src_offset
));
1308 /* TODO: Alignment */
1309 assert((offset
& 0xF) == 0);
1311 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1312 emit_ubo_read(ctx
, reg
, offset
/ 16, NULL
, uindex
);
1313 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1314 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
, t
);
1315 } else if (ctx
->is_blend
) {
1316 /* For blend shaders, load the input color, which is
1317 * preloaded to r0 */
1319 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), blank_alu_src
, reg
);
1320 emit_mir_instruction(ctx
, move
);
1321 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1322 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1323 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1324 ins
.mask
= mask_of(nr_comp
);
1326 /* Use the type appropriate load */
1330 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1333 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1335 case nir_type_float
:
1336 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1339 unreachable("Attempted to load unknown type");
1343 emit_mir_instruction(ctx
, ins
);
1345 DBG("Unknown load\n");
1352 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1354 case nir_intrinsic_load_raw_output_pan
:
1355 reg
= nir_dest_index(ctx
, &instr
->dest
);
1356 assert(ctx
->is_blend
);
1358 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1359 emit_mir_instruction(ctx
, ins
);
1362 case nir_intrinsic_load_blend_const_color_rgba
: {
1363 assert(ctx
->is_blend
);
1364 reg
= nir_dest_index(ctx
, &instr
->dest
);
1366 /* Blend constants are embedded directly in the shader and
1367 * patched in, so we use some magic routing */
1369 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1370 ins
.has_constants
= true;
1371 ins
.has_blend_constant
= true;
1372 emit_mir_instruction(ctx
, ins
);
1376 case nir_intrinsic_store_output
:
1377 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1379 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1381 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1383 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1384 /* gl_FragColor is not emitted with load/store
1385 * instructions. Instead, it gets plonked into
1386 * r0 at the end of the shader and we do the
1387 * framebuffer writeout dance. TODO: Defer
1390 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1391 emit_mir_instruction(ctx
, move
);
1393 /* Save the index we're writing to for later reference
1394 * in the epilogue */
1396 ctx
->fragment_output
= reg
;
1397 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1398 /* We should have been vectorized, though we don't
1399 * currently check that st_vary is emitted only once
1400 * per slot (this is relevant, since there's not a mask
1401 * parameter available on the store [set to 0 by the
1402 * blob]). We do respect the component by adjusting the
1403 * swizzle. If this is a constant source, we'll need to
1404 * emit that explicitly. */
1406 emit_explicit_constant(ctx
, reg
, reg
);
1408 unsigned component
= nir_intrinsic_component(instr
);
1410 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1411 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1412 st
.load_store
.swizzle
= SWIZZLE_XYZW
<< (2*component
);
1413 emit_mir_instruction(ctx
, st
);
1415 DBG("Unknown store\n");
1421 /* Special case of store_output for lowered blend shaders */
1422 case nir_intrinsic_store_raw_output_pan
:
1423 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1424 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1426 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1427 emit_mir_instruction(ctx
, move
);
1428 ctx
->fragment_output
= reg
;
1432 case nir_intrinsic_load_alpha_ref_float
:
1433 assert(instr
->dest
.is_ssa
);
1435 float ref_value
= ctx
->alpha_ref
;
1437 /* See emit_load_const */
1438 float *v
= ralloc_array(NULL
, float, 4);
1439 memcpy(v
, &ref_value
, sizeof(float));
1440 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (instr
->dest
.ssa
.index
<< 1) + 1, v
);
1443 case nir_intrinsic_load_viewport_scale
:
1444 case nir_intrinsic_load_viewport_offset
:
1445 emit_sysval_read(ctx
, &instr
->instr
);
1449 printf ("Unhandled intrinsic\n");
1456 midgard_tex_format(enum glsl_sampler_dim dim
)
1459 case GLSL_SAMPLER_DIM_1D
:
1460 case GLSL_SAMPLER_DIM_BUF
:
1463 case GLSL_SAMPLER_DIM_2D
:
1464 case GLSL_SAMPLER_DIM_EXTERNAL
:
1467 case GLSL_SAMPLER_DIM_3D
:
1470 case GLSL_SAMPLER_DIM_CUBE
:
1471 return MALI_TEX_CUBE
;
1474 DBG("Unknown sampler dim type\n");
1480 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1484 pan_attach_constant_bias(
1485 compiler_context
*ctx
,
1487 midgard_texture_word
*word
)
1489 /* To attach as constant, it has to *be* constant */
1491 if (!nir_src_is_const(lod
))
1494 float f
= nir_src_as_float(lod
);
1496 /* Break into fixed-point */
1498 float lod_frac
= f
- lod_int
;
1500 /* Carry over negative fractions */
1501 if (lod_frac
< 0.0) {
1507 word
->bias
= float_to_ubyte(lod_frac
);
1508 word
->bias_int
= lod_int
;
1513 static enum mali_sampler_type
1514 midgard_sampler_type(nir_alu_type t
) {
1515 switch (nir_alu_type_get_base_type(t
))
1517 case nir_type_float
:
1518 return MALI_SAMPLER_FLOAT
;
1520 return MALI_SAMPLER_SIGNED
;
1522 return MALI_SAMPLER_UNSIGNED
;
1524 unreachable("Unknown sampler type");
1529 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1530 unsigned midgard_texop
)
1533 //assert (!instr->sampler);
1534 //assert (!instr->texture_array_size);
1536 int texture_index
= instr
->texture_index
;
1537 int sampler_index
= texture_index
;
1539 /* No helper to build texture words -- we do it all here */
1540 midgard_instruction ins
= {
1541 .type
= TAG_TEXTURE_4
,
1544 .dest
= nir_dest_index(ctx
, &instr
->dest
),
1549 .op
= midgard_texop
,
1550 .format
= midgard_tex_format(instr
->sampler_dim
),
1551 .texture_handle
= texture_index
,
1552 .sampler_handle
= sampler_index
,
1553 .swizzle
= SWIZZLE_XYZW
,
1554 .in_reg_swizzle
= SWIZZLE_XYZW
,
1560 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1564 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1565 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1566 midgard_vector_alu_src alu_src
= blank_alu_src
;
1568 switch (instr
->src
[i
].src_type
) {
1569 case nir_tex_src_coord
: {
1570 emit_explicit_constant(ctx
, index
, index
);
1572 /* Texelfetch coordinates uses all four elements
1573 * (xyz/index) regardless of texture dimensionality,
1574 * which means it's necessary to zero the unused
1575 * components to keep everything happy */
1577 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1578 unsigned old_index
= index
;
1580 index
= make_compiler_temp(ctx
);
1582 /* mov index, old_index */
1583 midgard_instruction mov
= v_mov(old_index
, blank_alu_src
, index
);
1585 emit_mir_instruction(ctx
, mov
);
1587 /* mov index.zw, #0 */
1588 mov
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
),
1589 blank_alu_src
, index
);
1590 mov
.has_constants
= true;
1591 mov
.mask
= (1 << COMPONENT_Z
) | (1 << COMPONENT_W
);
1592 emit_mir_instruction(ctx
, mov
);
1595 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1596 /* texelFetch is undefined on samplerCube */
1597 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1599 /* For cubemaps, we use a special ld/st op to
1600 * select the face and copy the xy into the
1601 * texture register */
1603 unsigned temp
= make_compiler_temp(ctx
);
1605 midgard_instruction st
= m_st_cubemap_coords(temp
, 0);
1606 st
.ssa_args
.src0
= index
;
1607 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1608 st
.mask
= 0x3; /* xy */
1609 st
.load_store
.swizzle
= alu_src
.swizzle
;
1610 emit_mir_instruction(ctx
, st
);
1612 ins
.ssa_args
.src0
= temp
;
1614 ins
.ssa_args
.src0
= index
;
1617 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1618 /* Array component in w but NIR wants it in z */
1619 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYZZ
;
1625 case nir_tex_src_bias
:
1626 case nir_tex_src_lod
: {
1627 /* Try as a constant if we can */
1629 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1630 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1633 ins
.texture
.lod_register
= true;
1634 ins
.ssa_args
.src1
= index
;
1635 emit_explicit_constant(ctx
, index
, index
);
1641 unreachable("Unknown texture source type\n");
1645 emit_mir_instruction(ctx
, ins
);
1647 /* Used for .cont and .last hinting */
1648 ctx
->texture_op_count
++;
1652 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1654 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1655 * generic tex in some cases (which confuses the hardware) */
1657 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1659 if (is_vertex
&& instr
->op
== nir_texop_tex
)
1660 instr
->op
= nir_texop_txl
;
1662 switch (instr
->op
) {
1665 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1668 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1671 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1674 emit_sysval_read(ctx
, &instr
->instr
);
1677 unreachable("Unhanlded texture op");
1682 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1684 switch (instr
->type
) {
1685 case nir_jump_break
: {
1686 /* Emit a branch out of the loop */
1687 struct midgard_instruction br
= v_branch(false, false);
1688 br
.branch
.target_type
= TARGET_BREAK
;
1689 br
.branch
.target_break
= ctx
->current_loop_depth
;
1690 emit_mir_instruction(ctx
, br
);
1695 DBG("Unknown jump type %d\n", instr
->type
);
1701 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1703 switch (instr
->type
) {
1704 case nir_instr_type_load_const
:
1705 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1708 case nir_instr_type_intrinsic
:
1709 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1712 case nir_instr_type_alu
:
1713 emit_alu(ctx
, nir_instr_as_alu(instr
));
1716 case nir_instr_type_tex
:
1717 emit_tex(ctx
, nir_instr_as_tex(instr
));
1720 case nir_instr_type_jump
:
1721 emit_jump(ctx
, nir_instr_as_jump(instr
));
1724 case nir_instr_type_ssa_undef
:
1729 DBG("Unhandled instruction type\n");
1735 /* ALU instructions can inline or embed constants, which decreases register
1736 * pressure and saves space. */
1738 #define CONDITIONAL_ATTACH(src) { \
1739 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1742 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1743 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1748 inline_alu_constants(compiler_context
*ctx
)
1750 mir_foreach_instr(ctx
, alu
) {
1751 /* Other instructions cannot inline constants */
1752 if (alu
->type
!= TAG_ALU_4
) continue;
1754 /* If there is already a constant here, we can do nothing */
1755 if (alu
->has_constants
) continue;
1757 CONDITIONAL_ATTACH(src0
);
1759 if (!alu
->has_constants
) {
1760 CONDITIONAL_ATTACH(src1
)
1761 } else if (!alu
->inline_constant
) {
1762 /* Corner case: _two_ vec4 constants, for instance with a
1763 * csel. For this case, we can only use a constant
1764 * register for one, we'll have to emit a move for the
1765 * other. Note, if both arguments are constants, then
1766 * necessarily neither argument depends on the value of
1767 * any particular register. As the destination register
1768 * will be wiped, that means we can spill the constant
1769 * to the destination register.
1772 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
1773 unsigned scratch
= alu
->ssa_args
.dest
;
1776 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1777 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
1779 /* Force a break XXX Defer r31 writes */
1780 ins
.unit
= UNIT_VLUT
;
1782 /* Set the source */
1783 alu
->ssa_args
.src1
= scratch
;
1785 /* Inject us -before- the last instruction which set r31 */
1786 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1792 /* Midgard supports two types of constants, embedded constants (128-bit) and
1793 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1794 * constants can be demoted to inline constants, for space savings and
1795 * sometimes a performance boost */
1798 embedded_to_inline_constant(compiler_context
*ctx
)
1800 mir_foreach_instr(ctx
, ins
) {
1801 if (!ins
->has_constants
) continue;
1803 if (ins
->ssa_args
.inline_constant
) continue;
1805 /* Blend constants must not be inlined by definition */
1806 if (ins
->has_blend_constant
) continue;
1808 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
1809 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
1810 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
1812 if (!(is_16
|| is_32
))
1815 /* src1 cannot be an inline constant due to encoding
1816 * restrictions. So, if possible we try to flip the arguments
1819 int op
= ins
->alu
.op
;
1821 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1823 /* These ops require an operational change to flip
1824 * their arguments TODO */
1825 case midgard_alu_op_flt
:
1826 case midgard_alu_op_fle
:
1827 case midgard_alu_op_ilt
:
1828 case midgard_alu_op_ile
:
1829 case midgard_alu_op_fcsel
:
1830 case midgard_alu_op_icsel
:
1831 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
1836 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
1837 /* Flip the SSA numbers */
1838 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
1839 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1841 /* And flip the modifiers */
1845 src_temp
= ins
->alu
.src2
;
1846 ins
->alu
.src2
= ins
->alu
.src1
;
1847 ins
->alu
.src1
= src_temp
;
1851 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1852 /* Extract the source information */
1854 midgard_vector_alu_src
*src
;
1855 int q
= ins
->alu
.src2
;
1856 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1859 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1860 int component
= src
->swizzle
& 3;
1862 /* Scale constant appropriately, if we can legally */
1863 uint16_t scaled_constant
= 0;
1865 if (midgard_is_integer_op(op
) || is_16
) {
1866 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
1867 scaled_constant
= (uint16_t) iconstants
[component
];
1869 /* Constant overflow after resize */
1870 if (scaled_constant
!= iconstants
[component
])
1873 float original
= (float) ins
->constants
[component
];
1874 scaled_constant
= _mesa_float_to_half(original
);
1876 /* Check for loss of precision. If this is
1877 * mediump, we don't care, but for a highp
1878 * shader, we need to pay attention. NIR
1879 * doesn't yet tell us which mode we're in!
1880 * Practically this prevents most constants
1881 * from being inlined, sadly. */
1883 float fp32
= _mesa_half_to_float(scaled_constant
);
1885 if (fp32
!= original
)
1889 /* We don't know how to handle these with a constant */
1891 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
1892 DBG("Bailing inline constant...\n");
1896 /* Make sure that the constant is not itself a
1897 * vector by checking if all accessed values
1898 * (by the swizzle) are the same. */
1900 uint32_t *cons
= (uint32_t *) ins
->constants
;
1901 uint32_t value
= cons
[component
];
1903 bool is_vector
= false;
1904 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
1906 for (int c
= 1; c
< 4; ++c
) {
1907 /* We only care if this component is actually used */
1908 if (!(mask
& (1 << c
)))
1911 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
1913 if (test
!= value
) {
1922 /* Get rid of the embedded constant */
1923 ins
->has_constants
= false;
1924 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
1925 ins
->ssa_args
.inline_constant
= true;
1926 ins
->inline_constant
= scaled_constant
;
1931 /* Dead code elimination for branches at the end of a block - only one branch
1932 * per block is legal semantically */
1935 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
1937 bool branched
= false;
1939 mir_foreach_instr_in_block_safe(block
, ins
) {
1940 if (!midgard_is_branch_unit(ins
->unit
)) continue;
1942 /* We ignore prepacked branches since the fragment epilogue is
1943 * just generally special */
1944 if (ins
->prepacked_branch
) continue;
1946 /* Discards are similarly special and may not correspond to the
1949 if (ins
->branch
.target_type
== TARGET_DISCARD
) continue;
1952 /* We already branched, so this is dead */
1953 mir_remove_instruction(ins
);
1960 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
1961 * the move can be propagated away entirely */
1964 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
1967 if (comp
== midgard_outmod_none
)
1970 if (*outmod
== midgard_outmod_none
) {
1975 /* TODO: Compose rules */
1980 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
1982 bool progress
= false;
1984 mir_foreach_instr_in_block_safe(block
, ins
) {
1985 if (ins
->type
!= TAG_ALU_4
) continue;
1986 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
1987 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
1989 /* TODO: Registers? */
1990 unsigned src
= ins
->ssa_args
.src1
;
1991 if (src
& IS_REG
) continue;
1992 assert(!mir_has_multiple_writes(ctx
, src
));
1994 /* There might be a source modifier, too */
1995 if (mir_nontrivial_source2_mod(ins
)) continue;
1997 /* Backpropagate the modifier */
1998 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
1999 if (v
->type
!= TAG_ALU_4
) continue;
2000 if (v
->ssa_args
.dest
!= src
) continue;
2002 /* Can we even take a float outmod? */
2003 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2005 midgard_outmod_float temp
= v
->alu
.outmod
;
2006 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2008 /* Throw in the towel.. */
2009 if (!progress
) break;
2011 /* Otherwise, transfer the modifier */
2012 v
->alu
.outmod
= temp
;
2013 ins
->alu
.outmod
= midgard_outmod_none
;
2023 emit_fragment_epilogue(compiler_context
*ctx
)
2025 emit_explicit_constant(ctx
, ctx
->fragment_output
, SSA_FIXED_REGISTER(0));
2027 /* Perform the actual fragment writeout. We have two writeout/branch
2028 * instructions, forming a loop until writeout is successful as per the
2029 * docs. TODO: gl_FragDepth */
2031 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2032 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2035 static midgard_block
*
2036 emit_block(compiler_context
*ctx
, nir_block
*block
)
2038 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
2039 list_addtail(&this_block
->link
, &ctx
->blocks
);
2041 this_block
->is_scheduled
= false;
2044 ctx
->texture_index
[0] = -1;
2045 ctx
->texture_index
[1] = -1;
2047 /* Add us as a successor to the block we are following */
2048 if (ctx
->current_block
)
2049 midgard_block_add_successor(ctx
->current_block
, this_block
);
2051 /* Set up current block */
2052 list_inithead(&this_block
->instructions
);
2053 ctx
->current_block
= this_block
;
2055 nir_foreach_instr(instr
, block
) {
2056 emit_instr(ctx
, instr
);
2057 ++ctx
->instruction_count
;
2060 inline_alu_constants(ctx
);
2061 embedded_to_inline_constant(ctx
);
2063 /* Append fragment shader epilogue (value writeout) */
2064 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2065 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2066 emit_fragment_epilogue(ctx
);
2070 if (block
== nir_start_block(ctx
->func
->impl
))
2071 ctx
->initial_block
= this_block
;
2073 if (block
== nir_impl_last_block(ctx
->func
->impl
))
2074 ctx
->final_block
= this_block
;
2076 /* Allow the next control flow to access us retroactively, for
2078 ctx
->current_block
= this_block
;
2080 /* Document the fallthrough chain */
2081 ctx
->previous_source_block
= this_block
;
2086 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2089 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2091 /* Conditional branches expect the condition in r31.w; emit a move for
2092 * that in the _previous_ block (which is the current block). */
2093 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2095 /* Speculatively emit the branch, but we can't fill it in until later */
2096 EMIT(branch
, true, true);
2097 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2099 /* Emit the two subblocks */
2100 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2102 /* Emit a jump from the end of the then block to the end of the else */
2103 EMIT(branch
, false, false);
2104 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2106 /* Emit second block, and check if it's empty */
2108 int else_idx
= ctx
->block_count
;
2109 int count_in
= ctx
->instruction_count
;
2110 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2111 int after_else_idx
= ctx
->block_count
;
2113 /* Now that we have the subblocks emitted, fix up the branches */
2118 if (ctx
->instruction_count
== count_in
) {
2119 /* The else block is empty, so don't emit an exit jump */
2120 mir_remove_instruction(then_exit
);
2121 then_branch
->branch
.target_block
= after_else_idx
;
2123 then_branch
->branch
.target_block
= else_idx
;
2124 then_exit
->branch
.target_block
= after_else_idx
;
2129 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2131 /* Remember where we are */
2132 midgard_block
*start_block
= ctx
->current_block
;
2134 /* Allocate a loop number, growing the current inner loop depth */
2135 int loop_idx
= ++ctx
->current_loop_depth
;
2137 /* Get index from before the body so we can loop back later */
2138 int start_idx
= ctx
->block_count
;
2140 /* Emit the body itself */
2141 emit_cf_list(ctx
, &nloop
->body
);
2143 /* Branch back to loop back */
2144 struct midgard_instruction br_back
= v_branch(false, false);
2145 br_back
.branch
.target_block
= start_idx
;
2146 emit_mir_instruction(ctx
, br_back
);
2148 /* Mark down that branch in the graph. Note that we're really branching
2149 * to the block *after* we started in. TODO: Why doesn't the branch
2150 * itself have an off-by-one then...? */
2151 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
2153 /* Find the index of the block about to follow us (note: we don't add
2154 * one; blocks are 0-indexed so we get a fencepost problem) */
2155 int break_block_idx
= ctx
->block_count
;
2157 /* Fix up the break statements we emitted to point to the right place,
2158 * now that we can allocate a block number for them */
2160 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2161 mir_foreach_instr_in_block(block
, ins
) {
2162 if (ins
->type
!= TAG_ALU_4
) continue;
2163 if (!ins
->compact_branch
) continue;
2164 if (ins
->prepacked_branch
) continue;
2166 /* We found a branch -- check the type to see if we need to do anything */
2167 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2169 /* It's a break! Check if it's our break */
2170 if (ins
->branch
.target_break
!= loop_idx
) continue;
2172 /* Okay, cool, we're breaking out of this loop.
2173 * Rewrite from a break to a goto */
2175 ins
->branch
.target_type
= TARGET_GOTO
;
2176 ins
->branch
.target_block
= break_block_idx
;
2180 /* Now that we've finished emitting the loop, free up the depth again
2181 * so we play nice with recursion amid nested loops */
2182 --ctx
->current_loop_depth
;
2184 /* Dump loop stats */
2188 static midgard_block
*
2189 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2191 midgard_block
*start_block
= NULL
;
2193 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2194 switch (node
->type
) {
2195 case nir_cf_node_block
: {
2196 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2199 start_block
= block
;
2204 case nir_cf_node_if
:
2205 emit_if(ctx
, nir_cf_node_as_if(node
));
2208 case nir_cf_node_loop
:
2209 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2212 case nir_cf_node_function
:
2221 /* Due to lookahead, we need to report the first tag executed in the command
2222 * stream and in branch targets. An initial block might be empty, so iterate
2223 * until we find one that 'works' */
2226 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2228 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2230 unsigned first_tag
= 0;
2233 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
2235 if (initial_bundle
) {
2236 first_tag
= initial_bundle
->tag
;
2240 /* Initial block is empty, try the next block */
2241 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
2242 } while(initial_block
!= NULL
);
2249 midgard_compile_shader_nir(struct midgard_screen
*screen
, nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2251 struct util_dynarray
*compiled
= &program
->compiled
;
2253 midgard_debug
= debug_get_option_midgard_debug();
2255 compiler_context ictx
= {
2258 .stage
= nir
->info
.stage
,
2261 .is_blend
= is_blend
,
2262 .blend_constant_offset
= 0,
2264 .alpha_ref
= program
->alpha_ref
2267 compiler_context
*ctx
= &ictx
;
2269 /* Start off with a safe cutoff, allowing usage of all 16 work
2270 * registers. Later, we'll promote uniform reads to uniform registers
2271 * if we determine it is beneficial to do so */
2272 ctx
->uniform_cutoff
= 8;
2274 /* Initialize at a global (not block) level hash tables */
2276 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2277 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2278 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2280 /* Record the varying mapping for the command stream's bookkeeping */
2282 struct exec_list
*varyings
=
2283 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2285 unsigned max_varying
= 0;
2286 nir_foreach_variable(var
, varyings
) {
2287 unsigned loc
= var
->data
.driver_location
;
2288 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2290 for (int c
= 0; c
< sz
; ++c
) {
2291 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2292 max_varying
= MAX2(max_varying
, loc
+ c
);
2296 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2297 * (so we don't accidentally duplicate the epilogue since mesa/st has
2298 * messed with our I/O quite a bit already) */
2300 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2302 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2303 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2304 NIR_PASS_V(nir
, nir_clamp_psiz
, 1.0, 1024.0);
2307 NIR_PASS_V(nir
, nir_lower_var_copies
);
2308 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2309 NIR_PASS_V(nir
, nir_split_var_copies
);
2310 NIR_PASS_V(nir
, nir_lower_var_copies
);
2311 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2312 NIR_PASS_V(nir
, nir_lower_var_copies
);
2313 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2315 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2317 /* Optimisation passes */
2321 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2322 nir_print_shader(nir
, stdout
);
2325 /* Assign sysvals and counts, now that we're sure
2326 * (post-optimisation) */
2328 midgard_nir_assign_sysvals(ctx
, nir
);
2330 program
->uniform_count
= nir
->num_uniforms
;
2331 program
->sysval_count
= ctx
->sysval_count
;
2332 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2334 nir_foreach_function(func
, nir
) {
2338 list_inithead(&ctx
->blocks
);
2339 ctx
->block_count
= 0;
2342 emit_cf_list(ctx
, &func
->impl
->body
);
2343 emit_block(ctx
, func
->impl
->end_block
);
2345 break; /* TODO: Multi-function shaders */
2348 util_dynarray_init(compiled
, NULL
);
2350 /* MIR-level optimizations */
2352 bool progress
= false;
2357 mir_foreach_block(ctx
, block
) {
2358 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2359 progress
|= midgard_opt_copy_prop(ctx
, block
);
2360 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2361 progress
|= midgard_opt_combine_projection(ctx
, block
);
2362 progress
|= midgard_opt_varying_projection(ctx
, block
);
2366 mir_foreach_block(ctx
, block
) {
2367 midgard_lower_invert(ctx
, block
);
2368 midgard_lower_derivatives(ctx
, block
);
2371 /* Nested control-flow can result in dead branches at the end of the
2372 * block. This messes with our analysis and is just dead code, so cull
2374 mir_foreach_block(ctx
, block
) {
2375 midgard_opt_cull_dead_branch(ctx
, block
);
2378 /* Ensure we were lowered */
2379 mir_foreach_instr_global(ctx
, ins
) {
2380 assert(!ins
->invert
);
2384 schedule_program(ctx
);
2386 /* Now that all the bundles are scheduled and we can calculate block
2387 * sizes, emit actual branch instructions rather than placeholders */
2389 int br_block_idx
= 0;
2391 mir_foreach_block(ctx
, block
) {
2392 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2393 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2394 midgard_instruction
*ins
= bundle
->instructions
[c
];
2396 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2398 if (ins
->prepacked_branch
) continue;
2400 /* Parse some basic branch info */
2401 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2402 bool is_conditional
= ins
->branch
.conditional
;
2403 bool is_inverted
= ins
->branch
.invert_conditional
;
2404 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2406 /* Determine the block we're jumping to */
2407 int target_number
= ins
->branch
.target_block
;
2409 /* Report the destination tag */
2410 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2412 /* Count up the number of quadwords we're
2413 * jumping over = number of quadwords until
2414 * (br_block_idx, target_number) */
2416 int quadword_offset
= 0;
2420 } else if (target_number
> br_block_idx
) {
2423 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2424 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2427 quadword_offset
+= blk
->quadword_count
;
2430 /* Jump backwards */
2432 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2433 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2436 quadword_offset
-= blk
->quadword_count
;
2440 /* Unconditional extended branches (far jumps)
2441 * have issues, so we always use a conditional
2442 * branch, setting the condition to always for
2443 * unconditional. For compact unconditional
2444 * branches, cond isn't used so it doesn't
2445 * matter what we pick. */
2447 midgard_condition cond
=
2448 !is_conditional
? midgard_condition_always
:
2449 is_inverted
? midgard_condition_false
:
2450 midgard_condition_true
;
2452 midgard_jmp_writeout_op op
=
2453 is_discard
? midgard_jmp_writeout_op_discard
:
2454 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2455 midgard_jmp_writeout_op_branch_cond
;
2458 midgard_branch_extended branch
=
2459 midgard_create_branch_extended(
2464 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2465 } else if (is_conditional
|| is_discard
) {
2466 midgard_branch_cond branch
= {
2468 .dest_tag
= dest_tag
,
2469 .offset
= quadword_offset
,
2473 assert(branch
.offset
== quadword_offset
);
2475 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2477 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2479 midgard_branch_uncond branch
= {
2481 .dest_tag
= dest_tag
,
2482 .offset
= quadword_offset
,
2486 assert(branch
.offset
== quadword_offset
);
2488 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2496 /* Emit flat binary from the instruction arrays. Iterate each block in
2497 * sequence. Save instruction boundaries such that lookahead tags can
2498 * be assigned easily */
2500 /* Cache _all_ bundles in source order for lookahead across failed branches */
2502 int bundle_count
= 0;
2503 mir_foreach_block(ctx
, block
) {
2504 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2506 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2508 mir_foreach_block(ctx
, block
) {
2509 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2510 source_order_bundles
[bundle_idx
++] = bundle
;
2514 int current_bundle
= 0;
2516 /* Midgard prefetches instruction types, so during emission we
2517 * need to lookahead. Unless this is the last instruction, in
2518 * which we return 1. Or if this is the second to last and the
2519 * last is an ALU, then it's also 1... */
2521 mir_foreach_block(ctx
, block
) {
2522 mir_foreach_bundle_in_block(block
, bundle
) {
2525 if (current_bundle
+ 1 < bundle_count
) {
2526 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2528 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2535 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2539 /* TODO: Free deeper */
2540 //util_dynarray_fini(&block->instructions);
2543 free(source_order_bundles
);
2545 /* Report the very first tag executed */
2546 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2548 /* Deal with off-by-one related to the fencepost problem */
2549 program
->work_register_count
= ctx
->work_registers
+ 1;
2550 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2552 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2553 program
->tls_size
= ctx
->tls_size
;
2555 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2556 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);
2558 if (midgard_debug
& MIDGARD_DBG_SHADERDB
) {
2559 unsigned nr_bundles
= 0, nr_ins
= 0, nr_quadwords
= 0;
2561 /* Count instructions and bundles */
2563 mir_foreach_instr_global(ctx
, ins
) {
2567 mir_foreach_block(ctx
, block
) {
2568 nr_bundles
+= util_dynarray_num_elements(
2569 &block
->bundles
, midgard_bundle
);
2571 nr_quadwords
+= block
->quadword_count
;
2574 /* Calculate thread count. There are certain cutoffs by
2575 * register count for thread count */
2577 unsigned nr_registers
= program
->work_register_count
;
2579 unsigned nr_threads
=
2580 (nr_registers
<= 4) ? 4 :
2581 (nr_registers
<= 8) ? 2 :
2586 fprintf(stderr
, "shader%d - %s shader: "
2587 "%u inst, %u bundles, %u quadwords, "
2588 "%u registers, %u threads, %u loops, "
2589 "%d:%d spills:fills\n",
2591 gl_shader_stage_name(ctx
->stage
),
2592 nr_ins
, nr_bundles
, nr_quadwords
,
2593 nr_registers
, nr_threads
,
2595 ctx
->spills
, ctx
->fills
);