2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
50 #include "midgard_quirks.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
63 unsigned SHADER_DB_COUNT
= 0;
65 int midgard_debug
= 0;
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block
*
72 create_empty_block(compiler_context
*ctx
)
74 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
76 blk
->base
.predecessors
= _mesa_set_create(blk
,
78 _mesa_key_pointer_equal
);
80 blk
->base
.name
= ctx
->block_source_count
++;
86 schedule_barrier(compiler_context
*ctx
)
88 midgard_block
*temp
= ctx
->after_block
;
89 ctx
->after_block
= create_empty_block(ctx
);
91 list_addtail(&ctx
->after_block
->base
.link
, &ctx
->blocks
);
92 list_inithead(&ctx
->after_block
->base
.instructions
);
93 pan_block_add_successor(&ctx
->current_block
->base
, &ctx
->after_block
->base
);
94 ctx
->current_block
= ctx
->after_block
;
95 ctx
->after_block
= temp
;
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
112 .op = midgard_op_##name, \
119 i.src_types[0] = T; \
127 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
128 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
131 * the corresponding Midgard source */
133 static midgard_vector_alu_src
134 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
135 bool half
, bool sext
)
137 /* Figure out how many components there are so we can adjust.
138 * Specifically we want to broadcast the last channel so things like
142 if (broadcast_count
&& src
) {
143 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
145 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
146 src
->swizzle
[c
] = last_component
;
150 midgard_vector_alu_src alu_src
= {
157 alu_src
.mod
= midgard_int_normal
;
159 /* Sign/zero-extend if needed */
163 midgard_int_sign_extend
164 : midgard_int_zero_extend
;
167 /* These should have been lowered away */
169 assert(!(src
->abs
|| src
->negate
));
172 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
178 M_LOAD(ld_attr_32
, nir_type_uint32
);
179 M_LOAD(ld_vary_32
, nir_type_uint32
);
180 M_LOAD(ld_ubo_int4
, nir_type_uint32
);
181 M_LOAD(ld_int4
, nir_type_uint32
);
182 M_STORE(st_int4
, nir_type_uint32
);
183 M_LOAD(ld_color_buffer_32u
, nir_type_uint32
);
184 M_STORE(st_vary_32
, nir_type_uint32
);
185 M_LOAD(ld_cubemap_coords
, nir_type_uint32
);
186 M_LOAD(ld_compute_id
, nir_type_uint32
);
188 static midgard_instruction
189 v_branch(bool conditional
, bool invert
)
191 midgard_instruction ins
= {
193 .unit
= ALU_ENAB_BRANCH
,
194 .compact_branch
= true,
196 .conditional
= conditional
,
197 .invert_conditional
= invert
200 .src
= { ~0, ~0, ~0, ~0 },
206 static midgard_branch_extended
207 midgard_create_branch_extended( midgard_condition cond
,
208 midgard_jmp_writeout_op op
,
210 signed quadword_offset
)
212 /* The condition code is actually a LUT describing a function to
213 * combine multiple condition codes. However, we only support a single
214 * condition code at the moment, so we just duplicate over a bunch of
217 uint16_t duplicated_cond
=
227 midgard_branch_extended branch
= {
229 .dest_tag
= dest_tag
,
230 .offset
= quadword_offset
,
231 .cond
= duplicated_cond
238 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
240 ins
->has_constants
= true;
241 memcpy(&ins
->constants
, constants
, 16);
245 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
247 return glsl_count_attribute_slots(type
, false);
250 /* Lower fdot2 to a vector multiplication followed by channel addition */
252 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
254 if (alu
->op
!= nir_op_fdot2
)
257 b
->cursor
= nir_before_instr(&alu
->instr
);
259 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
260 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
262 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
264 nir_ssa_def
*sum
= nir_fadd(b
,
265 nir_channel(b
, product
, 0),
266 nir_channel(b
, product
, 1));
268 /* Replace the fdot2 with this sum */
269 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
273 midgard_nir_lower_fdot2(nir_shader
*shader
)
275 bool progress
= false;
277 nir_foreach_function(function
, shader
) {
278 if (!function
->impl
) continue;
281 nir_builder
*b
= &_b
;
282 nir_builder_init(b
, function
->impl
);
284 nir_foreach_block(block
, function
->impl
) {
285 nir_foreach_instr_safe(instr
, block
) {
286 if (instr
->type
!= nir_instr_type_alu
) continue;
288 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
289 midgard_nir_lower_fdot2_body(b
, alu
);
295 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
302 /* Midgard can't write depth and stencil separately. It has to happen in a
303 * single store operation containing both. Let's add a panfrost specific
304 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
308 midgard_nir_lower_zs_store(nir_shader
*nir
)
310 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
313 nir_variable
*z_var
= NULL
, *s_var
= NULL
;
315 nir_foreach_variable(var
, &nir
->outputs
) {
316 if (var
->data
.location
== FRAG_RESULT_DEPTH
)
318 else if (var
->data
.location
== FRAG_RESULT_STENCIL
)
322 if (!z_var
&& !s_var
)
325 bool progress
= false;
327 nir_foreach_function(function
, nir
) {
328 if (!function
->impl
) continue;
330 nir_intrinsic_instr
*z_store
= NULL
, *s_store
= NULL
, *last_store
= NULL
;
332 nir_foreach_block(block
, function
->impl
) {
333 nir_foreach_instr_safe(instr
, block
) {
334 if (instr
->type
!= nir_instr_type_intrinsic
)
337 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
338 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
341 if (z_var
&& nir_intrinsic_base(intr
) == z_var
->data
.driver_location
) {
347 if (s_var
&& nir_intrinsic_base(intr
) == s_var
->data
.driver_location
) {
355 if (!z_store
&& !s_store
) continue;
358 nir_builder_init(&b
, function
->impl
);
360 b
.cursor
= nir_before_instr(&last_store
->instr
);
362 nir_ssa_def
*zs_store_src
;
364 if (z_store
&& s_store
) {
365 nir_ssa_def
*srcs
[2] = {
366 nir_ssa_for_src(&b
, z_store
->src
[0], 1),
367 nir_ssa_for_src(&b
, s_store
->src
[0], 1),
370 zs_store_src
= nir_vec(&b
, srcs
, 2);
372 zs_store_src
= nir_ssa_for_src(&b
, last_store
->src
[0], 1);
375 nir_intrinsic_instr
*zs_store
;
377 zs_store
= nir_intrinsic_instr_create(b
.shader
,
378 nir_intrinsic_store_zs_output_pan
);
379 zs_store
->src
[0] = nir_src_for_ssa(zs_store_src
);
380 zs_store
->num_components
= z_store
&& s_store
? 2 : 1;
381 nir_intrinsic_set_component(zs_store
, z_store
? 0 : 1);
383 /* Replace the Z and S store by a ZS store */
384 nir_builder_instr_insert(&b
, &zs_store
->instr
);
387 nir_instr_remove(&z_store
->instr
);
390 nir_instr_remove(&s_store
->instr
);
392 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
399 /* Flushes undefined values to zero */
402 optimise_nir(nir_shader
*nir
, unsigned quirks
)
405 unsigned lower_flrp
=
406 (nir
->options
->lower_flrp16
? 16 : 0) |
407 (nir
->options
->lower_flrp32
? 32 : 0) |
408 (nir
->options
->lower_flrp64
? 64 : 0);
410 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
411 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
413 nir_lower_tex_options lower_tex_options
= {
414 .lower_txs_lod
= true,
416 .lower_tex_without_implicit_lod
=
417 (quirks
& MIDGARD_EXPLICIT_LOD
),
419 /* TODO: we have native gradient.. */
423 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
425 /* Must lower fdot2 after tex is lowered */
426 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
428 /* T720 is broken. */
430 if (quirks
& MIDGARD_BROKEN_LOD
)
431 NIR_PASS_V(nir
, midgard_nir_lod_errata
);
436 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
437 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
439 NIR_PASS(progress
, nir
, nir_copy_prop
);
440 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
441 NIR_PASS(progress
, nir
, nir_opt_dce
);
442 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
443 NIR_PASS(progress
, nir
, nir_opt_cse
);
444 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
445 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
446 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
448 if (lower_flrp
!= 0) {
449 bool lower_flrp_progress
= false;
450 NIR_PASS(lower_flrp_progress
,
454 false /* always_precise */,
455 nir
->options
->lower_ffma
);
456 if (lower_flrp_progress
) {
457 NIR_PASS(progress
, nir
,
458 nir_opt_constant_folding
);
462 /* Nothing should rematerialize any flrps, so we only
463 * need to do this lowering once.
468 NIR_PASS(progress
, nir
, nir_opt_undef
);
469 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
471 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
474 nir_var_function_temp
);
476 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
479 /* Must be run at the end to prevent creation of fsin/fcos ops */
480 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
485 NIR_PASS(progress
, nir
, nir_opt_dce
);
486 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
487 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
488 NIR_PASS(progress
, nir
, nir_copy_prop
);
491 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
492 NIR_PASS(progress
, nir
, nir_opt_algebraic_distribute_src_mods
);
494 /* We implement booleans as 32-bit 0/~0 */
495 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
497 /* Now that booleans are lowered, we can run out late opts */
498 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
500 /* Lower mods for float ops only. Integer ops don't support modifiers
501 * (saturate doesn't make sense on integers, neg/abs require dedicated
504 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
505 NIR_PASS(progress
, nir
, nir_copy_prop
);
506 NIR_PASS(progress
, nir
, nir_opt_dce
);
508 /* Take us out of SSA */
509 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
510 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
512 /* We are a vector architecture; write combine where possible */
513 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
514 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
516 NIR_PASS(progress
, nir
, nir_opt_dce
);
519 /* Do not actually emit a load; instead, cache the constant for inlining */
522 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
524 nir_ssa_def def
= instr
->def
;
526 midgard_constants
*consts
= rzalloc(NULL
, midgard_constants
);
528 assert(instr
->def
.num_components
* instr
->def
.bit_size
<= sizeof(*consts
) * 8);
530 #define RAW_CONST_COPY(bits) \
531 nir_const_value_to_array(consts->u##bits, instr->value, \
532 instr->def.num_components, u##bits)
534 switch (instr
->def
.bit_size
) {
548 unreachable("Invalid bit_size for load_const instruction\n");
551 /* Shifted for SSA, +1 for off-by-one */
552 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, consts
);
555 /* Normally constants are embedded implicitly, but for I/O and such we have to
556 * explicitly emit a move with the constant source */
559 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
561 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
563 if (constant_value
) {
564 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), to
);
565 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
566 emit_mir_instruction(ctx
, ins
);
571 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
573 unsigned comp
= src
->swizzle
[0];
575 for (unsigned c
= 1; c
< nr_components
; ++c
) {
576 if (src
->swizzle
[c
] != comp
)
583 #define ALU_CASE(nir, _op) \
585 op = midgard_alu_op_##_op; \
586 assert(src_bitsize == dst_bitsize); \
589 #define ALU_CASE_BCAST(nir, _op, count) \
591 op = midgard_alu_op_##_op; \
592 broadcast_swizzle = count; \
593 assert(src_bitsize == dst_bitsize); \
596 nir_is_fzero_constant(nir_src src
)
598 if (!nir_src_is_const(src
))
601 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
602 if (nir_src_comp_as_float(src
, c
) != 0.0)
609 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
610 * special treatment override this anyway. */
612 static midgard_reg_mode
613 reg_mode_for_nir(nir_alu_instr
*instr
)
615 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
617 switch (src_bitsize
) {
619 return midgard_reg_mode_8
;
621 return midgard_reg_mode_16
;
623 return midgard_reg_mode_32
;
625 return midgard_reg_mode_64
;
627 unreachable("Invalid bit size");
632 mir_copy_src(midgard_instruction
*ins
, nir_alu_instr
*instr
, unsigned i
, unsigned to
)
634 unsigned bits
= nir_src_bit_size(instr
->src
[i
].src
);
636 ins
->src
[to
] = nir_src_index(NULL
, &instr
->src
[i
].src
);
637 ins
->src_types
[to
] = nir_op_infos
[instr
->op
].input_types
[i
] | bits
;
641 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
643 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
644 * is handled elsewhere */
646 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
647 midgard_emit_derivatives(ctx
, instr
);
651 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
653 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
654 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
657 /* Number of components valid to check for the instruction (the rest
658 * will be forced to the last), or 0 to use as-is. Relevant as
659 * ball-type instructions have a channel count in NIR but are all vec4
662 unsigned broadcast_swizzle
= 0;
664 /* What register mode should we operate in? */
665 midgard_reg_mode reg_mode
=
666 reg_mode_for_nir(instr
);
668 /* Do we need a destination override? Used for inline
671 midgard_dest_override dest_override
=
672 midgard_dest_override_none
;
674 /* Should we use a smaller respective source and sign-extend? */
676 bool half_1
= false, sext_1
= false;
677 bool half_2
= false, sext_2
= false;
679 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
680 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
683 ALU_CASE(fadd
, fadd
);
684 ALU_CASE(fmul
, fmul
);
685 ALU_CASE(fmin
, fmin
);
686 ALU_CASE(fmax
, fmax
);
687 ALU_CASE(imin
, imin
);
688 ALU_CASE(imax
, imax
);
689 ALU_CASE(umin
, umin
);
690 ALU_CASE(umax
, umax
);
691 ALU_CASE(ffloor
, ffloor
);
692 ALU_CASE(fround_even
, froundeven
);
693 ALU_CASE(ftrunc
, ftrunc
);
694 ALU_CASE(fceil
, fceil
);
695 ALU_CASE(fdot3
, fdot3
);
696 ALU_CASE(fdot4
, fdot4
);
697 ALU_CASE(iadd
, iadd
);
698 ALU_CASE(isub
, isub
);
699 ALU_CASE(imul
, imul
);
701 /* Zero shoved as second-arg */
702 ALU_CASE(iabs
, iabsdiff
);
706 ALU_CASE(feq32
, feq
);
707 ALU_CASE(fne32
, fne
);
708 ALU_CASE(flt32
, flt
);
709 ALU_CASE(ieq32
, ieq
);
710 ALU_CASE(ine32
, ine
);
711 ALU_CASE(ilt32
, ilt
);
712 ALU_CASE(ult32
, ult
);
714 /* We don't have a native b2f32 instruction. Instead, like many
715 * GPUs, we exploit booleans as 0/~0 for false/true, and
716 * correspondingly AND
717 * by 1.0 to do the type conversion. For the moment, prime us
720 * iand [whatever], #0
722 * At the end of emit_alu (as MIR), we'll fix-up the constant
725 ALU_CASE(b2f32
, iand
);
726 ALU_CASE(b2i32
, iand
);
728 /* Likewise, we don't have a dedicated f2b32 instruction, but
729 * we can do a "not equal to 0.0" test. */
731 ALU_CASE(f2b32
, fne
);
732 ALU_CASE(i2b32
, ine
);
734 ALU_CASE(frcp
, frcp
);
735 ALU_CASE(frsq
, frsqrt
);
736 ALU_CASE(fsqrt
, fsqrt
);
737 ALU_CASE(fexp2
, fexp2
);
738 ALU_CASE(flog2
, flog2
);
740 ALU_CASE(f2i64
, f2i_rtz
);
741 ALU_CASE(f2u64
, f2u_rtz
);
742 ALU_CASE(i2f64
, i2f_rtz
);
743 ALU_CASE(u2f64
, u2f_rtz
);
745 ALU_CASE(f2i32
, f2i_rtz
);
746 ALU_CASE(f2u32
, f2u_rtz
);
747 ALU_CASE(i2f32
, i2f_rtz
);
748 ALU_CASE(u2f32
, u2f_rtz
);
750 ALU_CASE(f2i16
, f2i_rtz
);
751 ALU_CASE(f2u16
, f2u_rtz
);
752 ALU_CASE(i2f16
, i2f_rtz
);
753 ALU_CASE(u2f16
, u2f_rtz
);
755 ALU_CASE(fsin
, fsin
);
756 ALU_CASE(fcos
, fcos
);
758 /* We'll set invert */
759 ALU_CASE(inot
, imov
);
760 ALU_CASE(iand
, iand
);
762 ALU_CASE(ixor
, ixor
);
763 ALU_CASE(ishl
, ishl
);
764 ALU_CASE(ishr
, iasr
);
765 ALU_CASE(ushr
, ilsr
);
767 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
768 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
769 ALU_CASE(b32all_fequal4
, fball_eq
);
771 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
772 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
773 ALU_CASE(b32any_fnequal4
, fbany_neq
);
775 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
776 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
777 ALU_CASE(b32all_iequal4
, iball_eq
);
779 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
780 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
781 ALU_CASE(b32any_inequal4
, ibany_neq
);
783 /* Source mods will be shoved in later */
784 ALU_CASE(fabs
, fmov
);
785 ALU_CASE(fneg
, fmov
);
786 ALU_CASE(fsat
, fmov
);
788 /* For size conversion, we use a move. Ideally though we would squash
789 * these ops together; maybe that has to happen after in NIR as part of
790 * propagation...? An earlier algebraic pass ensured we step down by
791 * only / exactly one size. If stepping down, we use a dest override to
792 * reduce the size; if stepping up, we use a larger-sized move with a
793 * half source and a sign/zero-extension modifier */
799 /* If we end up upscale, we'll need a sign-extend on the
800 * operand (the second argument) */
811 if (instr
->op
== nir_op_f2f16
|| instr
->op
== nir_op_f2f32
||
812 instr
->op
== nir_op_f2f64
)
813 op
= midgard_alu_op_fmov
;
815 op
= midgard_alu_op_imov
;
817 if (dst_bitsize
== (src_bitsize
* 2)) {
821 /* Use a greater register mode */
823 } else if (src_bitsize
== (dst_bitsize
* 2)) {
824 /* Converting down */
825 dest_override
= midgard_dest_override_lower
;
831 /* For greater-or-equal, we lower to less-or-equal and flip the
839 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
840 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
841 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
842 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
845 /* Swap via temporary */
846 nir_alu_src temp
= instr
->src
[1];
847 instr
->src
[1] = instr
->src
[0];
848 instr
->src
[0] = temp
;
853 case nir_op_b32csel
: {
854 /* Midgard features both fcsel and icsel, depending on
855 * the type of the arguments/output. However, as long
856 * as we're careful we can _always_ use icsel and
857 * _never_ need fcsel, since the latter does additional
858 * floating-point-specific processing whereas the
859 * former just moves bits on the wire. It's not obvious
860 * why these are separate opcodes, save for the ability
861 * to do things like sat/pos/abs/neg for free */
863 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
864 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
866 /* The condition is the first argument; move the other
867 * arguments up one to be a binary instruction for
868 * Midgard with the condition last */
870 nir_alu_src temp
= instr
->src
[2];
872 instr
->src
[2] = instr
->src
[0];
873 instr
->src
[0] = instr
->src
[1];
874 instr
->src
[1] = temp
;
880 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
885 /* Midgard can perform certain modifiers on output of an ALU op */
888 if (midgard_is_integer_out_op(op
)) {
889 outmod
= midgard_outmod_int_wrap
;
891 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
892 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
895 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
897 if (instr
->op
== nir_op_fmax
) {
898 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
899 op
= midgard_alu_op_fmov
;
901 outmod
= midgard_outmod_pos
;
902 instr
->src
[0] = instr
->src
[1];
903 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
904 op
= midgard_alu_op_fmov
;
906 outmod
= midgard_outmod_pos
;
910 /* Fetch unit, quirks, etc information */
911 unsigned opcode_props
= alu_opcode_props
[op
].props
;
912 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
914 midgard_instruction ins
= {
916 .dest
= nir_dest_index(&instr
->dest
.dest
),
917 .dest_type
= nir_op_infos
[instr
->op
].output_type
918 | nir_dest_bit_size(instr
->dest
.dest
),
921 for (unsigned i
= nr_inputs
; i
< ARRAY_SIZE(ins
.src
); ++i
)
924 if (quirk_flipped_r24
) {
926 mir_copy_src(&ins
, instr
, 0, 1);
928 for (unsigned i
= 0; i
< nr_inputs
; ++i
)
929 mir_copy_src(&ins
, instr
, i
, quirk_flipped_r24
? 1 : i
);
932 nir_alu_src
*nirmods
[3] = { NULL
};
934 if (nr_inputs
>= 2) {
935 nirmods
[0] = &instr
->src
[0];
936 nirmods
[1] = &instr
->src
[1];
937 } else if (nr_inputs
== 1) {
938 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
944 nirmods
[2] = &instr
->src
[2];
946 /* These were lowered to a move, so apply the corresponding mod */
948 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
949 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
951 if (instr
->op
== nir_op_fneg
)
952 s
->negate
= !s
->negate
;
954 if (instr
->op
== nir_op_fabs
)
958 bool is_int
= midgard_is_integer_op(op
);
960 ins
.mask
= mask_of(nr_components
);
962 midgard_vector_alu alu
= {
964 .reg_mode
= reg_mode
,
965 .dest_override
= dest_override
,
968 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
969 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
972 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
975 ins
.mask
&= instr
->dest
.write_mask
;
977 for (unsigned m
= 0; m
< 3; ++m
) {
981 for (unsigned c
= 0; c
< NIR_MAX_VEC_COMPONENTS
; ++c
)
982 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[c
];
984 /* Replicate. TODO: remove when vec16 lands */
985 for (unsigned c
= NIR_MAX_VEC_COMPONENTS
; c
< MIR_VEC_COMPONENTS
; ++c
)
986 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[NIR_MAX_VEC_COMPONENTS
- 1];
989 if (nr_inputs
== 3) {
990 /* Conditions can't have mods */
991 assert(!nirmods
[2]->abs
);
992 assert(!nirmods
[2]->negate
);
997 /* Late fixup for emulated instructions */
999 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1000 /* Presently, our second argument is an inline #0 constant.
1001 * Switch over to an embedded 1.0 constant (that can't fit
1002 * inline, since we're 32-bit, not 16-bit like the inline
1005 ins
.has_inline_constant
= false;
1006 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1007 ins
.src_types
[1] = nir_type_float32
;
1008 ins
.has_constants
= true;
1010 if (instr
->op
== nir_op_b2f32
)
1011 ins
.constants
.f32
[0] = 1.0f
;
1013 ins
.constants
.i32
[0] = 1;
1015 for (unsigned c
= 0; c
< 16; ++c
)
1016 ins
.swizzle
[1][c
] = 0;
1017 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1018 /* Lots of instructions need a 0 plonked in */
1019 ins
.has_inline_constant
= false;
1020 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1021 ins
.src_types
[1] = nir_type_uint32
;
1022 ins
.has_constants
= true;
1023 ins
.constants
.u32
[0] = 0;
1025 for (unsigned c
= 0; c
< 16; ++c
)
1026 ins
.swizzle
[1][c
] = 0;
1027 } else if (instr
->op
== nir_op_inot
) {
1031 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1032 /* To avoid duplicating the lookup tables (probably), true LUT
1033 * instructions can only operate as if they were scalars. Lower
1034 * them here by changing the component. */
1036 unsigned orig_mask
= ins
.mask
;
1038 for (int i
= 0; i
< nr_components
; ++i
) {
1039 /* Mask the associated component, dropping the
1040 * instruction if needed */
1043 ins
.mask
&= orig_mask
;
1048 for (unsigned j
= 0; j
< MIR_VEC_COMPONENTS
; ++j
)
1049 ins
.swizzle
[0][j
] = nirmods
[0]->swizzle
[i
]; /* Pull from the correct component */
1051 emit_mir_instruction(ctx
, ins
);
1054 emit_mir_instruction(ctx
, ins
);
1061 mir_set_intr_mask(nir_instr
*instr
, midgard_instruction
*ins
, bool is_read
)
1063 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1064 unsigned nir_mask
= 0;
1068 nir_mask
= mask_of(nir_intrinsic_dest_components(intr
));
1069 dsize
= nir_dest_bit_size(intr
->dest
);
1071 nir_mask
= nir_intrinsic_write_mask(intr
);
1075 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1076 unsigned bytemask
= pan_to_bytemask(dsize
, nir_mask
);
1077 mir_set_bytemask(ins
, bytemask
);
1080 ins
->load_64
= true;
1083 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1084 * optimized) versions of UBO #0 */
1086 static midgard_instruction
*
1088 compiler_context
*ctx
,
1092 nir_src
*indirect_offset
,
1093 unsigned indirect_shift
,
1096 /* TODO: half-floats */
1098 midgard_instruction ins
= m_ld_ubo_int4(dest
, 0);
1099 ins
.constants
.u32
[0] = offset
;
1101 if (instr
->type
== nir_instr_type_intrinsic
)
1102 mir_set_intr_mask(instr
, &ins
, true);
1104 if (indirect_offset
) {
1105 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1106 ins
.src_types
[2] = nir_type_uint32
;
1107 ins
.load_store
.arg_2
= (indirect_shift
<< 5);
1109 ins
.load_store
.arg_2
= 0x1E;
1112 ins
.load_store
.arg_1
= index
;
1114 return emit_mir_instruction(ctx
, ins
);
1117 /* Globals are like UBOs if you squint. And shared memory is like globals if
1118 * you squint even harder */
1122 compiler_context
*ctx
,
1131 midgard_instruction ins
;
1134 ins
= m_ld_int4(srcdest
, 0);
1136 ins
= m_st_int4(srcdest
, 0);
1138 mir_set_offset(ctx
, &ins
, offset
, is_shared
);
1139 mir_set_intr_mask(instr
, &ins
, is_read
);
1141 emit_mir_instruction(ctx
, ins
);
1146 compiler_context
*ctx
,
1147 unsigned dest
, unsigned offset
,
1148 unsigned nr_comp
, unsigned component
,
1149 nir_src
*indirect_offset
, nir_alu_type type
, bool flat
)
1151 /* XXX: Half-floats? */
1152 /* TODO: swizzle, mask */
1154 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1155 ins
.mask
= mask_of(nr_comp
);
1157 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
)
1158 ins
.swizzle
[0][i
] = MIN2(i
+ component
, COMPONENT_W
);
1160 midgard_varying_parameter p
= {
1162 .interpolation
= midgard_interp_default
,
1167 memcpy(&u
, &p
, sizeof(p
));
1168 ins
.load_store
.varying_parameters
= u
;
1170 if (indirect_offset
) {
1171 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1172 ins
.src_types
[2] = nir_type_uint32
;
1174 ins
.load_store
.arg_2
= 0x1E;
1176 ins
.load_store
.arg_1
= 0x9E;
1178 /* Use the type appropriate load */
1182 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1185 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1187 case nir_type_float
:
1188 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1191 unreachable("Attempted to load unknown type");
1195 emit_mir_instruction(ctx
, ins
);
1200 compiler_context
*ctx
,
1201 unsigned dest
, unsigned offset
,
1202 unsigned nr_comp
, nir_alu_type t
)
1204 midgard_instruction ins
= m_ld_attr_32(dest
, offset
);
1205 ins
.load_store
.arg_1
= 0x1E;
1206 ins
.load_store
.arg_2
= 0x1E;
1207 ins
.mask
= mask_of(nr_comp
);
1209 /* Use the type appropriate load */
1213 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1216 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1218 case nir_type_float
:
1219 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1222 unreachable("Attempted to load unknown type");
1226 emit_mir_instruction(ctx
, ins
);
1230 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
,
1231 unsigned nr_components
, unsigned offset
)
1235 /* Figure out which uniform this is */
1236 int sysval
= panfrost_sysval_for_instr(instr
, &nir_dest
);
1237 void *val
= _mesa_hash_table_u64_search(ctx
->sysvals
.sysval_to_id
, sysval
);
1239 unsigned dest
= nir_dest_index(&nir_dest
);
1241 /* Sysvals are prefix uniforms */
1242 unsigned uniform
= ((uintptr_t) val
) - 1;
1244 /* Emit the read itself -- this is never indirect */
1245 midgard_instruction
*ins
=
1246 emit_ubo_read(ctx
, instr
, dest
, (uniform
* 16) + offset
, NULL
, 0, 0);
1248 ins
->mask
= mask_of(nr_components
);
1252 compute_builtin_arg(nir_op op
)
1255 case nir_intrinsic_load_work_group_id
:
1257 case nir_intrinsic_load_local_invocation_id
:
1260 unreachable("Invalid compute paramater loaded");
1265 emit_fragment_store(compiler_context
*ctx
, unsigned src
, enum midgard_rt_id rt
)
1267 assert(rt
< ARRAY_SIZE(ctx
->writeout_branch
));
1269 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
1273 emit_explicit_constant(ctx
, src
, src
);
1275 struct midgard_instruction ins
=
1276 v_branch(false, false);
1278 ins
.writeout
= true;
1280 /* Add dependencies */
1282 ins
.src_types
[0] = nir_type_uint32
;
1283 ins
.constants
.u32
[0] = rt
== MIDGARD_ZS_RT
?
1284 0xFF : (rt
- MIDGARD_COLOR_RT0
) * 0x100;
1286 /* Emit the branch */
1287 br
= emit_mir_instruction(ctx
, ins
);
1288 schedule_barrier(ctx
);
1289 ctx
->writeout_branch
[rt
] = br
;
1291 /* Push our current location = current block count - 1 = where we'll
1292 * jump to. Maybe a bit too clever for my own good */
1294 br
->branch
.target_block
= ctx
->block_count
- 1;
1298 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1300 unsigned reg
= nir_dest_index(&instr
->dest
);
1301 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1302 ins
.mask
= mask_of(3);
1303 ins
.swizzle
[0][3] = COMPONENT_X
; /* xyzx */
1304 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1305 emit_mir_instruction(ctx
, ins
);
1309 vertex_builtin_arg(nir_op op
)
1312 case nir_intrinsic_load_vertex_id
:
1313 return PAN_VERTEX_ID
;
1314 case nir_intrinsic_load_instance_id
:
1315 return PAN_INSTANCE_ID
;
1317 unreachable("Invalid vertex builtin");
1322 emit_vertex_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1324 unsigned reg
= nir_dest_index(&instr
->dest
);
1325 emit_attr_read(ctx
, reg
, vertex_builtin_arg(instr
->intrinsic
), 1, nir_type_int
);
1329 emit_control_barrier(compiler_context
*ctx
)
1331 midgard_instruction ins
= {
1332 .type
= TAG_TEXTURE_4
,
1333 .src
= { ~0, ~0, ~0, ~0 },
1335 .op
= TEXTURE_OP_BARRIER
,
1337 /* TODO: optimize */
1338 .barrier_buffer
= 1,
1343 emit_mir_instruction(ctx
, ins
);
1346 static const nir_variable
*
1347 search_var(struct exec_list
*vars
, unsigned driver_loc
)
1349 nir_foreach_variable(var
, vars
) {
1350 if (var
->data
.driver_location
== driver_loc
)
1358 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1360 unsigned offset
= 0, reg
;
1362 switch (instr
->intrinsic
) {
1363 case nir_intrinsic_discard_if
:
1364 case nir_intrinsic_discard
: {
1365 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1366 struct midgard_instruction discard
= v_branch(conditional
, false);
1367 discard
.branch
.target_type
= TARGET_DISCARD
;
1370 discard
.src
[0] = nir_src_index(ctx
, &instr
->src
[0]);
1371 discard
.src_types
[0] = nir_type_uint32
;
1374 emit_mir_instruction(ctx
, discard
);
1375 schedule_barrier(ctx
);
1380 case nir_intrinsic_load_uniform
:
1381 case nir_intrinsic_load_ubo
:
1382 case nir_intrinsic_load_global
:
1383 case nir_intrinsic_load_shared
:
1384 case nir_intrinsic_load_input
:
1385 case nir_intrinsic_load_interpolated_input
: {
1386 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1387 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1388 bool is_global
= instr
->intrinsic
== nir_intrinsic_load_global
;
1389 bool is_shared
= instr
->intrinsic
== nir_intrinsic_load_shared
;
1390 bool is_flat
= instr
->intrinsic
== nir_intrinsic_load_input
;
1391 bool is_interp
= instr
->intrinsic
== nir_intrinsic_load_interpolated_input
;
1393 /* Get the base type of the intrinsic */
1394 /* TODO: Infer type? Does it matter? */
1396 (is_ubo
|| is_global
|| is_shared
) ? nir_type_uint
:
1397 (is_interp
) ? nir_type_float
:
1398 nir_intrinsic_type(instr
);
1400 t
= nir_alu_type_get_base_type(t
);
1402 if (!(is_ubo
|| is_global
)) {
1403 offset
= nir_intrinsic_base(instr
);
1406 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1408 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1410 bool direct
= nir_src_is_const(*src_offset
);
1411 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1414 offset
+= nir_src_as_uint(*src_offset
);
1416 /* We may need to apply a fractional offset */
1417 int component
= (is_flat
|| is_interp
) ?
1418 nir_intrinsic_component(instr
) : 0;
1419 reg
= nir_dest_index(&instr
->dest
);
1421 if (is_uniform
&& !ctx
->is_blend
) {
1422 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysvals
.sysval_count
+ offset
) * 16, indirect_offset
, 4, 0);
1423 } else if (is_ubo
) {
1424 nir_src index
= instr
->src
[0];
1426 /* TODO: Is indirect block number possible? */
1427 assert(nir_src_is_const(index
));
1429 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1430 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, indirect_offset
, 0, uindex
);
1431 } else if (is_global
|| is_shared
) {
1432 emit_global(ctx
, &instr
->instr
, true, reg
, src_offset
, is_shared
);
1433 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1434 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, indirect_offset
, t
, is_flat
);
1435 } else if (ctx
->is_blend
) {
1436 /* For blend shaders, load the input color, which is
1437 * preloaded to r0 */
1439 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), reg
);
1440 emit_mir_instruction(ctx
, move
);
1441 schedule_barrier(ctx
);
1442 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1443 emit_attr_read(ctx
, reg
, offset
, nr_comp
, t
);
1445 DBG("Unknown load\n");
1452 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1453 case nir_intrinsic_load_barycentric_pixel
:
1454 case nir_intrinsic_load_barycentric_centroid
:
1457 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1459 case nir_intrinsic_load_raw_output_pan
:
1460 case nir_intrinsic_load_output_u8_as_fp16_pan
:
1461 reg
= nir_dest_index(&instr
->dest
);
1462 assert(ctx
->is_blend
);
1464 /* T720 and below use different blend opcodes with slightly
1465 * different semantics than T760 and up */
1467 midgard_instruction ld
= m_ld_color_buffer_32u(reg
, 0);
1468 bool old_blend
= ctx
->quirks
& MIDGARD_OLD_BLEND
;
1470 if (instr
->intrinsic
== nir_intrinsic_load_output_u8_as_fp16_pan
) {
1471 ld
.load_store
.op
= old_blend
?
1472 midgard_op_ld_color_buffer_u8_as_fp16_old
:
1473 midgard_op_ld_color_buffer_u8_as_fp16
;
1476 ld
.load_store
.address
= 1;
1477 ld
.load_store
.arg_2
= 0x1E;
1480 for (unsigned c
= 2; c
< 16; ++c
)
1481 ld
.swizzle
[0][c
] = 0;
1484 emit_mir_instruction(ctx
, ld
);
1487 case nir_intrinsic_load_blend_const_color_rgba
: {
1488 assert(ctx
->is_blend
);
1489 reg
= nir_dest_index(&instr
->dest
);
1491 /* Blend constants are embedded directly in the shader and
1492 * patched in, so we use some magic routing */
1494 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), reg
);
1495 ins
.has_constants
= true;
1496 ins
.has_blend_constant
= true;
1497 emit_mir_instruction(ctx
, ins
);
1501 case nir_intrinsic_store_zs_output_pan
: {
1502 assert(ctx
->stage
== MESA_SHADER_FRAGMENT
);
1503 emit_fragment_store(ctx
, nir_src_index(ctx
, &instr
->src
[0]),
1506 midgard_instruction
*br
= ctx
->writeout_branch
[MIDGARD_ZS_RT
];
1508 if (!nir_intrinsic_component(instr
))
1509 br
->writeout_depth
= true;
1510 if (nir_intrinsic_component(instr
) ||
1511 instr
->num_components
)
1512 br
->writeout_stencil
= true;
1513 assert(br
->writeout_depth
| br
->writeout_stencil
);
1517 case nir_intrinsic_store_output
:
1518 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1520 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1522 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1524 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1525 const nir_variable
*var
;
1526 enum midgard_rt_id rt
;
1528 var
= search_var(&ctx
->nir
->outputs
,
1529 nir_intrinsic_base(instr
));
1531 if (var
->data
.location
== FRAG_RESULT_COLOR
)
1532 rt
= MIDGARD_COLOR_RT0
;
1533 else if (var
->data
.location
>= FRAG_RESULT_DATA0
)
1534 rt
= MIDGARD_COLOR_RT0
+ var
->data
.location
-
1539 emit_fragment_store(ctx
, reg
, rt
);
1540 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1541 /* We should have been vectorized, though we don't
1542 * currently check that st_vary is emitted only once
1543 * per slot (this is relevant, since there's not a mask
1544 * parameter available on the store [set to 0 by the
1545 * blob]). We do respect the component by adjusting the
1546 * swizzle. If this is a constant source, we'll need to
1547 * emit that explicitly. */
1549 emit_explicit_constant(ctx
, reg
, reg
);
1551 unsigned dst_component
= nir_intrinsic_component(instr
);
1552 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1554 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1555 st
.load_store
.arg_1
= 0x9E;
1556 st
.load_store
.arg_2
= 0x1E;
1558 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr
))) {
1561 st
.load_store
.op
= midgard_op_st_vary_32u
;
1564 st
.load_store
.op
= midgard_op_st_vary_32i
;
1566 case nir_type_float
:
1567 st
.load_store
.op
= midgard_op_st_vary_32
;
1570 unreachable("Attempted to store unknown type");
1574 /* nir_intrinsic_component(store_intr) encodes the
1575 * destination component start. Source component offset
1576 * adjustment is taken care of in
1577 * install_registers_instr(), when offset_swizzle() is
1580 unsigned src_component
= COMPONENT_X
;
1582 assert(nr_comp
> 0);
1583 for (unsigned i
= 0; i
< ARRAY_SIZE(st
.swizzle
); ++i
) {
1584 st
.swizzle
[0][i
] = src_component
;
1585 if (i
>= dst_component
&& i
< dst_component
+ nr_comp
- 1)
1589 emit_mir_instruction(ctx
, st
);
1591 DBG("Unknown store\n");
1597 /* Special case of store_output for lowered blend shaders */
1598 case nir_intrinsic_store_raw_output_pan
:
1599 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1600 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1602 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1603 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1604 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1607 * imov r0.xyzw, r0.xxxx
1610 unsigned expanded
= make_compiler_temp(ctx
);
1612 midgard_instruction splatter
= v_mov(reg
, expanded
);
1614 for (unsigned c
= 0; c
< 16; ++c
)
1615 splatter
.swizzle
[1][c
] = 0;
1617 emit_mir_instruction(ctx
, splatter
);
1618 emit_fragment_store(ctx
, expanded
, ctx
->blend_rt
);
1620 emit_fragment_store(ctx
, reg
, ctx
->blend_rt
);
1624 case nir_intrinsic_store_global
:
1625 case nir_intrinsic_store_shared
:
1626 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1627 emit_explicit_constant(ctx
, reg
, reg
);
1629 emit_global(ctx
, &instr
->instr
, false, reg
, &instr
->src
[1], instr
->intrinsic
== nir_intrinsic_store_shared
);
1632 case nir_intrinsic_load_ssbo_address
:
1633 emit_sysval_read(ctx
, &instr
->instr
, 1, 0);
1636 case nir_intrinsic_get_buffer_size
:
1637 emit_sysval_read(ctx
, &instr
->instr
, 1, 8);
1640 case nir_intrinsic_load_viewport_scale
:
1641 case nir_intrinsic_load_viewport_offset
:
1642 case nir_intrinsic_load_num_work_groups
:
1643 case nir_intrinsic_load_sampler_lod_parameters_pan
:
1644 emit_sysval_read(ctx
, &instr
->instr
, 3, 0);
1647 case nir_intrinsic_load_work_group_id
:
1648 case nir_intrinsic_load_local_invocation_id
:
1649 emit_compute_builtin(ctx
, instr
);
1652 case nir_intrinsic_load_vertex_id
:
1653 case nir_intrinsic_load_instance_id
:
1654 emit_vertex_builtin(ctx
, instr
);
1657 case nir_intrinsic_memory_barrier_buffer
:
1658 case nir_intrinsic_memory_barrier_shared
:
1661 case nir_intrinsic_control_barrier
:
1662 schedule_barrier(ctx
);
1663 emit_control_barrier(ctx
);
1664 schedule_barrier(ctx
);
1668 fprintf(stderr
, "Unhandled intrinsic %s\n", nir_intrinsic_infos
[instr
->intrinsic
].name
);
1675 midgard_tex_format(enum glsl_sampler_dim dim
)
1678 case GLSL_SAMPLER_DIM_1D
:
1679 case GLSL_SAMPLER_DIM_BUF
:
1682 case GLSL_SAMPLER_DIM_2D
:
1683 case GLSL_SAMPLER_DIM_EXTERNAL
:
1684 case GLSL_SAMPLER_DIM_RECT
:
1687 case GLSL_SAMPLER_DIM_3D
:
1690 case GLSL_SAMPLER_DIM_CUBE
:
1691 return MALI_TEX_CUBE
;
1694 DBG("Unknown sampler dim type\n");
1700 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1704 pan_attach_constant_bias(
1705 compiler_context
*ctx
,
1707 midgard_texture_word
*word
)
1709 /* To attach as constant, it has to *be* constant */
1711 if (!nir_src_is_const(lod
))
1714 float f
= nir_src_as_float(lod
);
1716 /* Break into fixed-point */
1718 float lod_frac
= f
- lod_int
;
1720 /* Carry over negative fractions */
1721 if (lod_frac
< 0.0) {
1727 word
->bias
= float_to_ubyte(lod_frac
);
1728 word
->bias_int
= lod_int
;
1734 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1735 unsigned midgard_texop
)
1738 //assert (!instr->sampler);
1740 int texture_index
= instr
->texture_index
;
1741 int sampler_index
= texture_index
;
1743 nir_alu_type dest_base
= nir_alu_type_get_base_type(instr
->dest_type
);
1744 nir_alu_type dest_type
= dest_base
| nir_dest_bit_size(instr
->dest
);
1746 midgard_instruction ins
= {
1747 .type
= TAG_TEXTURE_4
,
1749 .dest
= nir_dest_index(&instr
->dest
),
1750 .src
= { ~0, ~0, ~0, ~0 },
1751 .dest_type
= dest_type
,
1752 .swizzle
= SWIZZLE_IDENTITY_4
,
1754 .op
= midgard_texop
,
1755 .format
= midgard_tex_format(instr
->sampler_dim
),
1756 .texture_handle
= texture_index
,
1757 .sampler_handle
= sampler_index
,
1758 .shadow
= instr
->is_shadow
,
1762 if (instr
->is_shadow
&& !instr
->is_new_style_shadow
)
1763 for (int i
= 0; i
< 4; ++i
)
1764 ins
.swizzle
[0][i
] = COMPONENT_X
;
1766 /* We may need a temporary for the coordinate */
1768 bool needs_temp_coord
=
1769 (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) ||
1770 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) ||
1773 unsigned coords
= needs_temp_coord
? make_compiler_temp_reg(ctx
) : 0;
1775 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1776 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1777 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
1778 unsigned sz
= nir_src_bit_size(instr
->src
[i
].src
);
1779 nir_alu_type T
= nir_tex_instr_src_type(instr
, i
) | sz
;
1781 switch (instr
->src
[i
].src_type
) {
1782 case nir_tex_src_coord
: {
1783 emit_explicit_constant(ctx
, index
, index
);
1785 unsigned coord_mask
= mask_of(instr
->coord_components
);
1787 bool flip_zw
= (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) && (coord_mask
& (1 << COMPONENT_Z
));
1790 coord_mask
^= ((1 << COMPONENT_Z
) | (1 << COMPONENT_W
));
1792 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1793 /* texelFetch is undefined on samplerCube */
1794 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1796 /* For cubemaps, we use a special ld/st op to
1797 * select the face and copy the xy into the
1798 * texture register */
1800 midgard_instruction ld
= m_ld_cubemap_coords(coords
, 0);
1802 ld
.src_types
[1] = T
;
1803 ld
.mask
= 0x3; /* xy */
1804 ld
.load_store
.arg_1
= 0x20;
1805 ld
.swizzle
[1][3] = COMPONENT_X
;
1806 emit_mir_instruction(ctx
, ld
);
1809 ins
.swizzle
[1][2] = instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
1810 ins
.swizzle
[1][3] = COMPONENT_X
;
1811 } else if (needs_temp_coord
) {
1812 /* mov coord_temp, coords */
1813 midgard_instruction mov
= v_mov(index
, coords
);
1814 mov
.mask
= coord_mask
;
1817 mov
.swizzle
[1][COMPONENT_W
] = COMPONENT_Z
;
1819 emit_mir_instruction(ctx
, mov
);
1824 ins
.src
[1] = coords
;
1825 ins
.src_types
[1] = T
;
1827 /* Texelfetch coordinates uses all four elements
1828 * (xyz/index) regardless of texture dimensionality,
1829 * which means it's necessary to zero the unused
1830 * components to keep everything happy */
1832 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1833 /* mov index.zw, #0, or generalized */
1834 midgard_instruction mov
=
1835 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), coords
);
1836 mov
.has_constants
= true;
1837 mov
.mask
= coord_mask
^ 0xF;
1838 emit_mir_instruction(ctx
, mov
);
1841 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1842 /* Array component in w but NIR wants it in z,
1843 * but if we have a temp coord we already fixed
1846 if (nr_components
== 3) {
1847 ins
.swizzle
[1][2] = COMPONENT_Z
;
1848 ins
.swizzle
[1][3] = needs_temp_coord
? COMPONENT_W
: COMPONENT_Z
;
1849 } else if (nr_components
== 2) {
1851 instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
1852 ins
.swizzle
[1][3] = COMPONENT_X
;
1854 unreachable("Invalid texture 2D components");
1857 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1859 ins
.swizzle
[1][2] = COMPONENT_Z
;
1860 ins
.swizzle
[1][3] = COMPONENT_W
;
1866 case nir_tex_src_bias
:
1867 case nir_tex_src_lod
: {
1868 /* Try as a constant if we can */
1870 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1871 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1874 ins
.texture
.lod_register
= true;
1876 ins
.src_types
[2] = T
;
1878 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
1879 ins
.swizzle
[2][c
] = COMPONENT_X
;
1881 emit_explicit_constant(ctx
, index
, index
);
1886 case nir_tex_src_offset
: {
1887 ins
.texture
.offset_register
= true;
1889 ins
.src_types
[3] = T
;
1891 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
1892 ins
.swizzle
[3][c
] = (c
> COMPONENT_Z
) ? 0 : c
;
1894 emit_explicit_constant(ctx
, index
, index
);
1898 case nir_tex_src_comparator
: {
1899 unsigned comp
= COMPONENT_Z
;
1901 /* mov coord_temp.foo, coords */
1902 midgard_instruction mov
= v_mov(index
, coords
);
1903 mov
.mask
= 1 << comp
;
1905 for (unsigned i
= 0; i
< MIR_VEC_COMPONENTS
; ++i
)
1906 mov
.swizzle
[1][i
] = COMPONENT_X
;
1908 emit_mir_instruction(ctx
, mov
);
1913 fprintf(stderr
, "Unknown texture source type: %d\n", instr
->src
[i
].src_type
);
1919 emit_mir_instruction(ctx
, ins
);
1921 /* Used for .cont and .last hinting */
1922 ctx
->texture_op_count
++;
1926 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1928 switch (instr
->op
) {
1931 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1934 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1937 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1940 emit_sysval_read(ctx
, &instr
->instr
, 4, 0);
1943 fprintf(stderr
, "Unhandled texture op: %d\n", instr
->op
);
1950 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1952 switch (instr
->type
) {
1953 case nir_jump_break
: {
1954 /* Emit a branch out of the loop */
1955 struct midgard_instruction br
= v_branch(false, false);
1956 br
.branch
.target_type
= TARGET_BREAK
;
1957 br
.branch
.target_break
= ctx
->current_loop_depth
;
1958 emit_mir_instruction(ctx
, br
);
1963 DBG("Unknown jump type %d\n", instr
->type
);
1969 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1971 switch (instr
->type
) {
1972 case nir_instr_type_load_const
:
1973 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1976 case nir_instr_type_intrinsic
:
1977 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1980 case nir_instr_type_alu
:
1981 emit_alu(ctx
, nir_instr_as_alu(instr
));
1984 case nir_instr_type_tex
:
1985 emit_tex(ctx
, nir_instr_as_tex(instr
));
1988 case nir_instr_type_jump
:
1989 emit_jump(ctx
, nir_instr_as_jump(instr
));
1992 case nir_instr_type_ssa_undef
:
1997 DBG("Unhandled instruction type\n");
2003 /* ALU instructions can inline or embed constants, which decreases register
2004 * pressure and saves space. */
2006 #define CONDITIONAL_ATTACH(idx) { \
2007 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2010 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2011 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2016 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
2018 mir_foreach_instr_in_block(block
, alu
) {
2019 /* Other instructions cannot inline constants */
2020 if (alu
->type
!= TAG_ALU_4
) continue;
2021 if (alu
->compact_branch
) continue;
2023 /* If there is already a constant here, we can do nothing */
2024 if (alu
->has_constants
) continue;
2026 CONDITIONAL_ATTACH(0);
2028 if (!alu
->has_constants
) {
2029 CONDITIONAL_ATTACH(1)
2030 } else if (!alu
->inline_constant
) {
2031 /* Corner case: _two_ vec4 constants, for instance with a
2032 * csel. For this case, we can only use a constant
2033 * register for one, we'll have to emit a move for the
2036 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
2037 unsigned scratch
= make_compiler_temp(ctx
);
2040 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), scratch
);
2041 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
2043 /* Set the source */
2044 alu
->src
[1] = scratch
;
2046 /* Inject us -before- the last instruction which set r31 */
2047 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
2053 /* Midgard supports two types of constants, embedded constants (128-bit) and
2054 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2055 * constants can be demoted to inline constants, for space savings and
2056 * sometimes a performance boost */
2059 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
2061 mir_foreach_instr_in_block(block
, ins
) {
2062 if (!ins
->has_constants
) continue;
2063 if (ins
->has_inline_constant
) continue;
2065 /* Blend constants must not be inlined by definition */
2066 if (ins
->has_blend_constant
) continue;
2068 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2069 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
2070 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
2072 if (!(is_16
|| is_32
))
2075 /* src1 cannot be an inline constant due to encoding
2076 * restrictions. So, if possible we try to flip the arguments
2079 int op
= ins
->alu
.op
;
2081 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
) &&
2082 alu_opcode_props
[op
].props
& OP_COMMUTES
) {
2086 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2087 /* Extract the source information */
2089 midgard_vector_alu_src
*src
;
2090 int q
= ins
->alu
.src2
;
2091 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2094 /* Component is from the swizzle. Take a nonzero component */
2096 unsigned first_comp
= ffs(ins
->mask
) - 1;
2097 unsigned component
= ins
->swizzle
[1][first_comp
];
2099 /* Scale constant appropriately, if we can legally */
2100 uint16_t scaled_constant
= 0;
2103 scaled_constant
= ins
->constants
.u16
[component
];
2104 } else if (midgard_is_integer_op(op
)) {
2105 scaled_constant
= ins
->constants
.u32
[component
];
2107 /* Constant overflow after resize */
2108 if (scaled_constant
!= ins
->constants
.u32
[component
])
2111 float original
= ins
->constants
.f32
[component
];
2112 scaled_constant
= _mesa_float_to_half(original
);
2114 /* Check for loss of precision. If this is
2115 * mediump, we don't care, but for a highp
2116 * shader, we need to pay attention. NIR
2117 * doesn't yet tell us which mode we're in!
2118 * Practically this prevents most constants
2119 * from being inlined, sadly. */
2121 float fp32
= _mesa_half_to_float(scaled_constant
);
2123 if (fp32
!= original
)
2127 /* We don't know how to handle these with a constant */
2129 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
2130 DBG("Bailing inline constant...\n");
2134 /* Make sure that the constant is not itself a vector
2135 * by checking if all accessed values are the same. */
2137 const midgard_constants
*cons
= &ins
->constants
;
2138 uint32_t value
= is_16
? cons
->u16
[component
] : cons
->u32
[component
];
2140 bool is_vector
= false;
2141 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2143 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
2144 /* We only care if this component is actually used */
2145 if (!(mask
& (1 << c
)))
2148 uint32_t test
= is_16
?
2149 cons
->u16
[ins
->swizzle
[1][c
]] :
2150 cons
->u32
[ins
->swizzle
[1][c
]];
2152 if (test
!= value
) {
2161 /* Get rid of the embedded constant */
2162 ins
->has_constants
= false;
2164 ins
->has_inline_constant
= true;
2165 ins
->inline_constant
= scaled_constant
;
2170 /* Dead code elimination for branches at the end of a block - only one branch
2171 * per block is legal semantically */
2174 midgard_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2176 bool branched
= false;
2178 mir_foreach_instr_in_block_safe(block
, ins
) {
2179 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2182 mir_remove_instruction(ins
);
2188 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2189 * the move can be propagated away entirely */
2192 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2195 if (comp
== midgard_outmod_none
)
2198 if (*outmod
== midgard_outmod_none
) {
2203 /* TODO: Compose rules */
2208 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2210 bool progress
= false;
2212 mir_foreach_instr_in_block_safe(block
, ins
) {
2213 if (ins
->type
!= TAG_ALU_4
) continue;
2214 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2215 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2217 /* TODO: Registers? */
2218 unsigned src
= ins
->src
[1];
2219 if (src
& PAN_IS_REG
) continue;
2221 /* There might be a source modifier, too */
2222 if (mir_nontrivial_source2_mod(ins
)) continue;
2224 /* Backpropagate the modifier */
2225 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2226 if (v
->type
!= TAG_ALU_4
) continue;
2227 if (v
->dest
!= src
) continue;
2229 /* Can we even take a float outmod? */
2230 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2232 midgard_outmod_float temp
= v
->alu
.outmod
;
2233 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2235 /* Throw in the towel.. */
2236 if (!progress
) break;
2238 /* Otherwise, transfer the modifier */
2239 v
->alu
.outmod
= temp
;
2240 ins
->alu
.outmod
= midgard_outmod_none
;
2250 emit_fragment_epilogue(compiler_context
*ctx
, unsigned rt
)
2252 /* Loop to ourselves */
2253 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2254 struct midgard_instruction ins
= v_branch(false, false);
2255 ins
.writeout
= true;
2256 ins
.writeout_depth
= br
->writeout_depth
;
2257 ins
.writeout_stencil
= br
->writeout_stencil
;
2258 ins
.branch
.target_block
= ctx
->block_count
- 1;
2259 ins
.constants
.u32
[0] = br
->constants
.u32
[0];
2260 emit_mir_instruction(ctx
, ins
);
2262 ctx
->current_block
->epilogue
= true;
2263 schedule_barrier(ctx
);
2264 return ins
.branch
.target_block
;
2267 static midgard_block
*
2268 emit_block(compiler_context
*ctx
, nir_block
*block
)
2270 midgard_block
*this_block
= ctx
->after_block
;
2271 ctx
->after_block
= NULL
;
2274 this_block
= create_empty_block(ctx
);
2276 list_addtail(&this_block
->base
.link
, &ctx
->blocks
);
2278 this_block
->scheduled
= false;
2281 /* Set up current block */
2282 list_inithead(&this_block
->base
.instructions
);
2283 ctx
->current_block
= this_block
;
2285 nir_foreach_instr(instr
, block
) {
2286 emit_instr(ctx
, instr
);
2287 ++ctx
->instruction_count
;
2293 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2296 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2298 midgard_block
*before_block
= ctx
->current_block
;
2300 /* Speculatively emit the branch, but we can't fill it in until later */
2301 EMIT(branch
, true, true);
2302 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2303 then_branch
->src
[0] = nir_src_index(ctx
, &nif
->condition
);
2304 then_branch
->src_types
[0] = nir_type_uint32
;
2306 /* Emit the two subblocks. */
2307 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2308 midgard_block
*end_then_block
= ctx
->current_block
;
2310 /* Emit a jump from the end of the then block to the end of the else */
2311 EMIT(branch
, false, false);
2312 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2314 /* Emit second block, and check if it's empty */
2316 int else_idx
= ctx
->block_count
;
2317 int count_in
= ctx
->instruction_count
;
2318 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2319 midgard_block
*end_else_block
= ctx
->current_block
;
2320 int after_else_idx
= ctx
->block_count
;
2322 /* Now that we have the subblocks emitted, fix up the branches */
2327 if (ctx
->instruction_count
== count_in
) {
2328 /* The else block is empty, so don't emit an exit jump */
2329 mir_remove_instruction(then_exit
);
2330 then_branch
->branch
.target_block
= after_else_idx
;
2332 then_branch
->branch
.target_block
= else_idx
;
2333 then_exit
->branch
.target_block
= after_else_idx
;
2336 /* Wire up the successors */
2338 ctx
->after_block
= create_empty_block(ctx
);
2340 pan_block_add_successor(&before_block
->base
, &then_block
->base
);
2341 pan_block_add_successor(&before_block
->base
, &else_block
->base
);
2343 pan_block_add_successor(&end_then_block
->base
, &ctx
->after_block
->base
);
2344 pan_block_add_successor(&end_else_block
->base
, &ctx
->after_block
->base
);
2348 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2350 /* Remember where we are */
2351 midgard_block
*start_block
= ctx
->current_block
;
2353 /* Allocate a loop number, growing the current inner loop depth */
2354 int loop_idx
= ++ctx
->current_loop_depth
;
2356 /* Get index from before the body so we can loop back later */
2357 int start_idx
= ctx
->block_count
;
2359 /* Emit the body itself */
2360 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2362 /* Branch back to loop back */
2363 struct midgard_instruction br_back
= v_branch(false, false);
2364 br_back
.branch
.target_block
= start_idx
;
2365 emit_mir_instruction(ctx
, br_back
);
2367 /* Mark down that branch in the graph. */
2368 pan_block_add_successor(&start_block
->base
, &loop_block
->base
);
2369 pan_block_add_successor(&ctx
->current_block
->base
, &loop_block
->base
);
2371 /* Find the index of the block about to follow us (note: we don't add
2372 * one; blocks are 0-indexed so we get a fencepost problem) */
2373 int break_block_idx
= ctx
->block_count
;
2375 /* Fix up the break statements we emitted to point to the right place,
2376 * now that we can allocate a block number for them */
2377 ctx
->after_block
= create_empty_block(ctx
);
2379 mir_foreach_block_from(ctx
, start_block
, _block
) {
2380 mir_foreach_instr_in_block(((midgard_block
*) _block
), ins
) {
2381 if (ins
->type
!= TAG_ALU_4
) continue;
2382 if (!ins
->compact_branch
) continue;
2384 /* We found a branch -- check the type to see if we need to do anything */
2385 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2387 /* It's a break! Check if it's our break */
2388 if (ins
->branch
.target_break
!= loop_idx
) continue;
2390 /* Okay, cool, we're breaking out of this loop.
2391 * Rewrite from a break to a goto */
2393 ins
->branch
.target_type
= TARGET_GOTO
;
2394 ins
->branch
.target_block
= break_block_idx
;
2396 pan_block_add_successor(_block
, &ctx
->after_block
->base
);
2400 /* Now that we've finished emitting the loop, free up the depth again
2401 * so we play nice with recursion amid nested loops */
2402 --ctx
->current_loop_depth
;
2404 /* Dump loop stats */
2408 static midgard_block
*
2409 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2411 midgard_block
*start_block
= NULL
;
2413 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2414 switch (node
->type
) {
2415 case nir_cf_node_block
: {
2416 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2419 start_block
= block
;
2424 case nir_cf_node_if
:
2425 emit_if(ctx
, nir_cf_node_as_if(node
));
2428 case nir_cf_node_loop
:
2429 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2432 case nir_cf_node_function
:
2441 /* Due to lookahead, we need to report the first tag executed in the command
2442 * stream and in branch targets. An initial block might be empty, so iterate
2443 * until we find one that 'works' */
2446 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2448 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2450 mir_foreach_block_from(ctx
, initial_block
, _v
) {
2451 midgard_block
*v
= (midgard_block
*) _v
;
2452 if (v
->quadword_count
) {
2453 midgard_bundle
*initial_bundle
=
2454 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2456 return initial_bundle
->tag
;
2460 /* Default to a tag 1 which will break from the shader, in case we jump
2461 * to the exit block (i.e. `return` in a compute shader) */
2466 /* For each fragment writeout instruction, generate a writeout loop to
2467 * associate with it */
2470 mir_add_writeout_loops(compiler_context
*ctx
)
2472 for (unsigned rt
= 0; rt
< ARRAY_SIZE(ctx
->writeout_branch
); ++rt
) {
2473 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2476 unsigned popped
= br
->branch
.target_block
;
2477 pan_block_add_successor(&(mir_get_block(ctx
, popped
- 1)->base
), &ctx
->current_block
->base
);
2478 br
->branch
.target_block
= emit_fragment_epilogue(ctx
, rt
);
2479 br
->branch
.target_type
= TARGET_GOTO
;
2481 /* If we have more RTs, we'll need to restore back after our
2482 * loop terminates */
2484 if ((rt
+ 1) < ARRAY_SIZE(ctx
->writeout_branch
) && ctx
->writeout_branch
[rt
+ 1]) {
2485 midgard_instruction uncond
= v_branch(false, false);
2486 uncond
.branch
.target_block
= popped
;
2487 uncond
.branch
.target_type
= TARGET_GOTO
;
2488 emit_mir_instruction(ctx
, uncond
);
2489 pan_block_add_successor(&ctx
->current_block
->base
, &(mir_get_block(ctx
, popped
)->base
));
2490 schedule_barrier(ctx
);
2492 /* We're last, so we can terminate here */
2493 br
->last_writeout
= true;
2499 midgard_compile_shader_nir(nir_shader
*nir
, panfrost_program
*program
, bool is_blend
, unsigned blend_rt
, unsigned gpu_id
, bool shaderdb
)
2501 struct util_dynarray
*compiled
= &program
->compiled
;
2503 midgard_debug
= debug_get_option_midgard_debug();
2505 /* TODO: Bound against what? */
2506 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2509 ctx
->stage
= nir
->info
.stage
;
2510 ctx
->is_blend
= is_blend
;
2511 ctx
->alpha_ref
= program
->alpha_ref
;
2512 ctx
->blend_rt
= MIDGARD_COLOR_RT0
+ blend_rt
;
2513 ctx
->quirks
= midgard_get_quirks(gpu_id
);
2515 /* Start off with a safe cutoff, allowing usage of all 16 work
2516 * registers. Later, we'll promote uniform reads to uniform registers
2517 * if we determine it is beneficial to do so */
2518 ctx
->uniform_cutoff
= 8;
2520 /* Initialize at a global (not block) level hash tables */
2522 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2523 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2525 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2526 * (so we don't accidentally duplicate the epilogue since mesa/st has
2527 * messed with our I/O quite a bit already) */
2529 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2531 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2532 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2533 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2536 NIR_PASS_V(nir
, nir_lower_var_copies
);
2537 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2538 NIR_PASS_V(nir
, nir_split_var_copies
);
2539 NIR_PASS_V(nir
, nir_lower_var_copies
);
2540 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2541 NIR_PASS_V(nir
, nir_lower_var_copies
);
2542 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2544 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2545 NIR_PASS_V(nir
, nir_lower_ssbo
);
2546 NIR_PASS_V(nir
, midgard_nir_lower_zs_store
);
2548 /* Optimisation passes */
2550 optimise_nir(nir
, ctx
->quirks
);
2552 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2553 nir_print_shader(nir
, stdout
);
2556 /* Assign sysvals and counts, now that we're sure
2557 * (post-optimisation) */
2559 panfrost_nir_assign_sysvals(&ctx
->sysvals
, nir
);
2560 program
->sysval_count
= ctx
->sysvals
.sysval_count
;
2561 memcpy(program
->sysvals
, ctx
->sysvals
.sysvals
, sizeof(ctx
->sysvals
.sysvals
[0]) * ctx
->sysvals
.sysval_count
);
2563 nir_foreach_function(func
, nir
) {
2567 list_inithead(&ctx
->blocks
);
2568 ctx
->block_count
= 0;
2571 emit_cf_list(ctx
, &func
->impl
->body
);
2572 break; /* TODO: Multi-function shaders */
2575 util_dynarray_init(compiled
, NULL
);
2577 /* Per-block lowering before opts */
2579 mir_foreach_block(ctx
, _block
) {
2580 midgard_block
*block
= (midgard_block
*) _block
;
2581 inline_alu_constants(ctx
, block
);
2582 midgard_opt_promote_fmov(ctx
, block
);
2583 embedded_to_inline_constant(ctx
, block
);
2585 /* MIR-level optimizations */
2587 bool progress
= false;
2592 mir_foreach_block(ctx
, _block
) {
2593 midgard_block
*block
= (midgard_block
*) _block
;
2594 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2595 progress
|= midgard_opt_copy_prop(ctx
, block
);
2596 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2597 progress
|= midgard_opt_combine_projection(ctx
, block
);
2598 progress
|= midgard_opt_varying_projection(ctx
, block
);
2599 progress
|= midgard_opt_not_propagate(ctx
, block
);
2600 progress
|= midgard_opt_fuse_src_invert(ctx
, block
);
2601 progress
|= midgard_opt_fuse_dest_invert(ctx
, block
);
2602 progress
|= midgard_opt_csel_invert(ctx
, block
);
2603 progress
|= midgard_opt_drop_cmp_invert(ctx
, block
);
2604 progress
|= midgard_opt_invert_branch(ctx
, block
);
2608 mir_foreach_block(ctx
, _block
) {
2609 midgard_block
*block
= (midgard_block
*) _block
;
2610 midgard_lower_invert(ctx
, block
);
2611 midgard_lower_derivatives(ctx
, block
);
2614 /* Nested control-flow can result in dead branches at the end of the
2615 * block. This messes with our analysis and is just dead code, so cull
2617 mir_foreach_block(ctx
, _block
) {
2618 midgard_block
*block
= (midgard_block
*) _block
;
2619 midgard_cull_dead_branch(ctx
, block
);
2622 /* Ensure we were lowered */
2623 mir_foreach_instr_global(ctx
, ins
) {
2624 assert(!ins
->invert
);
2627 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2628 mir_add_writeout_loops(ctx
);
2631 midgard_schedule_program(ctx
);
2634 /* Now that all the bundles are scheduled and we can calculate block
2635 * sizes, emit actual branch instructions rather than placeholders */
2637 int br_block_idx
= 0;
2639 mir_foreach_block(ctx
, _block
) {
2640 midgard_block
*block
= (midgard_block
*) _block
;
2641 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2642 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2643 midgard_instruction
*ins
= bundle
->instructions
[c
];
2645 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2647 /* Parse some basic branch info */
2648 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2649 bool is_conditional
= ins
->branch
.conditional
;
2650 bool is_inverted
= ins
->branch
.invert_conditional
;
2651 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2652 bool is_writeout
= ins
->writeout
;
2654 /* Determine the block we're jumping to */
2655 int target_number
= ins
->branch
.target_block
;
2657 /* Report the destination tag */
2658 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2660 /* Count up the number of quadwords we're
2661 * jumping over = number of quadwords until
2662 * (br_block_idx, target_number) */
2664 int quadword_offset
= 0;
2668 } else if (target_number
> br_block_idx
) {
2671 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2672 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2675 quadword_offset
+= blk
->quadword_count
;
2678 /* Jump backwards */
2680 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2681 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2684 quadword_offset
-= blk
->quadword_count
;
2688 /* Unconditional extended branches (far jumps)
2689 * have issues, so we always use a conditional
2690 * branch, setting the condition to always for
2691 * unconditional. For compact unconditional
2692 * branches, cond isn't used so it doesn't
2693 * matter what we pick. */
2695 midgard_condition cond
=
2696 !is_conditional
? midgard_condition_always
:
2697 is_inverted
? midgard_condition_false
:
2698 midgard_condition_true
;
2700 midgard_jmp_writeout_op op
=
2701 is_discard
? midgard_jmp_writeout_op_discard
:
2702 is_writeout
? midgard_jmp_writeout_op_writeout
:
2703 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2704 midgard_jmp_writeout_op_branch_cond
;
2707 midgard_branch_extended branch
=
2708 midgard_create_branch_extended(
2713 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2714 } else if (is_conditional
|| is_discard
) {
2715 midgard_branch_cond branch
= {
2717 .dest_tag
= dest_tag
,
2718 .offset
= quadword_offset
,
2722 assert(branch
.offset
== quadword_offset
);
2724 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2726 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2728 midgard_branch_uncond branch
= {
2730 .dest_tag
= dest_tag
,
2731 .offset
= quadword_offset
,
2735 assert(branch
.offset
== quadword_offset
);
2737 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2745 /* Emit flat binary from the instruction arrays. Iterate each block in
2746 * sequence. Save instruction boundaries such that lookahead tags can
2747 * be assigned easily */
2749 /* Cache _all_ bundles in source order for lookahead across failed branches */
2751 int bundle_count
= 0;
2752 mir_foreach_block(ctx
, _block
) {
2753 midgard_block
*block
= (midgard_block
*) _block
;
2754 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2756 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2758 mir_foreach_block(ctx
, _block
) {
2759 midgard_block
*block
= (midgard_block
*) _block
;
2760 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2761 source_order_bundles
[bundle_idx
++] = bundle
;
2765 int current_bundle
= 0;
2767 /* Midgard prefetches instruction types, so during emission we
2768 * need to lookahead. Unless this is the last instruction, in
2769 * which we return 1. */
2771 mir_foreach_block(ctx
, _block
) {
2772 midgard_block
*block
= (midgard_block
*) _block
;
2773 mir_foreach_bundle_in_block(block
, bundle
) {
2776 if (!bundle
->last_writeout
&& (current_bundle
+ 1 < bundle_count
))
2777 lookahead
= source_order_bundles
[current_bundle
+ 1]->tag
;
2779 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2783 /* TODO: Free deeper */
2784 //util_dynarray_fini(&block->instructions);
2787 free(source_order_bundles
);
2789 /* Report the very first tag executed */
2790 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2792 /* Deal with off-by-one related to the fencepost problem */
2793 program
->work_register_count
= ctx
->work_registers
+ 1;
2794 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2796 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2797 program
->tls_size
= ctx
->tls_size
;
2799 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2800 disassemble_midgard(stdout
, program
->compiled
.data
, program
->compiled
.size
, gpu_id
, ctx
->stage
);
2802 if (midgard_debug
& MIDGARD_DBG_SHADERDB
|| shaderdb
) {
2803 unsigned nr_bundles
= 0, nr_ins
= 0;
2805 /* Count instructions and bundles */
2807 mir_foreach_block(ctx
, _block
) {
2808 midgard_block
*block
= (midgard_block
*) _block
;
2809 nr_bundles
+= util_dynarray_num_elements(
2810 &block
->bundles
, midgard_bundle
);
2812 mir_foreach_bundle_in_block(block
, bun
)
2813 nr_ins
+= bun
->instruction_count
;
2816 /* Calculate thread count. There are certain cutoffs by
2817 * register count for thread count */
2819 unsigned nr_registers
= program
->work_register_count
;
2821 unsigned nr_threads
=
2822 (nr_registers
<= 4) ? 4 :
2823 (nr_registers
<= 8) ? 2 :
2828 fprintf(stderr
, "shader%d - %s shader: "
2829 "%u inst, %u bundles, %u quadwords, "
2830 "%u registers, %u threads, %u loops, "
2831 "%u:%u spills:fills\n",
2833 gl_shader_stage_name(ctx
->stage
),
2834 nr_ins
, nr_bundles
, ctx
->quadword_count
,
2835 nr_registers
, nr_threads
,
2837 ctx
->spills
, ctx
->fills
);