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[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
44
45 #include "midgard.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
49 #include "helpers.h"
50 #include "compiler.h"
51 #include "midgard_quirks.h"
52
53 #include "disassemble.h"
54
55 static const struct debug_named_value debug_options[] = {
56 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
57 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
58 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
59 DEBUG_NAMED_VALUE_END
60 };
61
62 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
63
64 unsigned SHADER_DB_COUNT = 0;
65
66 int midgard_debug = 0;
67
68 #define DBG(fmt, ...) \
69 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
70 fprintf(stderr, "%s:%d: "fmt, \
71 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
72
73 static bool
74 midgard_is_branch_unit(unsigned unit)
75 {
76 return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
77 }
78
79 static midgard_block *
80 create_empty_block(compiler_context *ctx)
81 {
82 midgard_block *blk = rzalloc(ctx, midgard_block);
83
84 blk->predecessors = _mesa_set_create(blk,
85 _mesa_hash_pointer,
86 _mesa_key_pointer_equal);
87
88 blk->source_id = ctx->block_source_count++;
89
90 return blk;
91 }
92
93 static void
94 midgard_block_add_successor(midgard_block *block, midgard_block *successor)
95 {
96 assert(block);
97 assert(successor);
98
99 /* Deduplicate */
100 for (unsigned i = 0; i < block->nr_successors; ++i) {
101 if (block->successors[i] == successor)
102 return;
103 }
104
105 block->successors[block->nr_successors++] = successor;
106 assert(block->nr_successors <= ARRAY_SIZE(block->successors));
107
108 /* Note the predecessor in the other direction */
109 _mesa_set_add(successor->predecessors, block);
110 }
111
112 static void
113 schedule_barrier(compiler_context *ctx)
114 {
115 midgard_block *temp = ctx->after_block;
116 ctx->after_block = create_empty_block(ctx);
117 ctx->block_count++;
118 list_addtail(&ctx->after_block->link, &ctx->blocks);
119 list_inithead(&ctx->after_block->instructions);
120 midgard_block_add_successor(ctx->current_block, ctx->after_block);
121 ctx->current_block = ctx->after_block;
122 ctx->after_block = temp;
123 }
124
125 /* Helpers to generate midgard_instruction's using macro magic, since every
126 * driver seems to do it that way */
127
128 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
129
130 #define M_LOAD_STORE(name, store) \
131 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
132 midgard_instruction i = { \
133 .type = TAG_LOAD_STORE_4, \
134 .mask = 0xF, \
135 .dest = ~0, \
136 .src = { ~0, ~0, ~0, ~0 }, \
137 .swizzle = SWIZZLE_IDENTITY_4, \
138 .load_store = { \
139 .op = midgard_op_##name, \
140 .address = address \
141 } \
142 }; \
143 \
144 if (store) \
145 i.src[0] = ssa; \
146 else \
147 i.dest = ssa; \
148 \
149 return i; \
150 }
151
152 #define M_LOAD(name) M_LOAD_STORE(name, false)
153 #define M_STORE(name) M_LOAD_STORE(name, true)
154
155 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
156 * the corresponding Midgard source */
157
158 static midgard_vector_alu_src
159 vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
160 bool half, bool sext)
161 {
162 /* Figure out how many components there are so we can adjust.
163 * Specifically we want to broadcast the last channel so things like
164 * ball2/3 work.
165 */
166
167 if (broadcast_count && src) {
168 uint8_t last_component = src->swizzle[broadcast_count - 1];
169
170 for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) {
171 src->swizzle[c] = last_component;
172 }
173 }
174
175 midgard_vector_alu_src alu_src = {
176 .rep_low = 0,
177 .rep_high = 0,
178 .half = half
179 };
180
181 if (is_int) {
182 alu_src.mod = midgard_int_normal;
183
184 /* Sign/zero-extend if needed */
185
186 if (half) {
187 alu_src.mod = sext ?
188 midgard_int_sign_extend
189 : midgard_int_zero_extend;
190 }
191
192 /* These should have been lowered away */
193 if (src)
194 assert(!(src->abs || src->negate));
195 } else {
196 if (src)
197 alu_src.mod = (src->abs << 0) | (src->negate << 1);
198 }
199
200 return alu_src;
201 }
202
203 /* load/store instructions have both 32-bit and 16-bit variants, depending on
204 * whether we are using vectors composed of highp or mediump. At the moment, we
205 * don't support half-floats -- this requires changes in other parts of the
206 * compiler -- therefore the 16-bit versions are commented out. */
207
208 //M_LOAD(ld_attr_16);
209 M_LOAD(ld_attr_32);
210 //M_LOAD(ld_vary_16);
211 M_LOAD(ld_vary_32);
212 M_LOAD(ld_ubo_int4);
213 M_LOAD(ld_int4);
214 M_STORE(st_int4);
215 M_LOAD(ld_color_buffer_8);
216 //M_STORE(st_vary_16);
217 M_STORE(st_vary_32);
218 M_LOAD(ld_cubemap_coords);
219 M_LOAD(ld_compute_id);
220
221 static midgard_instruction
222 v_alu_br_compact_cond(midgard_jmp_writeout_op op, unsigned tag, signed offset, unsigned cond)
223 {
224 midgard_branch_cond branch = {
225 .op = op,
226 .dest_tag = tag,
227 .offset = offset,
228 .cond = cond
229 };
230
231 uint16_t compact;
232 memcpy(&compact, &branch, sizeof(branch));
233
234 midgard_instruction ins = {
235 .type = TAG_ALU_4,
236 .unit = ALU_ENAB_BR_COMPACT,
237 .prepacked_branch = true,
238 .compact_branch = true,
239 .br_compact = compact,
240 .dest = ~0,
241 .src = { ~0, ~0, ~0, ~0 },
242 };
243
244 if (op == midgard_jmp_writeout_op_writeout)
245 ins.writeout = true;
246
247 return ins;
248 }
249
250 static midgard_instruction
251 v_branch(bool conditional, bool invert)
252 {
253 midgard_instruction ins = {
254 .type = TAG_ALU_4,
255 .unit = ALU_ENAB_BRANCH,
256 .compact_branch = true,
257 .branch = {
258 .conditional = conditional,
259 .invert_conditional = invert
260 },
261 .dest = ~0,
262 .src = { ~0, ~0, ~0, ~0 },
263 };
264
265 return ins;
266 }
267
268 static midgard_branch_extended
269 midgard_create_branch_extended( midgard_condition cond,
270 midgard_jmp_writeout_op op,
271 unsigned dest_tag,
272 signed quadword_offset)
273 {
274 /* The condition code is actually a LUT describing a function to
275 * combine multiple condition codes. However, we only support a single
276 * condition code at the moment, so we just duplicate over a bunch of
277 * times. */
278
279 uint16_t duplicated_cond =
280 (cond << 14) |
281 (cond << 12) |
282 (cond << 10) |
283 (cond << 8) |
284 (cond << 6) |
285 (cond << 4) |
286 (cond << 2) |
287 (cond << 0);
288
289 midgard_branch_extended branch = {
290 .op = op,
291 .dest_tag = dest_tag,
292 .offset = quadword_offset,
293 .cond = duplicated_cond
294 };
295
296 return branch;
297 }
298
299 static void
300 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
301 {
302 ins->has_constants = true;
303 memcpy(&ins->constants, constants, 16);
304 }
305
306 static int
307 glsl_type_size(const struct glsl_type *type, bool bindless)
308 {
309 return glsl_count_attribute_slots(type, false);
310 }
311
312 /* Lower fdot2 to a vector multiplication followed by channel addition */
313 static void
314 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
315 {
316 if (alu->op != nir_op_fdot2)
317 return;
318
319 b->cursor = nir_before_instr(&alu->instr);
320
321 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
322 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
323
324 nir_ssa_def *product = nir_fmul(b, src0, src1);
325
326 nir_ssa_def *sum = nir_fadd(b,
327 nir_channel(b, product, 0),
328 nir_channel(b, product, 1));
329
330 /* Replace the fdot2 with this sum */
331 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
332 }
333
334 static int
335 midgard_sysval_for_ssbo(nir_intrinsic_instr *instr)
336 {
337 /* This is way too meta */
338 bool is_store = instr->intrinsic == nir_intrinsic_store_ssbo;
339 unsigned idx_idx = is_store ? 1 : 0;
340
341 nir_src index = instr->src[idx_idx];
342 assert(nir_src_is_const(index));
343 uint32_t uindex = nir_src_as_uint(index);
344
345 return PAN_SYSVAL(SSBO, uindex);
346 }
347
348 static int
349 midgard_sysval_for_sampler(nir_intrinsic_instr *instr)
350 {
351 /* TODO: indirect samplers !!! */
352 nir_src index = instr->src[0];
353 assert(nir_src_is_const(index));
354 uint32_t uindex = nir_src_as_uint(index);
355
356 return PAN_SYSVAL(SAMPLER, uindex);
357 }
358
359 static int
360 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
361 {
362 switch (instr->intrinsic) {
363 case nir_intrinsic_load_viewport_scale:
364 return PAN_SYSVAL_VIEWPORT_SCALE;
365 case nir_intrinsic_load_viewport_offset:
366 return PAN_SYSVAL_VIEWPORT_OFFSET;
367 case nir_intrinsic_load_num_work_groups:
368 return PAN_SYSVAL_NUM_WORK_GROUPS;
369 case nir_intrinsic_load_ssbo:
370 case nir_intrinsic_store_ssbo:
371 return midgard_sysval_for_ssbo(instr);
372 case nir_intrinsic_load_sampler_lod_parameters_pan:
373 return midgard_sysval_for_sampler(instr);
374 default:
375 return ~0;
376 }
377 }
378
379 static int sysval_for_instr(compiler_context *ctx, nir_instr *instr,
380 unsigned *dest)
381 {
382 nir_intrinsic_instr *intr;
383 nir_dest *dst = NULL;
384 nir_tex_instr *tex;
385 int sysval = -1;
386
387 bool is_store = false;
388
389 switch (instr->type) {
390 case nir_instr_type_intrinsic:
391 intr = nir_instr_as_intrinsic(instr);
392 sysval = midgard_nir_sysval_for_intrinsic(intr);
393 dst = &intr->dest;
394 is_store |= intr->intrinsic == nir_intrinsic_store_ssbo;
395 break;
396 case nir_instr_type_tex:
397 tex = nir_instr_as_tex(instr);
398 if (tex->op != nir_texop_txs)
399 break;
400
401 sysval = PAN_SYSVAL(TEXTURE_SIZE,
402 PAN_TXS_SYSVAL_ID(tex->texture_index,
403 nir_tex_instr_dest_size(tex) -
404 (tex->is_array ? 1 : 0),
405 tex->is_array));
406 dst = &tex->dest;
407 break;
408 default:
409 break;
410 }
411
412 if (dest && dst && !is_store)
413 *dest = nir_dest_index(ctx, dst);
414
415 return sysval;
416 }
417
418 static void
419 midgard_nir_assign_sysval_body(compiler_context *ctx, nir_instr *instr)
420 {
421 int sysval;
422
423 sysval = sysval_for_instr(ctx, instr, NULL);
424 if (sysval < 0)
425 return;
426
427 /* We have a sysval load; check if it's already been assigned */
428
429 if (_mesa_hash_table_u64_search(ctx->sysval_to_id, sysval))
430 return;
431
432 /* It hasn't -- so assign it now! */
433
434 unsigned id = ctx->sysval_count++;
435 _mesa_hash_table_u64_insert(ctx->sysval_to_id, sysval, (void *) ((uintptr_t) id + 1));
436 ctx->sysvals[id] = sysval;
437 }
438
439 static void
440 midgard_nir_assign_sysvals(compiler_context *ctx, nir_shader *shader)
441 {
442 ctx->sysval_count = 0;
443
444 nir_foreach_function(function, shader) {
445 if (!function->impl) continue;
446
447 nir_foreach_block(block, function->impl) {
448 nir_foreach_instr_safe(instr, block) {
449 midgard_nir_assign_sysval_body(ctx, instr);
450 }
451 }
452 }
453 }
454
455 static bool
456 midgard_nir_lower_fdot2(nir_shader *shader)
457 {
458 bool progress = false;
459
460 nir_foreach_function(function, shader) {
461 if (!function->impl) continue;
462
463 nir_builder _b;
464 nir_builder *b = &_b;
465 nir_builder_init(b, function->impl);
466
467 nir_foreach_block(block, function->impl) {
468 nir_foreach_instr_safe(instr, block) {
469 if (instr->type != nir_instr_type_alu) continue;
470
471 nir_alu_instr *alu = nir_instr_as_alu(instr);
472 midgard_nir_lower_fdot2_body(b, alu);
473
474 progress |= true;
475 }
476 }
477
478 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
479
480 }
481
482 return progress;
483 }
484
485 /* Flushes undefined values to zero */
486
487 static void
488 optimise_nir(nir_shader *nir, unsigned quirks)
489 {
490 bool progress;
491 unsigned lower_flrp =
492 (nir->options->lower_flrp16 ? 16 : 0) |
493 (nir->options->lower_flrp32 ? 32 : 0) |
494 (nir->options->lower_flrp64 ? 64 : 0);
495
496 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
497 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
498
499 nir_lower_tex_options lower_tex_options = {
500 .lower_txs_lod = true,
501 .lower_txp = ~0,
502 .lower_tex_without_implicit_lod =
503 (quirks & MIDGARD_EXPLICIT_LOD),
504
505 /* TODO: we have native gradient.. */
506 .lower_txd = true,
507 };
508
509 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
510
511 /* Must lower fdot2 after tex is lowered */
512 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
513
514 /* T720 is broken. */
515
516 if (quirks & MIDGARD_BROKEN_LOD)
517 NIR_PASS_V(nir, midgard_nir_lod_errata);
518
519 do {
520 progress = false;
521
522 NIR_PASS(progress, nir, nir_lower_var_copies);
523 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
524
525 NIR_PASS(progress, nir, nir_copy_prop);
526 NIR_PASS(progress, nir, nir_opt_dce);
527 NIR_PASS(progress, nir, nir_opt_dead_cf);
528 NIR_PASS(progress, nir, nir_opt_cse);
529 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
530 NIR_PASS(progress, nir, nir_opt_algebraic);
531 NIR_PASS(progress, nir, nir_opt_constant_folding);
532
533 if (lower_flrp != 0) {
534 bool lower_flrp_progress = false;
535 NIR_PASS(lower_flrp_progress,
536 nir,
537 nir_lower_flrp,
538 lower_flrp,
539 false /* always_precise */,
540 nir->options->lower_ffma);
541 if (lower_flrp_progress) {
542 NIR_PASS(progress, nir,
543 nir_opt_constant_folding);
544 progress = true;
545 }
546
547 /* Nothing should rematerialize any flrps, so we only
548 * need to do this lowering once.
549 */
550 lower_flrp = 0;
551 }
552
553 NIR_PASS(progress, nir, nir_opt_undef);
554 NIR_PASS(progress, nir, nir_undef_to_zero);
555
556 NIR_PASS(progress, nir, nir_opt_loop_unroll,
557 nir_var_shader_in |
558 nir_var_shader_out |
559 nir_var_function_temp);
560
561 NIR_PASS(progress, nir, nir_opt_vectorize);
562 } while (progress);
563
564 /* Must be run at the end to prevent creation of fsin/fcos ops */
565 NIR_PASS(progress, nir, midgard_nir_scale_trig);
566
567 do {
568 progress = false;
569
570 NIR_PASS(progress, nir, nir_opt_dce);
571 NIR_PASS(progress, nir, nir_opt_algebraic);
572 NIR_PASS(progress, nir, nir_opt_constant_folding);
573 NIR_PASS(progress, nir, nir_copy_prop);
574 } while (progress);
575
576 NIR_PASS(progress, nir, nir_opt_algebraic_late);
577
578 /* We implement booleans as 32-bit 0/~0 */
579 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
580
581 /* Now that booleans are lowered, we can run out late opts */
582 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
583
584 /* Lower mods for float ops only. Integer ops don't support modifiers
585 * (saturate doesn't make sense on integers, neg/abs require dedicated
586 * instructions) */
587
588 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
589 NIR_PASS(progress, nir, nir_copy_prop);
590 NIR_PASS(progress, nir, nir_opt_dce);
591
592 /* Take us out of SSA */
593 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
594 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
595
596 /* We are a vector architecture; write combine where possible */
597 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
598 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
599
600 NIR_PASS(progress, nir, nir_opt_dce);
601 }
602
603 /* Do not actually emit a load; instead, cache the constant for inlining */
604
605 static void
606 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
607 {
608 nir_ssa_def def = instr->def;
609
610 float *v = rzalloc_array(NULL, float, 4);
611 nir_const_value_to_array(v, instr->value, instr->def.num_components, f32);
612
613 /* Shifted for SSA, +1 for off-by-one */
614 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, v);
615 }
616
617 /* Normally constants are embedded implicitly, but for I/O and such we have to
618 * explicitly emit a move with the constant source */
619
620 static void
621 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
622 {
623 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
624
625 if (constant_value) {
626 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
627 attach_constants(ctx, &ins, constant_value, node + 1);
628 emit_mir_instruction(ctx, ins);
629 }
630 }
631
632 static bool
633 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
634 {
635 unsigned comp = src->swizzle[0];
636
637 for (unsigned c = 1; c < nr_components; ++c) {
638 if (src->swizzle[c] != comp)
639 return true;
640 }
641
642 return false;
643 }
644
645 #define ALU_CASE(nir, _op) \
646 case nir_op_##nir: \
647 op = midgard_alu_op_##_op; \
648 assert(src_bitsize == dst_bitsize); \
649 break;
650
651 #define ALU_CASE_BCAST(nir, _op, count) \
652 case nir_op_##nir: \
653 op = midgard_alu_op_##_op; \
654 broadcast_swizzle = count; \
655 assert(src_bitsize == dst_bitsize); \
656 break;
657 static bool
658 nir_is_fzero_constant(nir_src src)
659 {
660 if (!nir_src_is_const(src))
661 return false;
662
663 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
664 if (nir_src_comp_as_float(src, c) != 0.0)
665 return false;
666 }
667
668 return true;
669 }
670
671 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
672 * special treatment override this anyway. */
673
674 static midgard_reg_mode
675 reg_mode_for_nir(nir_alu_instr *instr)
676 {
677 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
678
679 switch (src_bitsize) {
680 case 8:
681 return midgard_reg_mode_8;
682 case 16:
683 return midgard_reg_mode_16;
684 case 32:
685 return midgard_reg_mode_32;
686 case 64:
687 return midgard_reg_mode_64;
688 default:
689 unreachable("Invalid bit size");
690 }
691 }
692
693 static void
694 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
695 {
696 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
697 * is handled elsewhere */
698
699 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
700 midgard_emit_derivatives(ctx, instr);
701 return;
702 }
703
704 bool is_ssa = instr->dest.dest.is_ssa;
705
706 unsigned dest = nir_dest_index(ctx, &instr->dest.dest);
707 unsigned nr_components = nir_dest_num_components(instr->dest.dest);
708 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
709
710 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
711 * supported. A few do not and are commented for now. Also, there are a
712 * number of NIR ops which Midgard does not support and need to be
713 * lowered, also TODO. This switch block emits the opcode and calling
714 * convention of the Midgard instruction; actual packing is done in
715 * emit_alu below */
716
717 unsigned op;
718
719 /* Number of components valid to check for the instruction (the rest
720 * will be forced to the last), or 0 to use as-is. Relevant as
721 * ball-type instructions have a channel count in NIR but are all vec4
722 * in Midgard */
723
724 unsigned broadcast_swizzle = 0;
725
726 /* What register mode should we operate in? */
727 midgard_reg_mode reg_mode =
728 reg_mode_for_nir(instr);
729
730 /* Do we need a destination override? Used for inline
731 * type conversion */
732
733 midgard_dest_override dest_override =
734 midgard_dest_override_none;
735
736 /* Should we use a smaller respective source and sign-extend? */
737
738 bool half_1 = false, sext_1 = false;
739 bool half_2 = false, sext_2 = false;
740
741 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
742 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
743
744 switch (instr->op) {
745 ALU_CASE(fadd, fadd);
746 ALU_CASE(fmul, fmul);
747 ALU_CASE(fmin, fmin);
748 ALU_CASE(fmax, fmax);
749 ALU_CASE(imin, imin);
750 ALU_CASE(imax, imax);
751 ALU_CASE(umin, umin);
752 ALU_CASE(umax, umax);
753 ALU_CASE(ffloor, ffloor);
754 ALU_CASE(fround_even, froundeven);
755 ALU_CASE(ftrunc, ftrunc);
756 ALU_CASE(fceil, fceil);
757 ALU_CASE(fdot3, fdot3);
758 ALU_CASE(fdot4, fdot4);
759 ALU_CASE(iadd, iadd);
760 ALU_CASE(isub, isub);
761 ALU_CASE(imul, imul);
762
763 /* Zero shoved as second-arg */
764 ALU_CASE(iabs, iabsdiff);
765
766 ALU_CASE(mov, imov);
767
768 ALU_CASE(feq32, feq);
769 ALU_CASE(fne32, fne);
770 ALU_CASE(flt32, flt);
771 ALU_CASE(ieq32, ieq);
772 ALU_CASE(ine32, ine);
773 ALU_CASE(ilt32, ilt);
774 ALU_CASE(ult32, ult);
775
776 /* We don't have a native b2f32 instruction. Instead, like many
777 * GPUs, we exploit booleans as 0/~0 for false/true, and
778 * correspondingly AND
779 * by 1.0 to do the type conversion. For the moment, prime us
780 * to emit:
781 *
782 * iand [whatever], #0
783 *
784 * At the end of emit_alu (as MIR), we'll fix-up the constant
785 */
786
787 ALU_CASE(b2f32, iand);
788 ALU_CASE(b2i32, iand);
789
790 /* Likewise, we don't have a dedicated f2b32 instruction, but
791 * we can do a "not equal to 0.0" test. */
792
793 ALU_CASE(f2b32, fne);
794 ALU_CASE(i2b32, ine);
795
796 ALU_CASE(frcp, frcp);
797 ALU_CASE(frsq, frsqrt);
798 ALU_CASE(fsqrt, fsqrt);
799 ALU_CASE(fexp2, fexp2);
800 ALU_CASE(flog2, flog2);
801
802 ALU_CASE(f2i32, f2i_rtz);
803 ALU_CASE(f2u32, f2u_rtz);
804 ALU_CASE(i2f32, i2f_rtz);
805 ALU_CASE(u2f32, u2f_rtz);
806
807 ALU_CASE(f2i16, f2i_rtz);
808 ALU_CASE(f2u16, f2u_rtz);
809 ALU_CASE(i2f16, i2f_rtz);
810 ALU_CASE(u2f16, u2f_rtz);
811
812 ALU_CASE(fsin, fsin);
813 ALU_CASE(fcos, fcos);
814
815 /* We'll set invert */
816 ALU_CASE(inot, imov);
817 ALU_CASE(iand, iand);
818 ALU_CASE(ior, ior);
819 ALU_CASE(ixor, ixor);
820 ALU_CASE(ishl, ishl);
821 ALU_CASE(ishr, iasr);
822 ALU_CASE(ushr, ilsr);
823
824 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
825 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
826 ALU_CASE(b32all_fequal4, fball_eq);
827
828 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
829 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
830 ALU_CASE(b32any_fnequal4, fbany_neq);
831
832 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
833 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
834 ALU_CASE(b32all_iequal4, iball_eq);
835
836 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
837 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
838 ALU_CASE(b32any_inequal4, ibany_neq);
839
840 /* Source mods will be shoved in later */
841 ALU_CASE(fabs, fmov);
842 ALU_CASE(fneg, fmov);
843 ALU_CASE(fsat, fmov);
844
845 /* For size conversion, we use a move. Ideally though we would squash
846 * these ops together; maybe that has to happen after in NIR as part of
847 * propagation...? An earlier algebraic pass ensured we step down by
848 * only / exactly one size. If stepping down, we use a dest override to
849 * reduce the size; if stepping up, we use a larger-sized move with a
850 * half source and a sign/zero-extension modifier */
851
852 case nir_op_i2i8:
853 case nir_op_i2i16:
854 case nir_op_i2i32:
855 case nir_op_i2i64:
856 /* If we end up upscale, we'll need a sign-extend on the
857 * operand (the second argument) */
858
859 sext_2 = true;
860 /* fallthrough */
861 case nir_op_u2u8:
862 case nir_op_u2u16:
863 case nir_op_u2u32:
864 case nir_op_u2u64: {
865 op = midgard_alu_op_imov;
866
867 if (dst_bitsize == (src_bitsize * 2)) {
868 /* Converting up */
869 half_2 = true;
870
871 /* Use a greater register mode */
872 reg_mode++;
873 } else if (src_bitsize == (dst_bitsize * 2)) {
874 /* Converting down */
875 dest_override = midgard_dest_override_lower;
876 }
877
878 break;
879 }
880
881 case nir_op_f2f16: {
882 assert(src_bitsize == 32);
883
884 op = midgard_alu_op_fmov;
885 dest_override = midgard_dest_override_lower;
886 break;
887 }
888
889 case nir_op_f2f32: {
890 assert(src_bitsize == 16);
891
892 op = midgard_alu_op_fmov;
893 half_2 = true;
894 reg_mode++;
895 break;
896 }
897
898
899 /* For greater-or-equal, we lower to less-or-equal and flip the
900 * arguments */
901
902 case nir_op_fge:
903 case nir_op_fge32:
904 case nir_op_ige32:
905 case nir_op_uge32: {
906 op =
907 instr->op == nir_op_fge ? midgard_alu_op_fle :
908 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
909 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
910 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
911 0;
912
913 /* Swap via temporary */
914 nir_alu_src temp = instr->src[1];
915 instr->src[1] = instr->src[0];
916 instr->src[0] = temp;
917
918 break;
919 }
920
921 case nir_op_b32csel: {
922 /* Midgard features both fcsel and icsel, depending on
923 * the type of the arguments/output. However, as long
924 * as we're careful we can _always_ use icsel and
925 * _never_ need fcsel, since the latter does additional
926 * floating-point-specific processing whereas the
927 * former just moves bits on the wire. It's not obvious
928 * why these are separate opcodes, save for the ability
929 * to do things like sat/pos/abs/neg for free */
930
931 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
932 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
933
934 /* The condition is the first argument; move the other
935 * arguments up one to be a binary instruction for
936 * Midgard with the condition last */
937
938 nir_alu_src temp = instr->src[2];
939
940 instr->src[2] = instr->src[0];
941 instr->src[0] = instr->src[1];
942 instr->src[1] = temp;
943
944 break;
945 }
946
947 default:
948 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
949 assert(0);
950 return;
951 }
952
953 /* Midgard can perform certain modifiers on output of an ALU op */
954 unsigned outmod;
955
956 if (midgard_is_integer_out_op(op)) {
957 outmod = midgard_outmod_int_wrap;
958 } else {
959 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
960 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
961 }
962
963 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
964
965 if (instr->op == nir_op_fmax) {
966 if (nir_is_fzero_constant(instr->src[0].src)) {
967 op = midgard_alu_op_fmov;
968 nr_inputs = 1;
969 outmod = midgard_outmod_pos;
970 instr->src[0] = instr->src[1];
971 } else if (nir_is_fzero_constant(instr->src[1].src)) {
972 op = midgard_alu_op_fmov;
973 nr_inputs = 1;
974 outmod = midgard_outmod_pos;
975 }
976 }
977
978 /* Fetch unit, quirks, etc information */
979 unsigned opcode_props = alu_opcode_props[op].props;
980 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
981
982 /* src0 will always exist afaik, but src1 will not for 1-argument
983 * instructions. The latter can only be fetched if the instruction
984 * needs it, or else we may segfault. */
985
986 unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
987 unsigned src1 = nr_inputs >= 2 ? nir_alu_src_index(ctx, &instr->src[1]) : ~0;
988 unsigned src2 = nr_inputs == 3 ? nir_alu_src_index(ctx, &instr->src[2]) : ~0;
989 assert(nr_inputs <= 3);
990
991 /* Rather than use the instruction generation helpers, we do it
992 * ourselves here to avoid the mess */
993
994 midgard_instruction ins = {
995 .type = TAG_ALU_4,
996 .src = {
997 quirk_flipped_r24 ? ~0 : src0,
998 quirk_flipped_r24 ? src0 : src1,
999 src2,
1000 ~0
1001 },
1002 .dest = dest,
1003 };
1004
1005 nir_alu_src *nirmods[3] = { NULL };
1006
1007 if (nr_inputs >= 2) {
1008 nirmods[0] = &instr->src[0];
1009 nirmods[1] = &instr->src[1];
1010 } else if (nr_inputs == 1) {
1011 nirmods[quirk_flipped_r24] = &instr->src[0];
1012 } else {
1013 assert(0);
1014 }
1015
1016 if (nr_inputs == 3)
1017 nirmods[2] = &instr->src[2];
1018
1019 /* These were lowered to a move, so apply the corresponding mod */
1020
1021 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1022 nir_alu_src *s = nirmods[quirk_flipped_r24];
1023
1024 if (instr->op == nir_op_fneg)
1025 s->negate = !s->negate;
1026
1027 if (instr->op == nir_op_fabs)
1028 s->abs = !s->abs;
1029 }
1030
1031 bool is_int = midgard_is_integer_op(op);
1032
1033 ins.mask = mask_of(nr_components);
1034
1035 midgard_vector_alu alu = {
1036 .op = op,
1037 .reg_mode = reg_mode,
1038 .dest_override = dest_override,
1039 .outmod = outmod,
1040
1041 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)),
1042 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)),
1043 };
1044
1045 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1046
1047 if (!is_ssa)
1048 ins.mask &= instr->dest.write_mask;
1049
1050 for (unsigned m = 0; m < 3; ++m) {
1051 if (!nirmods[m])
1052 continue;
1053
1054 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c)
1055 ins.swizzle[m][c] = nirmods[m]->swizzle[c];
1056
1057 /* Replicate. TODO: remove when vec16 lands */
1058 for (unsigned c = NIR_MAX_VEC_COMPONENTS; c < MIR_VEC_COMPONENTS; ++c)
1059 ins.swizzle[m][c] = nirmods[m]->swizzle[NIR_MAX_VEC_COMPONENTS - 1];
1060 }
1061
1062 if (nr_inputs == 3) {
1063 /* Conditions can't have mods */
1064 assert(!nirmods[2]->abs);
1065 assert(!nirmods[2]->negate);
1066 }
1067
1068 ins.alu = alu;
1069
1070 /* Late fixup for emulated instructions */
1071
1072 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1073 /* Presently, our second argument is an inline #0 constant.
1074 * Switch over to an embedded 1.0 constant (that can't fit
1075 * inline, since we're 32-bit, not 16-bit like the inline
1076 * constants) */
1077
1078 ins.has_inline_constant = false;
1079 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1080 ins.has_constants = true;
1081
1082 if (instr->op == nir_op_b2f32) {
1083 float f = 1.0f;
1084 memcpy(&ins.constants, &f, sizeof(float));
1085 } else {
1086 ins.constants[0] = 1;
1087 }
1088
1089
1090 for (unsigned c = 0; c < 16; ++c)
1091 ins.swizzle[1][c] = 0;
1092 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1093 /* Lots of instructions need a 0 plonked in */
1094 ins.has_inline_constant = false;
1095 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1096 ins.has_constants = true;
1097 ins.constants[0] = 0;
1098
1099 for (unsigned c = 0; c < 16; ++c)
1100 ins.swizzle[1][c] = 0;
1101 } else if (instr->op == nir_op_inot) {
1102 ins.invert = true;
1103 }
1104
1105 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1106 /* To avoid duplicating the lookup tables (probably), true LUT
1107 * instructions can only operate as if they were scalars. Lower
1108 * them here by changing the component. */
1109
1110 unsigned orig_mask = ins.mask;
1111
1112 for (int i = 0; i < nr_components; ++i) {
1113 /* Mask the associated component, dropping the
1114 * instruction if needed */
1115
1116 ins.mask = 1 << i;
1117 ins.mask &= orig_mask;
1118
1119 if (!ins.mask)
1120 continue;
1121
1122 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1123 ins.swizzle[0][j] = nirmods[0]->swizzle[i]; /* Pull from the correct component */
1124
1125 emit_mir_instruction(ctx, ins);
1126 }
1127 } else {
1128 emit_mir_instruction(ctx, ins);
1129 }
1130 }
1131
1132 #undef ALU_CASE
1133
1134 static void
1135 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1136 {
1137 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1138 unsigned nir_mask = 0;
1139 unsigned dsize = 0;
1140
1141 if (is_read) {
1142 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1143 dsize = nir_dest_bit_size(intr->dest);
1144 } else {
1145 nir_mask = nir_intrinsic_write_mask(intr);
1146 dsize = 32;
1147 }
1148
1149 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1150 unsigned bytemask = mir_to_bytemask(mir_mode_for_destsize(dsize), nir_mask);
1151 mir_set_bytemask(ins, bytemask);
1152
1153 if (dsize == 64)
1154 ins->load_64 = true;
1155 }
1156
1157 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1158 * optimized) versions of UBO #0 */
1159
1160 midgard_instruction *
1161 emit_ubo_read(
1162 compiler_context *ctx,
1163 nir_instr *instr,
1164 unsigned dest,
1165 unsigned offset,
1166 nir_src *indirect_offset,
1167 unsigned index)
1168 {
1169 /* TODO: half-floats */
1170
1171 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1172 ins.constants[0] = offset;
1173
1174 if (instr->type == nir_instr_type_intrinsic)
1175 mir_set_intr_mask(instr, &ins, true);
1176
1177 if (indirect_offset) {
1178 ins.src[2] = nir_src_index(ctx, indirect_offset);
1179 ins.load_store.arg_2 = 0x80;
1180 } else {
1181 ins.load_store.arg_2 = 0x1E;
1182 }
1183
1184 ins.load_store.arg_1 = index;
1185
1186 return emit_mir_instruction(ctx, ins);
1187 }
1188
1189 /* SSBO reads are like UBO reads if you squint */
1190
1191 static void
1192 emit_ssbo_access(
1193 compiler_context *ctx,
1194 nir_instr *instr,
1195 bool is_read,
1196 unsigned srcdest,
1197 unsigned offset,
1198 nir_src *indirect_offset,
1199 unsigned index)
1200 {
1201 /* TODO: types */
1202
1203 midgard_instruction ins;
1204
1205 if (is_read)
1206 ins = m_ld_int4(srcdest, offset);
1207 else
1208 ins = m_st_int4(srcdest, offset);
1209
1210 /* SSBO reads use a generic memory read interface, so we need the
1211 * address of the SSBO as the first argument. This is a sysval. */
1212
1213 unsigned addr = make_compiler_temp(ctx);
1214 emit_sysval_read(ctx, instr, addr, 2);
1215
1216 /* The source array:
1217 *
1218 * src[0] = store ? value : unused
1219 * src[1] = arg_1
1220 * src[2] = arg_2
1221 *
1222 * We would like arg_1 = the address and
1223 * arg_2 = the offset.
1224 */
1225
1226 ins.src[1] = addr;
1227
1228 /* TODO: What is this? It looks superficially like a shift << 5, but
1229 * arg_1 doesn't take a shift Should it be E0 or A0? We also need the
1230 * indirect offset. */
1231
1232 if (indirect_offset) {
1233 ins.load_store.arg_1 |= 0xE0;
1234 ins.src[2] = nir_src_index(ctx, indirect_offset);
1235 } else {
1236 ins.load_store.arg_2 = 0x7E;
1237 }
1238
1239 /* TODO: Bounds check */
1240
1241 /* Finally, we emit the direct offset */
1242
1243 ins.load_store.varying_parameters = (offset & 0x1FF) << 1;
1244 ins.load_store.address = (offset >> 9);
1245 mir_set_intr_mask(instr, &ins, is_read);
1246
1247 emit_mir_instruction(ctx, ins);
1248 }
1249
1250 static void
1251 emit_varying_read(
1252 compiler_context *ctx,
1253 unsigned dest, unsigned offset,
1254 unsigned nr_comp, unsigned component,
1255 nir_src *indirect_offset, nir_alu_type type)
1256 {
1257 /* XXX: Half-floats? */
1258 /* TODO: swizzle, mask */
1259
1260 midgard_instruction ins = m_ld_vary_32(dest, offset);
1261 ins.mask = mask_of(nr_comp);
1262
1263 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1264 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1265
1266 midgard_varying_parameter p = {
1267 .is_varying = 1,
1268 .interpolation = midgard_interp_default,
1269 .flat = /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1270 };
1271
1272 unsigned u;
1273 memcpy(&u, &p, sizeof(p));
1274 ins.load_store.varying_parameters = u;
1275
1276 if (indirect_offset)
1277 ins.src[2] = nir_src_index(ctx, indirect_offset);
1278 else
1279 ins.load_store.arg_2 = 0x1E;
1280
1281 ins.load_store.arg_1 = 0x9E;
1282
1283 /* Use the type appropriate load */
1284 switch (type) {
1285 case nir_type_uint:
1286 case nir_type_bool:
1287 ins.load_store.op = midgard_op_ld_vary_32u;
1288 break;
1289 case nir_type_int:
1290 ins.load_store.op = midgard_op_ld_vary_32i;
1291 break;
1292 case nir_type_float:
1293 ins.load_store.op = midgard_op_ld_vary_32;
1294 break;
1295 default:
1296 unreachable("Attempted to load unknown type");
1297 break;
1298 }
1299
1300 emit_mir_instruction(ctx, ins);
1301 }
1302
1303 void
1304 emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override,
1305 unsigned nr_components)
1306 {
1307 unsigned dest = 0;
1308
1309 /* Figure out which uniform this is */
1310 int sysval = sysval_for_instr(ctx, instr, &dest);
1311 void *val = _mesa_hash_table_u64_search(ctx->sysval_to_id, sysval);
1312
1313 if (dest_override >= 0)
1314 dest = dest_override;
1315
1316 /* Sysvals are prefix uniforms */
1317 unsigned uniform = ((uintptr_t) val) - 1;
1318
1319 /* Emit the read itself -- this is never indirect */
1320 midgard_instruction *ins =
1321 emit_ubo_read(ctx, instr, dest, uniform * 16, NULL, 0);
1322
1323 ins->mask = mask_of(nr_components);
1324 }
1325
1326 static unsigned
1327 compute_builtin_arg(nir_op op)
1328 {
1329 switch (op) {
1330 case nir_intrinsic_load_work_group_id:
1331 return 0x14;
1332 case nir_intrinsic_load_local_invocation_id:
1333 return 0x10;
1334 default:
1335 unreachable("Invalid compute paramater loaded");
1336 }
1337 }
1338
1339 /* Emit store for a fragment shader, which is encoded via a fancy branch. TODO:
1340 * Handle MRT here */
1341 static void
1342 emit_fragment_epilogue(compiler_context *ctx, unsigned rt);
1343
1344 static void
1345 emit_fragment_store(compiler_context *ctx, unsigned src, unsigned rt)
1346 {
1347 emit_explicit_constant(ctx, src, src);
1348
1349 struct midgard_instruction ins =
1350 v_alu_br_compact_cond(midgard_jmp_writeout_op_writeout, TAG_ALU_8, 0, midgard_condition_always);
1351
1352 /* Add dependencies */
1353 ins.src[0] = src;
1354 ins.constants[0] = rt * 0x100;
1355
1356 /* Emit the branch */
1357 emit_mir_instruction(ctx, ins);
1358 schedule_barrier(ctx);
1359
1360 emit_fragment_epilogue(ctx, rt);
1361 }
1362
1363 static void
1364 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1365 {
1366 unsigned reg = nir_dest_index(ctx, &instr->dest);
1367 midgard_instruction ins = m_ld_compute_id(reg, 0);
1368 ins.mask = mask_of(3);
1369 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1370 emit_mir_instruction(ctx, ins);
1371 }
1372 static void
1373 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1374 {
1375 unsigned offset = 0, reg;
1376
1377 switch (instr->intrinsic) {
1378 case nir_intrinsic_discard_if:
1379 case nir_intrinsic_discard: {
1380 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1381 struct midgard_instruction discard = v_branch(conditional, false);
1382 discard.branch.target_type = TARGET_DISCARD;
1383
1384 if (conditional)
1385 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1386
1387 emit_mir_instruction(ctx, discard);
1388 schedule_barrier(ctx);
1389
1390 break;
1391 }
1392
1393 case nir_intrinsic_load_uniform:
1394 case nir_intrinsic_load_ubo:
1395 case nir_intrinsic_load_ssbo:
1396 case nir_intrinsic_load_input: {
1397 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1398 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1399 bool is_ssbo = instr->intrinsic == nir_intrinsic_load_ssbo;
1400
1401 /* Get the base type of the intrinsic */
1402 /* TODO: Infer type? Does it matter? */
1403 nir_alu_type t =
1404 (is_ubo || is_ssbo) ? nir_type_uint : nir_intrinsic_type(instr);
1405 t = nir_alu_type_get_base_type(t);
1406
1407 if (!(is_ubo || is_ssbo)) {
1408 offset = nir_intrinsic_base(instr);
1409 }
1410
1411 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1412
1413 nir_src *src_offset = nir_get_io_offset_src(instr);
1414
1415 bool direct = nir_src_is_const(*src_offset);
1416 nir_src *indirect_offset = direct ? NULL : src_offset;
1417
1418 if (direct)
1419 offset += nir_src_as_uint(*src_offset);
1420
1421 /* We may need to apply a fractional offset */
1422 int component = instr->intrinsic == nir_intrinsic_load_input ?
1423 nir_intrinsic_component(instr) : 0;
1424 reg = nir_dest_index(ctx, &instr->dest);
1425
1426 if (is_uniform && !ctx->is_blend) {
1427 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysval_count + offset) * 16, indirect_offset, 0);
1428 } else if (is_ubo) {
1429 nir_src index = instr->src[0];
1430
1431 /* We don't yet support indirect UBOs. For indirect
1432 * block numbers (if that's possible), we don't know
1433 * enough about the hardware yet. For indirect sources,
1434 * we know what we need but we need to add some NIR
1435 * support for lowering correctly with respect to
1436 * 128-bit reads */
1437
1438 assert(nir_src_is_const(index));
1439 assert(nir_src_is_const(*src_offset));
1440
1441 uint32_t uindex = nir_src_as_uint(index) + 1;
1442 emit_ubo_read(ctx, &instr->instr, reg, offset, NULL, uindex);
1443 } else if (is_ssbo) {
1444 nir_src index = instr->src[0];
1445 assert(nir_src_is_const(index));
1446 uint32_t uindex = nir_src_as_uint(index);
1447
1448 emit_ssbo_access(ctx, &instr->instr, true, reg, offset, indirect_offset, uindex);
1449 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1450 emit_varying_read(ctx, reg, offset, nr_comp, component, !direct ? &instr->src[0] : NULL, t);
1451 } else if (ctx->is_blend) {
1452 /* For blend shaders, load the input color, which is
1453 * preloaded to r0 */
1454
1455 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1456 emit_mir_instruction(ctx, move);
1457 schedule_barrier(ctx);
1458 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1459 midgard_instruction ins = m_ld_attr_32(reg, offset);
1460 ins.load_store.arg_1 = 0x1E;
1461 ins.load_store.arg_2 = 0x1E;
1462 ins.mask = mask_of(nr_comp);
1463
1464 /* Use the type appropriate load */
1465 switch (t) {
1466 case nir_type_uint:
1467 case nir_type_bool:
1468 ins.load_store.op = midgard_op_ld_attr_32u;
1469 break;
1470 case nir_type_int:
1471 ins.load_store.op = midgard_op_ld_attr_32i;
1472 break;
1473 case nir_type_float:
1474 ins.load_store.op = midgard_op_ld_attr_32;
1475 break;
1476 default:
1477 unreachable("Attempted to load unknown type");
1478 break;
1479 }
1480
1481 emit_mir_instruction(ctx, ins);
1482 } else {
1483 DBG("Unknown load\n");
1484 assert(0);
1485 }
1486
1487 break;
1488 }
1489
1490 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1491
1492 case nir_intrinsic_load_raw_output_pan:
1493 case nir_intrinsic_load_output_u8_as_fp16_pan:
1494 reg = nir_dest_index(ctx, &instr->dest);
1495 assert(ctx->is_blend);
1496
1497 /* T720 and below use different blend opcodes with slightly
1498 * different semantics than T760 and up */
1499
1500 midgard_instruction ld = m_ld_color_buffer_8(reg, 0);
1501 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1502
1503 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1504 ld.load_store.op = old_blend ?
1505 midgard_op_ld_color_buffer_u8_as_fp16_old :
1506 midgard_op_ld_color_buffer_u8_as_fp16;
1507
1508 if (old_blend) {
1509 ld.load_store.address = 1;
1510 ld.load_store.arg_2 = 0x1E;
1511 }
1512
1513 for (unsigned c = 2; c < 16; ++c)
1514 ld.swizzle[0][c] = 0;
1515 }
1516
1517 emit_mir_instruction(ctx, ld);
1518 break;
1519
1520 case nir_intrinsic_load_blend_const_color_rgba: {
1521 assert(ctx->is_blend);
1522 reg = nir_dest_index(ctx, &instr->dest);
1523
1524 /* Blend constants are embedded directly in the shader and
1525 * patched in, so we use some magic routing */
1526
1527 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1528 ins.has_constants = true;
1529 ins.has_blend_constant = true;
1530 emit_mir_instruction(ctx, ins);
1531 break;
1532 }
1533
1534 case nir_intrinsic_store_output:
1535 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1536
1537 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1538
1539 reg = nir_src_index(ctx, &instr->src[0]);
1540
1541 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1542 /* Determine number of render targets */
1543 emit_fragment_store(ctx, reg, offset);
1544 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1545 /* We should have been vectorized, though we don't
1546 * currently check that st_vary is emitted only once
1547 * per slot (this is relevant, since there's not a mask
1548 * parameter available on the store [set to 0 by the
1549 * blob]). We do respect the component by adjusting the
1550 * swizzle. If this is a constant source, we'll need to
1551 * emit that explicitly. */
1552
1553 emit_explicit_constant(ctx, reg, reg);
1554
1555 unsigned component = nir_intrinsic_component(instr);
1556 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1557
1558 midgard_instruction st = m_st_vary_32(reg, offset);
1559 st.load_store.arg_1 = 0x9E;
1560 st.load_store.arg_2 = 0x1E;
1561
1562 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle[0]); ++i)
1563 st.swizzle[0][i] = MIN2(i + component, nr_comp);
1564
1565 emit_mir_instruction(ctx, st);
1566 } else {
1567 DBG("Unknown store\n");
1568 assert(0);
1569 }
1570
1571 break;
1572
1573 /* Special case of store_output for lowered blend shaders */
1574 case nir_intrinsic_store_raw_output_pan:
1575 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1576 reg = nir_src_index(ctx, &instr->src[0]);
1577
1578 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1579 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1580 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1581 * of:
1582 *
1583 * imov r0.xyzw, r0.xxxx
1584 */
1585
1586 unsigned expanded = make_compiler_temp(ctx);
1587
1588 midgard_instruction splatter = v_mov(reg, expanded);
1589
1590 for (unsigned c = 0; c < 16; ++c)
1591 splatter.swizzle[1][c] = 0;
1592
1593 emit_mir_instruction(ctx, splatter);
1594 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1595 } else
1596 emit_fragment_store(ctx, reg, ctx->blend_rt);
1597
1598 break;
1599
1600 case nir_intrinsic_store_ssbo:
1601 assert(nir_src_is_const(instr->src[1]));
1602
1603 bool direct_offset = nir_src_is_const(instr->src[2]);
1604 offset = direct_offset ? nir_src_as_uint(instr->src[2]) : 0;
1605 nir_src *indirect_offset = direct_offset ? NULL : &instr->src[2];
1606 reg = nir_src_index(ctx, &instr->src[0]);
1607
1608 uint32_t uindex = nir_src_as_uint(instr->src[1]);
1609
1610 emit_explicit_constant(ctx, reg, reg);
1611 emit_ssbo_access(ctx, &instr->instr, false, reg, offset, indirect_offset, uindex);
1612 break;
1613
1614 case nir_intrinsic_load_viewport_scale:
1615 case nir_intrinsic_load_viewport_offset:
1616 case nir_intrinsic_load_num_work_groups:
1617 case nir_intrinsic_load_sampler_lod_parameters_pan:
1618 emit_sysval_read(ctx, &instr->instr, ~0, 3);
1619 break;
1620
1621 case nir_intrinsic_load_work_group_id:
1622 case nir_intrinsic_load_local_invocation_id:
1623 emit_compute_builtin(ctx, instr);
1624 break;
1625
1626 default:
1627 printf ("Unhandled intrinsic\n");
1628 assert(0);
1629 break;
1630 }
1631 }
1632
1633 static unsigned
1634 midgard_tex_format(enum glsl_sampler_dim dim)
1635 {
1636 switch (dim) {
1637 case GLSL_SAMPLER_DIM_1D:
1638 case GLSL_SAMPLER_DIM_BUF:
1639 return MALI_TEX_1D;
1640
1641 case GLSL_SAMPLER_DIM_2D:
1642 case GLSL_SAMPLER_DIM_EXTERNAL:
1643 case GLSL_SAMPLER_DIM_RECT:
1644 return MALI_TEX_2D;
1645
1646 case GLSL_SAMPLER_DIM_3D:
1647 return MALI_TEX_3D;
1648
1649 case GLSL_SAMPLER_DIM_CUBE:
1650 return MALI_TEX_CUBE;
1651
1652 default:
1653 DBG("Unknown sampler dim type\n");
1654 assert(0);
1655 return 0;
1656 }
1657 }
1658
1659 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1660 * was successful */
1661
1662 static bool
1663 pan_attach_constant_bias(
1664 compiler_context *ctx,
1665 nir_src lod,
1666 midgard_texture_word *word)
1667 {
1668 /* To attach as constant, it has to *be* constant */
1669
1670 if (!nir_src_is_const(lod))
1671 return false;
1672
1673 float f = nir_src_as_float(lod);
1674
1675 /* Break into fixed-point */
1676 signed lod_int = f;
1677 float lod_frac = f - lod_int;
1678
1679 /* Carry over negative fractions */
1680 if (lod_frac < 0.0) {
1681 lod_int--;
1682 lod_frac += 1.0;
1683 }
1684
1685 /* Encode */
1686 word->bias = float_to_ubyte(lod_frac);
1687 word->bias_int = lod_int;
1688
1689 return true;
1690 }
1691
1692 static enum mali_sampler_type
1693 midgard_sampler_type(nir_alu_type t) {
1694 switch (nir_alu_type_get_base_type(t))
1695 {
1696 case nir_type_float:
1697 return MALI_SAMPLER_FLOAT;
1698 case nir_type_int:
1699 return MALI_SAMPLER_SIGNED;
1700 case nir_type_uint:
1701 return MALI_SAMPLER_UNSIGNED;
1702 default:
1703 unreachable("Unknown sampler type");
1704 }
1705 }
1706
1707 static void
1708 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1709 unsigned midgard_texop)
1710 {
1711 /* TODO */
1712 //assert (!instr->sampler);
1713 //assert (!instr->texture_array_size);
1714
1715 int texture_index = instr->texture_index;
1716 int sampler_index = texture_index;
1717
1718 /* No helper to build texture words -- we do it all here */
1719 midgard_instruction ins = {
1720 .type = TAG_TEXTURE_4,
1721 .mask = 0xF,
1722 .dest = nir_dest_index(ctx, &instr->dest),
1723 .src = { ~0, ~0, ~0, ~0 },
1724 .swizzle = SWIZZLE_IDENTITY_4,
1725 .texture = {
1726 .op = midgard_texop,
1727 .format = midgard_tex_format(instr->sampler_dim),
1728 .texture_handle = texture_index,
1729 .sampler_handle = sampler_index,
1730
1731 /* TODO: half */
1732 .in_reg_full = 1,
1733 .out_full = 1,
1734
1735 .sampler_type = midgard_sampler_type(instr->dest_type),
1736 .shadow = instr->is_shadow,
1737 }
1738 };
1739
1740 /* We may need a temporary for the coordinate */
1741
1742 bool needs_temp_coord =
1743 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1744 (instr->is_shadow);
1745
1746 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1747
1748 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1749 int index = nir_src_index(ctx, &instr->src[i].src);
1750 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1751
1752 switch (instr->src[i].src_type) {
1753 case nir_tex_src_coord: {
1754 emit_explicit_constant(ctx, index, index);
1755
1756 if (needs_temp_coord) {
1757 /* mov coord_temp, coords */
1758 midgard_instruction mov = v_mov(index, coords);
1759 mov.mask = 0x3;
1760 emit_mir_instruction(ctx, mov);
1761 } else {
1762 coords = index;
1763 }
1764
1765 /* Texelfetch coordinates uses all four elements
1766 * (xyz/index) regardless of texture dimensionality,
1767 * which means it's necessary to zero the unused
1768 * components to keep everything happy */
1769
1770 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1771 /* mov index.zw, #0 */
1772 midgard_instruction mov =
1773 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1774 mov.has_constants = true;
1775 mov.mask = (1 << COMPONENT_Z) | (1 << COMPONENT_W);
1776 emit_mir_instruction(ctx, mov);
1777 }
1778
1779 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1780 /* texelFetch is undefined on samplerCube */
1781 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1782
1783 /* For cubemaps, we use a special ld/st op to
1784 * select the face and copy the xy into the
1785 * texture register */
1786
1787 unsigned temp = make_compiler_temp(ctx);
1788 midgard_instruction ld = m_ld_cubemap_coords(temp, 0);
1789 ld.src[1] = coords;
1790 ld.mask = 0x3; /* xy */
1791 ld.load_store.arg_1 = 0x20;
1792 ld.swizzle[1][3] = COMPONENT_X;
1793 emit_mir_instruction(ctx, ld);
1794
1795 ins.src[1] = temp;
1796 /* xyzw -> xyxx */
1797 ins.swizzle[1][2] = COMPONENT_X;
1798 ins.swizzle[1][3] = COMPONENT_X;
1799 } else {
1800 ins.src[1] = coords;
1801 }
1802
1803 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1804 /* Array component in w but NIR wants it in z */
1805 if (nr_components == 3) {
1806 ins.swizzle[1][2] = COMPONENT_Z;
1807 ins.swizzle[1][3] = COMPONENT_Z;
1808 } else if (nr_components == 2) {
1809 ins.swizzle[1][2] =
1810 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1811 ins.swizzle[1][3] = COMPONENT_X;
1812 } else
1813 unreachable("Invalid texture 2D components");
1814 }
1815
1816 break;
1817 }
1818
1819 case nir_tex_src_bias:
1820 case nir_tex_src_lod: {
1821 /* Try as a constant if we can */
1822
1823 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1824 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1825 break;
1826
1827 ins.texture.lod_register = true;
1828 ins.src[2] = index;
1829 emit_explicit_constant(ctx, index, index);
1830
1831 break;
1832 };
1833
1834 case nir_tex_src_offset: {
1835 ins.texture.offset_register = true;
1836 ins.src[3] = index;
1837
1838 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1839 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1840
1841 emit_explicit_constant(ctx, index, index);
1842 };
1843
1844 case nir_tex_src_comparator: {
1845 /* TODO: generalize */
1846 unsigned comp = COMPONENT_Z;
1847
1848 /* mov coord_temp.foo, coords */
1849 midgard_instruction mov = v_mov(index, coords);
1850 mov.mask = 1 << comp;
1851
1852 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1853 mov.swizzle[1][i] = COMPONENT_X;
1854
1855 emit_mir_instruction(ctx, mov);
1856 break;
1857 }
1858
1859 default:
1860 unreachable("Unknown texture source type\n");
1861 }
1862 }
1863
1864 emit_mir_instruction(ctx, ins);
1865
1866 /* Used for .cont and .last hinting */
1867 ctx->texture_op_count++;
1868 }
1869
1870 static void
1871 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1872 {
1873 switch (instr->op) {
1874 case nir_texop_tex:
1875 case nir_texop_txb:
1876 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1877 break;
1878 case nir_texop_txl:
1879 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1880 break;
1881 case nir_texop_txf:
1882 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1883 break;
1884 case nir_texop_txs:
1885 emit_sysval_read(ctx, &instr->instr, ~0, 4);
1886 break;
1887 default:
1888 unreachable("Unhanlded texture op");
1889 }
1890 }
1891
1892 static void
1893 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1894 {
1895 switch (instr->type) {
1896 case nir_jump_break: {
1897 /* Emit a branch out of the loop */
1898 struct midgard_instruction br = v_branch(false, false);
1899 br.branch.target_type = TARGET_BREAK;
1900 br.branch.target_break = ctx->current_loop_depth;
1901 emit_mir_instruction(ctx, br);
1902 break;
1903 }
1904
1905 default:
1906 DBG("Unknown jump type %d\n", instr->type);
1907 break;
1908 }
1909 }
1910
1911 static void
1912 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1913 {
1914 switch (instr->type) {
1915 case nir_instr_type_load_const:
1916 emit_load_const(ctx, nir_instr_as_load_const(instr));
1917 break;
1918
1919 case nir_instr_type_intrinsic:
1920 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1921 break;
1922
1923 case nir_instr_type_alu:
1924 emit_alu(ctx, nir_instr_as_alu(instr));
1925 break;
1926
1927 case nir_instr_type_tex:
1928 emit_tex(ctx, nir_instr_as_tex(instr));
1929 break;
1930
1931 case nir_instr_type_jump:
1932 emit_jump(ctx, nir_instr_as_jump(instr));
1933 break;
1934
1935 case nir_instr_type_ssa_undef:
1936 /* Spurious */
1937 break;
1938
1939 default:
1940 DBG("Unhandled instruction type\n");
1941 break;
1942 }
1943 }
1944
1945
1946 /* ALU instructions can inline or embed constants, which decreases register
1947 * pressure and saves space. */
1948
1949 #define CONDITIONAL_ATTACH(idx) { \
1950 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
1951 \
1952 if (entry) { \
1953 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
1954 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1955 } \
1956 }
1957
1958 static void
1959 inline_alu_constants(compiler_context *ctx, midgard_block *block)
1960 {
1961 mir_foreach_instr_in_block(block, alu) {
1962 /* Other instructions cannot inline constants */
1963 if (alu->type != TAG_ALU_4) continue;
1964 if (alu->compact_branch) continue;
1965
1966 /* If there is already a constant here, we can do nothing */
1967 if (alu->has_constants) continue;
1968
1969 CONDITIONAL_ATTACH(0);
1970
1971 if (!alu->has_constants) {
1972 CONDITIONAL_ATTACH(1)
1973 } else if (!alu->inline_constant) {
1974 /* Corner case: _two_ vec4 constants, for instance with a
1975 * csel. For this case, we can only use a constant
1976 * register for one, we'll have to emit a move for the
1977 * other. Note, if both arguments are constants, then
1978 * necessarily neither argument depends on the value of
1979 * any particular register. As the destination register
1980 * will be wiped, that means we can spill the constant
1981 * to the destination register.
1982 */
1983
1984 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
1985 unsigned scratch = alu->dest;
1986
1987 if (entry) {
1988 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
1989 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
1990
1991 /* Set the source */
1992 alu->src[1] = scratch;
1993
1994 /* Inject us -before- the last instruction which set r31 */
1995 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
1996 }
1997 }
1998 }
1999 }
2000
2001 /* Being a little silly with the names, but returns the op that is the bitwise
2002 * inverse of the op with the argument switched. I.e. (f and g are
2003 * contrapositives):
2004 *
2005 * f(a, b) = ~g(b, a)
2006 *
2007 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
2008 *
2009 * f(a, b) = ~g(b, a)
2010 * ~f(a, b) = g(b, a)
2011 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
2012 * f(a, b) = h(a, b)
2013 *
2014 * Thus we define this function in pairs.
2015 */
2016
2017 static inline midgard_alu_op
2018 mir_contrapositive(midgard_alu_op op)
2019 {
2020 switch (op) {
2021 case midgard_alu_op_flt:
2022 return midgard_alu_op_fle;
2023 case midgard_alu_op_fle:
2024 return midgard_alu_op_flt;
2025
2026 case midgard_alu_op_ilt:
2027 return midgard_alu_op_ile;
2028 case midgard_alu_op_ile:
2029 return midgard_alu_op_ilt;
2030
2031 default:
2032 unreachable("No known contrapositive");
2033 }
2034 }
2035
2036 /* Midgard supports two types of constants, embedded constants (128-bit) and
2037 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2038 * constants can be demoted to inline constants, for space savings and
2039 * sometimes a performance boost */
2040
2041 static void
2042 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2043 {
2044 mir_foreach_instr_in_block(block, ins) {
2045 if (!ins->has_constants) continue;
2046 if (ins->has_inline_constant) continue;
2047
2048 /* Blend constants must not be inlined by definition */
2049 if (ins->has_blend_constant) continue;
2050
2051 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2052 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2053 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2054
2055 if (!(is_16 || is_32))
2056 continue;
2057
2058 /* src1 cannot be an inline constant due to encoding
2059 * restrictions. So, if possible we try to flip the arguments
2060 * in that case */
2061
2062 int op = ins->alu.op;
2063
2064 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2065 bool flip = alu_opcode_props[op].props & OP_COMMUTES;
2066
2067 switch (op) {
2068 /* Conditionals can be inverted */
2069 case midgard_alu_op_flt:
2070 case midgard_alu_op_ilt:
2071 case midgard_alu_op_fle:
2072 case midgard_alu_op_ile:
2073 ins->alu.op = mir_contrapositive(ins->alu.op);
2074 ins->invert = true;
2075 flip = true;
2076 break;
2077
2078 case midgard_alu_op_fcsel:
2079 case midgard_alu_op_icsel:
2080 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
2081 default:
2082 break;
2083 }
2084
2085 if (flip)
2086 mir_flip(ins);
2087 }
2088
2089 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2090 /* Extract the source information */
2091
2092 midgard_vector_alu_src *src;
2093 int q = ins->alu.src2;
2094 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2095 src = m;
2096
2097 /* Component is from the swizzle. Take a nonzero component */
2098 assert(ins->mask);
2099 unsigned first_comp = ffs(ins->mask) - 1;
2100 unsigned component = ins->swizzle[1][first_comp];
2101
2102 /* Scale constant appropriately, if we can legally */
2103 uint16_t scaled_constant = 0;
2104
2105 if (midgard_is_integer_op(op) || is_16) {
2106 unsigned int *iconstants = (unsigned int *) ins->constants;
2107 scaled_constant = (uint16_t) iconstants[component];
2108
2109 /* Constant overflow after resize */
2110 if (scaled_constant != iconstants[component])
2111 continue;
2112 } else {
2113 float *f = (float *) ins->constants;
2114 float original = f[component];
2115 scaled_constant = _mesa_float_to_half(original);
2116
2117 /* Check for loss of precision. If this is
2118 * mediump, we don't care, but for a highp
2119 * shader, we need to pay attention. NIR
2120 * doesn't yet tell us which mode we're in!
2121 * Practically this prevents most constants
2122 * from being inlined, sadly. */
2123
2124 float fp32 = _mesa_half_to_float(scaled_constant);
2125
2126 if (fp32 != original)
2127 continue;
2128 }
2129
2130 /* We don't know how to handle these with a constant */
2131
2132 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2133 DBG("Bailing inline constant...\n");
2134 continue;
2135 }
2136
2137 /* Make sure that the constant is not itself a vector
2138 * by checking if all accessed values are the same. */
2139
2140 uint32_t *cons = ins->constants;
2141 uint32_t value = cons[component];
2142
2143 bool is_vector = false;
2144 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2145
2146 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2147 /* We only care if this component is actually used */
2148 if (!(mask & (1 << c)))
2149 continue;
2150
2151 uint32_t test = cons[ins->swizzle[1][c]];
2152
2153 if (test != value) {
2154 is_vector = true;
2155 break;
2156 }
2157 }
2158
2159 if (is_vector)
2160 continue;
2161
2162 /* Get rid of the embedded constant */
2163 ins->has_constants = false;
2164 ins->src[1] = ~0;
2165 ins->has_inline_constant = true;
2166 ins->inline_constant = scaled_constant;
2167 }
2168 }
2169 }
2170
2171 /* Dead code elimination for branches at the end of a block - only one branch
2172 * per block is legal semantically */
2173
2174 static void
2175 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2176 {
2177 bool branched = false;
2178
2179 mir_foreach_instr_in_block_safe(block, ins) {
2180 if (!midgard_is_branch_unit(ins->unit)) continue;
2181
2182 if (branched)
2183 mir_remove_instruction(ins);
2184
2185 branched = true;
2186 }
2187 }
2188
2189 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2190 * the move can be propagated away entirely */
2191
2192 static bool
2193 mir_compose_float_outmod(midgard_outmod_float *outmod, midgard_outmod_float comp)
2194 {
2195 /* Nothing to do */
2196 if (comp == midgard_outmod_none)
2197 return true;
2198
2199 if (*outmod == midgard_outmod_none) {
2200 *outmod = comp;
2201 return true;
2202 }
2203
2204 /* TODO: Compose rules */
2205 return false;
2206 }
2207
2208 static bool
2209 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
2210 {
2211 bool progress = false;
2212
2213 mir_foreach_instr_in_block_safe(block, ins) {
2214 if (ins->type != TAG_ALU_4) continue;
2215 if (ins->alu.op != midgard_alu_op_fmov) continue;
2216 if (ins->alu.outmod != midgard_outmod_pos) continue;
2217
2218 /* TODO: Registers? */
2219 unsigned src = ins->src[1];
2220 if (src & IS_REG) continue;
2221
2222 /* There might be a source modifier, too */
2223 if (mir_nontrivial_source2_mod(ins)) continue;
2224
2225 /* Backpropagate the modifier */
2226 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
2227 if (v->type != TAG_ALU_4) continue;
2228 if (v->dest != src) continue;
2229
2230 /* Can we even take a float outmod? */
2231 if (midgard_is_integer_out_op(v->alu.op)) continue;
2232
2233 midgard_outmod_float temp = v->alu.outmod;
2234 progress |= mir_compose_float_outmod(&temp, ins->alu.outmod);
2235
2236 /* Throw in the towel.. */
2237 if (!progress) break;
2238
2239 /* Otherwise, transfer the modifier */
2240 v->alu.outmod = temp;
2241 ins->alu.outmod = midgard_outmod_none;
2242
2243 break;
2244 }
2245 }
2246
2247 return progress;
2248 }
2249
2250 static void
2251 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2252 {
2253 /* Include a move to specify the render target */
2254
2255 if (rt > 0) {
2256 midgard_instruction rt_move = v_mov(SSA_FIXED_REGISTER(1),
2257 SSA_FIXED_REGISTER(1));
2258 rt_move.mask = 1 << COMPONENT_Z;
2259 rt_move.unit = UNIT_SADD;
2260 emit_mir_instruction(ctx, rt_move);
2261 }
2262
2263 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_8, -2, midgard_condition_always);
2264 ctx->current_block->epilogue = true;
2265 schedule_barrier(ctx);
2266 }
2267
2268 static midgard_block *
2269 emit_block(compiler_context *ctx, nir_block *block)
2270 {
2271 midgard_block *this_block = ctx->after_block;
2272 ctx->after_block = NULL;
2273
2274 if (!this_block)
2275 this_block = create_empty_block(ctx);
2276
2277 list_addtail(&this_block->link, &ctx->blocks);
2278
2279 this_block->is_scheduled = false;
2280 ++ctx->block_count;
2281
2282 /* Set up current block */
2283 list_inithead(&this_block->instructions);
2284 ctx->current_block = this_block;
2285
2286 nir_foreach_instr(instr, block) {
2287 emit_instr(ctx, instr);
2288 ++ctx->instruction_count;
2289 }
2290
2291 return this_block;
2292 }
2293
2294 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2295
2296 static void
2297 emit_if(struct compiler_context *ctx, nir_if *nif)
2298 {
2299 midgard_block *before_block = ctx->current_block;
2300
2301 /* Speculatively emit the branch, but we can't fill it in until later */
2302 EMIT(branch, true, true);
2303 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2304 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2305
2306 /* Emit the two subblocks. */
2307 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2308 midgard_block *end_then_block = ctx->current_block;
2309
2310 /* Emit a jump from the end of the then block to the end of the else */
2311 EMIT(branch, false, false);
2312 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2313
2314 /* Emit second block, and check if it's empty */
2315
2316 int else_idx = ctx->block_count;
2317 int count_in = ctx->instruction_count;
2318 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2319 midgard_block *end_else_block = ctx->current_block;
2320 int after_else_idx = ctx->block_count;
2321
2322 /* Now that we have the subblocks emitted, fix up the branches */
2323
2324 assert(then_block);
2325 assert(else_block);
2326
2327 if (ctx->instruction_count == count_in) {
2328 /* The else block is empty, so don't emit an exit jump */
2329 mir_remove_instruction(then_exit);
2330 then_branch->branch.target_block = after_else_idx;
2331 } else {
2332 then_branch->branch.target_block = else_idx;
2333 then_exit->branch.target_block = after_else_idx;
2334 }
2335
2336 /* Wire up the successors */
2337
2338 ctx->after_block = create_empty_block(ctx);
2339
2340 midgard_block_add_successor(before_block, then_block);
2341 midgard_block_add_successor(before_block, else_block);
2342
2343 midgard_block_add_successor(end_then_block, ctx->after_block);
2344 midgard_block_add_successor(end_else_block, ctx->after_block);
2345 }
2346
2347 static void
2348 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2349 {
2350 /* Remember where we are */
2351 midgard_block *start_block = ctx->current_block;
2352
2353 /* Allocate a loop number, growing the current inner loop depth */
2354 int loop_idx = ++ctx->current_loop_depth;
2355
2356 /* Get index from before the body so we can loop back later */
2357 int start_idx = ctx->block_count;
2358
2359 /* Emit the body itself */
2360 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2361
2362 /* Branch back to loop back */
2363 struct midgard_instruction br_back = v_branch(false, false);
2364 br_back.branch.target_block = start_idx;
2365 emit_mir_instruction(ctx, br_back);
2366
2367 /* Mark down that branch in the graph. */
2368 midgard_block_add_successor(start_block, loop_block);
2369 midgard_block_add_successor(ctx->current_block, loop_block);
2370
2371 /* Find the index of the block about to follow us (note: we don't add
2372 * one; blocks are 0-indexed so we get a fencepost problem) */
2373 int break_block_idx = ctx->block_count;
2374
2375 /* Fix up the break statements we emitted to point to the right place,
2376 * now that we can allocate a block number for them */
2377 ctx->after_block = create_empty_block(ctx);
2378
2379 list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
2380 mir_foreach_instr_in_block(block, ins) {
2381 if (ins->type != TAG_ALU_4) continue;
2382 if (!ins->compact_branch) continue;
2383 if (ins->prepacked_branch) continue;
2384
2385 /* We found a branch -- check the type to see if we need to do anything */
2386 if (ins->branch.target_type != TARGET_BREAK) continue;
2387
2388 /* It's a break! Check if it's our break */
2389 if (ins->branch.target_break != loop_idx) continue;
2390
2391 /* Okay, cool, we're breaking out of this loop.
2392 * Rewrite from a break to a goto */
2393
2394 ins->branch.target_type = TARGET_GOTO;
2395 ins->branch.target_block = break_block_idx;
2396
2397 midgard_block_add_successor(block, ctx->after_block);
2398 }
2399 }
2400
2401 /* Now that we've finished emitting the loop, free up the depth again
2402 * so we play nice with recursion amid nested loops */
2403 --ctx->current_loop_depth;
2404
2405 /* Dump loop stats */
2406 ++ctx->loop_count;
2407 }
2408
2409 static midgard_block *
2410 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2411 {
2412 midgard_block *start_block = NULL;
2413
2414 foreach_list_typed(nir_cf_node, node, node, list) {
2415 switch (node->type) {
2416 case nir_cf_node_block: {
2417 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2418
2419 if (!start_block)
2420 start_block = block;
2421
2422 break;
2423 }
2424
2425 case nir_cf_node_if:
2426 emit_if(ctx, nir_cf_node_as_if(node));
2427 break;
2428
2429 case nir_cf_node_loop:
2430 emit_loop(ctx, nir_cf_node_as_loop(node));
2431 break;
2432
2433 case nir_cf_node_function:
2434 assert(0);
2435 break;
2436 }
2437 }
2438
2439 return start_block;
2440 }
2441
2442 /* Due to lookahead, we need to report the first tag executed in the command
2443 * stream and in branch targets. An initial block might be empty, so iterate
2444 * until we find one that 'works' */
2445
2446 static unsigned
2447 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2448 {
2449 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2450
2451 unsigned first_tag = 0;
2452
2453 mir_foreach_block_from(ctx, initial_block, v) {
2454 if (v->quadword_count) {
2455 midgard_bundle *initial_bundle =
2456 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2457
2458 first_tag = initial_bundle->tag;
2459 break;
2460 }
2461 }
2462
2463 return first_tag;
2464 }
2465
2466 int
2467 midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2468 {
2469 struct util_dynarray *compiled = &program->compiled;
2470
2471 midgard_debug = debug_get_option_midgard_debug();
2472
2473 /* TODO: Bound against what? */
2474 compiler_context *ctx = rzalloc(NULL, compiler_context);
2475
2476 ctx->nir = nir;
2477 ctx->stage = nir->info.stage;
2478 ctx->is_blend = is_blend;
2479 ctx->alpha_ref = program->alpha_ref;
2480 ctx->blend_rt = blend_rt;
2481 ctx->quirks = midgard_get_quirks(gpu_id);
2482
2483 /* Start off with a safe cutoff, allowing usage of all 16 work
2484 * registers. Later, we'll promote uniform reads to uniform registers
2485 * if we determine it is beneficial to do so */
2486 ctx->uniform_cutoff = 8;
2487
2488 /* Initialize at a global (not block) level hash tables */
2489
2490 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2491 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2492 ctx->sysval_to_id = _mesa_hash_table_u64_create(NULL);
2493
2494 /* Record the varying mapping for the command stream's bookkeeping */
2495
2496 struct exec_list *varyings =
2497 ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs;
2498
2499 unsigned max_varying = 0;
2500 nir_foreach_variable(var, varyings) {
2501 unsigned loc = var->data.driver_location;
2502 unsigned sz = glsl_type_size(var->type, FALSE);
2503
2504 for (int c = 0; c < sz; ++c) {
2505 program->varyings[loc + c] = var->data.location + c;
2506 max_varying = MAX2(max_varying, loc + c);
2507 }
2508 }
2509
2510 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2511 * (so we don't accidentally duplicate the epilogue since mesa/st has
2512 * messed with our I/O quite a bit already) */
2513
2514 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2515
2516 if (ctx->stage == MESA_SHADER_VERTEX) {
2517 NIR_PASS_V(nir, nir_lower_viewport_transform);
2518 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2519 }
2520
2521 NIR_PASS_V(nir, nir_lower_var_copies);
2522 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2523 NIR_PASS_V(nir, nir_split_var_copies);
2524 NIR_PASS_V(nir, nir_lower_var_copies);
2525 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2526 NIR_PASS_V(nir, nir_lower_var_copies);
2527 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2528
2529 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2530
2531 /* Optimisation passes */
2532
2533 optimise_nir(nir, ctx->quirks);
2534
2535 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2536 nir_print_shader(nir, stdout);
2537 }
2538
2539 /* Assign sysvals and counts, now that we're sure
2540 * (post-optimisation) */
2541
2542 midgard_nir_assign_sysvals(ctx, nir);
2543
2544 program->uniform_count = nir->num_uniforms;
2545 program->sysval_count = ctx->sysval_count;
2546 memcpy(program->sysvals, ctx->sysvals, sizeof(ctx->sysvals[0]) * ctx->sysval_count);
2547
2548 nir_foreach_function(func, nir) {
2549 if (!func->impl)
2550 continue;
2551
2552 list_inithead(&ctx->blocks);
2553 ctx->block_count = 0;
2554 ctx->func = func;
2555
2556 emit_cf_list(ctx, &func->impl->body);
2557 break; /* TODO: Multi-function shaders */
2558 }
2559
2560 util_dynarray_init(compiled, NULL);
2561
2562 /* Per-block lowering before opts */
2563
2564 mir_foreach_block(ctx, block) {
2565 inline_alu_constants(ctx, block);
2566 midgard_opt_promote_fmov(ctx, block);
2567 embedded_to_inline_constant(ctx, block);
2568 }
2569 /* MIR-level optimizations */
2570
2571 bool progress = false;
2572
2573 do {
2574 progress = false;
2575
2576 mir_foreach_block(ctx, block) {
2577 progress |= midgard_opt_pos_propagate(ctx, block);
2578 progress |= midgard_opt_copy_prop(ctx, block);
2579 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2580 progress |= midgard_opt_combine_projection(ctx, block);
2581 progress |= midgard_opt_varying_projection(ctx, block);
2582 progress |= midgard_opt_not_propagate(ctx, block);
2583 progress |= midgard_opt_fuse_src_invert(ctx, block);
2584 progress |= midgard_opt_fuse_dest_invert(ctx, block);
2585 progress |= midgard_opt_csel_invert(ctx, block);
2586 progress |= midgard_opt_drop_cmp_invert(ctx, block);
2587 }
2588 } while (progress);
2589
2590 mir_foreach_block(ctx, block) {
2591 midgard_lower_invert(ctx, block);
2592 midgard_lower_derivatives(ctx, block);
2593 }
2594
2595 /* Nested control-flow can result in dead branches at the end of the
2596 * block. This messes with our analysis and is just dead code, so cull
2597 * them */
2598 mir_foreach_block(ctx, block) {
2599 midgard_opt_cull_dead_branch(ctx, block);
2600 }
2601
2602 /* Ensure we were lowered */
2603 mir_foreach_instr_global(ctx, ins) {
2604 assert(!ins->invert);
2605 }
2606
2607 /* Schedule! */
2608 schedule_program(ctx);
2609 mir_ra(ctx);
2610
2611 /* Now that all the bundles are scheduled and we can calculate block
2612 * sizes, emit actual branch instructions rather than placeholders */
2613
2614 int br_block_idx = 0;
2615
2616 mir_foreach_block(ctx, block) {
2617 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2618 for (int c = 0; c < bundle->instruction_count; ++c) {
2619 midgard_instruction *ins = bundle->instructions[c];
2620
2621 if (!midgard_is_branch_unit(ins->unit)) continue;
2622
2623 if (ins->prepacked_branch) continue;
2624
2625 /* Parse some basic branch info */
2626 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2627 bool is_conditional = ins->branch.conditional;
2628 bool is_inverted = ins->branch.invert_conditional;
2629 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2630
2631 /* Determine the block we're jumping to */
2632 int target_number = ins->branch.target_block;
2633
2634 /* Report the destination tag */
2635 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2636
2637 /* Count up the number of quadwords we're
2638 * jumping over = number of quadwords until
2639 * (br_block_idx, target_number) */
2640
2641 int quadword_offset = 0;
2642
2643 if (is_discard) {
2644 /* Ignored */
2645 } else if (target_number > br_block_idx) {
2646 /* Jump forward */
2647
2648 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2649 midgard_block *blk = mir_get_block(ctx, idx);
2650 assert(blk);
2651
2652 quadword_offset += blk->quadword_count;
2653 }
2654 } else {
2655 /* Jump backwards */
2656
2657 for (int idx = br_block_idx; idx >= target_number; --idx) {
2658 midgard_block *blk = mir_get_block(ctx, idx);
2659 assert(blk);
2660
2661 quadword_offset -= blk->quadword_count;
2662 }
2663 }
2664
2665 /* Unconditional extended branches (far jumps)
2666 * have issues, so we always use a conditional
2667 * branch, setting the condition to always for
2668 * unconditional. For compact unconditional
2669 * branches, cond isn't used so it doesn't
2670 * matter what we pick. */
2671
2672 midgard_condition cond =
2673 !is_conditional ? midgard_condition_always :
2674 is_inverted ? midgard_condition_false :
2675 midgard_condition_true;
2676
2677 midgard_jmp_writeout_op op =
2678 is_discard ? midgard_jmp_writeout_op_discard :
2679 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2680 midgard_jmp_writeout_op_branch_cond;
2681
2682 if (!is_compact) {
2683 midgard_branch_extended branch =
2684 midgard_create_branch_extended(
2685 cond, op,
2686 dest_tag,
2687 quadword_offset);
2688
2689 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2690 } else if (is_conditional || is_discard) {
2691 midgard_branch_cond branch = {
2692 .op = op,
2693 .dest_tag = dest_tag,
2694 .offset = quadword_offset,
2695 .cond = cond
2696 };
2697
2698 assert(branch.offset == quadword_offset);
2699
2700 memcpy(&ins->br_compact, &branch, sizeof(branch));
2701 } else {
2702 assert(op == midgard_jmp_writeout_op_branch_uncond);
2703
2704 midgard_branch_uncond branch = {
2705 .op = op,
2706 .dest_tag = dest_tag,
2707 .offset = quadword_offset,
2708 .unknown = 1
2709 };
2710
2711 assert(branch.offset == quadword_offset);
2712
2713 memcpy(&ins->br_compact, &branch, sizeof(branch));
2714 }
2715 }
2716 }
2717
2718 ++br_block_idx;
2719 }
2720
2721 /* Emit flat binary from the instruction arrays. Iterate each block in
2722 * sequence. Save instruction boundaries such that lookahead tags can
2723 * be assigned easily */
2724
2725 /* Cache _all_ bundles in source order for lookahead across failed branches */
2726
2727 int bundle_count = 0;
2728 mir_foreach_block(ctx, block) {
2729 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2730 }
2731 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2732 int bundle_idx = 0;
2733 mir_foreach_block(ctx, block) {
2734 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2735 source_order_bundles[bundle_idx++] = bundle;
2736 }
2737 }
2738
2739 int current_bundle = 0;
2740
2741 /* Midgard prefetches instruction types, so during emission we
2742 * need to lookahead. Unless this is the last instruction, in
2743 * which we return 1. Or if this is the second to last and the
2744 * last is an ALU, then it's also 1... */
2745
2746 mir_foreach_block(ctx, block) {
2747 mir_foreach_bundle_in_block(block, bundle) {
2748 int lookahead = 1;
2749
2750 if (current_bundle + 1 < bundle_count) {
2751 uint8_t next = source_order_bundles[current_bundle + 1]->tag;
2752
2753 if (!(current_bundle + 2 < bundle_count) && IS_ALU(next)) {
2754 lookahead = 1;
2755 } else {
2756 lookahead = next;
2757 }
2758 }
2759
2760 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2761 ++current_bundle;
2762 }
2763
2764 /* TODO: Free deeper */
2765 //util_dynarray_fini(&block->instructions);
2766 }
2767
2768 free(source_order_bundles);
2769
2770 /* Report the very first tag executed */
2771 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2772
2773 /* Deal with off-by-one related to the fencepost problem */
2774 program->work_register_count = ctx->work_registers + 1;
2775 program->uniform_cutoff = ctx->uniform_cutoff;
2776
2777 program->blend_patch_offset = ctx->blend_constant_offset;
2778 program->tls_size = ctx->tls_size;
2779
2780 if (midgard_debug & MIDGARD_DBG_SHADERS)
2781 disassemble_midgard(program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2782
2783 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2784 unsigned nr_bundles = 0, nr_ins = 0;
2785
2786 /* Count instructions and bundles */
2787
2788 mir_foreach_block(ctx, block) {
2789 nr_bundles += util_dynarray_num_elements(
2790 &block->bundles, midgard_bundle);
2791
2792 mir_foreach_bundle_in_block(block, bun)
2793 nr_ins += bun->instruction_count;
2794 }
2795
2796 /* Calculate thread count. There are certain cutoffs by
2797 * register count for thread count */
2798
2799 unsigned nr_registers = program->work_register_count;
2800
2801 unsigned nr_threads =
2802 (nr_registers <= 4) ? 4 :
2803 (nr_registers <= 8) ? 2 :
2804 1;
2805
2806 /* Dump stats */
2807
2808 fprintf(stderr, "shader%d - %s shader: "
2809 "%u inst, %u bundles, %u quadwords, "
2810 "%u registers, %u threads, %u loops, "
2811 "%u:%u spills:fills\n",
2812 SHADER_DB_COUNT++,
2813 gl_shader_stage_name(ctx->stage),
2814 nr_ins, nr_bundles, ctx->quadword_count,
2815 nr_registers, nr_threads,
2816 ctx->loop_count,
2817 ctx->spills, ctx->fills);
2818 }
2819
2820 ralloc_free(ctx);
2821
2822 return 0;
2823 }