2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
51 #include "midgard_quirks.h"
53 #include "disassemble.h"
55 static const struct debug_named_value debug_options
[] = {
56 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
57 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
62 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
64 unsigned SHADER_DB_COUNT
= 0;
66 int midgard_debug
= 0;
68 #define DBG(fmt, ...) \
69 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
70 fprintf(stderr, "%s:%d: "fmt, \
71 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
72 static midgard_block
*
73 create_empty_block(compiler_context
*ctx
)
75 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
77 blk
->predecessors
= _mesa_set_create(blk
,
79 _mesa_key_pointer_equal
);
81 blk
->source_id
= ctx
->block_source_count
++;
87 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
93 for (unsigned i
= 0; i
< block
->nr_successors
; ++i
) {
94 if (block
->successors
[i
] == successor
)
98 block
->successors
[block
->nr_successors
++] = successor
;
99 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
101 /* Note the predecessor in the other direction */
102 _mesa_set_add(successor
->predecessors
, block
);
106 schedule_barrier(compiler_context
*ctx
)
108 midgard_block
*temp
= ctx
->after_block
;
109 ctx
->after_block
= create_empty_block(ctx
);
111 list_addtail(&ctx
->after_block
->link
, &ctx
->blocks
);
112 list_inithead(&ctx
->after_block
->instructions
);
113 midgard_block_add_successor(ctx
->current_block
, ctx
->after_block
);
114 ctx
->current_block
= ctx
->after_block
;
115 ctx
->after_block
= temp
;
118 /* Helpers to generate midgard_instruction's using macro magic, since every
119 * driver seems to do it that way */
121 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
123 #define M_LOAD_STORE(name, store) \
124 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
125 midgard_instruction i = { \
126 .type = TAG_LOAD_STORE_4, \
129 .src = { ~0, ~0, ~0, ~0 }, \
130 .swizzle = SWIZZLE_IDENTITY_4, \
132 .op = midgard_op_##name, \
145 #define M_LOAD(name) M_LOAD_STORE(name, false)
146 #define M_STORE(name) M_LOAD_STORE(name, true)
148 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
149 * the corresponding Midgard source */
151 static midgard_vector_alu_src
152 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
153 bool half
, bool sext
)
155 /* Figure out how many components there are so we can adjust.
156 * Specifically we want to broadcast the last channel so things like
160 if (broadcast_count
&& src
) {
161 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
163 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
164 src
->swizzle
[c
] = last_component
;
168 midgard_vector_alu_src alu_src
= {
175 alu_src
.mod
= midgard_int_normal
;
177 /* Sign/zero-extend if needed */
181 midgard_int_sign_extend
182 : midgard_int_zero_extend
;
185 /* These should have been lowered away */
187 assert(!(src
->abs
|| src
->negate
));
190 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
196 /* load/store instructions have both 32-bit and 16-bit variants, depending on
197 * whether we are using vectors composed of highp or mediump. At the moment, we
198 * don't support half-floats -- this requires changes in other parts of the
199 * compiler -- therefore the 16-bit versions are commented out. */
201 //M_LOAD(ld_attr_16);
203 //M_LOAD(ld_vary_16);
208 M_LOAD(ld_color_buffer_32u
);
209 //M_STORE(st_vary_16);
211 M_LOAD(ld_cubemap_coords
);
212 M_LOAD(ld_compute_id
);
214 static midgard_instruction
215 v_branch(bool conditional
, bool invert
)
217 midgard_instruction ins
= {
219 .unit
= ALU_ENAB_BRANCH
,
220 .compact_branch
= true,
222 .conditional
= conditional
,
223 .invert_conditional
= invert
226 .src
= { ~0, ~0, ~0, ~0 },
232 static midgard_branch_extended
233 midgard_create_branch_extended( midgard_condition cond
,
234 midgard_jmp_writeout_op op
,
236 signed quadword_offset
)
238 /* The condition code is actually a LUT describing a function to
239 * combine multiple condition codes. However, we only support a single
240 * condition code at the moment, so we just duplicate over a bunch of
243 uint16_t duplicated_cond
=
253 midgard_branch_extended branch
= {
255 .dest_tag
= dest_tag
,
256 .offset
= quadword_offset
,
257 .cond
= duplicated_cond
264 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
266 ins
->has_constants
= true;
267 memcpy(&ins
->constants
, constants
, 16);
271 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
273 return glsl_count_attribute_slots(type
, false);
276 /* Lower fdot2 to a vector multiplication followed by channel addition */
278 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
280 if (alu
->op
!= nir_op_fdot2
)
283 b
->cursor
= nir_before_instr(&alu
->instr
);
285 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
286 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
288 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
290 nir_ssa_def
*sum
= nir_fadd(b
,
291 nir_channel(b
, product
, 0),
292 nir_channel(b
, product
, 1));
294 /* Replace the fdot2 with this sum */
295 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
299 midgard_sysval_for_ssbo(nir_intrinsic_instr
*instr
)
301 /* This is way too meta */
302 bool is_store
= instr
->intrinsic
== nir_intrinsic_store_ssbo
;
303 unsigned idx_idx
= is_store
? 1 : 0;
305 nir_src index
= instr
->src
[idx_idx
];
306 assert(nir_src_is_const(index
));
307 uint32_t uindex
= nir_src_as_uint(index
);
309 return PAN_SYSVAL(SSBO
, uindex
);
313 midgard_sysval_for_sampler(nir_intrinsic_instr
*instr
)
315 /* TODO: indirect samplers !!! */
316 nir_src index
= instr
->src
[0];
317 assert(nir_src_is_const(index
));
318 uint32_t uindex
= nir_src_as_uint(index
);
320 return PAN_SYSVAL(SAMPLER
, uindex
);
324 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
326 switch (instr
->intrinsic
) {
327 case nir_intrinsic_load_viewport_scale
:
328 return PAN_SYSVAL_VIEWPORT_SCALE
;
329 case nir_intrinsic_load_viewport_offset
:
330 return PAN_SYSVAL_VIEWPORT_OFFSET
;
331 case nir_intrinsic_load_num_work_groups
:
332 return PAN_SYSVAL_NUM_WORK_GROUPS
;
333 case nir_intrinsic_load_ssbo
:
334 case nir_intrinsic_store_ssbo
:
335 return midgard_sysval_for_ssbo(instr
);
336 case nir_intrinsic_load_sampler_lod_parameters_pan
:
337 return midgard_sysval_for_sampler(instr
);
343 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
346 nir_intrinsic_instr
*intr
;
347 nir_dest
*dst
= NULL
;
351 bool is_store
= false;
353 switch (instr
->type
) {
354 case nir_instr_type_intrinsic
:
355 intr
= nir_instr_as_intrinsic(instr
);
356 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
358 is_store
|= intr
->intrinsic
== nir_intrinsic_store_ssbo
;
360 case nir_instr_type_tex
:
361 tex
= nir_instr_as_tex(instr
);
362 if (tex
->op
!= nir_texop_txs
)
365 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
366 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
367 nir_tex_instr_dest_size(tex
) -
368 (tex
->is_array
? 1 : 0),
376 if (dest
&& dst
&& !is_store
)
377 *dest
= nir_dest_index(ctx
, dst
);
383 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
387 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
391 /* We have a sysval load; check if it's already been assigned */
393 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
396 /* It hasn't -- so assign it now! */
398 unsigned id
= ctx
->sysval_count
++;
399 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
400 ctx
->sysvals
[id
] = sysval
;
404 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
406 ctx
->sysval_count
= 0;
408 nir_foreach_function(function
, shader
) {
409 if (!function
->impl
) continue;
411 nir_foreach_block(block
, function
->impl
) {
412 nir_foreach_instr_safe(instr
, block
) {
413 midgard_nir_assign_sysval_body(ctx
, instr
);
420 midgard_nir_lower_fdot2(nir_shader
*shader
)
422 bool progress
= false;
424 nir_foreach_function(function
, shader
) {
425 if (!function
->impl
) continue;
428 nir_builder
*b
= &_b
;
429 nir_builder_init(b
, function
->impl
);
431 nir_foreach_block(block
, function
->impl
) {
432 nir_foreach_instr_safe(instr
, block
) {
433 if (instr
->type
!= nir_instr_type_alu
) continue;
435 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
436 midgard_nir_lower_fdot2_body(b
, alu
);
442 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
449 /* Midgard can't write depth and stencil separately. It has to happen in a
450 * single store operation containing both. Let's add a panfrost specific
451 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
455 midgard_nir_lower_zs_store(nir_shader
*nir
)
457 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
460 nir_variable
*z_var
= NULL
, *s_var
= NULL
;
462 nir_foreach_variable(var
, &nir
->outputs
) {
463 if (var
->data
.location
== FRAG_RESULT_DEPTH
)
465 else if (var
->data
.location
== FRAG_RESULT_STENCIL
)
469 if (!z_var
&& !s_var
)
472 bool progress
= false;
474 nir_foreach_function(function
, nir
) {
475 if (!function
->impl
) continue;
477 nir_intrinsic_instr
*z_store
= NULL
, *s_store
= NULL
, *last_store
= NULL
;
479 nir_foreach_block(block
, function
->impl
) {
480 nir_foreach_instr_safe(instr
, block
) {
481 if (instr
->type
!= nir_instr_type_intrinsic
)
484 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
485 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
488 if (z_var
&& nir_intrinsic_base(intr
) == z_var
->data
.driver_location
) {
494 if (s_var
&& nir_intrinsic_base(intr
) == s_var
->data
.driver_location
) {
502 if (!z_store
&& !s_store
) continue;
505 nir_builder_init(&b
, function
->impl
);
507 b
.cursor
= nir_before_instr(&last_store
->instr
);
509 nir_ssa_def
*zs_store_src
;
511 if (z_store
&& s_store
) {
512 nir_ssa_def
*srcs
[2] = {
513 nir_ssa_for_src(&b
, z_store
->src
[0], 1),
514 nir_ssa_for_src(&b
, s_store
->src
[0], 1),
517 zs_store_src
= nir_vec(&b
, srcs
, 2);
519 zs_store_src
= nir_ssa_for_src(&b
, last_store
->src
[0], 1);
522 nir_intrinsic_instr
*zs_store
;
524 zs_store
= nir_intrinsic_instr_create(b
.shader
,
525 nir_intrinsic_store_zs_output_pan
);
526 zs_store
->src
[0] = nir_src_for_ssa(zs_store_src
);
527 zs_store
->num_components
= z_store
&& s_store
? 2 : 1;
528 nir_intrinsic_set_component(zs_store
, z_store
? 0 : 1);
530 /* Replace the Z and S store by a ZS store */
531 nir_builder_instr_insert(&b
, &zs_store
->instr
);
534 nir_instr_remove(&z_store
->instr
);
537 nir_instr_remove(&s_store
->instr
);
539 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
546 /* Flushes undefined values to zero */
549 optimise_nir(nir_shader
*nir
, unsigned quirks
)
552 unsigned lower_flrp
=
553 (nir
->options
->lower_flrp16
? 16 : 0) |
554 (nir
->options
->lower_flrp32
? 32 : 0) |
555 (nir
->options
->lower_flrp64
? 64 : 0);
557 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
558 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
560 nir_lower_tex_options lower_tex_options
= {
561 .lower_txs_lod
= true,
563 .lower_tex_without_implicit_lod
=
564 (quirks
& MIDGARD_EXPLICIT_LOD
),
566 /* TODO: we have native gradient.. */
570 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
572 /* Must lower fdot2 after tex is lowered */
573 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
575 /* T720 is broken. */
577 if (quirks
& MIDGARD_BROKEN_LOD
)
578 NIR_PASS_V(nir
, midgard_nir_lod_errata
);
583 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
584 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
586 NIR_PASS(progress
, nir
, nir_copy_prop
);
587 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
588 NIR_PASS(progress
, nir
, nir_opt_dce
);
589 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
590 NIR_PASS(progress
, nir
, nir_opt_cse
);
591 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
592 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
593 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
595 if (lower_flrp
!= 0) {
596 bool lower_flrp_progress
= false;
597 NIR_PASS(lower_flrp_progress
,
601 false /* always_precise */,
602 nir
->options
->lower_ffma
);
603 if (lower_flrp_progress
) {
604 NIR_PASS(progress
, nir
,
605 nir_opt_constant_folding
);
609 /* Nothing should rematerialize any flrps, so we only
610 * need to do this lowering once.
615 NIR_PASS(progress
, nir
, nir_opt_undef
);
616 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
618 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
621 nir_var_function_temp
);
623 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
626 /* Must be run at the end to prevent creation of fsin/fcos ops */
627 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
632 NIR_PASS(progress
, nir
, nir_opt_dce
);
633 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
634 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
635 NIR_PASS(progress
, nir
, nir_copy_prop
);
638 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
640 /* We implement booleans as 32-bit 0/~0 */
641 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
643 /* Now that booleans are lowered, we can run out late opts */
644 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
646 /* Lower mods for float ops only. Integer ops don't support modifiers
647 * (saturate doesn't make sense on integers, neg/abs require dedicated
650 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
651 NIR_PASS(progress
, nir
, nir_copy_prop
);
652 NIR_PASS(progress
, nir
, nir_opt_dce
);
654 /* Take us out of SSA */
655 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
656 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
658 /* We are a vector architecture; write combine where possible */
659 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
660 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
662 NIR_PASS(progress
, nir
, nir_opt_dce
);
665 /* Do not actually emit a load; instead, cache the constant for inlining */
668 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
670 nir_ssa_def def
= instr
->def
;
672 midgard_constants
*consts
= rzalloc(NULL
, midgard_constants
);
674 assert(instr
->def
.num_components
* instr
->def
.bit_size
<= sizeof(*consts
) * 8);
676 #define RAW_CONST_COPY(bits) \
677 nir_const_value_to_array(consts->u##bits, instr->value, \
678 instr->def.num_components, u##bits)
680 switch (instr
->def
.bit_size
) {
694 unreachable("Invalid bit_size for load_const instruction\n");
697 /* Shifted for SSA, +1 for off-by-one */
698 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, consts
);
701 /* Normally constants are embedded implicitly, but for I/O and such we have to
702 * explicitly emit a move with the constant source */
705 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
707 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
709 if (constant_value
) {
710 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), to
);
711 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
712 emit_mir_instruction(ctx
, ins
);
717 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
719 unsigned comp
= src
->swizzle
[0];
721 for (unsigned c
= 1; c
< nr_components
; ++c
) {
722 if (src
->swizzle
[c
] != comp
)
729 #define ALU_CASE(nir, _op) \
731 op = midgard_alu_op_##_op; \
732 assert(src_bitsize == dst_bitsize); \
735 #define ALU_CASE_BCAST(nir, _op, count) \
737 op = midgard_alu_op_##_op; \
738 broadcast_swizzle = count; \
739 assert(src_bitsize == dst_bitsize); \
742 nir_is_fzero_constant(nir_src src
)
744 if (!nir_src_is_const(src
))
747 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
748 if (nir_src_comp_as_float(src
, c
) != 0.0)
755 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
756 * special treatment override this anyway. */
758 static midgard_reg_mode
759 reg_mode_for_nir(nir_alu_instr
*instr
)
761 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
763 switch (src_bitsize
) {
765 return midgard_reg_mode_8
;
767 return midgard_reg_mode_16
;
769 return midgard_reg_mode_32
;
771 return midgard_reg_mode_64
;
773 unreachable("Invalid bit size");
778 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
780 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
781 * is handled elsewhere */
783 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
784 midgard_emit_derivatives(ctx
, instr
);
788 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
790 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
791 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
792 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
794 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
795 * supported. A few do not and are commented for now. Also, there are a
796 * number of NIR ops which Midgard does not support and need to be
797 * lowered, also TODO. This switch block emits the opcode and calling
798 * convention of the Midgard instruction; actual packing is done in
803 /* Number of components valid to check for the instruction (the rest
804 * will be forced to the last), or 0 to use as-is. Relevant as
805 * ball-type instructions have a channel count in NIR but are all vec4
808 unsigned broadcast_swizzle
= 0;
810 /* What register mode should we operate in? */
811 midgard_reg_mode reg_mode
=
812 reg_mode_for_nir(instr
);
814 /* Do we need a destination override? Used for inline
817 midgard_dest_override dest_override
=
818 midgard_dest_override_none
;
820 /* Should we use a smaller respective source and sign-extend? */
822 bool half_1
= false, sext_1
= false;
823 bool half_2
= false, sext_2
= false;
825 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
826 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
829 ALU_CASE(fadd
, fadd
);
830 ALU_CASE(fmul
, fmul
);
831 ALU_CASE(fmin
, fmin
);
832 ALU_CASE(fmax
, fmax
);
833 ALU_CASE(imin
, imin
);
834 ALU_CASE(imax
, imax
);
835 ALU_CASE(umin
, umin
);
836 ALU_CASE(umax
, umax
);
837 ALU_CASE(ffloor
, ffloor
);
838 ALU_CASE(fround_even
, froundeven
);
839 ALU_CASE(ftrunc
, ftrunc
);
840 ALU_CASE(fceil
, fceil
);
841 ALU_CASE(fdot3
, fdot3
);
842 ALU_CASE(fdot4
, fdot4
);
843 ALU_CASE(iadd
, iadd
);
844 ALU_CASE(isub
, isub
);
845 ALU_CASE(imul
, imul
);
847 /* Zero shoved as second-arg */
848 ALU_CASE(iabs
, iabsdiff
);
852 ALU_CASE(feq32
, feq
);
853 ALU_CASE(fne32
, fne
);
854 ALU_CASE(flt32
, flt
);
855 ALU_CASE(ieq32
, ieq
);
856 ALU_CASE(ine32
, ine
);
857 ALU_CASE(ilt32
, ilt
);
858 ALU_CASE(ult32
, ult
);
860 /* We don't have a native b2f32 instruction. Instead, like many
861 * GPUs, we exploit booleans as 0/~0 for false/true, and
862 * correspondingly AND
863 * by 1.0 to do the type conversion. For the moment, prime us
866 * iand [whatever], #0
868 * At the end of emit_alu (as MIR), we'll fix-up the constant
871 ALU_CASE(b2f32
, iand
);
872 ALU_CASE(b2i32
, iand
);
874 /* Likewise, we don't have a dedicated f2b32 instruction, but
875 * we can do a "not equal to 0.0" test. */
877 ALU_CASE(f2b32
, fne
);
878 ALU_CASE(i2b32
, ine
);
880 ALU_CASE(frcp
, frcp
);
881 ALU_CASE(frsq
, frsqrt
);
882 ALU_CASE(fsqrt
, fsqrt
);
883 ALU_CASE(fexp2
, fexp2
);
884 ALU_CASE(flog2
, flog2
);
886 ALU_CASE(f2i64
, f2i_rtz
);
887 ALU_CASE(f2u64
, f2u_rtz
);
888 ALU_CASE(i2f64
, i2f_rtz
);
889 ALU_CASE(u2f64
, u2f_rtz
);
891 ALU_CASE(f2i32
, f2i_rtz
);
892 ALU_CASE(f2u32
, f2u_rtz
);
893 ALU_CASE(i2f32
, i2f_rtz
);
894 ALU_CASE(u2f32
, u2f_rtz
);
896 ALU_CASE(f2i16
, f2i_rtz
);
897 ALU_CASE(f2u16
, f2u_rtz
);
898 ALU_CASE(i2f16
, i2f_rtz
);
899 ALU_CASE(u2f16
, u2f_rtz
);
901 ALU_CASE(fsin
, fsin
);
902 ALU_CASE(fcos
, fcos
);
904 /* We'll set invert */
905 ALU_CASE(inot
, imov
);
906 ALU_CASE(iand
, iand
);
908 ALU_CASE(ixor
, ixor
);
909 ALU_CASE(ishl
, ishl
);
910 ALU_CASE(ishr
, iasr
);
911 ALU_CASE(ushr
, ilsr
);
913 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
914 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
915 ALU_CASE(b32all_fequal4
, fball_eq
);
917 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
918 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
919 ALU_CASE(b32any_fnequal4
, fbany_neq
);
921 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
922 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
923 ALU_CASE(b32all_iequal4
, iball_eq
);
925 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
926 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
927 ALU_CASE(b32any_inequal4
, ibany_neq
);
929 /* Source mods will be shoved in later */
930 ALU_CASE(fabs
, fmov
);
931 ALU_CASE(fneg
, fmov
);
932 ALU_CASE(fsat
, fmov
);
934 /* For size conversion, we use a move. Ideally though we would squash
935 * these ops together; maybe that has to happen after in NIR as part of
936 * propagation...? An earlier algebraic pass ensured we step down by
937 * only / exactly one size. If stepping down, we use a dest override to
938 * reduce the size; if stepping up, we use a larger-sized move with a
939 * half source and a sign/zero-extension modifier */
945 /* If we end up upscale, we'll need a sign-extend on the
946 * operand (the second argument) */
957 if (instr
->op
== nir_op_f2f16
|| instr
->op
== nir_op_f2f32
||
958 instr
->op
== nir_op_f2f64
)
959 op
= midgard_alu_op_fmov
;
961 op
= midgard_alu_op_imov
;
963 if (dst_bitsize
== (src_bitsize
* 2)) {
967 /* Use a greater register mode */
969 } else if (src_bitsize
== (dst_bitsize
* 2)) {
970 /* Converting down */
971 dest_override
= midgard_dest_override_lower
;
977 /* For greater-or-equal, we lower to less-or-equal and flip the
985 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
986 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
987 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
988 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
991 /* Swap via temporary */
992 nir_alu_src temp
= instr
->src
[1];
993 instr
->src
[1] = instr
->src
[0];
994 instr
->src
[0] = temp
;
999 case nir_op_b32csel
: {
1000 /* Midgard features both fcsel and icsel, depending on
1001 * the type of the arguments/output. However, as long
1002 * as we're careful we can _always_ use icsel and
1003 * _never_ need fcsel, since the latter does additional
1004 * floating-point-specific processing whereas the
1005 * former just moves bits on the wire. It's not obvious
1006 * why these are separate opcodes, save for the ability
1007 * to do things like sat/pos/abs/neg for free */
1009 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
1010 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
1012 /* The condition is the first argument; move the other
1013 * arguments up one to be a binary instruction for
1014 * Midgard with the condition last */
1016 nir_alu_src temp
= instr
->src
[2];
1018 instr
->src
[2] = instr
->src
[0];
1019 instr
->src
[0] = instr
->src
[1];
1020 instr
->src
[1] = temp
;
1026 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1031 /* Midgard can perform certain modifiers on output of an ALU op */
1034 if (midgard_is_integer_out_op(op
)) {
1035 outmod
= midgard_outmod_int_wrap
;
1037 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
1038 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
1041 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
1043 if (instr
->op
== nir_op_fmax
) {
1044 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
1045 op
= midgard_alu_op_fmov
;
1047 outmod
= midgard_outmod_pos
;
1048 instr
->src
[0] = instr
->src
[1];
1049 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1050 op
= midgard_alu_op_fmov
;
1052 outmod
= midgard_outmod_pos
;
1056 /* Fetch unit, quirks, etc information */
1057 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1058 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1060 /* src0 will always exist afaik, but src1 will not for 1-argument
1061 * instructions. The latter can only be fetched if the instruction
1062 * needs it, or else we may segfault. */
1064 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1065 unsigned src1
= nr_inputs
>= 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : ~0;
1066 unsigned src2
= nr_inputs
== 3 ? nir_alu_src_index(ctx
, &instr
->src
[2]) : ~0;
1067 assert(nr_inputs
<= 3);
1069 /* Rather than use the instruction generation helpers, we do it
1070 * ourselves here to avoid the mess */
1072 midgard_instruction ins
= {
1075 quirk_flipped_r24
? ~0 : src0
,
1076 quirk_flipped_r24
? src0
: src1
,
1083 nir_alu_src
*nirmods
[3] = { NULL
};
1085 if (nr_inputs
>= 2) {
1086 nirmods
[0] = &instr
->src
[0];
1087 nirmods
[1] = &instr
->src
[1];
1088 } else if (nr_inputs
== 1) {
1089 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1095 nirmods
[2] = &instr
->src
[2];
1097 /* These were lowered to a move, so apply the corresponding mod */
1099 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1100 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
1102 if (instr
->op
== nir_op_fneg
)
1103 s
->negate
= !s
->negate
;
1105 if (instr
->op
== nir_op_fabs
)
1109 bool is_int
= midgard_is_integer_op(op
);
1111 ins
.mask
= mask_of(nr_components
);
1113 midgard_vector_alu alu
= {
1115 .reg_mode
= reg_mode
,
1116 .dest_override
= dest_override
,
1119 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1120 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1123 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1126 ins
.mask
&= instr
->dest
.write_mask
;
1128 for (unsigned m
= 0; m
< 3; ++m
) {
1132 for (unsigned c
= 0; c
< NIR_MAX_VEC_COMPONENTS
; ++c
)
1133 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[c
];
1135 /* Replicate. TODO: remove when vec16 lands */
1136 for (unsigned c
= NIR_MAX_VEC_COMPONENTS
; c
< MIR_VEC_COMPONENTS
; ++c
)
1137 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[NIR_MAX_VEC_COMPONENTS
- 1];
1140 if (nr_inputs
== 3) {
1141 /* Conditions can't have mods */
1142 assert(!nirmods
[2]->abs
);
1143 assert(!nirmods
[2]->negate
);
1148 /* Late fixup for emulated instructions */
1150 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1151 /* Presently, our second argument is an inline #0 constant.
1152 * Switch over to an embedded 1.0 constant (that can't fit
1153 * inline, since we're 32-bit, not 16-bit like the inline
1156 ins
.has_inline_constant
= false;
1157 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1158 ins
.has_constants
= true;
1160 if (instr
->op
== nir_op_b2f32
)
1161 ins
.constants
.f32
[0] = 1.0f
;
1163 ins
.constants
.i32
[0] = 1;
1165 for (unsigned c
= 0; c
< 16; ++c
)
1166 ins
.swizzle
[1][c
] = 0;
1167 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1168 /* Lots of instructions need a 0 plonked in */
1169 ins
.has_inline_constant
= false;
1170 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1171 ins
.has_constants
= true;
1172 ins
.constants
.u32
[0] = 0;
1174 for (unsigned c
= 0; c
< 16; ++c
)
1175 ins
.swizzle
[1][c
] = 0;
1176 } else if (instr
->op
== nir_op_inot
) {
1180 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1181 /* To avoid duplicating the lookup tables (probably), true LUT
1182 * instructions can only operate as if they were scalars. Lower
1183 * them here by changing the component. */
1185 unsigned orig_mask
= ins
.mask
;
1187 for (int i
= 0; i
< nr_components
; ++i
) {
1188 /* Mask the associated component, dropping the
1189 * instruction if needed */
1192 ins
.mask
&= orig_mask
;
1197 for (unsigned j
= 0; j
< MIR_VEC_COMPONENTS
; ++j
)
1198 ins
.swizzle
[0][j
] = nirmods
[0]->swizzle
[i
]; /* Pull from the correct component */
1200 emit_mir_instruction(ctx
, ins
);
1203 emit_mir_instruction(ctx
, ins
);
1210 mir_set_intr_mask(nir_instr
*instr
, midgard_instruction
*ins
, bool is_read
)
1212 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1213 unsigned nir_mask
= 0;
1217 nir_mask
= mask_of(nir_intrinsic_dest_components(intr
));
1218 dsize
= nir_dest_bit_size(intr
->dest
);
1220 nir_mask
= nir_intrinsic_write_mask(intr
);
1224 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1225 unsigned bytemask
= mir_to_bytemask(mir_mode_for_destsize(dsize
), nir_mask
);
1226 mir_set_bytemask(ins
, bytemask
);
1229 ins
->load_64
= true;
1232 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1233 * optimized) versions of UBO #0 */
1235 static midgard_instruction
*
1237 compiler_context
*ctx
,
1241 nir_src
*indirect_offset
,
1242 unsigned indirect_shift
,
1245 /* TODO: half-floats */
1247 midgard_instruction ins
= m_ld_ubo_int4(dest
, 0);
1248 ins
.constants
.u32
[0] = offset
;
1250 if (instr
->type
== nir_instr_type_intrinsic
)
1251 mir_set_intr_mask(instr
, &ins
, true);
1253 if (indirect_offset
) {
1254 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1255 ins
.load_store
.arg_2
= (indirect_shift
<< 5);
1257 ins
.load_store
.arg_2
= 0x1E;
1260 ins
.load_store
.arg_1
= index
;
1262 return emit_mir_instruction(ctx
, ins
);
1265 /* SSBO reads are like UBO reads if you squint */
1269 compiler_context
*ctx
,
1274 nir_src
*indirect_offset
,
1279 midgard_instruction ins
;
1282 ins
= m_ld_int4(srcdest
, offset
);
1284 ins
= m_st_int4(srcdest
, offset
);
1286 /* SSBO reads use a generic memory read interface, so we need the
1287 * address of the SSBO as the first argument. This is a sysval. */
1289 unsigned addr
= make_compiler_temp(ctx
);
1290 emit_sysval_read(ctx
, instr
, addr
, 2);
1292 /* The source array:
1294 * src[0] = store ? value : unused
1298 * We would like arg_1 = the address and
1299 * arg_2 = the offset.
1304 /* TODO: What is this? It looks superficially like a shift << 5, but
1305 * arg_1 doesn't take a shift Should it be E0 or A0? We also need the
1306 * indirect offset. */
1308 if (indirect_offset
) {
1309 ins
.load_store
.arg_1
|= 0xE0;
1310 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1312 ins
.load_store
.arg_2
= 0x7E;
1315 /* TODO: Bounds check */
1317 /* Finally, we emit the direct offset */
1319 ins
.load_store
.varying_parameters
= (offset
& 0x1FF) << 1;
1320 ins
.load_store
.address
= (offset
>> 9);
1321 mir_set_intr_mask(instr
, &ins
, is_read
);
1323 emit_mir_instruction(ctx
, ins
);
1328 compiler_context
*ctx
,
1329 unsigned dest
, unsigned offset
,
1330 unsigned nr_comp
, unsigned component
,
1331 nir_src
*indirect_offset
, nir_alu_type type
, bool flat
)
1333 /* XXX: Half-floats? */
1334 /* TODO: swizzle, mask */
1336 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1337 ins
.mask
= mask_of(nr_comp
);
1339 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
)
1340 ins
.swizzle
[0][i
] = MIN2(i
+ component
, COMPONENT_W
);
1342 midgard_varying_parameter p
= {
1344 .interpolation
= midgard_interp_default
,
1349 memcpy(&u
, &p
, sizeof(p
));
1350 ins
.load_store
.varying_parameters
= u
;
1352 if (indirect_offset
)
1353 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1355 ins
.load_store
.arg_2
= 0x1E;
1357 ins
.load_store
.arg_1
= 0x9E;
1359 /* Use the type appropriate load */
1363 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1366 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1368 case nir_type_float
:
1369 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1372 unreachable("Attempted to load unknown type");
1376 emit_mir_instruction(ctx
, ins
);
1381 compiler_context
*ctx
,
1382 unsigned dest
, unsigned offset
,
1383 unsigned nr_comp
, nir_alu_type t
)
1385 midgard_instruction ins
= m_ld_attr_32(dest
, offset
);
1386 ins
.load_store
.arg_1
= 0x1E;
1387 ins
.load_store
.arg_2
= 0x1E;
1388 ins
.mask
= mask_of(nr_comp
);
1390 /* Use the type appropriate load */
1394 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1397 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1399 case nir_type_float
:
1400 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1403 unreachable("Attempted to load unknown type");
1407 emit_mir_instruction(ctx
, ins
);
1411 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
, signed dest_override
,
1412 unsigned nr_components
)
1416 /* Figure out which uniform this is */
1417 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1418 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1420 if (dest_override
>= 0)
1421 dest
= dest_override
;
1423 /* Sysvals are prefix uniforms */
1424 unsigned uniform
= ((uintptr_t) val
) - 1;
1426 /* Emit the read itself -- this is never indirect */
1427 midgard_instruction
*ins
=
1428 emit_ubo_read(ctx
, instr
, dest
, uniform
* 16, NULL
, 0, 0);
1430 ins
->mask
= mask_of(nr_components
);
1434 compute_builtin_arg(nir_op op
)
1437 case nir_intrinsic_load_work_group_id
:
1439 case nir_intrinsic_load_local_invocation_id
:
1442 unreachable("Invalid compute paramater loaded");
1447 emit_fragment_store(compiler_context
*ctx
, unsigned src
, enum midgard_rt_id rt
)
1449 assert(rt
< ARRAY_SIZE(ctx
->writeout_branch
));
1451 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
1455 emit_explicit_constant(ctx
, src
, src
);
1457 struct midgard_instruction ins
=
1458 v_branch(false, false);
1460 ins
.writeout
= true;
1462 /* Add dependencies */
1464 ins
.constants
.u32
[0] = rt
== MIDGARD_ZS_RT
?
1465 0xFF : (rt
- MIDGARD_COLOR_RT0
) * 0x100;
1467 /* Emit the branch */
1468 br
= emit_mir_instruction(ctx
, ins
);
1469 schedule_barrier(ctx
);
1470 ctx
->writeout_branch
[rt
] = br
;
1472 /* Push our current location = current block count - 1 = where we'll
1473 * jump to. Maybe a bit too clever for my own good */
1475 br
->branch
.target_block
= ctx
->block_count
- 1;
1479 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1481 unsigned reg
= nir_dest_index(ctx
, &instr
->dest
);
1482 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1483 ins
.mask
= mask_of(3);
1484 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1485 emit_mir_instruction(ctx
, ins
);
1489 vertex_builtin_arg(nir_op op
)
1492 case nir_intrinsic_load_vertex_id
:
1493 return PAN_VERTEX_ID
;
1494 case nir_intrinsic_load_instance_id
:
1495 return PAN_INSTANCE_ID
;
1497 unreachable("Invalid vertex builtin");
1502 emit_vertex_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1504 unsigned reg
= nir_dest_index(ctx
, &instr
->dest
);
1505 emit_attr_read(ctx
, reg
, vertex_builtin_arg(instr
->intrinsic
), 1, nir_type_int
);
1508 static const nir_variable
*
1509 search_var(struct exec_list
*vars
, unsigned driver_loc
)
1511 nir_foreach_variable(var
, vars
) {
1512 if (var
->data
.driver_location
== driver_loc
)
1520 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1522 unsigned offset
= 0, reg
;
1524 switch (instr
->intrinsic
) {
1525 case nir_intrinsic_discard_if
:
1526 case nir_intrinsic_discard
: {
1527 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1528 struct midgard_instruction discard
= v_branch(conditional
, false);
1529 discard
.branch
.target_type
= TARGET_DISCARD
;
1532 discard
.src
[0] = nir_src_index(ctx
, &instr
->src
[0]);
1534 emit_mir_instruction(ctx
, discard
);
1535 schedule_barrier(ctx
);
1540 case nir_intrinsic_load_uniform
:
1541 case nir_intrinsic_load_ubo
:
1542 case nir_intrinsic_load_ssbo
:
1543 case nir_intrinsic_load_input
:
1544 case nir_intrinsic_load_interpolated_input
: {
1545 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1546 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1547 bool is_ssbo
= instr
->intrinsic
== nir_intrinsic_load_ssbo
;
1548 bool is_flat
= instr
->intrinsic
== nir_intrinsic_load_input
;
1549 bool is_interp
= instr
->intrinsic
== nir_intrinsic_load_interpolated_input
;
1551 /* Get the base type of the intrinsic */
1552 /* TODO: Infer type? Does it matter? */
1554 (is_ubo
|| is_ssbo
) ? nir_type_uint
:
1555 (is_interp
) ? nir_type_float
:
1556 nir_intrinsic_type(instr
);
1558 t
= nir_alu_type_get_base_type(t
);
1560 if (!(is_ubo
|| is_ssbo
)) {
1561 offset
= nir_intrinsic_base(instr
);
1564 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1566 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1568 bool direct
= nir_src_is_const(*src_offset
);
1569 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1572 offset
+= nir_src_as_uint(*src_offset
);
1574 /* We may need to apply a fractional offset */
1575 int component
= (is_flat
|| is_interp
) ?
1576 nir_intrinsic_component(instr
) : 0;
1577 reg
= nir_dest_index(ctx
, &instr
->dest
);
1579 if (is_uniform
&& !ctx
->is_blend
) {
1580 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysval_count
+ offset
) * 16, indirect_offset
, 4, 0);
1581 } else if (is_ubo
) {
1582 nir_src index
= instr
->src
[0];
1584 /* TODO: Is indirect block number possible? */
1585 assert(nir_src_is_const(index
));
1587 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1588 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, indirect_offset
, 0, uindex
);
1589 } else if (is_ssbo
) {
1590 nir_src index
= instr
->src
[0];
1591 assert(nir_src_is_const(index
));
1592 uint32_t uindex
= nir_src_as_uint(index
);
1594 emit_ssbo_access(ctx
, &instr
->instr
, true, reg
, offset
, indirect_offset
, uindex
);
1595 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1596 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, indirect_offset
, t
, is_flat
);
1597 } else if (ctx
->is_blend
) {
1598 /* For blend shaders, load the input color, which is
1599 * preloaded to r0 */
1601 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), reg
);
1602 emit_mir_instruction(ctx
, move
);
1603 schedule_barrier(ctx
);
1604 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1605 emit_attr_read(ctx
, reg
, offset
, nr_comp
, t
);
1607 DBG("Unknown load\n");
1614 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1615 case nir_intrinsic_load_barycentric_pixel
:
1616 case nir_intrinsic_load_barycentric_centroid
:
1619 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1621 case nir_intrinsic_load_raw_output_pan
:
1622 case nir_intrinsic_load_output_u8_as_fp16_pan
:
1623 reg
= nir_dest_index(ctx
, &instr
->dest
);
1624 assert(ctx
->is_blend
);
1626 /* T720 and below use different blend opcodes with slightly
1627 * different semantics than T760 and up */
1629 midgard_instruction ld
= m_ld_color_buffer_32u(reg
, 0);
1630 bool old_blend
= ctx
->quirks
& MIDGARD_OLD_BLEND
;
1632 if (instr
->intrinsic
== nir_intrinsic_load_output_u8_as_fp16_pan
) {
1633 ld
.load_store
.op
= old_blend
?
1634 midgard_op_ld_color_buffer_u8_as_fp16_old
:
1635 midgard_op_ld_color_buffer_u8_as_fp16
;
1638 ld
.load_store
.address
= 1;
1639 ld
.load_store
.arg_2
= 0x1E;
1642 for (unsigned c
= 2; c
< 16; ++c
)
1643 ld
.swizzle
[0][c
] = 0;
1646 emit_mir_instruction(ctx
, ld
);
1649 case nir_intrinsic_load_blend_const_color_rgba
: {
1650 assert(ctx
->is_blend
);
1651 reg
= nir_dest_index(ctx
, &instr
->dest
);
1653 /* Blend constants are embedded directly in the shader and
1654 * patched in, so we use some magic routing */
1656 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), reg
);
1657 ins
.has_constants
= true;
1658 ins
.has_blend_constant
= true;
1659 emit_mir_instruction(ctx
, ins
);
1663 case nir_intrinsic_store_zs_output_pan
: {
1664 assert(ctx
->stage
== MESA_SHADER_FRAGMENT
);
1665 emit_fragment_store(ctx
, nir_src_index(ctx
, &instr
->src
[0]),
1668 midgard_instruction
*br
= ctx
->writeout_branch
[MIDGARD_ZS_RT
];
1670 if (!nir_intrinsic_component(instr
))
1671 br
->writeout_depth
= true;
1672 if (nir_intrinsic_component(instr
) ||
1673 instr
->num_components
)
1674 br
->writeout_stencil
= true;
1675 assert(br
->writeout_depth
| br
->writeout_stencil
);
1679 case nir_intrinsic_store_output
:
1680 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1682 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1684 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1686 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1687 const nir_variable
*var
;
1688 enum midgard_rt_id rt
;
1690 var
= search_var(&ctx
->nir
->outputs
,
1691 nir_intrinsic_base(instr
));
1693 if (var
->data
.location
== FRAG_RESULT_COLOR
)
1694 rt
= MIDGARD_COLOR_RT0
;
1695 else if (var
->data
.location
>= FRAG_RESULT_DATA0
)
1696 rt
= MIDGARD_COLOR_RT0
+ var
->data
.location
-
1701 emit_fragment_store(ctx
, reg
, rt
);
1702 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1703 /* We should have been vectorized, though we don't
1704 * currently check that st_vary is emitted only once
1705 * per slot (this is relevant, since there's not a mask
1706 * parameter available on the store [set to 0 by the
1707 * blob]). We do respect the component by adjusting the
1708 * swizzle. If this is a constant source, we'll need to
1709 * emit that explicitly. */
1711 emit_explicit_constant(ctx
, reg
, reg
);
1713 unsigned dst_component
= nir_intrinsic_component(instr
);
1714 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1716 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1717 st
.load_store
.arg_1
= 0x9E;
1718 st
.load_store
.arg_2
= 0x1E;
1720 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr
))) {
1723 st
.load_store
.op
= midgard_op_st_vary_32u
;
1726 st
.load_store
.op
= midgard_op_st_vary_32i
;
1728 case nir_type_float
:
1729 st
.load_store
.op
= midgard_op_st_vary_32
;
1732 unreachable("Attempted to store unknown type");
1736 /* nir_intrinsic_component(store_intr) encodes the
1737 * destination component start. Source component offset
1738 * adjustment is taken care of in
1739 * install_registers_instr(), when offset_swizzle() is
1742 unsigned src_component
= COMPONENT_X
;
1744 assert(nr_comp
> 0);
1745 for (unsigned i
= 0; i
< ARRAY_SIZE(st
.swizzle
); ++i
) {
1746 st
.swizzle
[0][i
] = src_component
;
1747 if (i
>= dst_component
&& i
< dst_component
+ nr_comp
- 1)
1751 emit_mir_instruction(ctx
, st
);
1753 DBG("Unknown store\n");
1759 /* Special case of store_output for lowered blend shaders */
1760 case nir_intrinsic_store_raw_output_pan
:
1761 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1762 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1764 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1765 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1766 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1769 * imov r0.xyzw, r0.xxxx
1772 unsigned expanded
= make_compiler_temp(ctx
);
1774 midgard_instruction splatter
= v_mov(reg
, expanded
);
1776 for (unsigned c
= 0; c
< 16; ++c
)
1777 splatter
.swizzle
[1][c
] = 0;
1779 emit_mir_instruction(ctx
, splatter
);
1780 emit_fragment_store(ctx
, expanded
, ctx
->blend_rt
);
1782 emit_fragment_store(ctx
, reg
, ctx
->blend_rt
);
1786 case nir_intrinsic_store_ssbo
:
1787 assert(nir_src_is_const(instr
->src
[1]));
1789 bool direct_offset
= nir_src_is_const(instr
->src
[2]);
1790 offset
= direct_offset
? nir_src_as_uint(instr
->src
[2]) : 0;
1791 nir_src
*indirect_offset
= direct_offset
? NULL
: &instr
->src
[2];
1792 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1794 uint32_t uindex
= nir_src_as_uint(instr
->src
[1]);
1796 emit_explicit_constant(ctx
, reg
, reg
);
1797 emit_ssbo_access(ctx
, &instr
->instr
, false, reg
, offset
, indirect_offset
, uindex
);
1800 case nir_intrinsic_load_viewport_scale
:
1801 case nir_intrinsic_load_viewport_offset
:
1802 case nir_intrinsic_load_num_work_groups
:
1803 case nir_intrinsic_load_sampler_lod_parameters_pan
:
1804 emit_sysval_read(ctx
, &instr
->instr
, ~0, 3);
1807 case nir_intrinsic_load_work_group_id
:
1808 case nir_intrinsic_load_local_invocation_id
:
1809 emit_compute_builtin(ctx
, instr
);
1812 case nir_intrinsic_load_vertex_id
:
1813 case nir_intrinsic_load_instance_id
:
1814 emit_vertex_builtin(ctx
, instr
);
1818 printf ("Unhandled intrinsic %s\n", nir_intrinsic_infos
[instr
->intrinsic
].name
);
1825 midgard_tex_format(enum glsl_sampler_dim dim
)
1828 case GLSL_SAMPLER_DIM_1D
:
1829 case GLSL_SAMPLER_DIM_BUF
:
1832 case GLSL_SAMPLER_DIM_2D
:
1833 case GLSL_SAMPLER_DIM_EXTERNAL
:
1834 case GLSL_SAMPLER_DIM_RECT
:
1837 case GLSL_SAMPLER_DIM_3D
:
1840 case GLSL_SAMPLER_DIM_CUBE
:
1841 return MALI_TEX_CUBE
;
1844 DBG("Unknown sampler dim type\n");
1850 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1854 pan_attach_constant_bias(
1855 compiler_context
*ctx
,
1857 midgard_texture_word
*word
)
1859 /* To attach as constant, it has to *be* constant */
1861 if (!nir_src_is_const(lod
))
1864 float f
= nir_src_as_float(lod
);
1866 /* Break into fixed-point */
1868 float lod_frac
= f
- lod_int
;
1870 /* Carry over negative fractions */
1871 if (lod_frac
< 0.0) {
1877 word
->bias
= float_to_ubyte(lod_frac
);
1878 word
->bias_int
= lod_int
;
1883 static enum mali_sampler_type
1884 midgard_sampler_type(nir_alu_type t
) {
1885 switch (nir_alu_type_get_base_type(t
))
1887 case nir_type_float
:
1888 return MALI_SAMPLER_FLOAT
;
1890 return MALI_SAMPLER_SIGNED
;
1892 return MALI_SAMPLER_UNSIGNED
;
1894 unreachable("Unknown sampler type");
1899 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1900 unsigned midgard_texop
)
1903 //assert (!instr->sampler);
1904 //assert (!instr->texture_array_size);
1906 int texture_index
= instr
->texture_index
;
1907 int sampler_index
= texture_index
;
1909 /* No helper to build texture words -- we do it all here */
1910 midgard_instruction ins
= {
1911 .type
= TAG_TEXTURE_4
,
1913 .dest
= nir_dest_index(ctx
, &instr
->dest
),
1914 .src
= { ~0, ~0, ~0, ~0 },
1915 .swizzle
= SWIZZLE_IDENTITY_4
,
1917 .op
= midgard_texop
,
1918 .format
= midgard_tex_format(instr
->sampler_dim
),
1919 .texture_handle
= texture_index
,
1920 .sampler_handle
= sampler_index
,
1926 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1927 .shadow
= instr
->is_shadow
,
1931 /* We may need a temporary for the coordinate */
1933 bool needs_temp_coord
=
1934 (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) ||
1935 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) ||
1938 unsigned coords
= needs_temp_coord
? make_compiler_temp_reg(ctx
) : 0;
1940 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1941 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1942 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
1944 switch (instr
->src
[i
].src_type
) {
1945 case nir_tex_src_coord
: {
1946 emit_explicit_constant(ctx
, index
, index
);
1948 unsigned coord_mask
= mask_of(instr
->coord_components
);
1950 bool flip_zw
= (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) && (coord_mask
& (1 << COMPONENT_Z
));
1953 coord_mask
^= ((1 << COMPONENT_Z
) | (1 << COMPONENT_W
));
1955 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1956 /* texelFetch is undefined on samplerCube */
1957 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1959 /* For cubemaps, we use a special ld/st op to
1960 * select the face and copy the xy into the
1961 * texture register */
1963 midgard_instruction ld
= m_ld_cubemap_coords(coords
, 0);
1965 ld
.mask
= 0x3; /* xy */
1966 ld
.load_store
.arg_1
= 0x20;
1967 ld
.swizzle
[1][3] = COMPONENT_X
;
1968 emit_mir_instruction(ctx
, ld
);
1971 ins
.swizzle
[1][2] = instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
1972 ins
.swizzle
[1][3] = COMPONENT_X
;
1973 } else if (needs_temp_coord
) {
1974 /* mov coord_temp, coords */
1975 midgard_instruction mov
= v_mov(index
, coords
);
1976 mov
.mask
= coord_mask
;
1979 mov
.swizzle
[1][COMPONENT_W
] = COMPONENT_Z
;
1981 emit_mir_instruction(ctx
, mov
);
1986 ins
.src
[1] = coords
;
1988 /* Texelfetch coordinates uses all four elements
1989 * (xyz/index) regardless of texture dimensionality,
1990 * which means it's necessary to zero the unused
1991 * components to keep everything happy */
1993 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1994 /* mov index.zw, #0, or generalized */
1995 midgard_instruction mov
=
1996 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), coords
);
1997 mov
.has_constants
= true;
1998 mov
.mask
= coord_mask
^ 0xF;
1999 emit_mir_instruction(ctx
, mov
);
2002 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
2003 /* Array component in w but NIR wants it in z,
2004 * but if we have a temp coord we already fixed
2007 if (nr_components
== 3) {
2008 ins
.swizzle
[1][2] = COMPONENT_Z
;
2009 ins
.swizzle
[1][3] = needs_temp_coord
? COMPONENT_W
: COMPONENT_Z
;
2010 } else if (nr_components
== 2) {
2012 instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
2013 ins
.swizzle
[1][3] = COMPONENT_X
;
2015 unreachable("Invalid texture 2D components");
2018 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
2020 ins
.swizzle
[1][2] = COMPONENT_Z
;
2021 ins
.swizzle
[1][3] = COMPONENT_W
;
2027 case nir_tex_src_bias
:
2028 case nir_tex_src_lod
: {
2029 /* Try as a constant if we can */
2031 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
2032 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
2035 ins
.texture
.lod_register
= true;
2038 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
2039 ins
.swizzle
[2][c
] = COMPONENT_X
;
2041 emit_explicit_constant(ctx
, index
, index
);
2046 case nir_tex_src_offset
: {
2047 ins
.texture
.offset_register
= true;
2050 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
2051 ins
.swizzle
[3][c
] = (c
> COMPONENT_Z
) ? 0 : c
;
2053 emit_explicit_constant(ctx
, index
, index
);
2057 case nir_tex_src_comparator
: {
2058 unsigned comp
= COMPONENT_Z
;
2060 /* mov coord_temp.foo, coords */
2061 midgard_instruction mov
= v_mov(index
, coords
);
2062 mov
.mask
= 1 << comp
;
2064 for (unsigned i
= 0; i
< MIR_VEC_COMPONENTS
; ++i
)
2065 mov
.swizzle
[1][i
] = COMPONENT_X
;
2067 emit_mir_instruction(ctx
, mov
);
2072 printf ("Unknown texture source type: %d\n", instr
->src
[i
].src_type
);
2078 emit_mir_instruction(ctx
, ins
);
2080 /* Used for .cont and .last hinting */
2081 ctx
->texture_op_count
++;
2085 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
2087 switch (instr
->op
) {
2090 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
2093 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
2096 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
2099 emit_sysval_read(ctx
, &instr
->instr
, ~0, 4);
2102 printf ("Unhandled texture op: %d\n", instr
->op
);
2109 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
2111 switch (instr
->type
) {
2112 case nir_jump_break
: {
2113 /* Emit a branch out of the loop */
2114 struct midgard_instruction br
= v_branch(false, false);
2115 br
.branch
.target_type
= TARGET_BREAK
;
2116 br
.branch
.target_break
= ctx
->current_loop_depth
;
2117 emit_mir_instruction(ctx
, br
);
2122 DBG("Unknown jump type %d\n", instr
->type
);
2128 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
2130 switch (instr
->type
) {
2131 case nir_instr_type_load_const
:
2132 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2135 case nir_instr_type_intrinsic
:
2136 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2139 case nir_instr_type_alu
:
2140 emit_alu(ctx
, nir_instr_as_alu(instr
));
2143 case nir_instr_type_tex
:
2144 emit_tex(ctx
, nir_instr_as_tex(instr
));
2147 case nir_instr_type_jump
:
2148 emit_jump(ctx
, nir_instr_as_jump(instr
));
2151 case nir_instr_type_ssa_undef
:
2156 DBG("Unhandled instruction type\n");
2162 /* ALU instructions can inline or embed constants, which decreases register
2163 * pressure and saves space. */
2165 #define CONDITIONAL_ATTACH(idx) { \
2166 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2169 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2170 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2175 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
2177 mir_foreach_instr_in_block(block
, alu
) {
2178 /* Other instructions cannot inline constants */
2179 if (alu
->type
!= TAG_ALU_4
) continue;
2180 if (alu
->compact_branch
) continue;
2182 /* If there is already a constant here, we can do nothing */
2183 if (alu
->has_constants
) continue;
2185 CONDITIONAL_ATTACH(0);
2187 if (!alu
->has_constants
) {
2188 CONDITIONAL_ATTACH(1)
2189 } else if (!alu
->inline_constant
) {
2190 /* Corner case: _two_ vec4 constants, for instance with a
2191 * csel. For this case, we can only use a constant
2192 * register for one, we'll have to emit a move for the
2193 * other. Note, if both arguments are constants, then
2194 * necessarily neither argument depends on the value of
2195 * any particular register. As the destination register
2196 * will be wiped, that means we can spill the constant
2197 * to the destination register.
2200 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
2201 unsigned scratch
= alu
->dest
;
2204 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), scratch
);
2205 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
2207 /* Set the source */
2208 alu
->src
[1] = scratch
;
2210 /* Inject us -before- the last instruction which set r31 */
2211 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
2217 /* Being a little silly with the names, but returns the op that is the bitwise
2218 * inverse of the op with the argument switched. I.e. (f and g are
2221 * f(a, b) = ~g(b, a)
2223 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
2225 * f(a, b) = ~g(b, a)
2226 * ~f(a, b) = g(b, a)
2227 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
2230 * Thus we define this function in pairs.
2233 static inline midgard_alu_op
2234 mir_contrapositive(midgard_alu_op op
)
2237 case midgard_alu_op_flt
:
2238 return midgard_alu_op_fle
;
2239 case midgard_alu_op_fle
:
2240 return midgard_alu_op_flt
;
2242 case midgard_alu_op_ilt
:
2243 return midgard_alu_op_ile
;
2244 case midgard_alu_op_ile
:
2245 return midgard_alu_op_ilt
;
2248 unreachable("No known contrapositive");
2252 /* Midgard supports two types of constants, embedded constants (128-bit) and
2253 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2254 * constants can be demoted to inline constants, for space savings and
2255 * sometimes a performance boost */
2258 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
2260 mir_foreach_instr_in_block(block
, ins
) {
2261 if (!ins
->has_constants
) continue;
2262 if (ins
->has_inline_constant
) continue;
2264 /* Blend constants must not be inlined by definition */
2265 if (ins
->has_blend_constant
) continue;
2267 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2268 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
2269 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
2271 if (!(is_16
|| is_32
))
2274 /* src1 cannot be an inline constant due to encoding
2275 * restrictions. So, if possible we try to flip the arguments
2278 int op
= ins
->alu
.op
;
2280 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2281 bool flip
= alu_opcode_props
[op
].props
& OP_COMMUTES
;
2284 /* Conditionals can be inverted */
2285 case midgard_alu_op_flt
:
2286 case midgard_alu_op_ilt
:
2287 case midgard_alu_op_fle
:
2288 case midgard_alu_op_ile
:
2289 ins
->alu
.op
= mir_contrapositive(ins
->alu
.op
);
2294 case midgard_alu_op_fcsel
:
2295 case midgard_alu_op_icsel
:
2296 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
2305 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2306 /* Extract the source information */
2308 midgard_vector_alu_src
*src
;
2309 int q
= ins
->alu
.src2
;
2310 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2313 /* Component is from the swizzle. Take a nonzero component */
2315 unsigned first_comp
= ffs(ins
->mask
) - 1;
2316 unsigned component
= ins
->swizzle
[1][first_comp
];
2318 /* Scale constant appropriately, if we can legally */
2319 uint16_t scaled_constant
= 0;
2322 scaled_constant
= ins
->constants
.u16
[component
];
2323 } else if (midgard_is_integer_op(op
)) {
2324 scaled_constant
= ins
->constants
.u32
[component
];
2326 /* Constant overflow after resize */
2327 if (scaled_constant
!= ins
->constants
.u32
[component
])
2330 float original
= ins
->constants
.f32
[component
];
2331 scaled_constant
= _mesa_float_to_half(original
);
2333 /* Check for loss of precision. If this is
2334 * mediump, we don't care, but for a highp
2335 * shader, we need to pay attention. NIR
2336 * doesn't yet tell us which mode we're in!
2337 * Practically this prevents most constants
2338 * from being inlined, sadly. */
2340 float fp32
= _mesa_half_to_float(scaled_constant
);
2342 if (fp32
!= original
)
2346 /* We don't know how to handle these with a constant */
2348 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
2349 DBG("Bailing inline constant...\n");
2353 /* Make sure that the constant is not itself a vector
2354 * by checking if all accessed values are the same. */
2356 const midgard_constants
*cons
= &ins
->constants
;
2357 uint32_t value
= is_16
? cons
->u16
[component
] : cons
->u32
[component
];
2359 bool is_vector
= false;
2360 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2362 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
2363 /* We only care if this component is actually used */
2364 if (!(mask
& (1 << c
)))
2367 uint32_t test
= is_16
?
2368 cons
->u16
[ins
->swizzle
[1][c
]] :
2369 cons
->u32
[ins
->swizzle
[1][c
]];
2371 if (test
!= value
) {
2380 /* Get rid of the embedded constant */
2381 ins
->has_constants
= false;
2383 ins
->has_inline_constant
= true;
2384 ins
->inline_constant
= scaled_constant
;
2389 /* Dead code elimination for branches at the end of a block - only one branch
2390 * per block is legal semantically */
2393 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2395 bool branched
= false;
2397 mir_foreach_instr_in_block_safe(block
, ins
) {
2398 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2401 mir_remove_instruction(ins
);
2407 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2408 * the move can be propagated away entirely */
2411 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2414 if (comp
== midgard_outmod_none
)
2417 if (*outmod
== midgard_outmod_none
) {
2422 /* TODO: Compose rules */
2427 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2429 bool progress
= false;
2431 mir_foreach_instr_in_block_safe(block
, ins
) {
2432 if (ins
->type
!= TAG_ALU_4
) continue;
2433 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2434 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2436 /* TODO: Registers? */
2437 unsigned src
= ins
->src
[1];
2438 if (src
& IS_REG
) continue;
2440 /* There might be a source modifier, too */
2441 if (mir_nontrivial_source2_mod(ins
)) continue;
2443 /* Backpropagate the modifier */
2444 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2445 if (v
->type
!= TAG_ALU_4
) continue;
2446 if (v
->dest
!= src
) continue;
2448 /* Can we even take a float outmod? */
2449 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2451 midgard_outmod_float temp
= v
->alu
.outmod
;
2452 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2454 /* Throw in the towel.. */
2455 if (!progress
) break;
2457 /* Otherwise, transfer the modifier */
2458 v
->alu
.outmod
= temp
;
2459 ins
->alu
.outmod
= midgard_outmod_none
;
2469 emit_fragment_epilogue(compiler_context
*ctx
, unsigned rt
)
2471 /* Loop to ourselves */
2472 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2473 struct midgard_instruction ins
= v_branch(false, false);
2474 ins
.writeout
= true;
2475 ins
.writeout_depth
= br
->writeout_depth
;
2476 ins
.writeout_stencil
= br
->writeout_stencil
;
2477 ins
.branch
.target_block
= ctx
->block_count
- 1;
2478 ins
.constants
.u32
[0] = br
->constants
.u32
[0];
2479 emit_mir_instruction(ctx
, ins
);
2481 ctx
->current_block
->epilogue
= true;
2482 schedule_barrier(ctx
);
2483 return ins
.branch
.target_block
;
2486 static midgard_block
*
2487 emit_block(compiler_context
*ctx
, nir_block
*block
)
2489 midgard_block
*this_block
= ctx
->after_block
;
2490 ctx
->after_block
= NULL
;
2493 this_block
= create_empty_block(ctx
);
2495 list_addtail(&this_block
->link
, &ctx
->blocks
);
2497 this_block
->is_scheduled
= false;
2500 /* Set up current block */
2501 list_inithead(&this_block
->instructions
);
2502 ctx
->current_block
= this_block
;
2504 nir_foreach_instr(instr
, block
) {
2505 emit_instr(ctx
, instr
);
2506 ++ctx
->instruction_count
;
2512 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2515 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2517 midgard_block
*before_block
= ctx
->current_block
;
2519 /* Speculatively emit the branch, but we can't fill it in until later */
2520 EMIT(branch
, true, true);
2521 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2522 then_branch
->src
[0] = nir_src_index(ctx
, &nif
->condition
);
2524 /* Emit the two subblocks. */
2525 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2526 midgard_block
*end_then_block
= ctx
->current_block
;
2528 /* Emit a jump from the end of the then block to the end of the else */
2529 EMIT(branch
, false, false);
2530 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2532 /* Emit second block, and check if it's empty */
2534 int else_idx
= ctx
->block_count
;
2535 int count_in
= ctx
->instruction_count
;
2536 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2537 midgard_block
*end_else_block
= ctx
->current_block
;
2538 int after_else_idx
= ctx
->block_count
;
2540 /* Now that we have the subblocks emitted, fix up the branches */
2545 if (ctx
->instruction_count
== count_in
) {
2546 /* The else block is empty, so don't emit an exit jump */
2547 mir_remove_instruction(then_exit
);
2548 then_branch
->branch
.target_block
= after_else_idx
;
2550 then_branch
->branch
.target_block
= else_idx
;
2551 then_exit
->branch
.target_block
= after_else_idx
;
2554 /* Wire up the successors */
2556 ctx
->after_block
= create_empty_block(ctx
);
2558 midgard_block_add_successor(before_block
, then_block
);
2559 midgard_block_add_successor(before_block
, else_block
);
2561 midgard_block_add_successor(end_then_block
, ctx
->after_block
);
2562 midgard_block_add_successor(end_else_block
, ctx
->after_block
);
2566 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2568 /* Remember where we are */
2569 midgard_block
*start_block
= ctx
->current_block
;
2571 /* Allocate a loop number, growing the current inner loop depth */
2572 int loop_idx
= ++ctx
->current_loop_depth
;
2574 /* Get index from before the body so we can loop back later */
2575 int start_idx
= ctx
->block_count
;
2577 /* Emit the body itself */
2578 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2580 /* Branch back to loop back */
2581 struct midgard_instruction br_back
= v_branch(false, false);
2582 br_back
.branch
.target_block
= start_idx
;
2583 emit_mir_instruction(ctx
, br_back
);
2585 /* Mark down that branch in the graph. */
2586 midgard_block_add_successor(start_block
, loop_block
);
2587 midgard_block_add_successor(ctx
->current_block
, loop_block
);
2589 /* Find the index of the block about to follow us (note: we don't add
2590 * one; blocks are 0-indexed so we get a fencepost problem) */
2591 int break_block_idx
= ctx
->block_count
;
2593 /* Fix up the break statements we emitted to point to the right place,
2594 * now that we can allocate a block number for them */
2595 ctx
->after_block
= create_empty_block(ctx
);
2597 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2598 mir_foreach_instr_in_block(block
, ins
) {
2599 if (ins
->type
!= TAG_ALU_4
) continue;
2600 if (!ins
->compact_branch
) continue;
2602 /* We found a branch -- check the type to see if we need to do anything */
2603 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2605 /* It's a break! Check if it's our break */
2606 if (ins
->branch
.target_break
!= loop_idx
) continue;
2608 /* Okay, cool, we're breaking out of this loop.
2609 * Rewrite from a break to a goto */
2611 ins
->branch
.target_type
= TARGET_GOTO
;
2612 ins
->branch
.target_block
= break_block_idx
;
2614 midgard_block_add_successor(block
, ctx
->after_block
);
2618 /* Now that we've finished emitting the loop, free up the depth again
2619 * so we play nice with recursion amid nested loops */
2620 --ctx
->current_loop_depth
;
2622 /* Dump loop stats */
2626 static midgard_block
*
2627 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2629 midgard_block
*start_block
= NULL
;
2631 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2632 switch (node
->type
) {
2633 case nir_cf_node_block
: {
2634 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2637 start_block
= block
;
2642 case nir_cf_node_if
:
2643 emit_if(ctx
, nir_cf_node_as_if(node
));
2646 case nir_cf_node_loop
:
2647 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2650 case nir_cf_node_function
:
2659 /* Due to lookahead, we need to report the first tag executed in the command
2660 * stream and in branch targets. An initial block might be empty, so iterate
2661 * until we find one that 'works' */
2664 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2666 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2668 unsigned first_tag
= 0;
2670 mir_foreach_block_from(ctx
, initial_block
, v
) {
2671 if (v
->quadword_count
) {
2672 midgard_bundle
*initial_bundle
=
2673 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2675 first_tag
= initial_bundle
->tag
;
2684 pan_format_from_nir_base(nir_alu_type base
)
2688 return MALI_FORMAT_SINT
;
2691 return MALI_FORMAT_UINT
;
2692 case nir_type_float
:
2693 return MALI_CHANNEL_FLOAT
;
2695 unreachable("Invalid base");
2700 pan_format_from_nir_size(nir_alu_type base
, unsigned size
)
2702 if (base
== nir_type_float
) {
2704 case 16: return MALI_FORMAT_SINT
;
2705 case 32: return MALI_FORMAT_UNORM
;
2707 unreachable("Invalid float size for format");
2712 case 8: return MALI_CHANNEL_8
;
2713 case 16: return MALI_CHANNEL_16
;
2714 case 32: return MALI_CHANNEL_32
;
2716 unreachable("Invalid int size for format");
2721 static enum mali_format
2722 pan_format_from_glsl(const struct glsl_type
*type
)
2724 enum glsl_base_type glsl_base
= glsl_get_base_type(glsl_without_array(type
));
2725 nir_alu_type t
= nir_get_nir_type_for_glsl_base_type(glsl_base
);
2727 unsigned base
= nir_alu_type_get_base_type(t
);
2728 unsigned size
= nir_alu_type_get_type_size(t
);
2730 return pan_format_from_nir_base(base
) |
2731 pan_format_from_nir_size(base
, size
) |
2732 MALI_NR_CHANNELS(4);
2735 /* For each fragment writeout instruction, generate a writeout loop to
2736 * associate with it */
2739 mir_add_writeout_loops(compiler_context
*ctx
)
2741 for (unsigned rt
= 0; rt
< ARRAY_SIZE(ctx
->writeout_branch
); ++rt
) {
2742 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2745 unsigned popped
= br
->branch
.target_block
;
2746 midgard_block_add_successor(mir_get_block(ctx
, popped
- 1), ctx
->current_block
);
2747 br
->branch
.target_block
= emit_fragment_epilogue(ctx
, rt
);
2749 /* If we have more RTs, we'll need to restore back after our
2750 * loop terminates */
2752 if ((rt
+ 1) < ARRAY_SIZE(ctx
->writeout_branch
) && ctx
->writeout_branch
[rt
+ 1]) {
2753 midgard_instruction uncond
= v_branch(false, false);
2754 uncond
.branch
.target_block
= popped
;
2755 emit_mir_instruction(ctx
, uncond
);
2756 midgard_block_add_successor(ctx
->current_block
, mir_get_block(ctx
, popped
));
2757 schedule_barrier(ctx
);
2759 /* We're last, so we can terminate here */
2760 br
->last_writeout
= true;
2766 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
, unsigned blend_rt
, unsigned gpu_id
, bool shaderdb
)
2768 struct util_dynarray
*compiled
= &program
->compiled
;
2770 midgard_debug
= debug_get_option_midgard_debug();
2772 /* TODO: Bound against what? */
2773 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2776 ctx
->stage
= nir
->info
.stage
;
2777 ctx
->is_blend
= is_blend
;
2778 ctx
->alpha_ref
= program
->alpha_ref
;
2779 ctx
->blend_rt
= MIDGARD_COLOR_RT0
+ blend_rt
;
2780 ctx
->quirks
= midgard_get_quirks(gpu_id
);
2782 /* Start off with a safe cutoff, allowing usage of all 16 work
2783 * registers. Later, we'll promote uniform reads to uniform registers
2784 * if we determine it is beneficial to do so */
2785 ctx
->uniform_cutoff
= 8;
2787 /* Initialize at a global (not block) level hash tables */
2789 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2790 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2791 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2793 /* Record the varying mapping for the command stream's bookkeeping */
2795 struct exec_list
*varyings
=
2796 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2798 unsigned max_varying
= 0;
2799 nir_foreach_variable(var
, varyings
) {
2800 unsigned loc
= var
->data
.driver_location
;
2801 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2803 for (int c
= 0; c
< sz
; ++c
) {
2804 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2805 program
->varying_type
[loc
+ c
] = pan_format_from_glsl(var
->type
);
2806 max_varying
= MAX2(max_varying
, loc
+ c
);
2810 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2811 * (so we don't accidentally duplicate the epilogue since mesa/st has
2812 * messed with our I/O quite a bit already) */
2814 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2816 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2817 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2818 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2821 NIR_PASS_V(nir
, nir_lower_var_copies
);
2822 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2823 NIR_PASS_V(nir
, nir_split_var_copies
);
2824 NIR_PASS_V(nir
, nir_lower_var_copies
);
2825 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2826 NIR_PASS_V(nir
, nir_lower_var_copies
);
2827 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2829 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2830 NIR_PASS_V(nir
, midgard_nir_lower_zs_store
);
2832 /* Optimisation passes */
2834 optimise_nir(nir
, ctx
->quirks
);
2836 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2837 nir_print_shader(nir
, stdout
);
2840 /* Assign sysvals and counts, now that we're sure
2841 * (post-optimisation) */
2843 midgard_nir_assign_sysvals(ctx
, nir
);
2845 program
->uniform_count
= nir
->num_uniforms
;
2846 program
->sysval_count
= ctx
->sysval_count
;
2847 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2849 nir_foreach_function(func
, nir
) {
2853 list_inithead(&ctx
->blocks
);
2854 ctx
->block_count
= 0;
2857 emit_cf_list(ctx
, &func
->impl
->body
);
2858 break; /* TODO: Multi-function shaders */
2861 util_dynarray_init(compiled
, NULL
);
2863 /* Per-block lowering before opts */
2865 mir_foreach_block(ctx
, block
) {
2866 inline_alu_constants(ctx
, block
);
2867 midgard_opt_promote_fmov(ctx
, block
);
2868 embedded_to_inline_constant(ctx
, block
);
2870 /* MIR-level optimizations */
2872 bool progress
= false;
2877 mir_foreach_block(ctx
, block
) {
2878 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2879 progress
|= midgard_opt_copy_prop(ctx
, block
);
2880 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2881 progress
|= midgard_opt_combine_projection(ctx
, block
);
2882 progress
|= midgard_opt_varying_projection(ctx
, block
);
2883 progress
|= midgard_opt_not_propagate(ctx
, block
);
2884 progress
|= midgard_opt_fuse_src_invert(ctx
, block
);
2885 progress
|= midgard_opt_fuse_dest_invert(ctx
, block
);
2886 progress
|= midgard_opt_csel_invert(ctx
, block
);
2887 progress
|= midgard_opt_drop_cmp_invert(ctx
, block
);
2888 progress
|= midgard_opt_invert_branch(ctx
, block
);
2892 mir_foreach_block(ctx
, block
) {
2893 midgard_lower_invert(ctx
, block
);
2894 midgard_lower_derivatives(ctx
, block
);
2897 /* Nested control-flow can result in dead branches at the end of the
2898 * block. This messes with our analysis and is just dead code, so cull
2900 mir_foreach_block(ctx
, block
) {
2901 midgard_opt_cull_dead_branch(ctx
, block
);
2904 /* Ensure we were lowered */
2905 mir_foreach_instr_global(ctx
, ins
) {
2906 assert(!ins
->invert
);
2909 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2910 mir_add_writeout_loops(ctx
);
2913 midgard_schedule_program(ctx
);
2916 /* Now that all the bundles are scheduled and we can calculate block
2917 * sizes, emit actual branch instructions rather than placeholders */
2919 int br_block_idx
= 0;
2921 mir_foreach_block(ctx
, block
) {
2922 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2923 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2924 midgard_instruction
*ins
= bundle
->instructions
[c
];
2926 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2928 /* Parse some basic branch info */
2929 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2930 bool is_conditional
= ins
->branch
.conditional
;
2931 bool is_inverted
= ins
->branch
.invert_conditional
;
2932 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2933 bool is_writeout
= ins
->writeout
;
2935 /* Determine the block we're jumping to */
2936 int target_number
= ins
->branch
.target_block
;
2938 /* Report the destination tag */
2939 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2941 /* Count up the number of quadwords we're
2942 * jumping over = number of quadwords until
2943 * (br_block_idx, target_number) */
2945 int quadword_offset
= 0;
2949 } else if (target_number
> br_block_idx
) {
2952 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2953 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2956 quadword_offset
+= blk
->quadword_count
;
2959 /* Jump backwards */
2961 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2962 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2965 quadword_offset
-= blk
->quadword_count
;
2969 /* Unconditional extended branches (far jumps)
2970 * have issues, so we always use a conditional
2971 * branch, setting the condition to always for
2972 * unconditional. For compact unconditional
2973 * branches, cond isn't used so it doesn't
2974 * matter what we pick. */
2976 midgard_condition cond
=
2977 !is_conditional
? midgard_condition_always
:
2978 is_inverted
? midgard_condition_false
:
2979 midgard_condition_true
;
2981 midgard_jmp_writeout_op op
=
2982 is_discard
? midgard_jmp_writeout_op_discard
:
2983 is_writeout
? midgard_jmp_writeout_op_writeout
:
2984 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2985 midgard_jmp_writeout_op_branch_cond
;
2988 midgard_branch_extended branch
=
2989 midgard_create_branch_extended(
2994 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2995 } else if (is_conditional
|| is_discard
) {
2996 midgard_branch_cond branch
= {
2998 .dest_tag
= dest_tag
,
2999 .offset
= quadword_offset
,
3003 assert(branch
.offset
== quadword_offset
);
3005 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3007 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3009 midgard_branch_uncond branch
= {
3011 .dest_tag
= dest_tag
,
3012 .offset
= quadword_offset
,
3016 assert(branch
.offset
== quadword_offset
);
3018 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3026 /* Emit flat binary from the instruction arrays. Iterate each block in
3027 * sequence. Save instruction boundaries such that lookahead tags can
3028 * be assigned easily */
3030 /* Cache _all_ bundles in source order for lookahead across failed branches */
3032 int bundle_count
= 0;
3033 mir_foreach_block(ctx
, block
) {
3034 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3036 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3038 mir_foreach_block(ctx
, block
) {
3039 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3040 source_order_bundles
[bundle_idx
++] = bundle
;
3044 int current_bundle
= 0;
3046 /* Midgard prefetches instruction types, so during emission we
3047 * need to lookahead. Unless this is the last instruction, in
3048 * which we return 1. */
3050 mir_foreach_block(ctx
, block
) {
3051 mir_foreach_bundle_in_block(block
, bundle
) {
3054 if (!bundle
->last_writeout
&& (current_bundle
+ 1 < bundle_count
))
3055 lookahead
= source_order_bundles
[current_bundle
+ 1]->tag
;
3057 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3061 /* TODO: Free deeper */
3062 //util_dynarray_fini(&block->instructions);
3065 free(source_order_bundles
);
3067 /* Report the very first tag executed */
3068 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3070 /* Deal with off-by-one related to the fencepost problem */
3071 program
->work_register_count
= ctx
->work_registers
+ 1;
3072 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3074 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3075 program
->tls_size
= ctx
->tls_size
;
3077 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3078 disassemble_midgard(stdout
, program
->compiled
.data
, program
->compiled
.size
, gpu_id
, ctx
->stage
);
3080 if (midgard_debug
& MIDGARD_DBG_SHADERDB
|| shaderdb
) {
3081 unsigned nr_bundles
= 0, nr_ins
= 0;
3083 /* Count instructions and bundles */
3085 mir_foreach_block(ctx
, block
) {
3086 nr_bundles
+= util_dynarray_num_elements(
3087 &block
->bundles
, midgard_bundle
);
3089 mir_foreach_bundle_in_block(block
, bun
)
3090 nr_ins
+= bun
->instruction_count
;
3093 /* Calculate thread count. There are certain cutoffs by
3094 * register count for thread count */
3096 unsigned nr_registers
= program
->work_register_count
;
3098 unsigned nr_threads
=
3099 (nr_registers
<= 4) ? 4 :
3100 (nr_registers
<= 8) ? 2 :
3105 fprintf(stderr
, "shader%d - %s shader: "
3106 "%u inst, %u bundles, %u quadwords, "
3107 "%u registers, %u threads, %u loops, "
3108 "%u:%u spills:fills\n",
3110 gl_shader_stage_name(ctx
->stage
),
3111 nr_ins
, nr_bundles
, ctx
->quadword_count
,
3112 nr_registers
, nr_threads
,
3114 ctx
->spills
, ctx
->fills
);