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pan/midgard: Pass uploaded midgard_instruction through
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
44
45 #include "midgard.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
49 #include "helpers.h"
50 #include "compiler.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71
72 static bool
73 midgard_is_branch_unit(unsigned unit)
74 {
75 return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
76 }
77
78 static void
79 midgard_block_add_successor(midgard_block *block, midgard_block *successor)
80 {
81 assert(block);
82 assert(successor);
83
84 /* Deduplicate */
85 for (unsigned i = 0; i < block->nr_successors; ++i) {
86 if (block->successors[i] == successor)
87 return;
88 }
89
90 block->successors[block->nr_successors++] = successor;
91 assert(block->nr_successors <= ARRAY_SIZE(block->successors));
92 }
93
94 /* Helpers to generate midgard_instruction's using macro magic, since every
95 * driver seems to do it that way */
96
97 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
98
99 #define M_LOAD_STORE(name, store) \
100 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
101 midgard_instruction i = { \
102 .type = TAG_LOAD_STORE_4, \
103 .mask = 0xF, \
104 .ssa_args = { \
105 .dest = -1, \
106 .src = { -1, -1, -1 }, \
107 }, \
108 .load_store = { \
109 .op = midgard_op_##name, \
110 .swizzle = SWIZZLE_XYZW, \
111 .address = address \
112 } \
113 }; \
114 \
115 if (store) \
116 i.ssa_args.src[0] = ssa; \
117 else \
118 i.ssa_args.dest = ssa; \
119 \
120 return i; \
121 }
122
123 #define M_LOAD(name) M_LOAD_STORE(name, false)
124 #define M_STORE(name) M_LOAD_STORE(name, true)
125
126 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
127 * the corresponding Midgard source */
128
129 static midgard_vector_alu_src
130 vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
131 bool half, bool sext)
132 {
133 if (!src) return blank_alu_src;
134
135 /* Figure out how many components there are so we can adjust the
136 * swizzle. Specifically we want to broadcast the last channel so
137 * things like ball2/3 work
138 */
139
140 if (broadcast_count) {
141 uint8_t last_component = src->swizzle[broadcast_count - 1];
142
143 for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) {
144 src->swizzle[c] = last_component;
145 }
146 }
147
148 midgard_vector_alu_src alu_src = {
149 .rep_low = 0,
150 .rep_high = 0,
151 .half = half,
152 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle)
153 };
154
155 if (is_int) {
156 alu_src.mod = midgard_int_normal;
157
158 /* Sign/zero-extend if needed */
159
160 if (half) {
161 alu_src.mod = sext ?
162 midgard_int_sign_extend
163 : midgard_int_zero_extend;
164 }
165
166 /* These should have been lowered away */
167 assert(!(src->abs || src->negate));
168 } else {
169 alu_src.mod = (src->abs << 0) | (src->negate << 1);
170 }
171
172 return alu_src;
173 }
174
175 /* load/store instructions have both 32-bit and 16-bit variants, depending on
176 * whether we are using vectors composed of highp or mediump. At the moment, we
177 * don't support half-floats -- this requires changes in other parts of the
178 * compiler -- therefore the 16-bit versions are commented out. */
179
180 //M_LOAD(ld_attr_16);
181 M_LOAD(ld_attr_32);
182 //M_LOAD(ld_vary_16);
183 M_LOAD(ld_vary_32);
184 //M_LOAD(ld_uniform_16);
185 M_LOAD(ld_uniform_32);
186 M_LOAD(ld_color_buffer_8);
187 //M_STORE(st_vary_16);
188 M_STORE(st_vary_32);
189 M_LOAD(st_cubemap_coords);
190
191 static midgard_instruction
192 v_alu_br_compact_cond(midgard_jmp_writeout_op op, unsigned tag, signed offset, unsigned cond)
193 {
194 midgard_branch_cond branch = {
195 .op = op,
196 .dest_tag = tag,
197 .offset = offset,
198 .cond = cond
199 };
200
201 uint16_t compact;
202 memcpy(&compact, &branch, sizeof(branch));
203
204 midgard_instruction ins = {
205 .type = TAG_ALU_4,
206 .unit = ALU_ENAB_BR_COMPACT,
207 .prepacked_branch = true,
208 .compact_branch = true,
209 .br_compact = compact,
210 .ssa_args = {
211 .dest = -1,
212 .src = { -1, -1, -1 },
213 }
214 };
215
216 if (op == midgard_jmp_writeout_op_writeout)
217 ins.writeout = true;
218
219 return ins;
220 }
221
222 static midgard_instruction
223 v_branch(bool conditional, bool invert)
224 {
225 midgard_instruction ins = {
226 .type = TAG_ALU_4,
227 .unit = ALU_ENAB_BRANCH,
228 .compact_branch = true,
229 .branch = {
230 .conditional = conditional,
231 .invert_conditional = invert
232 },
233 .ssa_args = {
234 .dest = -1,
235 .src = { -1, -1, -1 },
236 }
237 };
238
239 return ins;
240 }
241
242 static midgard_branch_extended
243 midgard_create_branch_extended( midgard_condition cond,
244 midgard_jmp_writeout_op op,
245 unsigned dest_tag,
246 signed quadword_offset)
247 {
248 /* The condition code is actually a LUT describing a function to
249 * combine multiple condition codes. However, we only support a single
250 * condition code at the moment, so we just duplicate over a bunch of
251 * times. */
252
253 uint16_t duplicated_cond =
254 (cond << 14) |
255 (cond << 12) |
256 (cond << 10) |
257 (cond << 8) |
258 (cond << 6) |
259 (cond << 4) |
260 (cond << 2) |
261 (cond << 0);
262
263 midgard_branch_extended branch = {
264 .op = op,
265 .dest_tag = dest_tag,
266 .offset = quadword_offset,
267 .cond = duplicated_cond
268 };
269
270 return branch;
271 }
272
273 static void
274 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
275 {
276 ins->has_constants = true;
277 memcpy(&ins->constants, constants, 16);
278 }
279
280 static int
281 glsl_type_size(const struct glsl_type *type, bool bindless)
282 {
283 return glsl_count_attribute_slots(type, false);
284 }
285
286 /* Lower fdot2 to a vector multiplication followed by channel addition */
287 static void
288 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
289 {
290 if (alu->op != nir_op_fdot2)
291 return;
292
293 b->cursor = nir_before_instr(&alu->instr);
294
295 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
296 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
297
298 nir_ssa_def *product = nir_fmul(b, src0, src1);
299
300 nir_ssa_def *sum = nir_fadd(b,
301 nir_channel(b, product, 0),
302 nir_channel(b, product, 1));
303
304 /* Replace the fdot2 with this sum */
305 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
306 }
307
308 static int
309 midgard_sysval_for_ssbo(nir_intrinsic_instr *instr)
310 {
311 nir_src index = instr->src[0];
312 assert(nir_src_is_const(index));
313 uint32_t uindex = nir_src_as_uint(index);
314
315 return PAN_SYSVAL(SSBO, uindex);
316 }
317
318 static int
319 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
320 {
321 switch (instr->intrinsic) {
322 case nir_intrinsic_load_viewport_scale:
323 return PAN_SYSVAL_VIEWPORT_SCALE;
324 case nir_intrinsic_load_viewport_offset:
325 return PAN_SYSVAL_VIEWPORT_OFFSET;
326 case nir_intrinsic_load_ssbo:
327 return midgard_sysval_for_ssbo(instr);
328 default:
329 return -1;
330 }
331 }
332
333 static int sysval_for_instr(compiler_context *ctx, nir_instr *instr,
334 unsigned *dest)
335 {
336 nir_intrinsic_instr *intr;
337 nir_dest *dst = NULL;
338 nir_tex_instr *tex;
339 int sysval = -1;
340
341 switch (instr->type) {
342 case nir_instr_type_intrinsic:
343 intr = nir_instr_as_intrinsic(instr);
344 sysval = midgard_nir_sysval_for_intrinsic(intr);
345 dst = &intr->dest;
346 break;
347 case nir_instr_type_tex:
348 tex = nir_instr_as_tex(instr);
349 if (tex->op != nir_texop_txs)
350 break;
351
352 sysval = PAN_SYSVAL(TEXTURE_SIZE,
353 PAN_TXS_SYSVAL_ID(tex->texture_index,
354 nir_tex_instr_dest_size(tex) -
355 (tex->is_array ? 1 : 0),
356 tex->is_array));
357 dst = &tex->dest;
358 break;
359 default:
360 break;
361 }
362
363 if (dest && dst)
364 *dest = nir_dest_index(ctx, dst);
365
366 return sysval;
367 }
368
369 static void
370 midgard_nir_assign_sysval_body(compiler_context *ctx, nir_instr *instr)
371 {
372 int sysval;
373
374 sysval = sysval_for_instr(ctx, instr, NULL);
375 if (sysval < 0)
376 return;
377
378 /* We have a sysval load; check if it's already been assigned */
379
380 if (_mesa_hash_table_u64_search(ctx->sysval_to_id, sysval))
381 return;
382
383 /* It hasn't -- so assign it now! */
384
385 unsigned id = ctx->sysval_count++;
386 _mesa_hash_table_u64_insert(ctx->sysval_to_id, sysval, (void *) ((uintptr_t) id + 1));
387 ctx->sysvals[id] = sysval;
388 }
389
390 static void
391 midgard_nir_assign_sysvals(compiler_context *ctx, nir_shader *shader)
392 {
393 ctx->sysval_count = 0;
394
395 nir_foreach_function(function, shader) {
396 if (!function->impl) continue;
397
398 nir_foreach_block(block, function->impl) {
399 nir_foreach_instr_safe(instr, block) {
400 midgard_nir_assign_sysval_body(ctx, instr);
401 }
402 }
403 }
404 }
405
406 static bool
407 midgard_nir_lower_fdot2(nir_shader *shader)
408 {
409 bool progress = false;
410
411 nir_foreach_function(function, shader) {
412 if (!function->impl) continue;
413
414 nir_builder _b;
415 nir_builder *b = &_b;
416 nir_builder_init(b, function->impl);
417
418 nir_foreach_block(block, function->impl) {
419 nir_foreach_instr_safe(instr, block) {
420 if (instr->type != nir_instr_type_alu) continue;
421
422 nir_alu_instr *alu = nir_instr_as_alu(instr);
423 midgard_nir_lower_fdot2_body(b, alu);
424
425 progress |= true;
426 }
427 }
428
429 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
430
431 }
432
433 return progress;
434 }
435
436 /* Flushes undefined values to zero */
437
438 static void
439 optimise_nir(nir_shader *nir)
440 {
441 bool progress;
442 unsigned lower_flrp =
443 (nir->options->lower_flrp16 ? 16 : 0) |
444 (nir->options->lower_flrp32 ? 32 : 0) |
445 (nir->options->lower_flrp64 ? 64 : 0);
446
447 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
448 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
449 NIR_PASS(progress, nir, nir_lower_idiv);
450
451 nir_lower_tex_options lower_tex_1st_pass_options = {
452 .lower_rect = true,
453 .lower_txp = ~0
454 };
455
456 nir_lower_tex_options lower_tex_2nd_pass_options = {
457 .lower_txs_lod = true,
458 };
459
460 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_1st_pass_options);
461 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_2nd_pass_options);
462
463 do {
464 progress = false;
465
466 NIR_PASS(progress, nir, nir_lower_var_copies);
467 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
468
469 NIR_PASS(progress, nir, nir_copy_prop);
470 NIR_PASS(progress, nir, nir_opt_dce);
471 NIR_PASS(progress, nir, nir_opt_dead_cf);
472 NIR_PASS(progress, nir, nir_opt_cse);
473 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
474 NIR_PASS(progress, nir, nir_opt_algebraic);
475 NIR_PASS(progress, nir, nir_opt_constant_folding);
476
477 if (lower_flrp != 0) {
478 bool lower_flrp_progress = false;
479 NIR_PASS(lower_flrp_progress,
480 nir,
481 nir_lower_flrp,
482 lower_flrp,
483 false /* always_precise */,
484 nir->options->lower_ffma);
485 if (lower_flrp_progress) {
486 NIR_PASS(progress, nir,
487 nir_opt_constant_folding);
488 progress = true;
489 }
490
491 /* Nothing should rematerialize any flrps, so we only
492 * need to do this lowering once.
493 */
494 lower_flrp = 0;
495 }
496
497 NIR_PASS(progress, nir, nir_opt_undef);
498 NIR_PASS(progress, nir, nir_undef_to_zero);
499
500 NIR_PASS(progress, nir, nir_opt_loop_unroll,
501 nir_var_shader_in |
502 nir_var_shader_out |
503 nir_var_function_temp);
504
505 NIR_PASS(progress, nir, nir_opt_vectorize);
506 } while (progress);
507
508 /* Must be run at the end to prevent creation of fsin/fcos ops */
509 NIR_PASS(progress, nir, midgard_nir_scale_trig);
510
511 do {
512 progress = false;
513
514 NIR_PASS(progress, nir, nir_opt_dce);
515 NIR_PASS(progress, nir, nir_opt_algebraic);
516 NIR_PASS(progress, nir, nir_opt_constant_folding);
517 NIR_PASS(progress, nir, nir_copy_prop);
518 } while (progress);
519
520 NIR_PASS(progress, nir, nir_opt_algebraic_late);
521
522 /* We implement booleans as 32-bit 0/~0 */
523 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
524
525 /* Now that booleans are lowered, we can run out late opts */
526 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
527
528 /* Lower mods for float ops only. Integer ops don't support modifiers
529 * (saturate doesn't make sense on integers, neg/abs require dedicated
530 * instructions) */
531
532 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
533 NIR_PASS(progress, nir, nir_copy_prop);
534 NIR_PASS(progress, nir, nir_opt_dce);
535
536 /* Take us out of SSA */
537 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
538 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
539
540 /* We are a vector architecture; write combine where possible */
541 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
542 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
543
544 NIR_PASS(progress, nir, nir_opt_dce);
545 }
546
547 /* Do not actually emit a load; instead, cache the constant for inlining */
548
549 static void
550 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
551 {
552 nir_ssa_def def = instr->def;
553
554 float *v = rzalloc_array(NULL, float, 4);
555 nir_const_load_to_arr(v, instr, f32);
556
557 /* Shifted for SSA, +1 for off-by-one */
558 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, v);
559 }
560
561 /* Normally constants are embedded implicitly, but for I/O and such we have to
562 * explicitly emit a move with the constant source */
563
564 static void
565 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
566 {
567 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
568
569 if (constant_value) {
570 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, to);
571 attach_constants(ctx, &ins, constant_value, node + 1);
572 emit_mir_instruction(ctx, ins);
573 }
574 }
575
576 static bool
577 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
578 {
579 unsigned comp = src->swizzle[0];
580
581 for (unsigned c = 1; c < nr_components; ++c) {
582 if (src->swizzle[c] != comp)
583 return true;
584 }
585
586 return false;
587 }
588
589 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
590 * output of a conditional test) into that register */
591
592 static void
593 emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned component)
594 {
595 int condition = nir_src_index(ctx, src);
596
597 /* Source to swizzle the desired component into w */
598
599 const midgard_vector_alu_src alu_src = {
600 .swizzle = SWIZZLE(component, component, component, component),
601 };
602
603 /* There is no boolean move instruction. Instead, we simulate a move by
604 * ANDing the condition with itself to get it into r31.w */
605
606 midgard_instruction ins = {
607 .type = TAG_ALU_4,
608
609 /* We need to set the conditional as close as possible */
610 .precede_break = true,
611 .unit = for_branch ? UNIT_SMUL : UNIT_SADD,
612 .mask = 1 << COMPONENT_W,
613
614 .ssa_args = {
615 .src = { condition, condition, -1 },
616 .dest = SSA_FIXED_REGISTER(31),
617 },
618
619 .alu = {
620 .op = midgard_alu_op_iand,
621 .outmod = midgard_outmod_int_wrap,
622 .reg_mode = midgard_reg_mode_32,
623 .dest_override = midgard_dest_override_none,
624 .src1 = vector_alu_srco_unsigned(alu_src),
625 .src2 = vector_alu_srco_unsigned(alu_src)
626 },
627 };
628
629 emit_mir_instruction(ctx, ins);
630 }
631
632 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
633 * r31 instead */
634
635 static void
636 emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp)
637 {
638 int condition = nir_src_index(ctx, &src->src);
639
640 /* Source to swizzle the desired component into w */
641
642 const midgard_vector_alu_src alu_src = {
643 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle),
644 };
645
646 /* There is no boolean move instruction. Instead, we simulate a move by
647 * ANDing the condition with itself to get it into r31.w */
648
649 midgard_instruction ins = {
650 .type = TAG_ALU_4,
651 .precede_break = true,
652 .mask = mask_of(nr_comp),
653 .ssa_args = {
654 .src = { condition, condition, -1 },
655 .dest = SSA_FIXED_REGISTER(31),
656 },
657 .alu = {
658 .op = midgard_alu_op_iand,
659 .outmod = midgard_outmod_int_wrap,
660 .reg_mode = midgard_reg_mode_32,
661 .dest_override = midgard_dest_override_none,
662 .src1 = vector_alu_srco_unsigned(alu_src),
663 .src2 = vector_alu_srco_unsigned(alu_src)
664 },
665 };
666
667 emit_mir_instruction(ctx, ins);
668 }
669
670 #define ALU_CASE(nir, _op) \
671 case nir_op_##nir: \
672 op = midgard_alu_op_##_op; \
673 assert(src_bitsize == dst_bitsize); \
674 break;
675
676 #define ALU_CASE_BCAST(nir, _op, count) \
677 case nir_op_##nir: \
678 op = midgard_alu_op_##_op; \
679 broadcast_swizzle = count; \
680 assert(src_bitsize == dst_bitsize); \
681 break;
682 static bool
683 nir_is_fzero_constant(nir_src src)
684 {
685 if (!nir_src_is_const(src))
686 return false;
687
688 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
689 if (nir_src_comp_as_float(src, c) != 0.0)
690 return false;
691 }
692
693 return true;
694 }
695
696 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
697 * special treatment override this anyway. */
698
699 static midgard_reg_mode
700 reg_mode_for_nir(nir_alu_instr *instr)
701 {
702 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
703
704 switch (src_bitsize) {
705 case 8:
706 return midgard_reg_mode_8;
707 case 16:
708 return midgard_reg_mode_16;
709 case 32:
710 return midgard_reg_mode_32;
711 case 64:
712 return midgard_reg_mode_64;
713 default:
714 unreachable("Invalid bit size");
715 }
716 }
717
718 static void
719 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
720 {
721 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
722 * is handled elsewhere */
723
724 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
725 midgard_emit_derivatives(ctx, instr);
726 return;
727 }
728
729 bool is_ssa = instr->dest.dest.is_ssa;
730
731 unsigned dest = nir_dest_index(ctx, &instr->dest.dest);
732 unsigned nr_components = nir_dest_num_components(instr->dest.dest);
733 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
734
735 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
736 * supported. A few do not and are commented for now. Also, there are a
737 * number of NIR ops which Midgard does not support and need to be
738 * lowered, also TODO. This switch block emits the opcode and calling
739 * convention of the Midgard instruction; actual packing is done in
740 * emit_alu below */
741
742 unsigned op;
743
744 /* Number of components valid to check for the instruction (the rest
745 * will be forced to the last), or 0 to use as-is. Relevant as
746 * ball-type instructions have a channel count in NIR but are all vec4
747 * in Midgard */
748
749 unsigned broadcast_swizzle = 0;
750
751 /* What register mode should we operate in? */
752 midgard_reg_mode reg_mode =
753 reg_mode_for_nir(instr);
754
755 /* Do we need a destination override? Used for inline
756 * type conversion */
757
758 midgard_dest_override dest_override =
759 midgard_dest_override_none;
760
761 /* Should we use a smaller respective source and sign-extend? */
762
763 bool half_1 = false, sext_1 = false;
764 bool half_2 = false, sext_2 = false;
765
766 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
767 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
768
769 switch (instr->op) {
770 ALU_CASE(fadd, fadd);
771 ALU_CASE(fmul, fmul);
772 ALU_CASE(fmin, fmin);
773 ALU_CASE(fmax, fmax);
774 ALU_CASE(imin, imin);
775 ALU_CASE(imax, imax);
776 ALU_CASE(umin, umin);
777 ALU_CASE(umax, umax);
778 ALU_CASE(ffloor, ffloor);
779 ALU_CASE(fround_even, froundeven);
780 ALU_CASE(ftrunc, ftrunc);
781 ALU_CASE(fceil, fceil);
782 ALU_CASE(fdot3, fdot3);
783 ALU_CASE(fdot4, fdot4);
784 ALU_CASE(iadd, iadd);
785 ALU_CASE(isub, isub);
786 ALU_CASE(imul, imul);
787
788 /* Zero shoved as second-arg */
789 ALU_CASE(iabs, iabsdiff);
790
791 ALU_CASE(mov, imov);
792
793 ALU_CASE(feq32, feq);
794 ALU_CASE(fne32, fne);
795 ALU_CASE(flt32, flt);
796 ALU_CASE(ieq32, ieq);
797 ALU_CASE(ine32, ine);
798 ALU_CASE(ilt32, ilt);
799 ALU_CASE(ult32, ult);
800
801 /* We don't have a native b2f32 instruction. Instead, like many
802 * GPUs, we exploit booleans as 0/~0 for false/true, and
803 * correspondingly AND
804 * by 1.0 to do the type conversion. For the moment, prime us
805 * to emit:
806 *
807 * iand [whatever], #0
808 *
809 * At the end of emit_alu (as MIR), we'll fix-up the constant
810 */
811
812 ALU_CASE(b2f32, iand);
813 ALU_CASE(b2i32, iand);
814
815 /* Likewise, we don't have a dedicated f2b32 instruction, but
816 * we can do a "not equal to 0.0" test. */
817
818 ALU_CASE(f2b32, fne);
819 ALU_CASE(i2b32, ine);
820
821 ALU_CASE(frcp, frcp);
822 ALU_CASE(frsq, frsqrt);
823 ALU_CASE(fsqrt, fsqrt);
824 ALU_CASE(fexp2, fexp2);
825 ALU_CASE(flog2, flog2);
826
827 ALU_CASE(f2i32, f2i_rtz);
828 ALU_CASE(f2u32, f2u_rtz);
829 ALU_CASE(i2f32, i2f_rtz);
830 ALU_CASE(u2f32, u2f_rtz);
831
832 ALU_CASE(f2i16, f2i_rtz);
833 ALU_CASE(f2u16, f2u_rtz);
834 ALU_CASE(i2f16, i2f_rtz);
835 ALU_CASE(u2f16, u2f_rtz);
836
837 ALU_CASE(fsin, fsin);
838 ALU_CASE(fcos, fcos);
839
840 /* We'll set invert */
841 ALU_CASE(inot, imov);
842 ALU_CASE(iand, iand);
843 ALU_CASE(ior, ior);
844 ALU_CASE(ixor, ixor);
845 ALU_CASE(ishl, ishl);
846 ALU_CASE(ishr, iasr);
847 ALU_CASE(ushr, ilsr);
848
849 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
850 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
851 ALU_CASE(b32all_fequal4, fball_eq);
852
853 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
854 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
855 ALU_CASE(b32any_fnequal4, fbany_neq);
856
857 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
858 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
859 ALU_CASE(b32all_iequal4, iball_eq);
860
861 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
862 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
863 ALU_CASE(b32any_inequal4, ibany_neq);
864
865 /* Source mods will be shoved in later */
866 ALU_CASE(fabs, fmov);
867 ALU_CASE(fneg, fmov);
868 ALU_CASE(fsat, fmov);
869
870 /* For size conversion, we use a move. Ideally though we would squash
871 * these ops together; maybe that has to happen after in NIR as part of
872 * propagation...? An earlier algebraic pass ensured we step down by
873 * only / exactly one size. If stepping down, we use a dest override to
874 * reduce the size; if stepping up, we use a larger-sized move with a
875 * half source and a sign/zero-extension modifier */
876
877 case nir_op_i2i8:
878 case nir_op_i2i16:
879 case nir_op_i2i32:
880 /* If we end up upscale, we'll need a sign-extend on the
881 * operand (the second argument) */
882
883 sext_2 = true;
884 case nir_op_u2u8:
885 case nir_op_u2u16:
886 case nir_op_u2u32: {
887 op = midgard_alu_op_imov;
888
889 if (dst_bitsize == (src_bitsize * 2)) {
890 /* Converting up */
891 half_2 = true;
892
893 /* Use a greater register mode */
894 reg_mode++;
895 } else if (src_bitsize == (dst_bitsize * 2)) {
896 /* Converting down */
897 dest_override = midgard_dest_override_lower;
898 }
899
900 break;
901 }
902
903 case nir_op_f2f16: {
904 assert(src_bitsize == 32);
905
906 op = midgard_alu_op_fmov;
907 dest_override = midgard_dest_override_lower;
908 break;
909 }
910
911 case nir_op_f2f32: {
912 assert(src_bitsize == 16);
913
914 op = midgard_alu_op_fmov;
915 half_2 = true;
916 reg_mode++;
917 break;
918 }
919
920
921 /* For greater-or-equal, we lower to less-or-equal and flip the
922 * arguments */
923
924 case nir_op_fge:
925 case nir_op_fge32:
926 case nir_op_ige32:
927 case nir_op_uge32: {
928 op =
929 instr->op == nir_op_fge ? midgard_alu_op_fle :
930 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
931 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
932 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
933 0;
934
935 /* Swap via temporary */
936 nir_alu_src temp = instr->src[1];
937 instr->src[1] = instr->src[0];
938 instr->src[0] = temp;
939
940 break;
941 }
942
943 case nir_op_b32csel: {
944 /* Midgard features both fcsel and icsel, depending on
945 * the type of the arguments/output. However, as long
946 * as we're careful we can _always_ use icsel and
947 * _never_ need fcsel, since the latter does additional
948 * floating-point-specific processing whereas the
949 * former just moves bits on the wire. It's not obvious
950 * why these are separate opcodes, save for the ability
951 * to do things like sat/pos/abs/neg for free */
952
953 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
954 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
955
956 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
957 nr_inputs = 2;
958
959 /* Emit the condition into r31 */
960
961 if (mixed)
962 emit_condition_mixed(ctx, &instr->src[0], nr_components);
963 else
964 emit_condition(ctx, &instr->src[0].src, false, instr->src[0].swizzle[0]);
965
966 /* The condition is the first argument; move the other
967 * arguments up one to be a binary instruction for
968 * Midgard */
969
970 memmove(instr->src, instr->src + 1, 2 * sizeof(nir_alu_src));
971 break;
972 }
973
974 default:
975 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
976 assert(0);
977 return;
978 }
979
980 /* Midgard can perform certain modifiers on output of an ALU op */
981 unsigned outmod;
982
983 if (midgard_is_integer_out_op(op)) {
984 outmod = midgard_outmod_int_wrap;
985 } else {
986 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
987 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
988 }
989
990 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
991
992 if (instr->op == nir_op_fmax) {
993 if (nir_is_fzero_constant(instr->src[0].src)) {
994 op = midgard_alu_op_fmov;
995 nr_inputs = 1;
996 outmod = midgard_outmod_pos;
997 instr->src[0] = instr->src[1];
998 } else if (nir_is_fzero_constant(instr->src[1].src)) {
999 op = midgard_alu_op_fmov;
1000 nr_inputs = 1;
1001 outmod = midgard_outmod_pos;
1002 }
1003 }
1004
1005 /* Fetch unit, quirks, etc information */
1006 unsigned opcode_props = alu_opcode_props[op].props;
1007 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
1008
1009 /* src0 will always exist afaik, but src1 will not for 1-argument
1010 * instructions. The latter can only be fetched if the instruction
1011 * needs it, or else we may segfault. */
1012
1013 unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
1014 unsigned src1 = nr_inputs == 2 ? nir_alu_src_index(ctx, &instr->src[1]) : SSA_UNUSED_0;
1015
1016 /* Rather than use the instruction generation helpers, we do it
1017 * ourselves here to avoid the mess */
1018
1019 midgard_instruction ins = {
1020 .type = TAG_ALU_4,
1021 .ssa_args = {
1022 .src = {
1023 quirk_flipped_r24 ? SSA_UNUSED_1 : src0,
1024 quirk_flipped_r24 ? src0 : src1,
1025 -1
1026 },
1027 .dest = dest,
1028 }
1029 };
1030
1031 nir_alu_src *nirmods[2] = { NULL };
1032
1033 if (nr_inputs == 2) {
1034 nirmods[0] = &instr->src[0];
1035 nirmods[1] = &instr->src[1];
1036 } else if (nr_inputs == 1) {
1037 nirmods[quirk_flipped_r24] = &instr->src[0];
1038 } else {
1039 assert(0);
1040 }
1041
1042 /* These were lowered to a move, so apply the corresponding mod */
1043
1044 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1045 nir_alu_src *s = nirmods[quirk_flipped_r24];
1046
1047 if (instr->op == nir_op_fneg)
1048 s->negate = !s->negate;
1049
1050 if (instr->op == nir_op_fabs)
1051 s->abs = !s->abs;
1052 }
1053
1054 bool is_int = midgard_is_integer_op(op);
1055
1056 ins.mask = mask_of(nr_components);
1057
1058 midgard_vector_alu alu = {
1059 .op = op,
1060 .reg_mode = reg_mode,
1061 .dest_override = dest_override,
1062 .outmod = outmod,
1063
1064 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)),
1065 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)),
1066 };
1067
1068 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1069
1070 if (!is_ssa)
1071 ins.mask &= instr->dest.write_mask;
1072
1073 ins.alu = alu;
1074
1075 /* Late fixup for emulated instructions */
1076
1077 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1078 /* Presently, our second argument is an inline #0 constant.
1079 * Switch over to an embedded 1.0 constant (that can't fit
1080 * inline, since we're 32-bit, not 16-bit like the inline
1081 * constants) */
1082
1083 ins.ssa_args.inline_constant = false;
1084 ins.ssa_args.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1085 ins.has_constants = true;
1086
1087 if (instr->op == nir_op_b2f32) {
1088 ins.constants[0] = 1.0f;
1089 } else {
1090 /* Type pun it into place */
1091 uint32_t one = 0x1;
1092 memcpy(&ins.constants[0], &one, sizeof(uint32_t));
1093 }
1094
1095 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
1096 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1097 /* Lots of instructions need a 0 plonked in */
1098 ins.ssa_args.inline_constant = false;
1099 ins.ssa_args.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1100 ins.has_constants = true;
1101 ins.constants[0] = 0.0f;
1102 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
1103 } else if (instr->op == nir_op_inot) {
1104 ins.invert = true;
1105 }
1106
1107 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1108 /* To avoid duplicating the lookup tables (probably), true LUT
1109 * instructions can only operate as if they were scalars. Lower
1110 * them here by changing the component. */
1111
1112 uint8_t original_swizzle[4];
1113 memcpy(original_swizzle, nirmods[0]->swizzle, sizeof(nirmods[0]->swizzle));
1114 unsigned orig_mask = ins.mask;
1115
1116 for (int i = 0; i < nr_components; ++i) {
1117 /* Mask the associated component, dropping the
1118 * instruction if needed */
1119
1120 ins.mask = 1 << i;
1121 ins.mask &= orig_mask;
1122
1123 if (!ins.mask)
1124 continue;
1125
1126 for (int j = 0; j < 4; ++j)
1127 nirmods[0]->swizzle[j] = original_swizzle[i]; /* Pull from the correct component */
1128
1129 ins.alu.src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, false));
1130 emit_mir_instruction(ctx, ins);
1131 }
1132 } else {
1133 emit_mir_instruction(ctx, ins);
1134 }
1135 }
1136
1137 #undef ALU_CASE
1138
1139 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1140 * optimized) versions of UBO #0 */
1141
1142 midgard_instruction *
1143 emit_ubo_read(
1144 compiler_context *ctx,
1145 unsigned dest,
1146 unsigned offset,
1147 nir_src *indirect_offset,
1148 unsigned index)
1149 {
1150 /* TODO: half-floats */
1151
1152 midgard_instruction ins = m_ld_uniform_32(dest, offset);
1153
1154 /* TODO: Don't split */
1155 ins.load_store.varying_parameters = (offset & 7) << 7;
1156 ins.load_store.address = offset >> 3;
1157
1158 if (indirect_offset) {
1159 ins.ssa_args.src[1] = nir_src_index(ctx, indirect_offset);
1160 ins.load_store.arg_2 = 0x80;
1161 } else {
1162 ins.load_store.arg_2 = 0x1E;
1163 }
1164
1165 ins.load_store.arg_1 = index;
1166
1167 return emit_mir_instruction(ctx, ins);
1168 }
1169
1170 static void
1171 emit_varying_read(
1172 compiler_context *ctx,
1173 unsigned dest, unsigned offset,
1174 unsigned nr_comp, unsigned component,
1175 nir_src *indirect_offset, nir_alu_type type)
1176 {
1177 /* XXX: Half-floats? */
1178 /* TODO: swizzle, mask */
1179
1180 midgard_instruction ins = m_ld_vary_32(dest, offset);
1181 ins.mask = mask_of(nr_comp);
1182 ins.load_store.swizzle = SWIZZLE_XYZW >> (2 * component);
1183
1184 midgard_varying_parameter p = {
1185 .is_varying = 1,
1186 .interpolation = midgard_interp_default,
1187 .flat = /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1188 };
1189
1190 unsigned u;
1191 memcpy(&u, &p, sizeof(p));
1192 ins.load_store.varying_parameters = u;
1193
1194 if (indirect_offset)
1195 ins.ssa_args.src[1] = nir_src_index(ctx, indirect_offset);
1196 else
1197 ins.load_store.arg_2 = 0x1E;
1198
1199 ins.load_store.arg_1 = 0x9E;
1200
1201 /* Use the type appropriate load */
1202 switch (type) {
1203 case nir_type_uint:
1204 case nir_type_bool:
1205 ins.load_store.op = midgard_op_ld_vary_32u;
1206 break;
1207 case nir_type_int:
1208 ins.load_store.op = midgard_op_ld_vary_32i;
1209 break;
1210 case nir_type_float:
1211 ins.load_store.op = midgard_op_ld_vary_32;
1212 break;
1213 default:
1214 unreachable("Attempted to load unknown type");
1215 break;
1216 }
1217
1218 emit_mir_instruction(ctx, ins);
1219 }
1220
1221 void
1222 emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override)
1223 {
1224 unsigned dest = 0;
1225
1226 /* Figure out which uniform this is */
1227 int sysval = sysval_for_instr(ctx, instr, &dest);
1228 void *val = _mesa_hash_table_u64_search(ctx->sysval_to_id, sysval);
1229
1230 if (dest_override >= 0)
1231 dest = dest_override;
1232
1233 /* Sysvals are prefix uniforms */
1234 unsigned uniform = ((uintptr_t) val) - 1;
1235
1236 /* Emit the read itself -- this is never indirect */
1237 emit_ubo_read(ctx, dest, uniform, NULL, 0);
1238 }
1239
1240 static void
1241 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1242 {
1243 unsigned offset = 0, reg;
1244
1245 switch (instr->intrinsic) {
1246 case nir_intrinsic_discard_if:
1247 emit_condition(ctx, &instr->src[0], true, COMPONENT_X);
1248
1249 /* fallthrough */
1250
1251 case nir_intrinsic_discard: {
1252 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1253 struct midgard_instruction discard = v_branch(conditional, false);
1254 discard.branch.target_type = TARGET_DISCARD;
1255 emit_mir_instruction(ctx, discard);
1256 break;
1257 }
1258
1259 case nir_intrinsic_load_uniform:
1260 case nir_intrinsic_load_ubo:
1261 case nir_intrinsic_load_input: {
1262 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1263 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1264
1265 /* Get the base type of the intrinsic */
1266 /* TODO: Infer type? Does it matter? */
1267 nir_alu_type t =
1268 is_ubo ? nir_type_uint : nir_intrinsic_type(instr);
1269 t = nir_alu_type_get_base_type(t);
1270
1271 if (!is_ubo) {
1272 offset = nir_intrinsic_base(instr);
1273 }
1274
1275 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1276
1277 nir_src *src_offset = nir_get_io_offset_src(instr);
1278
1279 bool direct = nir_src_is_const(*src_offset);
1280
1281 if (direct)
1282 offset += nir_src_as_uint(*src_offset);
1283
1284 /* We may need to apply a fractional offset */
1285 int component = instr->intrinsic == nir_intrinsic_load_input ?
1286 nir_intrinsic_component(instr) : 0;
1287 reg = nir_dest_index(ctx, &instr->dest);
1288
1289 if (is_uniform && !ctx->is_blend) {
1290 emit_ubo_read(ctx, reg, ctx->sysval_count + offset, !direct ? &instr->src[0] : NULL, 0);
1291 } else if (is_ubo) {
1292 nir_src index = instr->src[0];
1293
1294 /* We don't yet support indirect UBOs. For indirect
1295 * block numbers (if that's possible), we don't know
1296 * enough about the hardware yet. For indirect sources,
1297 * we know what we need but we need to add some NIR
1298 * support for lowering correctly with respect to
1299 * 128-bit reads */
1300
1301 assert(nir_src_is_const(index));
1302 assert(nir_src_is_const(*src_offset));
1303
1304 /* TODO: Alignment */
1305 assert((offset & 0xF) == 0);
1306
1307 uint32_t uindex = nir_src_as_uint(index) + 1;
1308 emit_ubo_read(ctx, reg, offset / 16, NULL, uindex);
1309 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1310 emit_varying_read(ctx, reg, offset, nr_comp, component, !direct ? &instr->src[0] : NULL, t);
1311 } else if (ctx->is_blend) {
1312 /* For blend shaders, load the input color, which is
1313 * preloaded to r0 */
1314
1315 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), blank_alu_src, reg);
1316 emit_mir_instruction(ctx, move);
1317 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1318 midgard_instruction ins = m_ld_attr_32(reg, offset);
1319 ins.load_store.arg_1 = 0x1E;
1320 ins.load_store.arg_2 = 0x1E;
1321 ins.mask = mask_of(nr_comp);
1322
1323 /* Use the type appropriate load */
1324 switch (t) {
1325 case nir_type_uint:
1326 case nir_type_bool:
1327 ins.load_store.op = midgard_op_ld_attr_32u;
1328 break;
1329 case nir_type_int:
1330 ins.load_store.op = midgard_op_ld_attr_32i;
1331 break;
1332 case nir_type_float:
1333 ins.load_store.op = midgard_op_ld_attr_32;
1334 break;
1335 default:
1336 unreachable("Attempted to load unknown type");
1337 break;
1338 }
1339
1340 emit_mir_instruction(ctx, ins);
1341 } else {
1342 DBG("Unknown load\n");
1343 assert(0);
1344 }
1345
1346 break;
1347 }
1348
1349 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1350
1351 case nir_intrinsic_load_raw_output_pan:
1352 reg = nir_dest_index(ctx, &instr->dest);
1353 assert(ctx->is_blend);
1354
1355 midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
1356 emit_mir_instruction(ctx, ins);
1357 break;
1358
1359 case nir_intrinsic_load_blend_const_color_rgba: {
1360 assert(ctx->is_blend);
1361 reg = nir_dest_index(ctx, &instr->dest);
1362
1363 /* Blend constants are embedded directly in the shader and
1364 * patched in, so we use some magic routing */
1365
1366 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, reg);
1367 ins.has_constants = true;
1368 ins.has_blend_constant = true;
1369 emit_mir_instruction(ctx, ins);
1370 break;
1371 }
1372
1373 case nir_intrinsic_store_output:
1374 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1375
1376 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1377
1378 reg = nir_src_index(ctx, &instr->src[0]);
1379
1380 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1381 /* gl_FragColor is not emitted with load/store
1382 * instructions. Instead, it gets plonked into
1383 * r0 at the end of the shader and we do the
1384 * framebuffer writeout dance. TODO: Defer
1385 * writes */
1386
1387 midgard_instruction move = v_mov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1388 emit_mir_instruction(ctx, move);
1389
1390 /* Save the index we're writing to for later reference
1391 * in the epilogue */
1392
1393 ctx->fragment_output = reg;
1394 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1395 /* We should have been vectorized, though we don't
1396 * currently check that st_vary is emitted only once
1397 * per slot (this is relevant, since there's not a mask
1398 * parameter available on the store [set to 0 by the
1399 * blob]). We do respect the component by adjusting the
1400 * swizzle. If this is a constant source, we'll need to
1401 * emit that explicitly. */
1402
1403 emit_explicit_constant(ctx, reg, reg);
1404
1405 unsigned component = nir_intrinsic_component(instr);
1406
1407 midgard_instruction st = m_st_vary_32(reg, offset);
1408 st.load_store.arg_1 = 0x9E;
1409 st.load_store.arg_2 = 0x1E;
1410 st.load_store.swizzle = SWIZZLE_XYZW << (2*component);
1411 emit_mir_instruction(ctx, st);
1412 } else {
1413 DBG("Unknown store\n");
1414 assert(0);
1415 }
1416
1417 break;
1418
1419 /* Special case of store_output for lowered blend shaders */
1420 case nir_intrinsic_store_raw_output_pan:
1421 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1422 reg = nir_src_index(ctx, &instr->src[0]);
1423
1424 midgard_instruction move = v_mov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1425 emit_mir_instruction(ctx, move);
1426 ctx->fragment_output = reg;
1427
1428 break;
1429
1430 case nir_intrinsic_load_alpha_ref_float:
1431 assert(instr->dest.is_ssa);
1432
1433 float ref_value = ctx->alpha_ref;
1434
1435 /* See emit_load_const */
1436 float *v = ralloc_array(NULL, float, 4);
1437 memcpy(v, &ref_value, sizeof(float));
1438 _mesa_hash_table_u64_insert(ctx->ssa_constants, (instr->dest.ssa.index << 1) + 1, v);
1439 break;
1440
1441 case nir_intrinsic_load_viewport_scale:
1442 case nir_intrinsic_load_viewport_offset:
1443 emit_sysval_read(ctx, &instr->instr, -1);
1444 break;
1445
1446 default:
1447 printf ("Unhandled intrinsic\n");
1448 assert(0);
1449 break;
1450 }
1451 }
1452
1453 static unsigned
1454 midgard_tex_format(enum glsl_sampler_dim dim)
1455 {
1456 switch (dim) {
1457 case GLSL_SAMPLER_DIM_1D:
1458 case GLSL_SAMPLER_DIM_BUF:
1459 return MALI_TEX_1D;
1460
1461 case GLSL_SAMPLER_DIM_2D:
1462 case GLSL_SAMPLER_DIM_EXTERNAL:
1463 return MALI_TEX_2D;
1464
1465 case GLSL_SAMPLER_DIM_3D:
1466 return MALI_TEX_3D;
1467
1468 case GLSL_SAMPLER_DIM_CUBE:
1469 return MALI_TEX_CUBE;
1470
1471 default:
1472 DBG("Unknown sampler dim type\n");
1473 assert(0);
1474 return 0;
1475 }
1476 }
1477
1478 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1479 * was successful */
1480
1481 static bool
1482 pan_attach_constant_bias(
1483 compiler_context *ctx,
1484 nir_src lod,
1485 midgard_texture_word *word)
1486 {
1487 /* To attach as constant, it has to *be* constant */
1488
1489 if (!nir_src_is_const(lod))
1490 return false;
1491
1492 float f = nir_src_as_float(lod);
1493
1494 /* Break into fixed-point */
1495 signed lod_int = f;
1496 float lod_frac = f - lod_int;
1497
1498 /* Carry over negative fractions */
1499 if (lod_frac < 0.0) {
1500 lod_int--;
1501 lod_frac += 1.0;
1502 }
1503
1504 /* Encode */
1505 word->bias = float_to_ubyte(lod_frac);
1506 word->bias_int = lod_int;
1507
1508 return true;
1509 }
1510
1511 static enum mali_sampler_type
1512 midgard_sampler_type(nir_alu_type t) {
1513 switch (nir_alu_type_get_base_type(t))
1514 {
1515 case nir_type_float:
1516 return MALI_SAMPLER_FLOAT;
1517 case nir_type_int:
1518 return MALI_SAMPLER_SIGNED;
1519 case nir_type_uint:
1520 return MALI_SAMPLER_UNSIGNED;
1521 default:
1522 unreachable("Unknown sampler type");
1523 }
1524 }
1525
1526 static void
1527 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1528 unsigned midgard_texop)
1529 {
1530 /* TODO */
1531 //assert (!instr->sampler);
1532 //assert (!instr->texture_array_size);
1533
1534 int texture_index = instr->texture_index;
1535 int sampler_index = texture_index;
1536
1537 /* No helper to build texture words -- we do it all here */
1538 midgard_instruction ins = {
1539 .type = TAG_TEXTURE_4,
1540 .mask = 0xF,
1541 .ssa_args = {
1542 .dest = nir_dest_index(ctx, &instr->dest),
1543 .src = { -1, -1, -1 },
1544 },
1545 .texture = {
1546 .op = midgard_texop,
1547 .format = midgard_tex_format(instr->sampler_dim),
1548 .texture_handle = texture_index,
1549 .sampler_handle = sampler_index,
1550 .swizzle = SWIZZLE_XYZW,
1551 .in_reg_swizzle = SWIZZLE_XYZW,
1552
1553 /* TODO: half */
1554 .in_reg_full = 1,
1555 .out_full = 1,
1556
1557 .sampler_type = midgard_sampler_type(instr->dest_type),
1558 }
1559 };
1560
1561 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1562 int index = nir_src_index(ctx, &instr->src[i].src);
1563 midgard_vector_alu_src alu_src = blank_alu_src;
1564
1565 switch (instr->src[i].src_type) {
1566 case nir_tex_src_coord: {
1567 emit_explicit_constant(ctx, index, index);
1568
1569 /* Texelfetch coordinates uses all four elements
1570 * (xyz/index) regardless of texture dimensionality,
1571 * which means it's necessary to zero the unused
1572 * components to keep everything happy */
1573
1574 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1575 unsigned old_index = index;
1576
1577 index = make_compiler_temp(ctx);
1578
1579 /* mov index, old_index */
1580 midgard_instruction mov = v_mov(old_index, blank_alu_src, index);
1581 mov.mask = 0x3;
1582 emit_mir_instruction(ctx, mov);
1583
1584 /* mov index.zw, #0 */
1585 mov = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT),
1586 blank_alu_src, index);
1587 mov.has_constants = true;
1588 mov.mask = (1 << COMPONENT_Z) | (1 << COMPONENT_W);
1589 emit_mir_instruction(ctx, mov);
1590 }
1591
1592 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1593 /* texelFetch is undefined on samplerCube */
1594 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1595
1596 /* For cubemaps, we use a special ld/st op to
1597 * select the face and copy the xy into the
1598 * texture register */
1599
1600 unsigned temp = make_compiler_temp(ctx);
1601 midgard_instruction st = m_st_cubemap_coords(temp, 0);
1602 st.ssa_args.src[0] = index;
1603 st.mask = 0x3; /* xy */
1604 st.load_store.arg_1 = 0x20;
1605 st.load_store.swizzle = alu_src.swizzle;
1606 emit_mir_instruction(ctx, st);
1607
1608 ins.ssa_args.src[0] = temp;
1609 } else {
1610 ins.ssa_args.src[0] = index;
1611 }
1612
1613 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1614 /* Array component in w but NIR wants it in z */
1615 ins.texture.in_reg_swizzle = SWIZZLE_XYZZ;
1616 }
1617
1618 break;
1619 }
1620
1621 case nir_tex_src_bias:
1622 case nir_tex_src_lod: {
1623 /* Try as a constant if we can */
1624
1625 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1626 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1627 break;
1628
1629 ins.texture.lod_register = true;
1630 ins.ssa_args.src[1] = index;
1631 emit_explicit_constant(ctx, index, index);
1632
1633 break;
1634 };
1635
1636 default:
1637 unreachable("Unknown texture source type\n");
1638 }
1639 }
1640
1641 emit_mir_instruction(ctx, ins);
1642
1643 /* Used for .cont and .last hinting */
1644 ctx->texture_op_count++;
1645 }
1646
1647 static void
1648 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1649 {
1650 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1651 * generic tex in some cases (which confuses the hardware) */
1652
1653 bool is_vertex = ctx->stage == MESA_SHADER_VERTEX;
1654
1655 if (is_vertex && instr->op == nir_texop_tex)
1656 instr->op = nir_texop_txl;
1657
1658 switch (instr->op) {
1659 case nir_texop_tex:
1660 case nir_texop_txb:
1661 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1662 break;
1663 case nir_texop_txl:
1664 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1665 break;
1666 case nir_texop_txf:
1667 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1668 break;
1669 case nir_texop_txs:
1670 emit_sysval_read(ctx, &instr->instr, -1);
1671 break;
1672 default:
1673 unreachable("Unhanlded texture op");
1674 }
1675 }
1676
1677 static void
1678 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1679 {
1680 switch (instr->type) {
1681 case nir_jump_break: {
1682 /* Emit a branch out of the loop */
1683 struct midgard_instruction br = v_branch(false, false);
1684 br.branch.target_type = TARGET_BREAK;
1685 br.branch.target_break = ctx->current_loop_depth;
1686 emit_mir_instruction(ctx, br);
1687 break;
1688 }
1689
1690 default:
1691 DBG("Unknown jump type %d\n", instr->type);
1692 break;
1693 }
1694 }
1695
1696 static void
1697 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1698 {
1699 switch (instr->type) {
1700 case nir_instr_type_load_const:
1701 emit_load_const(ctx, nir_instr_as_load_const(instr));
1702 break;
1703
1704 case nir_instr_type_intrinsic:
1705 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1706 break;
1707
1708 case nir_instr_type_alu:
1709 emit_alu(ctx, nir_instr_as_alu(instr));
1710 break;
1711
1712 case nir_instr_type_tex:
1713 emit_tex(ctx, nir_instr_as_tex(instr));
1714 break;
1715
1716 case nir_instr_type_jump:
1717 emit_jump(ctx, nir_instr_as_jump(instr));
1718 break;
1719
1720 case nir_instr_type_ssa_undef:
1721 /* Spurious */
1722 break;
1723
1724 default:
1725 DBG("Unhandled instruction type\n");
1726 break;
1727 }
1728 }
1729
1730
1731 /* ALU instructions can inline or embed constants, which decreases register
1732 * pressure and saves space. */
1733
1734 #define CONDITIONAL_ATTACH(src) { \
1735 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1736 \
1737 if (entry) { \
1738 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1739 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1740 } \
1741 }
1742
1743 static void
1744 inline_alu_constants(compiler_context *ctx)
1745 {
1746 mir_foreach_instr(ctx, alu) {
1747 /* Other instructions cannot inline constants */
1748 if (alu->type != TAG_ALU_4) continue;
1749
1750 /* If there is already a constant here, we can do nothing */
1751 if (alu->has_constants) continue;
1752
1753 CONDITIONAL_ATTACH(src[0]);
1754
1755 if (!alu->has_constants) {
1756 CONDITIONAL_ATTACH(src[1])
1757 } else if (!alu->inline_constant) {
1758 /* Corner case: _two_ vec4 constants, for instance with a
1759 * csel. For this case, we can only use a constant
1760 * register for one, we'll have to emit a move for the
1761 * other. Note, if both arguments are constants, then
1762 * necessarily neither argument depends on the value of
1763 * any particular register. As the destination register
1764 * will be wiped, that means we can spill the constant
1765 * to the destination register.
1766 */
1767
1768 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src[1] + 1);
1769 unsigned scratch = alu->ssa_args.dest;
1770
1771 if (entry) {
1772 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, scratch);
1773 attach_constants(ctx, &ins, entry, alu->ssa_args.src[1] + 1);
1774
1775 /* Force a break XXX Defer r31 writes */
1776 ins.unit = UNIT_VLUT;
1777
1778 /* Set the source */
1779 alu->ssa_args.src[1] = scratch;
1780
1781 /* Inject us -before- the last instruction which set r31 */
1782 mir_insert_instruction_before(mir_prev_op(alu), ins);
1783 }
1784 }
1785 }
1786 }
1787
1788 /* Being a little silly with the names, but returns the op that is the bitwise
1789 * inverse of the op with the argument switched. I.e. (f and g are
1790 * contrapositives):
1791 *
1792 * f(a, b) = ~g(b, a)
1793 *
1794 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
1795 *
1796 * f(a, b) = ~g(b, a)
1797 * ~f(a, b) = g(b, a)
1798 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
1799 * f(a, b) = h(a, b)
1800 *
1801 * Thus we define this function in pairs.
1802 */
1803
1804 static inline midgard_alu_op
1805 mir_contrapositive(midgard_alu_op op)
1806 {
1807 switch (op) {
1808 case midgard_alu_op_flt:
1809 return midgard_alu_op_fle;
1810 case midgard_alu_op_fle:
1811 return midgard_alu_op_flt;
1812
1813 case midgard_alu_op_ilt:
1814 return midgard_alu_op_ile;
1815 case midgard_alu_op_ile:
1816 return midgard_alu_op_ilt;
1817
1818 default:
1819 unreachable("No known contrapositive");
1820 }
1821 }
1822
1823 /* Midgard supports two types of constants, embedded constants (128-bit) and
1824 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1825 * constants can be demoted to inline constants, for space savings and
1826 * sometimes a performance boost */
1827
1828 static void
1829 embedded_to_inline_constant(compiler_context *ctx)
1830 {
1831 mir_foreach_instr(ctx, ins) {
1832 if (!ins->has_constants) continue;
1833
1834 if (ins->ssa_args.inline_constant) continue;
1835
1836 /* Blend constants must not be inlined by definition */
1837 if (ins->has_blend_constant) continue;
1838
1839 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
1840 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
1841 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
1842
1843 if (!(is_16 || is_32))
1844 continue;
1845
1846 /* src1 cannot be an inline constant due to encoding
1847 * restrictions. So, if possible we try to flip the arguments
1848 * in that case */
1849
1850 int op = ins->alu.op;
1851
1852 if (ins->ssa_args.src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1853 bool flip = alu_opcode_props[op].props & OP_COMMUTES;
1854
1855 switch (op) {
1856 /* Conditionals can be inverted */
1857 case midgard_alu_op_flt:
1858 case midgard_alu_op_ilt:
1859 case midgard_alu_op_fle:
1860 case midgard_alu_op_ile:
1861 ins->alu.op = mir_contrapositive(ins->alu.op);
1862 ins->invert = true;
1863 flip = true;
1864 break;
1865
1866 case midgard_alu_op_fcsel:
1867 case midgard_alu_op_icsel:
1868 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
1869 default:
1870 break;
1871 }
1872
1873 if (flip) {
1874 /* Flip the SSA numbers */
1875 ins->ssa_args.src[0] = ins->ssa_args.src[1];
1876 ins->ssa_args.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1877
1878 /* And flip the modifiers */
1879
1880 unsigned src_temp;
1881
1882 src_temp = ins->alu.src2;
1883 ins->alu.src2 = ins->alu.src1;
1884 ins->alu.src1 = src_temp;
1885 }
1886 }
1887
1888 if (ins->ssa_args.src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1889 /* Extract the source information */
1890
1891 midgard_vector_alu_src *src;
1892 int q = ins->alu.src2;
1893 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
1894 src = m;
1895
1896 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1897 int component = src->swizzle & 3;
1898
1899 /* Scale constant appropriately, if we can legally */
1900 uint16_t scaled_constant = 0;
1901
1902 if (midgard_is_integer_op(op) || is_16) {
1903 unsigned int *iconstants = (unsigned int *) ins->constants;
1904 scaled_constant = (uint16_t) iconstants[component];
1905
1906 /* Constant overflow after resize */
1907 if (scaled_constant != iconstants[component])
1908 continue;
1909 } else {
1910 float original = (float) ins->constants[component];
1911 scaled_constant = _mesa_float_to_half(original);
1912
1913 /* Check for loss of precision. If this is
1914 * mediump, we don't care, but for a highp
1915 * shader, we need to pay attention. NIR
1916 * doesn't yet tell us which mode we're in!
1917 * Practically this prevents most constants
1918 * from being inlined, sadly. */
1919
1920 float fp32 = _mesa_half_to_float(scaled_constant);
1921
1922 if (fp32 != original)
1923 continue;
1924 }
1925
1926 /* We don't know how to handle these with a constant */
1927
1928 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
1929 DBG("Bailing inline constant...\n");
1930 continue;
1931 }
1932
1933 /* Make sure that the constant is not itself a
1934 * vector by checking if all accessed values
1935 * (by the swizzle) are the same. */
1936
1937 uint32_t *cons = (uint32_t *) ins->constants;
1938 uint32_t value = cons[component];
1939
1940 bool is_vector = false;
1941 unsigned mask = effective_writemask(&ins->alu, ins->mask);
1942
1943 for (int c = 1; c < 4; ++c) {
1944 /* We only care if this component is actually used */
1945 if (!(mask & (1 << c)))
1946 continue;
1947
1948 uint32_t test = cons[(src->swizzle >> (2 * c)) & 3];
1949
1950 if (test != value) {
1951 is_vector = true;
1952 break;
1953 }
1954 }
1955
1956 if (is_vector)
1957 continue;
1958
1959 /* Get rid of the embedded constant */
1960 ins->has_constants = false;
1961 ins->ssa_args.src[1] = -1;
1962 ins->ssa_args.inline_constant = true;
1963 ins->inline_constant = scaled_constant;
1964 }
1965 }
1966 }
1967
1968 /* Dead code elimination for branches at the end of a block - only one branch
1969 * per block is legal semantically */
1970
1971 static void
1972 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
1973 {
1974 bool branched = false;
1975
1976 mir_foreach_instr_in_block_safe(block, ins) {
1977 if (!midgard_is_branch_unit(ins->unit)) continue;
1978
1979 /* We ignore prepacked branches since the fragment epilogue is
1980 * just generally special */
1981 if (ins->prepacked_branch) continue;
1982
1983 /* Discards are similarly special and may not correspond to the
1984 * end of a block */
1985
1986 if (ins->branch.target_type == TARGET_DISCARD) continue;
1987
1988 if (branched) {
1989 /* We already branched, so this is dead */
1990 mir_remove_instruction(ins);
1991 }
1992
1993 branched = true;
1994 }
1995 }
1996
1997 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
1998 * the move can be propagated away entirely */
1999
2000 static bool
2001 mir_compose_float_outmod(midgard_outmod_float *outmod, midgard_outmod_float comp)
2002 {
2003 /* Nothing to do */
2004 if (comp == midgard_outmod_none)
2005 return true;
2006
2007 if (*outmod == midgard_outmod_none) {
2008 *outmod = comp;
2009 return true;
2010 }
2011
2012 /* TODO: Compose rules */
2013 return false;
2014 }
2015
2016 static bool
2017 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
2018 {
2019 bool progress = false;
2020
2021 mir_foreach_instr_in_block_safe(block, ins) {
2022 if (ins->type != TAG_ALU_4) continue;
2023 if (ins->alu.op != midgard_alu_op_fmov) continue;
2024 if (ins->alu.outmod != midgard_outmod_pos) continue;
2025
2026 /* TODO: Registers? */
2027 unsigned src = ins->ssa_args.src[1];
2028 if (src & IS_REG) continue;
2029 assert(!mir_has_multiple_writes(ctx, src));
2030
2031 /* There might be a source modifier, too */
2032 if (mir_nontrivial_source2_mod(ins)) continue;
2033
2034 /* Backpropagate the modifier */
2035 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
2036 if (v->type != TAG_ALU_4) continue;
2037 if (v->ssa_args.dest != src) continue;
2038
2039 /* Can we even take a float outmod? */
2040 if (midgard_is_integer_out_op(v->alu.op)) continue;
2041
2042 midgard_outmod_float temp = v->alu.outmod;
2043 progress |= mir_compose_float_outmod(&temp, ins->alu.outmod);
2044
2045 /* Throw in the towel.. */
2046 if (!progress) break;
2047
2048 /* Otherwise, transfer the modifier */
2049 v->alu.outmod = temp;
2050 ins->alu.outmod = midgard_outmod_none;
2051
2052 break;
2053 }
2054 }
2055
2056 return progress;
2057 }
2058
2059 static void
2060 emit_fragment_epilogue(compiler_context *ctx)
2061 {
2062 emit_explicit_constant(ctx, ctx->fragment_output, SSA_FIXED_REGISTER(0));
2063
2064 /* Perform the actual fragment writeout. We have two writeout/branch
2065 * instructions, forming a loop until writeout is successful as per the
2066 * docs. TODO: gl_FragDepth */
2067
2068 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2069 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2070 }
2071
2072 static midgard_block *
2073 emit_block(compiler_context *ctx, nir_block *block)
2074 {
2075 midgard_block *this_block = ctx->after_block;
2076 ctx->after_block = NULL;
2077
2078 if (!this_block)
2079 this_block = calloc(sizeof(midgard_block), 1);
2080
2081 list_addtail(&this_block->link, &ctx->blocks);
2082
2083 this_block->is_scheduled = false;
2084 ++ctx->block_count;
2085
2086 ctx->texture_index[0] = -1;
2087 ctx->texture_index[1] = -1;
2088
2089 /* Set up current block */
2090 list_inithead(&this_block->instructions);
2091 ctx->current_block = this_block;
2092
2093 nir_foreach_instr(instr, block) {
2094 emit_instr(ctx, instr);
2095 ++ctx->instruction_count;
2096 }
2097
2098 inline_alu_constants(ctx);
2099 embedded_to_inline_constant(ctx);
2100
2101 /* Append fragment shader epilogue (value writeout) */
2102 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2103 if (block == nir_impl_last_block(ctx->func->impl)) {
2104 emit_fragment_epilogue(ctx);
2105 }
2106 }
2107
2108 /* Allow the next control flow to access us retroactively, for
2109 * branching etc */
2110 ctx->current_block = this_block;
2111
2112 return this_block;
2113 }
2114
2115 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2116
2117 static void
2118 emit_if(struct compiler_context *ctx, nir_if *nif)
2119 {
2120 midgard_block *before_block = ctx->current_block;
2121
2122 /* Conditional branches expect the condition in r31.w; emit a move for
2123 * that in the _previous_ block (which is the current block). */
2124 emit_condition(ctx, &nif->condition, true, COMPONENT_X);
2125
2126 /* Speculatively emit the branch, but we can't fill it in until later */
2127 EMIT(branch, true, true);
2128 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2129
2130 /* Emit the two subblocks. */
2131 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2132 midgard_block *end_then_block = ctx->current_block;
2133
2134 /* Emit a jump from the end of the then block to the end of the else */
2135 EMIT(branch, false, false);
2136 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2137
2138 /* Emit second block, and check if it's empty */
2139
2140 int else_idx = ctx->block_count;
2141 int count_in = ctx->instruction_count;
2142 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2143 midgard_block *end_else_block = ctx->current_block;
2144 int after_else_idx = ctx->block_count;
2145
2146 /* Now that we have the subblocks emitted, fix up the branches */
2147
2148 assert(then_block);
2149 assert(else_block);
2150
2151 if (ctx->instruction_count == count_in) {
2152 /* The else block is empty, so don't emit an exit jump */
2153 mir_remove_instruction(then_exit);
2154 then_branch->branch.target_block = after_else_idx;
2155 } else {
2156 then_branch->branch.target_block = else_idx;
2157 then_exit->branch.target_block = after_else_idx;
2158 }
2159
2160 /* Wire up the successors */
2161
2162 ctx->after_block = calloc(sizeof(midgard_block), 1);
2163
2164 midgard_block_add_successor(before_block, then_block);
2165 midgard_block_add_successor(before_block, else_block);
2166
2167 midgard_block_add_successor(end_then_block, ctx->after_block);
2168 midgard_block_add_successor(end_else_block, ctx->after_block);
2169 }
2170
2171 static void
2172 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2173 {
2174 /* Remember where we are */
2175 midgard_block *start_block = ctx->current_block;
2176
2177 /* Allocate a loop number, growing the current inner loop depth */
2178 int loop_idx = ++ctx->current_loop_depth;
2179
2180 /* Get index from before the body so we can loop back later */
2181 int start_idx = ctx->block_count;
2182
2183 /* Emit the body itself */
2184 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2185
2186 /* Branch back to loop back */
2187 struct midgard_instruction br_back = v_branch(false, false);
2188 br_back.branch.target_block = start_idx;
2189 emit_mir_instruction(ctx, br_back);
2190
2191 /* Mark down that branch in the graph. */
2192 midgard_block_add_successor(start_block, loop_block);
2193 midgard_block_add_successor(ctx->current_block, loop_block);
2194
2195 /* Find the index of the block about to follow us (note: we don't add
2196 * one; blocks are 0-indexed so we get a fencepost problem) */
2197 int break_block_idx = ctx->block_count;
2198
2199 /* Fix up the break statements we emitted to point to the right place,
2200 * now that we can allocate a block number for them */
2201 ctx->after_block = calloc(sizeof(midgard_block), 1);
2202
2203 list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
2204 mir_foreach_instr_in_block(block, ins) {
2205 if (ins->type != TAG_ALU_4) continue;
2206 if (!ins->compact_branch) continue;
2207 if (ins->prepacked_branch) continue;
2208
2209 /* We found a branch -- check the type to see if we need to do anything */
2210 if (ins->branch.target_type != TARGET_BREAK) continue;
2211
2212 /* It's a break! Check if it's our break */
2213 if (ins->branch.target_break != loop_idx) continue;
2214
2215 /* Okay, cool, we're breaking out of this loop.
2216 * Rewrite from a break to a goto */
2217
2218 ins->branch.target_type = TARGET_GOTO;
2219 ins->branch.target_block = break_block_idx;
2220
2221 midgard_block_add_successor(block, ctx->after_block);
2222 }
2223 }
2224
2225 /* Now that we've finished emitting the loop, free up the depth again
2226 * so we play nice with recursion amid nested loops */
2227 --ctx->current_loop_depth;
2228
2229 /* Dump loop stats */
2230 ++ctx->loop_count;
2231 }
2232
2233 static midgard_block *
2234 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2235 {
2236 midgard_block *start_block = NULL;
2237
2238 foreach_list_typed(nir_cf_node, node, node, list) {
2239 switch (node->type) {
2240 case nir_cf_node_block: {
2241 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2242
2243 if (!start_block)
2244 start_block = block;
2245
2246 break;
2247 }
2248
2249 case nir_cf_node_if:
2250 emit_if(ctx, nir_cf_node_as_if(node));
2251 break;
2252
2253 case nir_cf_node_loop:
2254 emit_loop(ctx, nir_cf_node_as_loop(node));
2255 break;
2256
2257 case nir_cf_node_function:
2258 assert(0);
2259 break;
2260 }
2261 }
2262
2263 return start_block;
2264 }
2265
2266 /* Due to lookahead, we need to report the first tag executed in the command
2267 * stream and in branch targets. An initial block might be empty, so iterate
2268 * until we find one that 'works' */
2269
2270 static unsigned
2271 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2272 {
2273 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2274
2275 unsigned first_tag = 0;
2276
2277 mir_foreach_block_from(ctx, initial_block, v) {
2278 midgard_bundle *initial_bundle =
2279 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2280
2281 if (initial_bundle) {
2282 first_tag = initial_bundle->tag;
2283 break;
2284 }
2285 }
2286
2287 return first_tag;
2288 }
2289
2290 int
2291 midgard_compile_shader_nir(struct midgard_screen *screen, nir_shader *nir, midgard_program *program, bool is_blend)
2292 {
2293 struct util_dynarray *compiled = &program->compiled;
2294
2295 midgard_debug = debug_get_option_midgard_debug();
2296
2297 compiler_context ictx = {
2298 .nir = nir,
2299 .screen = screen,
2300 .stage = nir->info.stage,
2301 .temp_alloc = 0,
2302
2303 .is_blend = is_blend,
2304 .blend_constant_offset = 0,
2305
2306 .alpha_ref = program->alpha_ref
2307 };
2308
2309 compiler_context *ctx = &ictx;
2310
2311 /* Start off with a safe cutoff, allowing usage of all 16 work
2312 * registers. Later, we'll promote uniform reads to uniform registers
2313 * if we determine it is beneficial to do so */
2314 ctx->uniform_cutoff = 8;
2315
2316 /* Initialize at a global (not block) level hash tables */
2317
2318 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2319 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2320 ctx->sysval_to_id = _mesa_hash_table_u64_create(NULL);
2321
2322 /* Record the varying mapping for the command stream's bookkeeping */
2323
2324 struct exec_list *varyings =
2325 ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs;
2326
2327 unsigned max_varying = 0;
2328 nir_foreach_variable(var, varyings) {
2329 unsigned loc = var->data.driver_location;
2330 unsigned sz = glsl_type_size(var->type, FALSE);
2331
2332 for (int c = 0; c < sz; ++c) {
2333 program->varyings[loc + c] = var->data.location + c;
2334 max_varying = MAX2(max_varying, loc + c);
2335 }
2336 }
2337
2338 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2339 * (so we don't accidentally duplicate the epilogue since mesa/st has
2340 * messed with our I/O quite a bit already) */
2341
2342 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2343
2344 if (ctx->stage == MESA_SHADER_VERTEX) {
2345 NIR_PASS_V(nir, nir_lower_viewport_transform);
2346 NIR_PASS_V(nir, nir_clamp_psiz, 1.0, 1024.0);
2347 }
2348
2349 NIR_PASS_V(nir, nir_lower_var_copies);
2350 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2351 NIR_PASS_V(nir, nir_split_var_copies);
2352 NIR_PASS_V(nir, nir_lower_var_copies);
2353 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2354 NIR_PASS_V(nir, nir_lower_var_copies);
2355 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2356
2357 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2358
2359 /* Optimisation passes */
2360
2361 optimise_nir(nir);
2362
2363 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2364 nir_print_shader(nir, stdout);
2365 }
2366
2367 /* Assign sysvals and counts, now that we're sure
2368 * (post-optimisation) */
2369
2370 midgard_nir_assign_sysvals(ctx, nir);
2371
2372 program->uniform_count = nir->num_uniforms;
2373 program->sysval_count = ctx->sysval_count;
2374 memcpy(program->sysvals, ctx->sysvals, sizeof(ctx->sysvals[0]) * ctx->sysval_count);
2375
2376 nir_foreach_function(func, nir) {
2377 if (!func->impl)
2378 continue;
2379
2380 list_inithead(&ctx->blocks);
2381 ctx->block_count = 0;
2382 ctx->func = func;
2383
2384 emit_cf_list(ctx, &func->impl->body);
2385 emit_block(ctx, func->impl->end_block);
2386
2387 break; /* TODO: Multi-function shaders */
2388 }
2389
2390 util_dynarray_init(compiled, NULL);
2391
2392 /* MIR-level optimizations */
2393
2394 bool progress = false;
2395
2396 do {
2397 progress = false;
2398
2399 mir_foreach_block(ctx, block) {
2400 progress |= midgard_opt_pos_propagate(ctx, block);
2401 progress |= midgard_opt_copy_prop(ctx, block);
2402 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2403 progress |= midgard_opt_combine_projection(ctx, block);
2404 progress |= midgard_opt_varying_projection(ctx, block);
2405 progress |= midgard_opt_not_propagate(ctx, block);
2406 progress |= midgard_opt_fuse_src_invert(ctx, block);
2407 progress |= midgard_opt_fuse_dest_invert(ctx, block);
2408 }
2409 } while (progress);
2410
2411 mir_foreach_block(ctx, block) {
2412 midgard_lower_invert(ctx, block);
2413 midgard_lower_derivatives(ctx, block);
2414 }
2415
2416 /* Nested control-flow can result in dead branches at the end of the
2417 * block. This messes with our analysis and is just dead code, so cull
2418 * them */
2419 mir_foreach_block(ctx, block) {
2420 midgard_opt_cull_dead_branch(ctx, block);
2421 }
2422
2423 /* Ensure we were lowered */
2424 mir_foreach_instr_global(ctx, ins) {
2425 assert(!ins->invert);
2426 }
2427
2428 /* Schedule! */
2429 schedule_program(ctx);
2430
2431 /* Now that all the bundles are scheduled and we can calculate block
2432 * sizes, emit actual branch instructions rather than placeholders */
2433
2434 int br_block_idx = 0;
2435
2436 mir_foreach_block(ctx, block) {
2437 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2438 for (int c = 0; c < bundle->instruction_count; ++c) {
2439 midgard_instruction *ins = bundle->instructions[c];
2440
2441 if (!midgard_is_branch_unit(ins->unit)) continue;
2442
2443 if (ins->prepacked_branch) continue;
2444
2445 /* Parse some basic branch info */
2446 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2447 bool is_conditional = ins->branch.conditional;
2448 bool is_inverted = ins->branch.invert_conditional;
2449 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2450
2451 /* Determine the block we're jumping to */
2452 int target_number = ins->branch.target_block;
2453
2454 /* Report the destination tag */
2455 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2456
2457 /* Count up the number of quadwords we're
2458 * jumping over = number of quadwords until
2459 * (br_block_idx, target_number) */
2460
2461 int quadword_offset = 0;
2462
2463 if (is_discard) {
2464 /* Ignored */
2465 } else if (target_number > br_block_idx) {
2466 /* Jump forward */
2467
2468 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2469 midgard_block *blk = mir_get_block(ctx, idx);
2470 assert(blk);
2471
2472 quadword_offset += blk->quadword_count;
2473 }
2474 } else {
2475 /* Jump backwards */
2476
2477 for (int idx = br_block_idx; idx >= target_number; --idx) {
2478 midgard_block *blk = mir_get_block(ctx, idx);
2479 assert(blk);
2480
2481 quadword_offset -= blk->quadword_count;
2482 }
2483 }
2484
2485 /* Unconditional extended branches (far jumps)
2486 * have issues, so we always use a conditional
2487 * branch, setting the condition to always for
2488 * unconditional. For compact unconditional
2489 * branches, cond isn't used so it doesn't
2490 * matter what we pick. */
2491
2492 midgard_condition cond =
2493 !is_conditional ? midgard_condition_always :
2494 is_inverted ? midgard_condition_false :
2495 midgard_condition_true;
2496
2497 midgard_jmp_writeout_op op =
2498 is_discard ? midgard_jmp_writeout_op_discard :
2499 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2500 midgard_jmp_writeout_op_branch_cond;
2501
2502 if (!is_compact) {
2503 midgard_branch_extended branch =
2504 midgard_create_branch_extended(
2505 cond, op,
2506 dest_tag,
2507 quadword_offset);
2508
2509 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2510 } else if (is_conditional || is_discard) {
2511 midgard_branch_cond branch = {
2512 .op = op,
2513 .dest_tag = dest_tag,
2514 .offset = quadword_offset,
2515 .cond = cond
2516 };
2517
2518 assert(branch.offset == quadword_offset);
2519
2520 memcpy(&ins->br_compact, &branch, sizeof(branch));
2521 } else {
2522 assert(op == midgard_jmp_writeout_op_branch_uncond);
2523
2524 midgard_branch_uncond branch = {
2525 .op = op,
2526 .dest_tag = dest_tag,
2527 .offset = quadword_offset,
2528 .unknown = 1
2529 };
2530
2531 assert(branch.offset == quadword_offset);
2532
2533 memcpy(&ins->br_compact, &branch, sizeof(branch));
2534 }
2535 }
2536 }
2537
2538 ++br_block_idx;
2539 }
2540
2541 /* Emit flat binary from the instruction arrays. Iterate each block in
2542 * sequence. Save instruction boundaries such that lookahead tags can
2543 * be assigned easily */
2544
2545 /* Cache _all_ bundles in source order for lookahead across failed branches */
2546
2547 int bundle_count = 0;
2548 mir_foreach_block(ctx, block) {
2549 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2550 }
2551 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2552 int bundle_idx = 0;
2553 mir_foreach_block(ctx, block) {
2554 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2555 source_order_bundles[bundle_idx++] = bundle;
2556 }
2557 }
2558
2559 int current_bundle = 0;
2560
2561 /* Midgard prefetches instruction types, so during emission we
2562 * need to lookahead. Unless this is the last instruction, in
2563 * which we return 1. Or if this is the second to last and the
2564 * last is an ALU, then it's also 1... */
2565
2566 mir_foreach_block(ctx, block) {
2567 mir_foreach_bundle_in_block(block, bundle) {
2568 int lookahead = 1;
2569
2570 if (current_bundle + 1 < bundle_count) {
2571 uint8_t next = source_order_bundles[current_bundle + 1]->tag;
2572
2573 if (!(current_bundle + 2 < bundle_count) && IS_ALU(next)) {
2574 lookahead = 1;
2575 } else {
2576 lookahead = next;
2577 }
2578 }
2579
2580 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2581 ++current_bundle;
2582 }
2583
2584 /* TODO: Free deeper */
2585 //util_dynarray_fini(&block->instructions);
2586 }
2587
2588 free(source_order_bundles);
2589
2590 /* Report the very first tag executed */
2591 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2592
2593 /* Deal with off-by-one related to the fencepost problem */
2594 program->work_register_count = ctx->work_registers + 1;
2595 program->uniform_cutoff = ctx->uniform_cutoff;
2596
2597 program->blend_patch_offset = ctx->blend_constant_offset;
2598 program->tls_size = ctx->tls_size;
2599
2600 if (midgard_debug & MIDGARD_DBG_SHADERS)
2601 disassemble_midgard(program->compiled.data, program->compiled.size);
2602
2603 if (midgard_debug & MIDGARD_DBG_SHADERDB) {
2604 unsigned nr_bundles = 0, nr_ins = 0, nr_quadwords = 0;
2605
2606 /* Count instructions and bundles */
2607
2608 mir_foreach_instr_global(ctx, ins) {
2609 nr_ins++;
2610 }
2611
2612 mir_foreach_block(ctx, block) {
2613 nr_bundles += util_dynarray_num_elements(
2614 &block->bundles, midgard_bundle);
2615
2616 nr_quadwords += block->quadword_count;
2617 }
2618
2619 /* Calculate thread count. There are certain cutoffs by
2620 * register count for thread count */
2621
2622 unsigned nr_registers = program->work_register_count;
2623
2624 unsigned nr_threads =
2625 (nr_registers <= 4) ? 4 :
2626 (nr_registers <= 8) ? 2 :
2627 1;
2628
2629 /* Dump stats */
2630
2631 fprintf(stderr, "shader%d - %s shader: "
2632 "%u inst, %u bundles, %u quadwords, "
2633 "%u registers, %u threads, %u loops, "
2634 "%d:%d spills:fills\n",
2635 SHADER_DB_COUNT++,
2636 gl_shader_stage_name(ctx->stage),
2637 nr_ins, nr_bundles, nr_quadwords,
2638 nr_registers, nr_threads,
2639 ctx->loop_count,
2640 ctx->spills, ctx->fills);
2641 }
2642
2643
2644 return 0;
2645 }