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[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) \
118 i.src[0] = ssa; \
119 else \
120 i.dest = ssa; \
121 \
122 return i; \
123 }
124
125 #define M_LOAD(name) M_LOAD_STORE(name, false)
126 #define M_STORE(name) M_LOAD_STORE(name, true)
127
128 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
129 * the corresponding Midgard source */
130
131 static midgard_vector_alu_src
132 vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
133 bool half, bool sext)
134 {
135 /* Figure out how many components there are so we can adjust.
136 * Specifically we want to broadcast the last channel so things like
137 * ball2/3 work.
138 */
139
140 if (broadcast_count && src) {
141 uint8_t last_component = src->swizzle[broadcast_count - 1];
142
143 for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) {
144 src->swizzle[c] = last_component;
145 }
146 }
147
148 midgard_vector_alu_src alu_src = {
149 .rep_low = 0,
150 .rep_high = 0,
151 .half = half
152 };
153
154 if (is_int) {
155 alu_src.mod = midgard_int_normal;
156
157 /* Sign/zero-extend if needed */
158
159 if (half) {
160 alu_src.mod = sext ?
161 midgard_int_sign_extend
162 : midgard_int_zero_extend;
163 }
164
165 /* These should have been lowered away */
166 if (src)
167 assert(!(src->abs || src->negate));
168 } else {
169 if (src)
170 alu_src.mod = (src->abs << 0) | (src->negate << 1);
171 }
172
173 return alu_src;
174 }
175
176 M_LOAD(ld_attr_32);
177 M_LOAD(ld_vary_32);
178 M_LOAD(ld_ubo_int4);
179 M_LOAD(ld_int4);
180 M_STORE(st_int4);
181 M_LOAD(ld_color_buffer_32u);
182 M_STORE(st_vary_32);
183 M_LOAD(ld_cubemap_coords);
184 M_LOAD(ld_compute_id);
185
186 static midgard_instruction
187 v_branch(bool conditional, bool invert)
188 {
189 midgard_instruction ins = {
190 .type = TAG_ALU_4,
191 .unit = ALU_ENAB_BRANCH,
192 .compact_branch = true,
193 .branch = {
194 .conditional = conditional,
195 .invert_conditional = invert
196 },
197 .dest = ~0,
198 .src = { ~0, ~0, ~0, ~0 },
199 };
200
201 return ins;
202 }
203
204 static midgard_branch_extended
205 midgard_create_branch_extended( midgard_condition cond,
206 midgard_jmp_writeout_op op,
207 unsigned dest_tag,
208 signed quadword_offset)
209 {
210 /* The condition code is actually a LUT describing a function to
211 * combine multiple condition codes. However, we only support a single
212 * condition code at the moment, so we just duplicate over a bunch of
213 * times. */
214
215 uint16_t duplicated_cond =
216 (cond << 14) |
217 (cond << 12) |
218 (cond << 10) |
219 (cond << 8) |
220 (cond << 6) |
221 (cond << 4) |
222 (cond << 2) |
223 (cond << 0);
224
225 midgard_branch_extended branch = {
226 .op = op,
227 .dest_tag = dest_tag,
228 .offset = quadword_offset,
229 .cond = duplicated_cond
230 };
231
232 return branch;
233 }
234
235 static void
236 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
237 {
238 ins->has_constants = true;
239 memcpy(&ins->constants, constants, 16);
240 }
241
242 static int
243 glsl_type_size(const struct glsl_type *type, bool bindless)
244 {
245 return glsl_count_attribute_slots(type, false);
246 }
247
248 /* Lower fdot2 to a vector multiplication followed by channel addition */
249 static void
250 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
251 {
252 if (alu->op != nir_op_fdot2)
253 return;
254
255 b->cursor = nir_before_instr(&alu->instr);
256
257 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
258 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
259
260 nir_ssa_def *product = nir_fmul(b, src0, src1);
261
262 nir_ssa_def *sum = nir_fadd(b,
263 nir_channel(b, product, 0),
264 nir_channel(b, product, 1));
265
266 /* Replace the fdot2 with this sum */
267 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
268 }
269
270 static bool
271 midgard_nir_lower_fdot2(nir_shader *shader)
272 {
273 bool progress = false;
274
275 nir_foreach_function(function, shader) {
276 if (!function->impl) continue;
277
278 nir_builder _b;
279 nir_builder *b = &_b;
280 nir_builder_init(b, function->impl);
281
282 nir_foreach_block(block, function->impl) {
283 nir_foreach_instr_safe(instr, block) {
284 if (instr->type != nir_instr_type_alu) continue;
285
286 nir_alu_instr *alu = nir_instr_as_alu(instr);
287 midgard_nir_lower_fdot2_body(b, alu);
288
289 progress |= true;
290 }
291 }
292
293 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
294
295 }
296
297 return progress;
298 }
299
300 /* Midgard can't write depth and stencil separately. It has to happen in a
301 * single store operation containing both. Let's add a panfrost specific
302 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
303 * one.
304 */
305 static bool
306 midgard_nir_lower_zs_store(nir_shader *nir)
307 {
308 if (nir->info.stage != MESA_SHADER_FRAGMENT)
309 return false;
310
311 nir_variable *z_var = NULL, *s_var = NULL;
312
313 nir_foreach_variable(var, &nir->outputs) {
314 if (var->data.location == FRAG_RESULT_DEPTH)
315 z_var = var;
316 else if (var->data.location == FRAG_RESULT_STENCIL)
317 s_var = var;
318 }
319
320 if (!z_var && !s_var)
321 return false;
322
323 bool progress = false;
324
325 nir_foreach_function(function, nir) {
326 if (!function->impl) continue;
327
328 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
329
330 nir_foreach_block(block, function->impl) {
331 nir_foreach_instr_safe(instr, block) {
332 if (instr->type != nir_instr_type_intrinsic)
333 continue;
334
335 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
336 if (intr->intrinsic != nir_intrinsic_store_output)
337 continue;
338
339 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
340 assert(!z_store);
341 z_store = intr;
342 last_store = intr;
343 }
344
345 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
346 assert(!s_store);
347 s_store = intr;
348 last_store = intr;
349 }
350 }
351 }
352
353 if (!z_store && !s_store) continue;
354
355 nir_builder b;
356 nir_builder_init(&b, function->impl);
357
358 b.cursor = nir_before_instr(&last_store->instr);
359
360 nir_ssa_def *zs_store_src;
361
362 if (z_store && s_store) {
363 nir_ssa_def *srcs[2] = {
364 nir_ssa_for_src(&b, z_store->src[0], 1),
365 nir_ssa_for_src(&b, s_store->src[0], 1),
366 };
367
368 zs_store_src = nir_vec(&b, srcs, 2);
369 } else {
370 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
371 }
372
373 nir_intrinsic_instr *zs_store;
374
375 zs_store = nir_intrinsic_instr_create(b.shader,
376 nir_intrinsic_store_zs_output_pan);
377 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
378 zs_store->num_components = z_store && s_store ? 2 : 1;
379 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
380
381 /* Replace the Z and S store by a ZS store */
382 nir_builder_instr_insert(&b, &zs_store->instr);
383
384 if (z_store)
385 nir_instr_remove(&z_store->instr);
386
387 if (s_store)
388 nir_instr_remove(&s_store->instr);
389
390 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
391 progress = true;
392 }
393
394 return progress;
395 }
396
397 /* Flushes undefined values to zero */
398
399 static void
400 optimise_nir(nir_shader *nir, unsigned quirks)
401 {
402 bool progress;
403 unsigned lower_flrp =
404 (nir->options->lower_flrp16 ? 16 : 0) |
405 (nir->options->lower_flrp32 ? 32 : 0) |
406 (nir->options->lower_flrp64 ? 64 : 0);
407
408 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
409 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
410
411 nir_lower_tex_options lower_tex_options = {
412 .lower_txs_lod = true,
413 .lower_txp = ~0,
414 .lower_tex_without_implicit_lod =
415 (quirks & MIDGARD_EXPLICIT_LOD),
416
417 /* TODO: we have native gradient.. */
418 .lower_txd = true,
419 };
420
421 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
422
423 /* Must lower fdot2 after tex is lowered */
424 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
425
426 /* T720 is broken. */
427
428 if (quirks & MIDGARD_BROKEN_LOD)
429 NIR_PASS_V(nir, midgard_nir_lod_errata);
430
431 do {
432 progress = false;
433
434 NIR_PASS(progress, nir, nir_lower_var_copies);
435 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
436
437 NIR_PASS(progress, nir, nir_copy_prop);
438 NIR_PASS(progress, nir, nir_opt_remove_phis);
439 NIR_PASS(progress, nir, nir_opt_dce);
440 NIR_PASS(progress, nir, nir_opt_dead_cf);
441 NIR_PASS(progress, nir, nir_opt_cse);
442 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
443 NIR_PASS(progress, nir, nir_opt_algebraic);
444 NIR_PASS(progress, nir, nir_opt_constant_folding);
445
446 if (lower_flrp != 0) {
447 bool lower_flrp_progress = false;
448 NIR_PASS(lower_flrp_progress,
449 nir,
450 nir_lower_flrp,
451 lower_flrp,
452 false /* always_precise */,
453 nir->options->lower_ffma);
454 if (lower_flrp_progress) {
455 NIR_PASS(progress, nir,
456 nir_opt_constant_folding);
457 progress = true;
458 }
459
460 /* Nothing should rematerialize any flrps, so we only
461 * need to do this lowering once.
462 */
463 lower_flrp = 0;
464 }
465
466 NIR_PASS(progress, nir, nir_opt_undef);
467 NIR_PASS(progress, nir, nir_undef_to_zero);
468
469 NIR_PASS(progress, nir, nir_opt_loop_unroll,
470 nir_var_shader_in |
471 nir_var_shader_out |
472 nir_var_function_temp);
473
474 NIR_PASS(progress, nir, nir_opt_vectorize);
475 } while (progress);
476
477 /* Must be run at the end to prevent creation of fsin/fcos ops */
478 NIR_PASS(progress, nir, midgard_nir_scale_trig);
479
480 do {
481 progress = false;
482
483 NIR_PASS(progress, nir, nir_opt_dce);
484 NIR_PASS(progress, nir, nir_opt_algebraic);
485 NIR_PASS(progress, nir, nir_opt_constant_folding);
486 NIR_PASS(progress, nir, nir_copy_prop);
487 } while (progress);
488
489 NIR_PASS(progress, nir, nir_opt_algebraic_late);
490
491 /* We implement booleans as 32-bit 0/~0 */
492 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
493
494 /* Now that booleans are lowered, we can run out late opts */
495 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
496
497 /* Lower mods for float ops only. Integer ops don't support modifiers
498 * (saturate doesn't make sense on integers, neg/abs require dedicated
499 * instructions) */
500
501 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
502 NIR_PASS(progress, nir, nir_copy_prop);
503 NIR_PASS(progress, nir, nir_opt_dce);
504
505 /* Take us out of SSA */
506 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
507 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
508
509 /* We are a vector architecture; write combine where possible */
510 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
511 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
512
513 NIR_PASS(progress, nir, nir_opt_dce);
514 }
515
516 /* Do not actually emit a load; instead, cache the constant for inlining */
517
518 static void
519 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
520 {
521 nir_ssa_def def = instr->def;
522
523 midgard_constants *consts = rzalloc(NULL, midgard_constants);
524
525 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
526
527 #define RAW_CONST_COPY(bits) \
528 nir_const_value_to_array(consts->u##bits, instr->value, \
529 instr->def.num_components, u##bits)
530
531 switch (instr->def.bit_size) {
532 case 64:
533 RAW_CONST_COPY(64);
534 break;
535 case 32:
536 RAW_CONST_COPY(32);
537 break;
538 case 16:
539 RAW_CONST_COPY(16);
540 break;
541 case 8:
542 RAW_CONST_COPY(8);
543 break;
544 default:
545 unreachable("Invalid bit_size for load_const instruction\n");
546 }
547
548 /* Shifted for SSA, +1 for off-by-one */
549 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
550 }
551
552 /* Normally constants are embedded implicitly, but for I/O and such we have to
553 * explicitly emit a move with the constant source */
554
555 static void
556 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
557 {
558 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
559
560 if (constant_value) {
561 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
562 attach_constants(ctx, &ins, constant_value, node + 1);
563 emit_mir_instruction(ctx, ins);
564 }
565 }
566
567 static bool
568 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
569 {
570 unsigned comp = src->swizzle[0];
571
572 for (unsigned c = 1; c < nr_components; ++c) {
573 if (src->swizzle[c] != comp)
574 return true;
575 }
576
577 return false;
578 }
579
580 #define ALU_CASE(nir, _op) \
581 case nir_op_##nir: \
582 op = midgard_alu_op_##_op; \
583 assert(src_bitsize == dst_bitsize); \
584 break;
585
586 #define ALU_CASE_BCAST(nir, _op, count) \
587 case nir_op_##nir: \
588 op = midgard_alu_op_##_op; \
589 broadcast_swizzle = count; \
590 assert(src_bitsize == dst_bitsize); \
591 break;
592 static bool
593 nir_is_fzero_constant(nir_src src)
594 {
595 if (!nir_src_is_const(src))
596 return false;
597
598 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
599 if (nir_src_comp_as_float(src, c) != 0.0)
600 return false;
601 }
602
603 return true;
604 }
605
606 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
607 * special treatment override this anyway. */
608
609 static midgard_reg_mode
610 reg_mode_for_nir(nir_alu_instr *instr)
611 {
612 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
613
614 switch (src_bitsize) {
615 case 8:
616 return midgard_reg_mode_8;
617 case 16:
618 return midgard_reg_mode_16;
619 case 32:
620 return midgard_reg_mode_32;
621 case 64:
622 return midgard_reg_mode_64;
623 default:
624 unreachable("Invalid bit size");
625 }
626 }
627
628 static void
629 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to)
630 {
631 unsigned bits = nir_src_bit_size(instr->src[i].src);
632
633 ins->src[to] = nir_src_index(NULL, &instr->src[i].src);
634 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
635 }
636
637 static void
638 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
639 {
640 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
641 * is handled elsewhere */
642
643 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
644 midgard_emit_derivatives(ctx, instr);
645 return;
646 }
647
648 bool is_ssa = instr->dest.dest.is_ssa;
649
650 unsigned nr_components = nir_dest_num_components(instr->dest.dest);
651 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
652 unsigned op = 0;
653
654 /* Number of components valid to check for the instruction (the rest
655 * will be forced to the last), or 0 to use as-is. Relevant as
656 * ball-type instructions have a channel count in NIR but are all vec4
657 * in Midgard */
658
659 unsigned broadcast_swizzle = 0;
660
661 /* What register mode should we operate in? */
662 midgard_reg_mode reg_mode =
663 reg_mode_for_nir(instr);
664
665 /* Do we need a destination override? Used for inline
666 * type conversion */
667
668 midgard_dest_override dest_override =
669 midgard_dest_override_none;
670
671 /* Should we use a smaller respective source and sign-extend? */
672
673 bool half_1 = false, sext_1 = false;
674 bool half_2 = false, sext_2 = false;
675
676 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
677 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
678
679 switch (instr->op) {
680 ALU_CASE(fadd, fadd);
681 ALU_CASE(fmul, fmul);
682 ALU_CASE(fmin, fmin);
683 ALU_CASE(fmax, fmax);
684 ALU_CASE(imin, imin);
685 ALU_CASE(imax, imax);
686 ALU_CASE(umin, umin);
687 ALU_CASE(umax, umax);
688 ALU_CASE(ffloor, ffloor);
689 ALU_CASE(fround_even, froundeven);
690 ALU_CASE(ftrunc, ftrunc);
691 ALU_CASE(fceil, fceil);
692 ALU_CASE(fdot3, fdot3);
693 ALU_CASE(fdot4, fdot4);
694 ALU_CASE(iadd, iadd);
695 ALU_CASE(isub, isub);
696 ALU_CASE(imul, imul);
697
698 /* Zero shoved as second-arg */
699 ALU_CASE(iabs, iabsdiff);
700
701 ALU_CASE(mov, imov);
702
703 ALU_CASE(feq32, feq);
704 ALU_CASE(fne32, fne);
705 ALU_CASE(flt32, flt);
706 ALU_CASE(ieq32, ieq);
707 ALU_CASE(ine32, ine);
708 ALU_CASE(ilt32, ilt);
709 ALU_CASE(ult32, ult);
710
711 /* We don't have a native b2f32 instruction. Instead, like many
712 * GPUs, we exploit booleans as 0/~0 for false/true, and
713 * correspondingly AND
714 * by 1.0 to do the type conversion. For the moment, prime us
715 * to emit:
716 *
717 * iand [whatever], #0
718 *
719 * At the end of emit_alu (as MIR), we'll fix-up the constant
720 */
721
722 ALU_CASE(b2f32, iand);
723 ALU_CASE(b2i32, iand);
724
725 /* Likewise, we don't have a dedicated f2b32 instruction, but
726 * we can do a "not equal to 0.0" test. */
727
728 ALU_CASE(f2b32, fne);
729 ALU_CASE(i2b32, ine);
730
731 ALU_CASE(frcp, frcp);
732 ALU_CASE(frsq, frsqrt);
733 ALU_CASE(fsqrt, fsqrt);
734 ALU_CASE(fexp2, fexp2);
735 ALU_CASE(flog2, flog2);
736
737 ALU_CASE(f2i64, f2i_rtz);
738 ALU_CASE(f2u64, f2u_rtz);
739 ALU_CASE(i2f64, i2f_rtz);
740 ALU_CASE(u2f64, u2f_rtz);
741
742 ALU_CASE(f2i32, f2i_rtz);
743 ALU_CASE(f2u32, f2u_rtz);
744 ALU_CASE(i2f32, i2f_rtz);
745 ALU_CASE(u2f32, u2f_rtz);
746
747 ALU_CASE(f2i16, f2i_rtz);
748 ALU_CASE(f2u16, f2u_rtz);
749 ALU_CASE(i2f16, i2f_rtz);
750 ALU_CASE(u2f16, u2f_rtz);
751
752 ALU_CASE(fsin, fsin);
753 ALU_CASE(fcos, fcos);
754
755 /* We'll set invert */
756 ALU_CASE(inot, imov);
757 ALU_CASE(iand, iand);
758 ALU_CASE(ior, ior);
759 ALU_CASE(ixor, ixor);
760 ALU_CASE(ishl, ishl);
761 ALU_CASE(ishr, iasr);
762 ALU_CASE(ushr, ilsr);
763
764 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
765 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
766 ALU_CASE(b32all_fequal4, fball_eq);
767
768 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
769 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
770 ALU_CASE(b32any_fnequal4, fbany_neq);
771
772 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
773 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
774 ALU_CASE(b32all_iequal4, iball_eq);
775
776 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
777 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
778 ALU_CASE(b32any_inequal4, ibany_neq);
779
780 /* Source mods will be shoved in later */
781 ALU_CASE(fabs, fmov);
782 ALU_CASE(fneg, fmov);
783 ALU_CASE(fsat, fmov);
784
785 /* For size conversion, we use a move. Ideally though we would squash
786 * these ops together; maybe that has to happen after in NIR as part of
787 * propagation...? An earlier algebraic pass ensured we step down by
788 * only / exactly one size. If stepping down, we use a dest override to
789 * reduce the size; if stepping up, we use a larger-sized move with a
790 * half source and a sign/zero-extension modifier */
791
792 case nir_op_i2i8:
793 case nir_op_i2i16:
794 case nir_op_i2i32:
795 case nir_op_i2i64:
796 /* If we end up upscale, we'll need a sign-extend on the
797 * operand (the second argument) */
798
799 sext_2 = true;
800 /* fallthrough */
801 case nir_op_u2u8:
802 case nir_op_u2u16:
803 case nir_op_u2u32:
804 case nir_op_u2u64:
805 case nir_op_f2f16:
806 case nir_op_f2f32:
807 case nir_op_f2f64: {
808 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
809 instr->op == nir_op_f2f64)
810 op = midgard_alu_op_fmov;
811 else
812 op = midgard_alu_op_imov;
813
814 if (dst_bitsize == (src_bitsize * 2)) {
815 /* Converting up */
816 half_2 = true;
817
818 /* Use a greater register mode */
819 reg_mode++;
820 } else if (src_bitsize == (dst_bitsize * 2)) {
821 /* Converting down */
822 dest_override = midgard_dest_override_lower;
823 }
824
825 break;
826 }
827
828 /* For greater-or-equal, we lower to less-or-equal and flip the
829 * arguments */
830
831 case nir_op_fge:
832 case nir_op_fge32:
833 case nir_op_ige32:
834 case nir_op_uge32: {
835 op =
836 instr->op == nir_op_fge ? midgard_alu_op_fle :
837 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
838 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
839 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
840 0;
841
842 /* Swap via temporary */
843 nir_alu_src temp = instr->src[1];
844 instr->src[1] = instr->src[0];
845 instr->src[0] = temp;
846
847 break;
848 }
849
850 case nir_op_b32csel: {
851 /* Midgard features both fcsel and icsel, depending on
852 * the type of the arguments/output. However, as long
853 * as we're careful we can _always_ use icsel and
854 * _never_ need fcsel, since the latter does additional
855 * floating-point-specific processing whereas the
856 * former just moves bits on the wire. It's not obvious
857 * why these are separate opcodes, save for the ability
858 * to do things like sat/pos/abs/neg for free */
859
860 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
861 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
862
863 /* The condition is the first argument; move the other
864 * arguments up one to be a binary instruction for
865 * Midgard with the condition last */
866
867 nir_alu_src temp = instr->src[2];
868
869 instr->src[2] = instr->src[0];
870 instr->src[0] = instr->src[1];
871 instr->src[1] = temp;
872
873 break;
874 }
875
876 default:
877 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
878 assert(0);
879 return;
880 }
881
882 /* Midgard can perform certain modifiers on output of an ALU op */
883 unsigned outmod;
884
885 if (midgard_is_integer_out_op(op)) {
886 outmod = midgard_outmod_int_wrap;
887 } else {
888 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
889 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
890 }
891
892 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
893
894 if (instr->op == nir_op_fmax) {
895 if (nir_is_fzero_constant(instr->src[0].src)) {
896 op = midgard_alu_op_fmov;
897 nr_inputs = 1;
898 outmod = midgard_outmod_pos;
899 instr->src[0] = instr->src[1];
900 } else if (nir_is_fzero_constant(instr->src[1].src)) {
901 op = midgard_alu_op_fmov;
902 nr_inputs = 1;
903 outmod = midgard_outmod_pos;
904 }
905 }
906
907 /* Fetch unit, quirks, etc information */
908 unsigned opcode_props = alu_opcode_props[op].props;
909 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
910
911 midgard_instruction ins = {
912 .type = TAG_ALU_4,
913 .dest = nir_dest_index(&instr->dest.dest),
914 .dest_type = nir_op_infos[instr->op].output_type
915 | nir_dest_bit_size(instr->dest.dest),
916 };
917
918 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
919 ins.src[i] = ~0;
920
921 if (quirk_flipped_r24) {
922 ins.src[0] = ~0;
923 mir_copy_src(&ins, instr, 0, 1);
924 } else {
925 for (unsigned i = 0; i < nr_inputs; ++i)
926 mir_copy_src(&ins, instr, i, quirk_flipped_r24 ? 1 : i);
927 }
928
929 nir_alu_src *nirmods[3] = { NULL };
930
931 if (nr_inputs >= 2) {
932 nirmods[0] = &instr->src[0];
933 nirmods[1] = &instr->src[1];
934 } else if (nr_inputs == 1) {
935 nirmods[quirk_flipped_r24] = &instr->src[0];
936 } else {
937 assert(0);
938 }
939
940 if (nr_inputs == 3)
941 nirmods[2] = &instr->src[2];
942
943 /* These were lowered to a move, so apply the corresponding mod */
944
945 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
946 nir_alu_src *s = nirmods[quirk_flipped_r24];
947
948 if (instr->op == nir_op_fneg)
949 s->negate = !s->negate;
950
951 if (instr->op == nir_op_fabs)
952 s->abs = !s->abs;
953 }
954
955 bool is_int = midgard_is_integer_op(op);
956
957 ins.mask = mask_of(nr_components);
958
959 midgard_vector_alu alu = {
960 .op = op,
961 .reg_mode = reg_mode,
962 .dest_override = dest_override,
963 .outmod = outmod,
964
965 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)),
966 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)),
967 };
968
969 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
970
971 if (!is_ssa)
972 ins.mask &= instr->dest.write_mask;
973
974 for (unsigned m = 0; m < 3; ++m) {
975 if (!nirmods[m])
976 continue;
977
978 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c)
979 ins.swizzle[m][c] = nirmods[m]->swizzle[c];
980
981 /* Replicate. TODO: remove when vec16 lands */
982 for (unsigned c = NIR_MAX_VEC_COMPONENTS; c < MIR_VEC_COMPONENTS; ++c)
983 ins.swizzle[m][c] = nirmods[m]->swizzle[NIR_MAX_VEC_COMPONENTS - 1];
984 }
985
986 if (nr_inputs == 3) {
987 /* Conditions can't have mods */
988 assert(!nirmods[2]->abs);
989 assert(!nirmods[2]->negate);
990 }
991
992 ins.alu = alu;
993
994 /* Late fixup for emulated instructions */
995
996 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
997 /* Presently, our second argument is an inline #0 constant.
998 * Switch over to an embedded 1.0 constant (that can't fit
999 * inline, since we're 32-bit, not 16-bit like the inline
1000 * constants) */
1001
1002 ins.has_inline_constant = false;
1003 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1004 ins.has_constants = true;
1005
1006 if (instr->op == nir_op_b2f32)
1007 ins.constants.f32[0] = 1.0f;
1008 else
1009 ins.constants.i32[0] = 1;
1010
1011 for (unsigned c = 0; c < 16; ++c)
1012 ins.swizzle[1][c] = 0;
1013 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1014 /* Lots of instructions need a 0 plonked in */
1015 ins.has_inline_constant = false;
1016 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1017 ins.has_constants = true;
1018 ins.constants.u32[0] = 0;
1019
1020 for (unsigned c = 0; c < 16; ++c)
1021 ins.swizzle[1][c] = 0;
1022 } else if (instr->op == nir_op_inot) {
1023 ins.invert = true;
1024 }
1025
1026 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1027 /* To avoid duplicating the lookup tables (probably), true LUT
1028 * instructions can only operate as if they were scalars. Lower
1029 * them here by changing the component. */
1030
1031 unsigned orig_mask = ins.mask;
1032
1033 for (int i = 0; i < nr_components; ++i) {
1034 /* Mask the associated component, dropping the
1035 * instruction if needed */
1036
1037 ins.mask = 1 << i;
1038 ins.mask &= orig_mask;
1039
1040 if (!ins.mask)
1041 continue;
1042
1043 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1044 ins.swizzle[0][j] = nirmods[0]->swizzle[i]; /* Pull from the correct component */
1045
1046 emit_mir_instruction(ctx, ins);
1047 }
1048 } else {
1049 emit_mir_instruction(ctx, ins);
1050 }
1051 }
1052
1053 #undef ALU_CASE
1054
1055 static void
1056 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1057 {
1058 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1059 unsigned nir_mask = 0;
1060 unsigned dsize = 0;
1061
1062 if (is_read) {
1063 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1064 dsize = nir_dest_bit_size(intr->dest);
1065 } else {
1066 nir_mask = nir_intrinsic_write_mask(intr);
1067 dsize = 32;
1068 }
1069
1070 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1071 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1072 mir_set_bytemask(ins, bytemask);
1073
1074 if (dsize == 64)
1075 ins->load_64 = true;
1076 }
1077
1078 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1079 * optimized) versions of UBO #0 */
1080
1081 static midgard_instruction *
1082 emit_ubo_read(
1083 compiler_context *ctx,
1084 nir_instr *instr,
1085 unsigned dest,
1086 unsigned offset,
1087 nir_src *indirect_offset,
1088 unsigned indirect_shift,
1089 unsigned index)
1090 {
1091 /* TODO: half-floats */
1092
1093 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1094 ins.constants.u32[0] = offset;
1095
1096 if (instr->type == nir_instr_type_intrinsic)
1097 mir_set_intr_mask(instr, &ins, true);
1098
1099 if (indirect_offset) {
1100 ins.src[2] = nir_src_index(ctx, indirect_offset);
1101 ins.load_store.arg_2 = (indirect_shift << 5);
1102 } else {
1103 ins.load_store.arg_2 = 0x1E;
1104 }
1105
1106 ins.load_store.arg_1 = index;
1107
1108 return emit_mir_instruction(ctx, ins);
1109 }
1110
1111 /* Globals are like UBOs if you squint. And shared memory is like globals if
1112 * you squint even harder */
1113
1114 static void
1115 emit_global(
1116 compiler_context *ctx,
1117 nir_instr *instr,
1118 bool is_read,
1119 unsigned srcdest,
1120 nir_src *offset,
1121 bool is_shared)
1122 {
1123 /* TODO: types */
1124
1125 midgard_instruction ins;
1126
1127 if (is_read)
1128 ins = m_ld_int4(srcdest, 0);
1129 else
1130 ins = m_st_int4(srcdest, 0);
1131
1132 mir_set_offset(ctx, &ins, offset, is_shared);
1133 mir_set_intr_mask(instr, &ins, is_read);
1134
1135 emit_mir_instruction(ctx, ins);
1136 }
1137
1138 static void
1139 emit_varying_read(
1140 compiler_context *ctx,
1141 unsigned dest, unsigned offset,
1142 unsigned nr_comp, unsigned component,
1143 nir_src *indirect_offset, nir_alu_type type, bool flat)
1144 {
1145 /* XXX: Half-floats? */
1146 /* TODO: swizzle, mask */
1147
1148 midgard_instruction ins = m_ld_vary_32(dest, offset);
1149 ins.mask = mask_of(nr_comp);
1150
1151 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1152 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1153
1154 midgard_varying_parameter p = {
1155 .is_varying = 1,
1156 .interpolation = midgard_interp_default,
1157 .flat = flat,
1158 };
1159
1160 unsigned u;
1161 memcpy(&u, &p, sizeof(p));
1162 ins.load_store.varying_parameters = u;
1163
1164 if (indirect_offset)
1165 ins.src[2] = nir_src_index(ctx, indirect_offset);
1166 else
1167 ins.load_store.arg_2 = 0x1E;
1168
1169 ins.load_store.arg_1 = 0x9E;
1170
1171 /* Use the type appropriate load */
1172 switch (type) {
1173 case nir_type_uint:
1174 case nir_type_bool:
1175 ins.load_store.op = midgard_op_ld_vary_32u;
1176 break;
1177 case nir_type_int:
1178 ins.load_store.op = midgard_op_ld_vary_32i;
1179 break;
1180 case nir_type_float:
1181 ins.load_store.op = midgard_op_ld_vary_32;
1182 break;
1183 default:
1184 unreachable("Attempted to load unknown type");
1185 break;
1186 }
1187
1188 emit_mir_instruction(ctx, ins);
1189 }
1190
1191 static void
1192 emit_attr_read(
1193 compiler_context *ctx,
1194 unsigned dest, unsigned offset,
1195 unsigned nr_comp, nir_alu_type t)
1196 {
1197 midgard_instruction ins = m_ld_attr_32(dest, offset);
1198 ins.load_store.arg_1 = 0x1E;
1199 ins.load_store.arg_2 = 0x1E;
1200 ins.mask = mask_of(nr_comp);
1201
1202 /* Use the type appropriate load */
1203 switch (t) {
1204 case nir_type_uint:
1205 case nir_type_bool:
1206 ins.load_store.op = midgard_op_ld_attr_32u;
1207 break;
1208 case nir_type_int:
1209 ins.load_store.op = midgard_op_ld_attr_32i;
1210 break;
1211 case nir_type_float:
1212 ins.load_store.op = midgard_op_ld_attr_32;
1213 break;
1214 default:
1215 unreachable("Attempted to load unknown type");
1216 break;
1217 }
1218
1219 emit_mir_instruction(ctx, ins);
1220 }
1221
1222 static void
1223 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1224 unsigned nr_components, unsigned offset)
1225 {
1226 nir_dest nir_dest;
1227
1228 /* Figure out which uniform this is */
1229 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1230 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1231
1232 unsigned dest = nir_dest_index(&nir_dest);
1233
1234 /* Sysvals are prefix uniforms */
1235 unsigned uniform = ((uintptr_t) val) - 1;
1236
1237 /* Emit the read itself -- this is never indirect */
1238 midgard_instruction *ins =
1239 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1240
1241 ins->mask = mask_of(nr_components);
1242 }
1243
1244 static unsigned
1245 compute_builtin_arg(nir_op op)
1246 {
1247 switch (op) {
1248 case nir_intrinsic_load_work_group_id:
1249 return 0x14;
1250 case nir_intrinsic_load_local_invocation_id:
1251 return 0x10;
1252 default:
1253 unreachable("Invalid compute paramater loaded");
1254 }
1255 }
1256
1257 static void
1258 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1259 {
1260 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1261
1262 midgard_instruction *br = ctx->writeout_branch[rt];
1263
1264 assert(!br);
1265
1266 emit_explicit_constant(ctx, src, src);
1267
1268 struct midgard_instruction ins =
1269 v_branch(false, false);
1270
1271 ins.writeout = true;
1272
1273 /* Add dependencies */
1274 ins.src[0] = src;
1275 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1276 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1277
1278 /* Emit the branch */
1279 br = emit_mir_instruction(ctx, ins);
1280 schedule_barrier(ctx);
1281 ctx->writeout_branch[rt] = br;
1282
1283 /* Push our current location = current block count - 1 = where we'll
1284 * jump to. Maybe a bit too clever for my own good */
1285
1286 br->branch.target_block = ctx->block_count - 1;
1287 }
1288
1289 static void
1290 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1291 {
1292 unsigned reg = nir_dest_index(&instr->dest);
1293 midgard_instruction ins = m_ld_compute_id(reg, 0);
1294 ins.mask = mask_of(3);
1295 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1296 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1297 emit_mir_instruction(ctx, ins);
1298 }
1299
1300 static unsigned
1301 vertex_builtin_arg(nir_op op)
1302 {
1303 switch (op) {
1304 case nir_intrinsic_load_vertex_id:
1305 return PAN_VERTEX_ID;
1306 case nir_intrinsic_load_instance_id:
1307 return PAN_INSTANCE_ID;
1308 default:
1309 unreachable("Invalid vertex builtin");
1310 }
1311 }
1312
1313 static void
1314 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1315 {
1316 unsigned reg = nir_dest_index(&instr->dest);
1317 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1318 }
1319
1320 static void
1321 emit_control_barrier(compiler_context *ctx)
1322 {
1323 midgard_instruction ins = {
1324 .type = TAG_TEXTURE_4,
1325 .src = { ~0, ~0, ~0, ~0 },
1326 .texture = {
1327 .op = TEXTURE_OP_BARRIER,
1328
1329 /* TODO: optimize */
1330 .barrier_buffer = 1,
1331 .barrier_shared = 1
1332 }
1333 };
1334
1335 emit_mir_instruction(ctx, ins);
1336 }
1337
1338 static const nir_variable *
1339 search_var(struct exec_list *vars, unsigned driver_loc)
1340 {
1341 nir_foreach_variable(var, vars) {
1342 if (var->data.driver_location == driver_loc)
1343 return var;
1344 }
1345
1346 return NULL;
1347 }
1348
1349 static void
1350 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1351 {
1352 unsigned offset = 0, reg;
1353
1354 switch (instr->intrinsic) {
1355 case nir_intrinsic_discard_if:
1356 case nir_intrinsic_discard: {
1357 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1358 struct midgard_instruction discard = v_branch(conditional, false);
1359 discard.branch.target_type = TARGET_DISCARD;
1360
1361 if (conditional)
1362 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1363
1364 emit_mir_instruction(ctx, discard);
1365 schedule_barrier(ctx);
1366
1367 break;
1368 }
1369
1370 case nir_intrinsic_load_uniform:
1371 case nir_intrinsic_load_ubo:
1372 case nir_intrinsic_load_global:
1373 case nir_intrinsic_load_shared:
1374 case nir_intrinsic_load_input:
1375 case nir_intrinsic_load_interpolated_input: {
1376 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1377 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1378 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1379 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1380 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1381 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1382
1383 /* Get the base type of the intrinsic */
1384 /* TODO: Infer type? Does it matter? */
1385 nir_alu_type t =
1386 (is_ubo || is_global || is_shared) ? nir_type_uint :
1387 (is_interp) ? nir_type_float :
1388 nir_intrinsic_type(instr);
1389
1390 t = nir_alu_type_get_base_type(t);
1391
1392 if (!(is_ubo || is_global)) {
1393 offset = nir_intrinsic_base(instr);
1394 }
1395
1396 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1397
1398 nir_src *src_offset = nir_get_io_offset_src(instr);
1399
1400 bool direct = nir_src_is_const(*src_offset);
1401 nir_src *indirect_offset = direct ? NULL : src_offset;
1402
1403 if (direct)
1404 offset += nir_src_as_uint(*src_offset);
1405
1406 /* We may need to apply a fractional offset */
1407 int component = (is_flat || is_interp) ?
1408 nir_intrinsic_component(instr) : 0;
1409 reg = nir_dest_index(&instr->dest);
1410
1411 if (is_uniform && !ctx->is_blend) {
1412 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1413 } else if (is_ubo) {
1414 nir_src index = instr->src[0];
1415
1416 /* TODO: Is indirect block number possible? */
1417 assert(nir_src_is_const(index));
1418
1419 uint32_t uindex = nir_src_as_uint(index) + 1;
1420 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1421 } else if (is_global || is_shared) {
1422 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1423 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1424 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1425 } else if (ctx->is_blend) {
1426 /* For blend shaders, load the input color, which is
1427 * preloaded to r0 */
1428
1429 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1430 emit_mir_instruction(ctx, move);
1431 schedule_barrier(ctx);
1432 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1433 emit_attr_read(ctx, reg, offset, nr_comp, t);
1434 } else {
1435 DBG("Unknown load\n");
1436 assert(0);
1437 }
1438
1439 break;
1440 }
1441
1442 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1443 case nir_intrinsic_load_barycentric_pixel:
1444 case nir_intrinsic_load_barycentric_centroid:
1445 break;
1446
1447 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1448
1449 case nir_intrinsic_load_raw_output_pan:
1450 case nir_intrinsic_load_output_u8_as_fp16_pan:
1451 reg = nir_dest_index(&instr->dest);
1452 assert(ctx->is_blend);
1453
1454 /* T720 and below use different blend opcodes with slightly
1455 * different semantics than T760 and up */
1456
1457 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1458 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1459
1460 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1461 ld.load_store.op = old_blend ?
1462 midgard_op_ld_color_buffer_u8_as_fp16_old :
1463 midgard_op_ld_color_buffer_u8_as_fp16;
1464
1465 if (old_blend) {
1466 ld.load_store.address = 1;
1467 ld.load_store.arg_2 = 0x1E;
1468 }
1469
1470 for (unsigned c = 2; c < 16; ++c)
1471 ld.swizzle[0][c] = 0;
1472 }
1473
1474 emit_mir_instruction(ctx, ld);
1475 break;
1476
1477 case nir_intrinsic_load_blend_const_color_rgba: {
1478 assert(ctx->is_blend);
1479 reg = nir_dest_index(&instr->dest);
1480
1481 /* Blend constants are embedded directly in the shader and
1482 * patched in, so we use some magic routing */
1483
1484 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1485 ins.has_constants = true;
1486 ins.has_blend_constant = true;
1487 emit_mir_instruction(ctx, ins);
1488 break;
1489 }
1490
1491 case nir_intrinsic_store_zs_output_pan: {
1492 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1493 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1494 MIDGARD_ZS_RT);
1495
1496 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1497
1498 if (!nir_intrinsic_component(instr))
1499 br->writeout_depth = true;
1500 if (nir_intrinsic_component(instr) ||
1501 instr->num_components)
1502 br->writeout_stencil = true;
1503 assert(br->writeout_depth | br->writeout_stencil);
1504 break;
1505 }
1506
1507 case nir_intrinsic_store_output:
1508 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1509
1510 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1511
1512 reg = nir_src_index(ctx, &instr->src[0]);
1513
1514 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1515 const nir_variable *var;
1516 enum midgard_rt_id rt;
1517
1518 var = search_var(&ctx->nir->outputs,
1519 nir_intrinsic_base(instr));
1520 assert(var);
1521 if (var->data.location == FRAG_RESULT_COLOR)
1522 rt = MIDGARD_COLOR_RT0;
1523 else if (var->data.location >= FRAG_RESULT_DATA0)
1524 rt = MIDGARD_COLOR_RT0 + var->data.location -
1525 FRAG_RESULT_DATA0;
1526 else
1527 assert(0);
1528
1529 emit_fragment_store(ctx, reg, rt);
1530 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1531 /* We should have been vectorized, though we don't
1532 * currently check that st_vary is emitted only once
1533 * per slot (this is relevant, since there's not a mask
1534 * parameter available on the store [set to 0 by the
1535 * blob]). We do respect the component by adjusting the
1536 * swizzle. If this is a constant source, we'll need to
1537 * emit that explicitly. */
1538
1539 emit_explicit_constant(ctx, reg, reg);
1540
1541 unsigned dst_component = nir_intrinsic_component(instr);
1542 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1543
1544 midgard_instruction st = m_st_vary_32(reg, offset);
1545 st.load_store.arg_1 = 0x9E;
1546 st.load_store.arg_2 = 0x1E;
1547
1548 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1549 case nir_type_uint:
1550 case nir_type_bool:
1551 st.load_store.op = midgard_op_st_vary_32u;
1552 break;
1553 case nir_type_int:
1554 st.load_store.op = midgard_op_st_vary_32i;
1555 break;
1556 case nir_type_float:
1557 st.load_store.op = midgard_op_st_vary_32;
1558 break;
1559 default:
1560 unreachable("Attempted to store unknown type");
1561 break;
1562 }
1563
1564 /* nir_intrinsic_component(store_intr) encodes the
1565 * destination component start. Source component offset
1566 * adjustment is taken care of in
1567 * install_registers_instr(), when offset_swizzle() is
1568 * called.
1569 */
1570 unsigned src_component = COMPONENT_X;
1571
1572 assert(nr_comp > 0);
1573 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1574 st.swizzle[0][i] = src_component;
1575 if (i >= dst_component && i < dst_component + nr_comp - 1)
1576 src_component++;
1577 }
1578
1579 emit_mir_instruction(ctx, st);
1580 } else {
1581 DBG("Unknown store\n");
1582 assert(0);
1583 }
1584
1585 break;
1586
1587 /* Special case of store_output for lowered blend shaders */
1588 case nir_intrinsic_store_raw_output_pan:
1589 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1590 reg = nir_src_index(ctx, &instr->src[0]);
1591
1592 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1593 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1594 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1595 * of:
1596 *
1597 * imov r0.xyzw, r0.xxxx
1598 */
1599
1600 unsigned expanded = make_compiler_temp(ctx);
1601
1602 midgard_instruction splatter = v_mov(reg, expanded);
1603
1604 for (unsigned c = 0; c < 16; ++c)
1605 splatter.swizzle[1][c] = 0;
1606
1607 emit_mir_instruction(ctx, splatter);
1608 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1609 } else
1610 emit_fragment_store(ctx, reg, ctx->blend_rt);
1611
1612 break;
1613
1614 case nir_intrinsic_store_global:
1615 case nir_intrinsic_store_shared:
1616 reg = nir_src_index(ctx, &instr->src[0]);
1617 emit_explicit_constant(ctx, reg, reg);
1618
1619 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1620 break;
1621
1622 case nir_intrinsic_load_ssbo_address:
1623 emit_sysval_read(ctx, &instr->instr, 1, 0);
1624 break;
1625
1626 case nir_intrinsic_get_buffer_size:
1627 emit_sysval_read(ctx, &instr->instr, 1, 8);
1628 break;
1629
1630 case nir_intrinsic_load_viewport_scale:
1631 case nir_intrinsic_load_viewport_offset:
1632 case nir_intrinsic_load_num_work_groups:
1633 case nir_intrinsic_load_sampler_lod_parameters_pan:
1634 emit_sysval_read(ctx, &instr->instr, 3, 0);
1635 break;
1636
1637 case nir_intrinsic_load_work_group_id:
1638 case nir_intrinsic_load_local_invocation_id:
1639 emit_compute_builtin(ctx, instr);
1640 break;
1641
1642 case nir_intrinsic_load_vertex_id:
1643 case nir_intrinsic_load_instance_id:
1644 emit_vertex_builtin(ctx, instr);
1645 break;
1646
1647 case nir_intrinsic_memory_barrier_buffer:
1648 case nir_intrinsic_memory_barrier_shared:
1649 break;
1650
1651 case nir_intrinsic_control_barrier:
1652 schedule_barrier(ctx);
1653 emit_control_barrier(ctx);
1654 schedule_barrier(ctx);
1655 break;
1656
1657 default:
1658 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1659 assert(0);
1660 break;
1661 }
1662 }
1663
1664 static unsigned
1665 midgard_tex_format(enum glsl_sampler_dim dim)
1666 {
1667 switch (dim) {
1668 case GLSL_SAMPLER_DIM_1D:
1669 case GLSL_SAMPLER_DIM_BUF:
1670 return MALI_TEX_1D;
1671
1672 case GLSL_SAMPLER_DIM_2D:
1673 case GLSL_SAMPLER_DIM_EXTERNAL:
1674 case GLSL_SAMPLER_DIM_RECT:
1675 return MALI_TEX_2D;
1676
1677 case GLSL_SAMPLER_DIM_3D:
1678 return MALI_TEX_3D;
1679
1680 case GLSL_SAMPLER_DIM_CUBE:
1681 return MALI_TEX_CUBE;
1682
1683 default:
1684 DBG("Unknown sampler dim type\n");
1685 assert(0);
1686 return 0;
1687 }
1688 }
1689
1690 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1691 * was successful */
1692
1693 static bool
1694 pan_attach_constant_bias(
1695 compiler_context *ctx,
1696 nir_src lod,
1697 midgard_texture_word *word)
1698 {
1699 /* To attach as constant, it has to *be* constant */
1700
1701 if (!nir_src_is_const(lod))
1702 return false;
1703
1704 float f = nir_src_as_float(lod);
1705
1706 /* Break into fixed-point */
1707 signed lod_int = f;
1708 float lod_frac = f - lod_int;
1709
1710 /* Carry over negative fractions */
1711 if (lod_frac < 0.0) {
1712 lod_int--;
1713 lod_frac += 1.0;
1714 }
1715
1716 /* Encode */
1717 word->bias = float_to_ubyte(lod_frac);
1718 word->bias_int = lod_int;
1719
1720 return true;
1721 }
1722
1723 static enum mali_sampler_type
1724 midgard_sampler_type(nir_alu_type t) {
1725 switch (nir_alu_type_get_base_type(t))
1726 {
1727 case nir_type_float:
1728 return MALI_SAMPLER_FLOAT;
1729 case nir_type_int:
1730 return MALI_SAMPLER_SIGNED;
1731 case nir_type_uint:
1732 return MALI_SAMPLER_UNSIGNED;
1733 default:
1734 unreachable("Unknown sampler type");
1735 }
1736 }
1737
1738 static void
1739 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1740 unsigned midgard_texop)
1741 {
1742 /* TODO */
1743 //assert (!instr->sampler);
1744
1745 int texture_index = instr->texture_index;
1746 int sampler_index = texture_index;
1747
1748 /* No helper to build texture words -- we do it all here */
1749 midgard_instruction ins = {
1750 .type = TAG_TEXTURE_4,
1751 .mask = 0xF,
1752 .dest = nir_dest_index(&instr->dest),
1753 .src = { ~0, ~0, ~0, ~0 },
1754 .swizzle = SWIZZLE_IDENTITY_4,
1755 .texture = {
1756 .op = midgard_texop,
1757 .format = midgard_tex_format(instr->sampler_dim),
1758 .texture_handle = texture_index,
1759 .sampler_handle = sampler_index,
1760
1761 /* TODO: half */
1762 .in_reg_full = 1,
1763 .out_full = 1,
1764
1765 .sampler_type = midgard_sampler_type(instr->dest_type),
1766 .shadow = instr->is_shadow,
1767 }
1768 };
1769
1770 /* We may need a temporary for the coordinate */
1771
1772 bool needs_temp_coord =
1773 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1774 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1775 (instr->is_shadow);
1776
1777 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1778
1779 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1780 int index = nir_src_index(ctx, &instr->src[i].src);
1781 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1782
1783 switch (instr->src[i].src_type) {
1784 case nir_tex_src_coord: {
1785 emit_explicit_constant(ctx, index, index);
1786
1787 unsigned coord_mask = mask_of(instr->coord_components);
1788
1789 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1790
1791 if (flip_zw)
1792 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1793
1794 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1795 /* texelFetch is undefined on samplerCube */
1796 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1797
1798 /* For cubemaps, we use a special ld/st op to
1799 * select the face and copy the xy into the
1800 * texture register */
1801
1802 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1803 ld.src[1] = index;
1804 ld.mask = 0x3; /* xy */
1805 ld.load_store.arg_1 = 0x20;
1806 ld.swizzle[1][3] = COMPONENT_X;
1807 emit_mir_instruction(ctx, ld);
1808
1809 /* xyzw -> xyxx */
1810 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1811 ins.swizzle[1][3] = COMPONENT_X;
1812 } else if (needs_temp_coord) {
1813 /* mov coord_temp, coords */
1814 midgard_instruction mov = v_mov(index, coords);
1815 mov.mask = coord_mask;
1816
1817 if (flip_zw)
1818 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1819
1820 emit_mir_instruction(ctx, mov);
1821 } else {
1822 coords = index;
1823 }
1824
1825 ins.src[1] = coords;
1826
1827 /* Texelfetch coordinates uses all four elements
1828 * (xyz/index) regardless of texture dimensionality,
1829 * which means it's necessary to zero the unused
1830 * components to keep everything happy */
1831
1832 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1833 /* mov index.zw, #0, or generalized */
1834 midgard_instruction mov =
1835 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1836 mov.has_constants = true;
1837 mov.mask = coord_mask ^ 0xF;
1838 emit_mir_instruction(ctx, mov);
1839 }
1840
1841 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1842 /* Array component in w but NIR wants it in z,
1843 * but if we have a temp coord we already fixed
1844 * that up */
1845
1846 if (nr_components == 3) {
1847 ins.swizzle[1][2] = COMPONENT_Z;
1848 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1849 } else if (nr_components == 2) {
1850 ins.swizzle[1][2] =
1851 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1852 ins.swizzle[1][3] = COMPONENT_X;
1853 } else
1854 unreachable("Invalid texture 2D components");
1855 }
1856
1857 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1858 /* We zeroed */
1859 ins.swizzle[1][2] = COMPONENT_Z;
1860 ins.swizzle[1][3] = COMPONENT_W;
1861 }
1862
1863 break;
1864 }
1865
1866 case nir_tex_src_bias:
1867 case nir_tex_src_lod: {
1868 /* Try as a constant if we can */
1869
1870 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1871 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1872 break;
1873
1874 ins.texture.lod_register = true;
1875 ins.src[2] = index;
1876
1877 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1878 ins.swizzle[2][c] = COMPONENT_X;
1879
1880 emit_explicit_constant(ctx, index, index);
1881
1882 break;
1883 };
1884
1885 case nir_tex_src_offset: {
1886 ins.texture.offset_register = true;
1887 ins.src[3] = index;
1888
1889 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1890 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1891
1892 emit_explicit_constant(ctx, index, index);
1893 break;
1894 };
1895
1896 case nir_tex_src_comparator: {
1897 unsigned comp = COMPONENT_Z;
1898
1899 /* mov coord_temp.foo, coords */
1900 midgard_instruction mov = v_mov(index, coords);
1901 mov.mask = 1 << comp;
1902
1903 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1904 mov.swizzle[1][i] = COMPONENT_X;
1905
1906 emit_mir_instruction(ctx, mov);
1907 break;
1908 }
1909
1910 default: {
1911 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1912 assert(0);
1913 }
1914 }
1915 }
1916
1917 emit_mir_instruction(ctx, ins);
1918
1919 /* Used for .cont and .last hinting */
1920 ctx->texture_op_count++;
1921 }
1922
1923 static void
1924 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1925 {
1926 switch (instr->op) {
1927 case nir_texop_tex:
1928 case nir_texop_txb:
1929 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1930 break;
1931 case nir_texop_txl:
1932 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1933 break;
1934 case nir_texop_txf:
1935 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1936 break;
1937 case nir_texop_txs:
1938 emit_sysval_read(ctx, &instr->instr, 4, 0);
1939 break;
1940 default: {
1941 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1942 assert(0);
1943 }
1944 }
1945 }
1946
1947 static void
1948 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1949 {
1950 switch (instr->type) {
1951 case nir_jump_break: {
1952 /* Emit a branch out of the loop */
1953 struct midgard_instruction br = v_branch(false, false);
1954 br.branch.target_type = TARGET_BREAK;
1955 br.branch.target_break = ctx->current_loop_depth;
1956 emit_mir_instruction(ctx, br);
1957 break;
1958 }
1959
1960 default:
1961 DBG("Unknown jump type %d\n", instr->type);
1962 break;
1963 }
1964 }
1965
1966 static void
1967 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1968 {
1969 switch (instr->type) {
1970 case nir_instr_type_load_const:
1971 emit_load_const(ctx, nir_instr_as_load_const(instr));
1972 break;
1973
1974 case nir_instr_type_intrinsic:
1975 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1976 break;
1977
1978 case nir_instr_type_alu:
1979 emit_alu(ctx, nir_instr_as_alu(instr));
1980 break;
1981
1982 case nir_instr_type_tex:
1983 emit_tex(ctx, nir_instr_as_tex(instr));
1984 break;
1985
1986 case nir_instr_type_jump:
1987 emit_jump(ctx, nir_instr_as_jump(instr));
1988 break;
1989
1990 case nir_instr_type_ssa_undef:
1991 /* Spurious */
1992 break;
1993
1994 default:
1995 DBG("Unhandled instruction type\n");
1996 break;
1997 }
1998 }
1999
2000
2001 /* ALU instructions can inline or embed constants, which decreases register
2002 * pressure and saves space. */
2003
2004 #define CONDITIONAL_ATTACH(idx) { \
2005 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2006 \
2007 if (entry) { \
2008 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2009 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2010 } \
2011 }
2012
2013 static void
2014 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2015 {
2016 mir_foreach_instr_in_block(block, alu) {
2017 /* Other instructions cannot inline constants */
2018 if (alu->type != TAG_ALU_4) continue;
2019 if (alu->compact_branch) continue;
2020
2021 /* If there is already a constant here, we can do nothing */
2022 if (alu->has_constants) continue;
2023
2024 CONDITIONAL_ATTACH(0);
2025
2026 if (!alu->has_constants) {
2027 CONDITIONAL_ATTACH(1)
2028 } else if (!alu->inline_constant) {
2029 /* Corner case: _two_ vec4 constants, for instance with a
2030 * csel. For this case, we can only use a constant
2031 * register for one, we'll have to emit a move for the
2032 * other. */
2033
2034 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2035 unsigned scratch = make_compiler_temp(ctx);
2036
2037 if (entry) {
2038 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2039 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2040
2041 /* Set the source */
2042 alu->src[1] = scratch;
2043
2044 /* Inject us -before- the last instruction which set r31 */
2045 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2046 }
2047 }
2048 }
2049 }
2050
2051 /* Being a little silly with the names, but returns the op that is the bitwise
2052 * inverse of the op with the argument switched. I.e. (f and g are
2053 * contrapositives):
2054 *
2055 * f(a, b) = ~g(b, a)
2056 *
2057 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
2058 *
2059 * f(a, b) = ~g(b, a)
2060 * ~f(a, b) = g(b, a)
2061 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
2062 * f(a, b) = h(a, b)
2063 *
2064 * Thus we define this function in pairs.
2065 */
2066
2067 static inline midgard_alu_op
2068 mir_contrapositive(midgard_alu_op op)
2069 {
2070 switch (op) {
2071 case midgard_alu_op_flt:
2072 return midgard_alu_op_fle;
2073 case midgard_alu_op_fle:
2074 return midgard_alu_op_flt;
2075
2076 case midgard_alu_op_ilt:
2077 return midgard_alu_op_ile;
2078 case midgard_alu_op_ile:
2079 return midgard_alu_op_ilt;
2080
2081 default:
2082 unreachable("No known contrapositive");
2083 }
2084 }
2085
2086 /* Midgard supports two types of constants, embedded constants (128-bit) and
2087 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2088 * constants can be demoted to inline constants, for space savings and
2089 * sometimes a performance boost */
2090
2091 static void
2092 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2093 {
2094 mir_foreach_instr_in_block(block, ins) {
2095 if (!ins->has_constants) continue;
2096 if (ins->has_inline_constant) continue;
2097
2098 /* Blend constants must not be inlined by definition */
2099 if (ins->has_blend_constant) continue;
2100
2101 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2102 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2103 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2104
2105 if (!(is_16 || is_32))
2106 continue;
2107
2108 /* src1 cannot be an inline constant due to encoding
2109 * restrictions. So, if possible we try to flip the arguments
2110 * in that case */
2111
2112 int op = ins->alu.op;
2113
2114 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2115 bool flip = alu_opcode_props[op].props & OP_COMMUTES;
2116
2117 switch (op) {
2118 /* Conditionals can be inverted */
2119 case midgard_alu_op_flt:
2120 case midgard_alu_op_ilt:
2121 case midgard_alu_op_fle:
2122 case midgard_alu_op_ile:
2123 ins->alu.op = mir_contrapositive(ins->alu.op);
2124 ins->invert = true;
2125 flip = true;
2126 break;
2127
2128 case midgard_alu_op_fcsel:
2129 case midgard_alu_op_icsel:
2130 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
2131 default:
2132 break;
2133 }
2134
2135 if (flip)
2136 mir_flip(ins);
2137 }
2138
2139 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2140 /* Extract the source information */
2141
2142 midgard_vector_alu_src *src;
2143 int q = ins->alu.src2;
2144 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2145 src = m;
2146
2147 /* Component is from the swizzle. Take a nonzero component */
2148 assert(ins->mask);
2149 unsigned first_comp = ffs(ins->mask) - 1;
2150 unsigned component = ins->swizzle[1][first_comp];
2151
2152 /* Scale constant appropriately, if we can legally */
2153 uint16_t scaled_constant = 0;
2154
2155 if (is_16) {
2156 scaled_constant = ins->constants.u16[component];
2157 } else if (midgard_is_integer_op(op)) {
2158 scaled_constant = ins->constants.u32[component];
2159
2160 /* Constant overflow after resize */
2161 if (scaled_constant != ins->constants.u32[component])
2162 continue;
2163 } else {
2164 float original = ins->constants.f32[component];
2165 scaled_constant = _mesa_float_to_half(original);
2166
2167 /* Check for loss of precision. If this is
2168 * mediump, we don't care, but for a highp
2169 * shader, we need to pay attention. NIR
2170 * doesn't yet tell us which mode we're in!
2171 * Practically this prevents most constants
2172 * from being inlined, sadly. */
2173
2174 float fp32 = _mesa_half_to_float(scaled_constant);
2175
2176 if (fp32 != original)
2177 continue;
2178 }
2179
2180 /* We don't know how to handle these with a constant */
2181
2182 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2183 DBG("Bailing inline constant...\n");
2184 continue;
2185 }
2186
2187 /* Make sure that the constant is not itself a vector
2188 * by checking if all accessed values are the same. */
2189
2190 const midgard_constants *cons = &ins->constants;
2191 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2192
2193 bool is_vector = false;
2194 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2195
2196 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2197 /* We only care if this component is actually used */
2198 if (!(mask & (1 << c)))
2199 continue;
2200
2201 uint32_t test = is_16 ?
2202 cons->u16[ins->swizzle[1][c]] :
2203 cons->u32[ins->swizzle[1][c]];
2204
2205 if (test != value) {
2206 is_vector = true;
2207 break;
2208 }
2209 }
2210
2211 if (is_vector)
2212 continue;
2213
2214 /* Get rid of the embedded constant */
2215 ins->has_constants = false;
2216 ins->src[1] = ~0;
2217 ins->has_inline_constant = true;
2218 ins->inline_constant = scaled_constant;
2219 }
2220 }
2221 }
2222
2223 /* Dead code elimination for branches at the end of a block - only one branch
2224 * per block is legal semantically */
2225
2226 static void
2227 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2228 {
2229 bool branched = false;
2230
2231 mir_foreach_instr_in_block_safe(block, ins) {
2232 if (!midgard_is_branch_unit(ins->unit)) continue;
2233
2234 if (branched)
2235 mir_remove_instruction(ins);
2236
2237 branched = true;
2238 }
2239 }
2240
2241 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2242 * the move can be propagated away entirely */
2243
2244 static bool
2245 mir_compose_float_outmod(midgard_outmod_float *outmod, midgard_outmod_float comp)
2246 {
2247 /* Nothing to do */
2248 if (comp == midgard_outmod_none)
2249 return true;
2250
2251 if (*outmod == midgard_outmod_none) {
2252 *outmod = comp;
2253 return true;
2254 }
2255
2256 /* TODO: Compose rules */
2257 return false;
2258 }
2259
2260 static bool
2261 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
2262 {
2263 bool progress = false;
2264
2265 mir_foreach_instr_in_block_safe(block, ins) {
2266 if (ins->type != TAG_ALU_4) continue;
2267 if (ins->alu.op != midgard_alu_op_fmov) continue;
2268 if (ins->alu.outmod != midgard_outmod_pos) continue;
2269
2270 /* TODO: Registers? */
2271 unsigned src = ins->src[1];
2272 if (src & PAN_IS_REG) continue;
2273
2274 /* There might be a source modifier, too */
2275 if (mir_nontrivial_source2_mod(ins)) continue;
2276
2277 /* Backpropagate the modifier */
2278 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
2279 if (v->type != TAG_ALU_4) continue;
2280 if (v->dest != src) continue;
2281
2282 /* Can we even take a float outmod? */
2283 if (midgard_is_integer_out_op(v->alu.op)) continue;
2284
2285 midgard_outmod_float temp = v->alu.outmod;
2286 progress |= mir_compose_float_outmod(&temp, ins->alu.outmod);
2287
2288 /* Throw in the towel.. */
2289 if (!progress) break;
2290
2291 /* Otherwise, transfer the modifier */
2292 v->alu.outmod = temp;
2293 ins->alu.outmod = midgard_outmod_none;
2294
2295 break;
2296 }
2297 }
2298
2299 return progress;
2300 }
2301
2302 static unsigned
2303 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2304 {
2305 /* Loop to ourselves */
2306 midgard_instruction *br = ctx->writeout_branch[rt];
2307 struct midgard_instruction ins = v_branch(false, false);
2308 ins.writeout = true;
2309 ins.writeout_depth = br->writeout_depth;
2310 ins.writeout_stencil = br->writeout_stencil;
2311 ins.branch.target_block = ctx->block_count - 1;
2312 ins.constants.u32[0] = br->constants.u32[0];
2313 emit_mir_instruction(ctx, ins);
2314
2315 ctx->current_block->epilogue = true;
2316 schedule_barrier(ctx);
2317 return ins.branch.target_block;
2318 }
2319
2320 static midgard_block *
2321 emit_block(compiler_context *ctx, nir_block *block)
2322 {
2323 midgard_block *this_block = ctx->after_block;
2324 ctx->after_block = NULL;
2325
2326 if (!this_block)
2327 this_block = create_empty_block(ctx);
2328
2329 list_addtail(&this_block->base.link, &ctx->blocks);
2330
2331 this_block->scheduled = false;
2332 ++ctx->block_count;
2333
2334 /* Set up current block */
2335 list_inithead(&this_block->base.instructions);
2336 ctx->current_block = this_block;
2337
2338 nir_foreach_instr(instr, block) {
2339 emit_instr(ctx, instr);
2340 ++ctx->instruction_count;
2341 }
2342
2343 return this_block;
2344 }
2345
2346 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2347
2348 static void
2349 emit_if(struct compiler_context *ctx, nir_if *nif)
2350 {
2351 midgard_block *before_block = ctx->current_block;
2352
2353 /* Speculatively emit the branch, but we can't fill it in until later */
2354 EMIT(branch, true, true);
2355 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2356 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2357
2358 /* Emit the two subblocks. */
2359 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2360 midgard_block *end_then_block = ctx->current_block;
2361
2362 /* Emit a jump from the end of the then block to the end of the else */
2363 EMIT(branch, false, false);
2364 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2365
2366 /* Emit second block, and check if it's empty */
2367
2368 int else_idx = ctx->block_count;
2369 int count_in = ctx->instruction_count;
2370 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2371 midgard_block *end_else_block = ctx->current_block;
2372 int after_else_idx = ctx->block_count;
2373
2374 /* Now that we have the subblocks emitted, fix up the branches */
2375
2376 assert(then_block);
2377 assert(else_block);
2378
2379 if (ctx->instruction_count == count_in) {
2380 /* The else block is empty, so don't emit an exit jump */
2381 mir_remove_instruction(then_exit);
2382 then_branch->branch.target_block = after_else_idx;
2383 } else {
2384 then_branch->branch.target_block = else_idx;
2385 then_exit->branch.target_block = after_else_idx;
2386 }
2387
2388 /* Wire up the successors */
2389
2390 ctx->after_block = create_empty_block(ctx);
2391
2392 pan_block_add_successor(&before_block->base, &then_block->base);
2393 pan_block_add_successor(&before_block->base, &else_block->base);
2394
2395 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2396 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2397 }
2398
2399 static void
2400 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2401 {
2402 /* Remember where we are */
2403 midgard_block *start_block = ctx->current_block;
2404
2405 /* Allocate a loop number, growing the current inner loop depth */
2406 int loop_idx = ++ctx->current_loop_depth;
2407
2408 /* Get index from before the body so we can loop back later */
2409 int start_idx = ctx->block_count;
2410
2411 /* Emit the body itself */
2412 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2413
2414 /* Branch back to loop back */
2415 struct midgard_instruction br_back = v_branch(false, false);
2416 br_back.branch.target_block = start_idx;
2417 emit_mir_instruction(ctx, br_back);
2418
2419 /* Mark down that branch in the graph. */
2420 pan_block_add_successor(&start_block->base, &loop_block->base);
2421 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2422
2423 /* Find the index of the block about to follow us (note: we don't add
2424 * one; blocks are 0-indexed so we get a fencepost problem) */
2425 int break_block_idx = ctx->block_count;
2426
2427 /* Fix up the break statements we emitted to point to the right place,
2428 * now that we can allocate a block number for them */
2429 ctx->after_block = create_empty_block(ctx);
2430
2431 mir_foreach_block_from(ctx, start_block, _block) {
2432 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2433 if (ins->type != TAG_ALU_4) continue;
2434 if (!ins->compact_branch) continue;
2435
2436 /* We found a branch -- check the type to see if we need to do anything */
2437 if (ins->branch.target_type != TARGET_BREAK) continue;
2438
2439 /* It's a break! Check if it's our break */
2440 if (ins->branch.target_break != loop_idx) continue;
2441
2442 /* Okay, cool, we're breaking out of this loop.
2443 * Rewrite from a break to a goto */
2444
2445 ins->branch.target_type = TARGET_GOTO;
2446 ins->branch.target_block = break_block_idx;
2447
2448 pan_block_add_successor(_block, &ctx->after_block->base);
2449 }
2450 }
2451
2452 /* Now that we've finished emitting the loop, free up the depth again
2453 * so we play nice with recursion amid nested loops */
2454 --ctx->current_loop_depth;
2455
2456 /* Dump loop stats */
2457 ++ctx->loop_count;
2458 }
2459
2460 static midgard_block *
2461 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2462 {
2463 midgard_block *start_block = NULL;
2464
2465 foreach_list_typed(nir_cf_node, node, node, list) {
2466 switch (node->type) {
2467 case nir_cf_node_block: {
2468 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2469
2470 if (!start_block)
2471 start_block = block;
2472
2473 break;
2474 }
2475
2476 case nir_cf_node_if:
2477 emit_if(ctx, nir_cf_node_as_if(node));
2478 break;
2479
2480 case nir_cf_node_loop:
2481 emit_loop(ctx, nir_cf_node_as_loop(node));
2482 break;
2483
2484 case nir_cf_node_function:
2485 assert(0);
2486 break;
2487 }
2488 }
2489
2490 return start_block;
2491 }
2492
2493 /* Due to lookahead, we need to report the first tag executed in the command
2494 * stream and in branch targets. An initial block might be empty, so iterate
2495 * until we find one that 'works' */
2496
2497 static unsigned
2498 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2499 {
2500 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2501
2502 mir_foreach_block_from(ctx, initial_block, _v) {
2503 midgard_block *v = (midgard_block *) _v;
2504 if (v->quadword_count) {
2505 midgard_bundle *initial_bundle =
2506 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2507
2508 return initial_bundle->tag;
2509 }
2510 }
2511
2512 /* Default to a tag 1 which will break from the shader, in case we jump
2513 * to the exit block (i.e. `return` in a compute shader) */
2514
2515 return 1;
2516 }
2517
2518 /* For each fragment writeout instruction, generate a writeout loop to
2519 * associate with it */
2520
2521 static void
2522 mir_add_writeout_loops(compiler_context *ctx)
2523 {
2524 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2525 midgard_instruction *br = ctx->writeout_branch[rt];
2526 if (!br) continue;
2527
2528 unsigned popped = br->branch.target_block;
2529 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2530 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2531
2532 /* If we have more RTs, we'll need to restore back after our
2533 * loop terminates */
2534
2535 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2536 midgard_instruction uncond = v_branch(false, false);
2537 uncond.branch.target_block = popped;
2538 emit_mir_instruction(ctx, uncond);
2539 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2540 schedule_barrier(ctx);
2541 } else {
2542 /* We're last, so we can terminate here */
2543 br->last_writeout = true;
2544 }
2545 }
2546 }
2547
2548 int
2549 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2550 {
2551 struct util_dynarray *compiled = &program->compiled;
2552
2553 midgard_debug = debug_get_option_midgard_debug();
2554
2555 /* TODO: Bound against what? */
2556 compiler_context *ctx = rzalloc(NULL, compiler_context);
2557
2558 ctx->nir = nir;
2559 ctx->stage = nir->info.stage;
2560 ctx->is_blend = is_blend;
2561 ctx->alpha_ref = program->alpha_ref;
2562 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2563 ctx->quirks = midgard_get_quirks(gpu_id);
2564
2565 /* Start off with a safe cutoff, allowing usage of all 16 work
2566 * registers. Later, we'll promote uniform reads to uniform registers
2567 * if we determine it is beneficial to do so */
2568 ctx->uniform_cutoff = 8;
2569
2570 /* Initialize at a global (not block) level hash tables */
2571
2572 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2573 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2574
2575 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2576 * (so we don't accidentally duplicate the epilogue since mesa/st has
2577 * messed with our I/O quite a bit already) */
2578
2579 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2580
2581 if (ctx->stage == MESA_SHADER_VERTEX) {
2582 NIR_PASS_V(nir, nir_lower_viewport_transform);
2583 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2584 }
2585
2586 NIR_PASS_V(nir, nir_lower_var_copies);
2587 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2588 NIR_PASS_V(nir, nir_split_var_copies);
2589 NIR_PASS_V(nir, nir_lower_var_copies);
2590 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2591 NIR_PASS_V(nir, nir_lower_var_copies);
2592 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2593
2594 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2595 NIR_PASS_V(nir, nir_lower_ssbo);
2596 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2597
2598 /* Optimisation passes */
2599
2600 optimise_nir(nir, ctx->quirks);
2601
2602 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2603 nir_print_shader(nir, stdout);
2604 }
2605
2606 /* Assign sysvals and counts, now that we're sure
2607 * (post-optimisation) */
2608
2609 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2610 program->sysval_count = ctx->sysvals.sysval_count;
2611 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2612
2613 nir_foreach_function(func, nir) {
2614 if (!func->impl)
2615 continue;
2616
2617 list_inithead(&ctx->blocks);
2618 ctx->block_count = 0;
2619 ctx->func = func;
2620
2621 emit_cf_list(ctx, &func->impl->body);
2622 break; /* TODO: Multi-function shaders */
2623 }
2624
2625 util_dynarray_init(compiled, NULL);
2626
2627 /* Per-block lowering before opts */
2628
2629 mir_foreach_block(ctx, _block) {
2630 midgard_block *block = (midgard_block *) _block;
2631 inline_alu_constants(ctx, block);
2632 midgard_opt_promote_fmov(ctx, block);
2633 embedded_to_inline_constant(ctx, block);
2634 }
2635 /* MIR-level optimizations */
2636
2637 bool progress = false;
2638
2639 do {
2640 progress = false;
2641
2642 mir_foreach_block(ctx, _block) {
2643 midgard_block *block = (midgard_block *) _block;
2644 progress |= midgard_opt_pos_propagate(ctx, block);
2645 progress |= midgard_opt_copy_prop(ctx, block);
2646 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2647 progress |= midgard_opt_combine_projection(ctx, block);
2648 progress |= midgard_opt_varying_projection(ctx, block);
2649 progress |= midgard_opt_not_propagate(ctx, block);
2650 progress |= midgard_opt_fuse_src_invert(ctx, block);
2651 progress |= midgard_opt_fuse_dest_invert(ctx, block);
2652 progress |= midgard_opt_csel_invert(ctx, block);
2653 progress |= midgard_opt_drop_cmp_invert(ctx, block);
2654 progress |= midgard_opt_invert_branch(ctx, block);
2655 }
2656 } while (progress);
2657
2658 mir_foreach_block(ctx, _block) {
2659 midgard_block *block = (midgard_block *) _block;
2660 midgard_lower_invert(ctx, block);
2661 midgard_lower_derivatives(ctx, block);
2662 }
2663
2664 /* Nested control-flow can result in dead branches at the end of the
2665 * block. This messes with our analysis and is just dead code, so cull
2666 * them */
2667 mir_foreach_block(ctx, _block) {
2668 midgard_block *block = (midgard_block *) _block;
2669 midgard_opt_cull_dead_branch(ctx, block);
2670 }
2671
2672 /* Ensure we were lowered */
2673 mir_foreach_instr_global(ctx, ins) {
2674 assert(!ins->invert);
2675 }
2676
2677 if (ctx->stage == MESA_SHADER_FRAGMENT)
2678 mir_add_writeout_loops(ctx);
2679
2680 /* Schedule! */
2681 midgard_schedule_program(ctx);
2682 mir_ra(ctx);
2683
2684 /* Now that all the bundles are scheduled and we can calculate block
2685 * sizes, emit actual branch instructions rather than placeholders */
2686
2687 int br_block_idx = 0;
2688
2689 mir_foreach_block(ctx, _block) {
2690 midgard_block *block = (midgard_block *) _block;
2691 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2692 for (int c = 0; c < bundle->instruction_count; ++c) {
2693 midgard_instruction *ins = bundle->instructions[c];
2694
2695 if (!midgard_is_branch_unit(ins->unit)) continue;
2696
2697 /* Parse some basic branch info */
2698 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2699 bool is_conditional = ins->branch.conditional;
2700 bool is_inverted = ins->branch.invert_conditional;
2701 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2702 bool is_writeout = ins->writeout;
2703
2704 /* Determine the block we're jumping to */
2705 int target_number = ins->branch.target_block;
2706
2707 /* Report the destination tag */
2708 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2709
2710 /* Count up the number of quadwords we're
2711 * jumping over = number of quadwords until
2712 * (br_block_idx, target_number) */
2713
2714 int quadword_offset = 0;
2715
2716 if (is_discard) {
2717 /* Ignored */
2718 } else if (target_number > br_block_idx) {
2719 /* Jump forward */
2720
2721 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2722 midgard_block *blk = mir_get_block(ctx, idx);
2723 assert(blk);
2724
2725 quadword_offset += blk->quadword_count;
2726 }
2727 } else {
2728 /* Jump backwards */
2729
2730 for (int idx = br_block_idx; idx >= target_number; --idx) {
2731 midgard_block *blk = mir_get_block(ctx, idx);
2732 assert(blk);
2733
2734 quadword_offset -= blk->quadword_count;
2735 }
2736 }
2737
2738 /* Unconditional extended branches (far jumps)
2739 * have issues, so we always use a conditional
2740 * branch, setting the condition to always for
2741 * unconditional. For compact unconditional
2742 * branches, cond isn't used so it doesn't
2743 * matter what we pick. */
2744
2745 midgard_condition cond =
2746 !is_conditional ? midgard_condition_always :
2747 is_inverted ? midgard_condition_false :
2748 midgard_condition_true;
2749
2750 midgard_jmp_writeout_op op =
2751 is_discard ? midgard_jmp_writeout_op_discard :
2752 is_writeout ? midgard_jmp_writeout_op_writeout :
2753 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2754 midgard_jmp_writeout_op_branch_cond;
2755
2756 if (!is_compact) {
2757 midgard_branch_extended branch =
2758 midgard_create_branch_extended(
2759 cond, op,
2760 dest_tag,
2761 quadword_offset);
2762
2763 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2764 } else if (is_conditional || is_discard) {
2765 midgard_branch_cond branch = {
2766 .op = op,
2767 .dest_tag = dest_tag,
2768 .offset = quadword_offset,
2769 .cond = cond
2770 };
2771
2772 assert(branch.offset == quadword_offset);
2773
2774 memcpy(&ins->br_compact, &branch, sizeof(branch));
2775 } else {
2776 assert(op == midgard_jmp_writeout_op_branch_uncond);
2777
2778 midgard_branch_uncond branch = {
2779 .op = op,
2780 .dest_tag = dest_tag,
2781 .offset = quadword_offset,
2782 .unknown = 1
2783 };
2784
2785 assert(branch.offset == quadword_offset);
2786
2787 memcpy(&ins->br_compact, &branch, sizeof(branch));
2788 }
2789 }
2790 }
2791
2792 ++br_block_idx;
2793 }
2794
2795 /* Emit flat binary from the instruction arrays. Iterate each block in
2796 * sequence. Save instruction boundaries such that lookahead tags can
2797 * be assigned easily */
2798
2799 /* Cache _all_ bundles in source order for lookahead across failed branches */
2800
2801 int bundle_count = 0;
2802 mir_foreach_block(ctx, _block) {
2803 midgard_block *block = (midgard_block *) _block;
2804 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2805 }
2806 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2807 int bundle_idx = 0;
2808 mir_foreach_block(ctx, _block) {
2809 midgard_block *block = (midgard_block *) _block;
2810 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2811 source_order_bundles[bundle_idx++] = bundle;
2812 }
2813 }
2814
2815 int current_bundle = 0;
2816
2817 /* Midgard prefetches instruction types, so during emission we
2818 * need to lookahead. Unless this is the last instruction, in
2819 * which we return 1. */
2820
2821 mir_foreach_block(ctx, _block) {
2822 midgard_block *block = (midgard_block *) _block;
2823 mir_foreach_bundle_in_block(block, bundle) {
2824 int lookahead = 1;
2825
2826 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2827 lookahead = source_order_bundles[current_bundle + 1]->tag;
2828
2829 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2830 ++current_bundle;
2831 }
2832
2833 /* TODO: Free deeper */
2834 //util_dynarray_fini(&block->instructions);
2835 }
2836
2837 free(source_order_bundles);
2838
2839 /* Report the very first tag executed */
2840 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2841
2842 /* Deal with off-by-one related to the fencepost problem */
2843 program->work_register_count = ctx->work_registers + 1;
2844 program->uniform_cutoff = ctx->uniform_cutoff;
2845
2846 program->blend_patch_offset = ctx->blend_constant_offset;
2847 program->tls_size = ctx->tls_size;
2848
2849 if (midgard_debug & MIDGARD_DBG_SHADERS)
2850 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2851
2852 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2853 unsigned nr_bundles = 0, nr_ins = 0;
2854
2855 /* Count instructions and bundles */
2856
2857 mir_foreach_block(ctx, _block) {
2858 midgard_block *block = (midgard_block *) _block;
2859 nr_bundles += util_dynarray_num_elements(
2860 &block->bundles, midgard_bundle);
2861
2862 mir_foreach_bundle_in_block(block, bun)
2863 nr_ins += bun->instruction_count;
2864 }
2865
2866 /* Calculate thread count. There are certain cutoffs by
2867 * register count for thread count */
2868
2869 unsigned nr_registers = program->work_register_count;
2870
2871 unsigned nr_threads =
2872 (nr_registers <= 4) ? 4 :
2873 (nr_registers <= 8) ? 2 :
2874 1;
2875
2876 /* Dump stats */
2877
2878 fprintf(stderr, "shader%d - %s shader: "
2879 "%u inst, %u bundles, %u quadwords, "
2880 "%u registers, %u threads, %u loops, "
2881 "%u:%u spills:fills\n",
2882 SHADER_DB_COUNT++,
2883 gl_shader_stage_name(ctx->stage),
2884 nr_ins, nr_bundles, ctx->quadword_count,
2885 nr_registers, nr_threads,
2886 ctx->loop_count,
2887 ctx->spills, ctx->fills);
2888 }
2889
2890 ralloc_free(ctx);
2891
2892 return 0;
2893 }