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pan/mdg: Handle f2u8
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 M_LOAD(ld_attr_32, nir_type_uint32);
132 M_LOAD(ld_vary_32, nir_type_uint32);
133 M_LOAD(ld_ubo_int4, nir_type_uint32);
134 M_LOAD(ld_int4, nir_type_uint32);
135 M_STORE(st_int4, nir_type_uint32);
136 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
137 M_STORE(st_vary_32, nir_type_uint32);
138 M_LOAD(ld_cubemap_coords, nir_type_uint32);
139 M_LOAD(ld_compute_id, nir_type_uint32);
140
141 static midgard_instruction
142 v_branch(bool conditional, bool invert)
143 {
144 midgard_instruction ins = {
145 .type = TAG_ALU_4,
146 .unit = ALU_ENAB_BRANCH,
147 .compact_branch = true,
148 .branch = {
149 .conditional = conditional,
150 .invert_conditional = invert
151 },
152 .dest = ~0,
153 .src = { ~0, ~0, ~0, ~0 },
154 };
155
156 return ins;
157 }
158
159 static midgard_branch_extended
160 midgard_create_branch_extended( midgard_condition cond,
161 midgard_jmp_writeout_op op,
162 unsigned dest_tag,
163 signed quadword_offset)
164 {
165 /* The condition code is actually a LUT describing a function to
166 * combine multiple condition codes. However, we only support a single
167 * condition code at the moment, so we just duplicate over a bunch of
168 * times. */
169
170 uint16_t duplicated_cond =
171 (cond << 14) |
172 (cond << 12) |
173 (cond << 10) |
174 (cond << 8) |
175 (cond << 6) |
176 (cond << 4) |
177 (cond << 2) |
178 (cond << 0);
179
180 midgard_branch_extended branch = {
181 .op = op,
182 .dest_tag = dest_tag,
183 .offset = quadword_offset,
184 .cond = duplicated_cond
185 };
186
187 return branch;
188 }
189
190 static void
191 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
192 {
193 ins->has_constants = true;
194 memcpy(&ins->constants, constants, 16);
195 }
196
197 static int
198 glsl_type_size(const struct glsl_type *type, bool bindless)
199 {
200 return glsl_count_attribute_slots(type, false);
201 }
202
203 /* Lower fdot2 to a vector multiplication followed by channel addition */
204 static void
205 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
206 {
207 if (alu->op != nir_op_fdot2)
208 return;
209
210 b->cursor = nir_before_instr(&alu->instr);
211
212 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
213 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
214
215 nir_ssa_def *product = nir_fmul(b, src0, src1);
216
217 nir_ssa_def *sum = nir_fadd(b,
218 nir_channel(b, product, 0),
219 nir_channel(b, product, 1));
220
221 /* Replace the fdot2 with this sum */
222 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
223 }
224
225 static bool
226 midgard_nir_lower_fdot2(nir_shader *shader)
227 {
228 bool progress = false;
229
230 nir_foreach_function(function, shader) {
231 if (!function->impl) continue;
232
233 nir_builder _b;
234 nir_builder *b = &_b;
235 nir_builder_init(b, function->impl);
236
237 nir_foreach_block(block, function->impl) {
238 nir_foreach_instr_safe(instr, block) {
239 if (instr->type != nir_instr_type_alu) continue;
240
241 nir_alu_instr *alu = nir_instr_as_alu(instr);
242 midgard_nir_lower_fdot2_body(b, alu);
243
244 progress |= true;
245 }
246 }
247
248 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
249
250 }
251
252 return progress;
253 }
254
255 /* Midgard can't write depth and stencil separately. It has to happen in a
256 * single store operation containing both. Let's add a panfrost specific
257 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
258 * one.
259 */
260 static bool
261 midgard_nir_lower_zs_store(nir_shader *nir)
262 {
263 if (nir->info.stage != MESA_SHADER_FRAGMENT)
264 return false;
265
266 nir_variable *z_var = NULL, *s_var = NULL;
267
268 nir_foreach_variable(var, &nir->outputs) {
269 if (var->data.location == FRAG_RESULT_DEPTH)
270 z_var = var;
271 else if (var->data.location == FRAG_RESULT_STENCIL)
272 s_var = var;
273 }
274
275 if (!z_var && !s_var)
276 return false;
277
278 bool progress = false;
279
280 nir_foreach_function(function, nir) {
281 if (!function->impl) continue;
282
283 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
284
285 nir_foreach_block(block, function->impl) {
286 nir_foreach_instr_safe(instr, block) {
287 if (instr->type != nir_instr_type_intrinsic)
288 continue;
289
290 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
291 if (intr->intrinsic != nir_intrinsic_store_output)
292 continue;
293
294 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
295 assert(!z_store);
296 z_store = intr;
297 last_store = intr;
298 }
299
300 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
301 assert(!s_store);
302 s_store = intr;
303 last_store = intr;
304 }
305 }
306 }
307
308 if (!z_store && !s_store) continue;
309
310 nir_builder b;
311 nir_builder_init(&b, function->impl);
312
313 b.cursor = nir_before_instr(&last_store->instr);
314
315 nir_ssa_def *zs_store_src;
316
317 if (z_store && s_store) {
318 nir_ssa_def *srcs[2] = {
319 nir_ssa_for_src(&b, z_store->src[0], 1),
320 nir_ssa_for_src(&b, s_store->src[0], 1),
321 };
322
323 zs_store_src = nir_vec(&b, srcs, 2);
324 } else {
325 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
326 }
327
328 nir_intrinsic_instr *zs_store;
329
330 zs_store = nir_intrinsic_instr_create(b.shader,
331 nir_intrinsic_store_zs_output_pan);
332 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
333 zs_store->num_components = z_store && s_store ? 2 : 1;
334 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
335
336 /* Replace the Z and S store by a ZS store */
337 nir_builder_instr_insert(&b, &zs_store->instr);
338
339 if (z_store)
340 nir_instr_remove(&z_store->instr);
341
342 if (s_store)
343 nir_instr_remove(&s_store->instr);
344
345 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
346 progress = true;
347 }
348
349 return progress;
350 }
351
352 /* Flushes undefined values to zero */
353
354 static void
355 optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
356 {
357 bool progress;
358 unsigned lower_flrp =
359 (nir->options->lower_flrp16 ? 16 : 0) |
360 (nir->options->lower_flrp32 ? 32 : 0) |
361 (nir->options->lower_flrp64 ? 64 : 0);
362
363 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
364 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
365
366 nir_lower_tex_options lower_tex_options = {
367 .lower_txs_lod = true,
368 .lower_txp = ~0,
369 .lower_tex_without_implicit_lod =
370 (quirks & MIDGARD_EXPLICIT_LOD),
371
372 /* TODO: we have native gradient.. */
373 .lower_txd = true,
374 };
375
376 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
377
378 /* Must lower fdot2 after tex is lowered */
379 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
380
381 /* T720 is broken. */
382
383 if (quirks & MIDGARD_BROKEN_LOD)
384 NIR_PASS_V(nir, midgard_nir_lod_errata);
385
386 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_early);
387
388 if (!is_blend)
389 NIR_PASS(progress, nir, nir_fuse_io_16);
390
391 do {
392 progress = false;
393
394 NIR_PASS(progress, nir, nir_lower_var_copies);
395 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
396
397 NIR_PASS(progress, nir, nir_copy_prop);
398 NIR_PASS(progress, nir, nir_opt_remove_phis);
399 NIR_PASS(progress, nir, nir_opt_dce);
400 NIR_PASS(progress, nir, nir_opt_dead_cf);
401 NIR_PASS(progress, nir, nir_opt_cse);
402 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
403 NIR_PASS(progress, nir, nir_opt_algebraic);
404 NIR_PASS(progress, nir, nir_opt_constant_folding);
405
406 if (lower_flrp != 0) {
407 bool lower_flrp_progress = false;
408 NIR_PASS(lower_flrp_progress,
409 nir,
410 nir_lower_flrp,
411 lower_flrp,
412 false /* always_precise */,
413 nir->options->lower_ffma);
414 if (lower_flrp_progress) {
415 NIR_PASS(progress, nir,
416 nir_opt_constant_folding);
417 progress = true;
418 }
419
420 /* Nothing should rematerialize any flrps, so we only
421 * need to do this lowering once.
422 */
423 lower_flrp = 0;
424 }
425
426 NIR_PASS(progress, nir, nir_opt_undef);
427 NIR_PASS(progress, nir, nir_undef_to_zero);
428
429 NIR_PASS(progress, nir, nir_opt_loop_unroll,
430 nir_var_shader_in |
431 nir_var_shader_out |
432 nir_var_function_temp);
433
434 NIR_PASS(progress, nir, nir_opt_vectorize);
435 } while (progress);
436
437 /* Must be run at the end to prevent creation of fsin/fcos ops */
438 NIR_PASS(progress, nir, midgard_nir_scale_trig);
439
440 do {
441 progress = false;
442
443 NIR_PASS(progress, nir, nir_opt_dce);
444 NIR_PASS(progress, nir, nir_opt_algebraic);
445 NIR_PASS(progress, nir, nir_opt_constant_folding);
446 NIR_PASS(progress, nir, nir_copy_prop);
447 } while (progress);
448
449 NIR_PASS(progress, nir, nir_opt_algebraic_late);
450 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
451
452 /* We implement booleans as 32-bit 0/~0 */
453 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
454
455 /* Now that booleans are lowered, we can run out late opts */
456 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
457 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
458
459 NIR_PASS(progress, nir, nir_copy_prop);
460 NIR_PASS(progress, nir, nir_opt_dce);
461
462 /* Take us out of SSA */
463 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
464 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
465
466 /* We are a vector architecture; write combine where possible */
467 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
468 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
469
470 NIR_PASS(progress, nir, nir_opt_dce);
471 }
472
473 /* Do not actually emit a load; instead, cache the constant for inlining */
474
475 static void
476 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
477 {
478 nir_ssa_def def = instr->def;
479
480 midgard_constants *consts = rzalloc(NULL, midgard_constants);
481
482 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
483
484 #define RAW_CONST_COPY(bits) \
485 nir_const_value_to_array(consts->u##bits, instr->value, \
486 instr->def.num_components, u##bits)
487
488 switch (instr->def.bit_size) {
489 case 64:
490 RAW_CONST_COPY(64);
491 break;
492 case 32:
493 RAW_CONST_COPY(32);
494 break;
495 case 16:
496 RAW_CONST_COPY(16);
497 break;
498 case 8:
499 RAW_CONST_COPY(8);
500 break;
501 default:
502 unreachable("Invalid bit_size for load_const instruction\n");
503 }
504
505 /* Shifted for SSA, +1 for off-by-one */
506 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
507 }
508
509 /* Normally constants are embedded implicitly, but for I/O and such we have to
510 * explicitly emit a move with the constant source */
511
512 static void
513 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
514 {
515 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
516
517 if (constant_value) {
518 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
519 attach_constants(ctx, &ins, constant_value, node + 1);
520 emit_mir_instruction(ctx, ins);
521 }
522 }
523
524 static bool
525 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
526 {
527 unsigned comp = src->swizzle[0];
528
529 for (unsigned c = 1; c < nr_components; ++c) {
530 if (src->swizzle[c] != comp)
531 return true;
532 }
533
534 return false;
535 }
536
537 #define ALU_CASE(nir, _op) \
538 case nir_op_##nir: \
539 op = midgard_alu_op_##_op; \
540 assert(src_bitsize == dst_bitsize); \
541 break;
542
543 #define ALU_CASE_RTZ(nir, _op) \
544 case nir_op_##nir: \
545 op = midgard_alu_op_##_op; \
546 roundmode = MIDGARD_RTZ; \
547 break;
548
549 #define ALU_CHECK_CMP(sext) \
550 assert(src_bitsize == 16 || src_bitsize == 32); \
551 assert(dst_bitsize == 16 || dst_bitsize == 32); \
552
553 #define ALU_CASE_BCAST(nir, _op, count) \
554 case nir_op_##nir: \
555 op = midgard_alu_op_##_op; \
556 broadcast_swizzle = count; \
557 ALU_CHECK_CMP(true); \
558 break;
559
560 #define ALU_CASE_CMP(nir, _op, sext) \
561 case nir_op_##nir: \
562 op = midgard_alu_op_##_op; \
563 ALU_CHECK_CMP(sext); \
564 break;
565
566 /* Analyze the sizes of the dest and inputs to determine reg mode. */
567
568 static midgard_reg_mode
569 reg_mode_for_nir(nir_alu_instr *instr)
570 {
571 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
572 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
573 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
574
575 /* We don't have fp16 LUTs, so we'll want to emit code like:
576 *
577 * vlut.fsinr hr0, hr0
578 *
579 * where both input and output are 16-bit but the operation is carried
580 * out in 32-bit
581 */
582
583 switch (instr->op) {
584 case nir_op_fsqrt:
585 case nir_op_frcp:
586 case nir_op_frsq:
587 case nir_op_fsin:
588 case nir_op_fcos:
589 case nir_op_fexp2:
590 case nir_op_flog2:
591 max_bitsize = MAX2(max_bitsize, 32);
592 break;
593
594 /* These get lowered to moves */
595 case nir_op_pack_32_4x8:
596 max_bitsize = 8;
597 break;
598 case nir_op_pack_32_2x16:
599 max_bitsize = 16;
600 break;
601 default:
602 break;
603 }
604
605
606 switch (max_bitsize) {
607 /* Use 16 pipe for 8 since we don't support vec16 yet */
608 case 8:
609 case 16:
610 return midgard_reg_mode_16;
611 case 32:
612 return midgard_reg_mode_32;
613 case 64:
614 return midgard_reg_mode_64;
615 default:
616 unreachable("Invalid bit size");
617 }
618 }
619
620 /* Compare mir_lower_invert */
621 static bool
622 nir_accepts_inot(nir_op op, unsigned src)
623 {
624 switch (op) {
625 case nir_op_ior:
626 case nir_op_iand: /* TODO: b2f16 */
627 case nir_op_ixor:
628 return true;
629 case nir_op_b32csel:
630 /* Only the condition */
631 return (src == 0);
632 default:
633 return false;
634 }
635 }
636
637 static bool
638 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
639 {
640 if (pan_has_dest_mod(dest, op)) {
641 assert((*dest)->is_ssa);
642 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
643 return true;
644 }
645
646 return false;
647 }
648
649 static void
650 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, enum midgard_roundmode *roundmode, bool is_int, unsigned bcast_count)
651 {
652 nir_alu_src src = instr->src[i];
653
654 if (!is_int) {
655 if (pan_has_source_mod(&src, nir_op_fneg))
656 *neg = !(*neg);
657
658 if (pan_has_source_mod(&src, nir_op_fabs))
659 *abs = true;
660 }
661
662 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
663 *not = true;
664
665 if (roundmode) {
666 if (pan_has_source_mod(&src, nir_op_fround_even))
667 *roundmode = MIDGARD_RTE;
668
669 if (pan_has_source_mod(&src, nir_op_ftrunc))
670 *roundmode = MIDGARD_RTZ;
671
672 if (pan_has_source_mod(&src, nir_op_ffloor))
673 *roundmode = MIDGARD_RTN;
674
675 if (pan_has_source_mod(&src, nir_op_fceil))
676 *roundmode = MIDGARD_RTP;
677 }
678
679 unsigned bits = nir_src_bit_size(src.src);
680
681 ins->src[to] = nir_src_index(NULL, &src.src);
682 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
683
684 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
685 ins->swizzle[to][c] = src.swizzle[
686 (!bcast_count || c < bcast_count) ? c :
687 (bcast_count - 1)];
688 }
689 }
690
691 /* Midgard features both fcsel and icsel, depending on whether you want int or
692 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
693 * we should emit an int or float csel depending on what modifiers could be
694 * placed. In the absense of modifiers, this is probably arbitrary. */
695
696 static bool
697 mir_is_bcsel_float(nir_alu_instr *instr)
698 {
699 nir_op intmods[] = {
700 nir_op_i2i8, nir_op_i2i16,
701 nir_op_i2i32, nir_op_i2i64
702 };
703
704 nir_op floatmods[] = {
705 nir_op_fabs, nir_op_fneg,
706 nir_op_f2f16, nir_op_f2f32,
707 nir_op_f2f64
708 };
709
710 nir_op floatdestmods[] = {
711 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
712 nir_op_f2f16, nir_op_f2f32
713 };
714
715 signed score = 0;
716
717 for (unsigned i = 1; i < 3; ++i) {
718 nir_alu_src s = instr->src[i];
719 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
720 if (pan_has_source_mod(&s, intmods[q]))
721 score--;
722 }
723 }
724
725 for (unsigned i = 1; i < 3; ++i) {
726 nir_alu_src s = instr->src[i];
727 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
728 if (pan_has_source_mod(&s, floatmods[q]))
729 score++;
730 }
731 }
732
733 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
734 nir_dest *dest = &instr->dest.dest;
735 if (pan_has_dest_mod(&dest, floatdestmods[q]))
736 score++;
737 }
738
739 return (score > 0);
740 }
741
742 static void
743 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
744 {
745 nir_dest *dest = &instr->dest.dest;
746
747 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
748 return;
749
750 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
751 * is handled elsewhere */
752
753 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
754 midgard_emit_derivatives(ctx, instr);
755 return;
756 }
757
758 bool is_ssa = dest->is_ssa;
759
760 unsigned nr_components = nir_dest_num_components(*dest);
761 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
762 unsigned op = 0;
763
764 /* Number of components valid to check for the instruction (the rest
765 * will be forced to the last), or 0 to use as-is. Relevant as
766 * ball-type instructions have a channel count in NIR but are all vec4
767 * in Midgard */
768
769 unsigned broadcast_swizzle = 0;
770
771 /* What register mode should we operate in? */
772 midgard_reg_mode reg_mode =
773 reg_mode_for_nir(instr);
774
775 /* Should we swap arguments? */
776 bool flip_src12 = false;
777
778 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
779 unsigned dst_bitsize = nir_dest_bit_size(*dest);
780
781 enum midgard_roundmode roundmode = MIDGARD_RTE;
782
783 switch (instr->op) {
784 ALU_CASE(fadd, fadd);
785 ALU_CASE(fmul, fmul);
786 ALU_CASE(fmin, fmin);
787 ALU_CASE(fmax, fmax);
788 ALU_CASE(imin, imin);
789 ALU_CASE(imax, imax);
790 ALU_CASE(umin, umin);
791 ALU_CASE(umax, umax);
792 ALU_CASE(ffloor, ffloor);
793 ALU_CASE(fround_even, froundeven);
794 ALU_CASE(ftrunc, ftrunc);
795 ALU_CASE(fceil, fceil);
796 ALU_CASE(fdot3, fdot3);
797 ALU_CASE(fdot4, fdot4);
798 ALU_CASE(iadd, iadd);
799 ALU_CASE(isub, isub);
800 ALU_CASE(imul, imul);
801
802 /* Zero shoved as second-arg */
803 ALU_CASE(iabs, iabsdiff);
804
805 ALU_CASE(mov, imov);
806
807 ALU_CASE_CMP(feq32, feq, false);
808 ALU_CASE_CMP(fne32, fne, false);
809 ALU_CASE_CMP(flt32, flt, false);
810 ALU_CASE_CMP(ieq32, ieq, true);
811 ALU_CASE_CMP(ine32, ine, true);
812 ALU_CASE_CMP(ilt32, ilt, true);
813 ALU_CASE_CMP(ult32, ult, false);
814
815 /* We don't have a native b2f32 instruction. Instead, like many
816 * GPUs, we exploit booleans as 0/~0 for false/true, and
817 * correspondingly AND
818 * by 1.0 to do the type conversion. For the moment, prime us
819 * to emit:
820 *
821 * iand [whatever], #0
822 *
823 * At the end of emit_alu (as MIR), we'll fix-up the constant
824 */
825
826 ALU_CASE_CMP(b2f32, iand, true);
827 ALU_CASE_CMP(b2f16, iand, true);
828 ALU_CASE_CMP(b2i32, iand, true);
829
830 /* Likewise, we don't have a dedicated f2b32 instruction, but
831 * we can do a "not equal to 0.0" test. */
832
833 ALU_CASE_CMP(f2b32, fne, false);
834 ALU_CASE_CMP(i2b32, ine, true);
835
836 ALU_CASE(frcp, frcp);
837 ALU_CASE(frsq, frsqrt);
838 ALU_CASE(fsqrt, fsqrt);
839 ALU_CASE(fexp2, fexp2);
840 ALU_CASE(flog2, flog2);
841
842 ALU_CASE_RTZ(f2i64, f2i_rte);
843 ALU_CASE_RTZ(f2u64, f2u_rte);
844 ALU_CASE_RTZ(i2f64, i2f_rte);
845 ALU_CASE_RTZ(u2f64, u2f_rte);
846
847 ALU_CASE_RTZ(f2i32, f2i_rte);
848 ALU_CASE_RTZ(f2u32, f2u_rte);
849 ALU_CASE_RTZ(i2f32, i2f_rte);
850 ALU_CASE_RTZ(u2f32, u2f_rte);
851
852 ALU_CASE_RTZ(f2i8, f2i_rte);
853 ALU_CASE_RTZ(f2u8, f2u_rte);
854
855 ALU_CASE_RTZ(f2i16, f2i_rte);
856 ALU_CASE_RTZ(f2u16, f2u_rte);
857 ALU_CASE_RTZ(i2f16, i2f_rte);
858 ALU_CASE_RTZ(u2f16, u2f_rte);
859
860 ALU_CASE(fsin, fsin);
861 ALU_CASE(fcos, fcos);
862
863 /* We'll get 0 in the second arg, so:
864 * ~a = ~(a | 0) = nor(a, 0) */
865 ALU_CASE(inot, inor);
866 ALU_CASE(iand, iand);
867 ALU_CASE(ior, ior);
868 ALU_CASE(ixor, ixor);
869 ALU_CASE(ishl, ishl);
870 ALU_CASE(ishr, iasr);
871 ALU_CASE(ushr, ilsr);
872
873 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
874 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
875 ALU_CASE_CMP(b32all_fequal4, fball_eq, true);
876
877 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
878 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
879 ALU_CASE_CMP(b32any_fnequal4, fbany_neq, true);
880
881 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
882 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
883 ALU_CASE_CMP(b32all_iequal4, iball_eq, true);
884
885 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
886 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
887 ALU_CASE_CMP(b32any_inequal4, ibany_neq, true);
888
889 /* Source mods will be shoved in later */
890 ALU_CASE(fabs, fmov);
891 ALU_CASE(fneg, fmov);
892 ALU_CASE(fsat, fmov);
893 ALU_CASE(fsat_signed, fmov);
894 ALU_CASE(fclamp_pos, fmov);
895
896 /* For size conversion, we use a move. Ideally though we would squash
897 * these ops together; maybe that has to happen after in NIR as part of
898 * propagation...? An earlier algebraic pass ensured we step down by
899 * only / exactly one size. If stepping down, we use a dest override to
900 * reduce the size; if stepping up, we use a larger-sized move with a
901 * half source and a sign/zero-extension modifier */
902
903 case nir_op_i2i8:
904 case nir_op_i2i16:
905 case nir_op_i2i32:
906 case nir_op_i2i64:
907 case nir_op_u2u8:
908 case nir_op_u2u16:
909 case nir_op_u2u32:
910 case nir_op_u2u64:
911 case nir_op_f2f16:
912 case nir_op_f2f32:
913 case nir_op_f2f64: {
914 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
915 instr->op == nir_op_f2f64)
916 op = midgard_alu_op_fmov;
917 else
918 op = midgard_alu_op_imov;
919
920 break;
921 }
922
923 /* For greater-or-equal, we lower to less-or-equal and flip the
924 * arguments */
925
926 case nir_op_fge:
927 case nir_op_fge32:
928 case nir_op_ige32:
929 case nir_op_uge32: {
930 op =
931 instr->op == nir_op_fge ? midgard_alu_op_fle :
932 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
933 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
934 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
935 0;
936
937 flip_src12 = true;
938 ALU_CHECK_CMP(false);
939 break;
940 }
941
942 case nir_op_b32csel: {
943 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
944 bool is_float = mir_is_bcsel_float(instr);
945 op = is_float ?
946 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
947 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
948
949 break;
950 }
951
952 case nir_op_unpack_32_2x16:
953 case nir_op_unpack_32_4x8:
954 case nir_op_pack_32_2x16:
955 case nir_op_pack_32_4x8: {
956 op = midgard_alu_op_imov;
957 break;
958 }
959
960 default:
961 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
962 assert(0);
963 return;
964 }
965
966 /* Promote imov to fmov if it might help inline a constant */
967 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
968 && nir_src_bit_size(instr->src[0].src) == 32
969 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
970 nir_src_num_components(instr->src[0].src))) {
971 op = midgard_alu_op_fmov;
972 }
973
974 /* Midgard can perform certain modifiers on output of an ALU op */
975
976 unsigned outmod = 0;
977 bool is_int = midgard_is_integer_op(op);
978
979 if (midgard_is_integer_out_op(op)) {
980 outmod = midgard_outmod_int_wrap;
981 } else if (instr->op == nir_op_fsat) {
982 outmod = midgard_outmod_sat;
983 } else if (instr->op == nir_op_fsat_signed) {
984 outmod = midgard_outmod_sat_signed;
985 } else if (instr->op == nir_op_fclamp_pos) {
986 outmod = midgard_outmod_pos;
987 }
988
989 /* Fetch unit, quirks, etc information */
990 unsigned opcode_props = alu_opcode_props[op].props;
991 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
992
993 /* Look for floating point mods. We have the mods fsat, fsat_signed,
994 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
995 *
996 * fsat_signed(fpos(x)) = fsat(x)
997 * fsat_signed(fsat(x)) = fsat(x)
998 * fpos(fsat_signed(x)) = fsat(x)
999 * fpos(fsat(x)) = fsat(x)
1000 * fsat(fsat_signed(x)) = fsat(x)
1001 * fsat(fpos(x)) = fsat(x)
1002 *
1003 * So by cases any composition of output modifiers is equivalent to
1004 * fsat alone.
1005 */
1006
1007 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
1008 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
1009 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
1010 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
1011 bool prior = (outmod != midgard_outmod_none);
1012 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
1013
1014 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
1015 fpos ? midgard_outmod_pos :
1016 ssat ? midgard_outmod_sat_signed :
1017 outmod;
1018 }
1019
1020 midgard_instruction ins = {
1021 .type = TAG_ALU_4,
1022 .dest = nir_dest_index(dest),
1023 .dest_type = nir_op_infos[instr->op].output_type
1024 | nir_dest_bit_size(*dest),
1025 .roundmode = roundmode,
1026 };
1027
1028 enum midgard_roundmode *roundptr = (opcode_props & MIDGARD_ROUNDS) ?
1029 &ins.roundmode : NULL;
1030
1031 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
1032 ins.src[i] = ~0;
1033
1034 if (quirk_flipped_r24) {
1035 ins.src[0] = ~0;
1036 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], roundptr, is_int, broadcast_swizzle);
1037 } else {
1038 for (unsigned i = 0; i < nr_inputs; ++i) {
1039 unsigned to = i;
1040
1041 if (instr->op == nir_op_b32csel) {
1042 /* The condition is the first argument; move
1043 * the other arguments up one to be a binary
1044 * instruction for Midgard with the condition
1045 * last */
1046
1047 if (i == 0)
1048 to = 2;
1049 else if (flip_src12)
1050 to = 2 - i;
1051 else
1052 to = i - 1;
1053 } else if (flip_src12) {
1054 to = 1 - to;
1055 }
1056
1057 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], roundptr, is_int, broadcast_swizzle);
1058
1059 /* (!c) ? a : b = c ? b : a */
1060 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1061 ins.src_invert[2] = false;
1062 flip_src12 ^= true;
1063 }
1064 }
1065 }
1066
1067 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1068 /* Lowered to move */
1069 if (instr->op == nir_op_fneg)
1070 ins.src_neg[1] ^= true;
1071
1072 if (instr->op == nir_op_fabs)
1073 ins.src_abs[1] = true;
1074 }
1075
1076 ins.mask = mask_of(nr_components);
1077
1078 midgard_vector_alu alu = {
1079 .op = op,
1080 .reg_mode = reg_mode,
1081 .outmod = outmod,
1082 };
1083
1084 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1085 * components that don't exist. Note modifier => SSA => !reg => no
1086 * writemask, so we don't have to worry about writemasks here.*/
1087
1088 if (!is_ssa)
1089 ins.mask &= instr->dest.write_mask;
1090
1091 ins.alu = alu;
1092
1093 /* Late fixup for emulated instructions */
1094
1095 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1096 /* Presently, our second argument is an inline #0 constant.
1097 * Switch over to an embedded 1.0 constant (that can't fit
1098 * inline, since we're 32-bit, not 16-bit like the inline
1099 * constants) */
1100
1101 ins.has_inline_constant = false;
1102 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1103 ins.src_types[1] = nir_type_float32;
1104 ins.has_constants = true;
1105
1106 if (instr->op == nir_op_b2f32)
1107 ins.constants.f32[0] = 1.0f;
1108 else
1109 ins.constants.i32[0] = 1;
1110
1111 for (unsigned c = 0; c < 16; ++c)
1112 ins.swizzle[1][c] = 0;
1113 } else if (instr->op == nir_op_b2f16) {
1114 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1115 ins.src_types[1] = nir_type_float16;
1116 ins.has_constants = true;
1117 ins.constants.i16[0] = _mesa_float_to_half(1.0);
1118
1119 for (unsigned c = 0; c < 16; ++c)
1120 ins.swizzle[1][c] = 0;
1121 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1122 /* Lots of instructions need a 0 plonked in */
1123 ins.has_inline_constant = false;
1124 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1125 ins.src_types[1] = nir_type_uint32;
1126 ins.has_constants = true;
1127 ins.constants.u32[0] = 0;
1128
1129 for (unsigned c = 0; c < 16; ++c)
1130 ins.swizzle[1][c] = 0;
1131 } else if (instr->op == nir_op_pack_32_2x16) {
1132 ins.dest_type = nir_type_uint16;
1133 ins.mask = mask_of(nr_components * 2);
1134 ins.is_pack = true;
1135 } else if (instr->op == nir_op_pack_32_4x8) {
1136 ins.dest_type = nir_type_uint8;
1137 ins.mask = mask_of(nr_components * 4);
1138 ins.is_pack = true;
1139 } else if (instr->op == nir_op_unpack_32_2x16) {
1140 ins.dest_type = nir_type_uint32;
1141 ins.mask = mask_of(nr_components >> 1);
1142 ins.is_pack = true;
1143 } else if (instr->op == nir_op_unpack_32_4x8) {
1144 ins.dest_type = nir_type_uint32;
1145 ins.mask = mask_of(nr_components >> 2);
1146 ins.is_pack = true;
1147 }
1148
1149 /* Arrange for creation of iandnot/iornot */
1150 if (ins.src_invert[0] && !ins.src_invert[1]) {
1151 mir_flip(&ins);
1152 ins.src_invert[0] = false;
1153 ins.src_invert[1] = true;
1154 }
1155
1156 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1157 /* To avoid duplicating the lookup tables (probably), true LUT
1158 * instructions can only operate as if they were scalars. Lower
1159 * them here by changing the component. */
1160
1161 unsigned orig_mask = ins.mask;
1162
1163 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1164 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1165
1166 for (int i = 0; i < nr_components; ++i) {
1167 /* Mask the associated component, dropping the
1168 * instruction if needed */
1169
1170 ins.mask = 1 << i;
1171 ins.mask &= orig_mask;
1172
1173 if (!ins.mask)
1174 continue;
1175
1176 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1177 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1178
1179 emit_mir_instruction(ctx, ins);
1180 }
1181 } else {
1182 emit_mir_instruction(ctx, ins);
1183 }
1184 }
1185
1186 #undef ALU_CASE
1187
1188 static void
1189 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1190 {
1191 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1192 unsigned nir_mask = 0;
1193 unsigned dsize = 0;
1194
1195 if (is_read) {
1196 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1197 dsize = nir_dest_bit_size(intr->dest);
1198 } else {
1199 nir_mask = nir_intrinsic_write_mask(intr);
1200 dsize = 32;
1201 }
1202
1203 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1204 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1205 mir_set_bytemask(ins, bytemask);
1206 ins->dest_type = nir_type_uint | dsize;
1207 }
1208
1209 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1210 * optimized) versions of UBO #0 */
1211
1212 static midgard_instruction *
1213 emit_ubo_read(
1214 compiler_context *ctx,
1215 nir_instr *instr,
1216 unsigned dest,
1217 unsigned offset,
1218 nir_src *indirect_offset,
1219 unsigned indirect_shift,
1220 unsigned index)
1221 {
1222 /* TODO: half-floats */
1223
1224 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1225 ins.constants.u32[0] = offset;
1226
1227 if (instr->type == nir_instr_type_intrinsic)
1228 mir_set_intr_mask(instr, &ins, true);
1229
1230 if (indirect_offset) {
1231 ins.src[2] = nir_src_index(ctx, indirect_offset);
1232 ins.src_types[2] = nir_type_uint32;
1233 ins.load_store.arg_2 = (indirect_shift << 5);
1234 } else {
1235 ins.load_store.arg_2 = 0x1E;
1236 }
1237
1238 ins.load_store.arg_1 = index;
1239
1240 return emit_mir_instruction(ctx, ins);
1241 }
1242
1243 /* Globals are like UBOs if you squint. And shared memory is like globals if
1244 * you squint even harder */
1245
1246 static void
1247 emit_global(
1248 compiler_context *ctx,
1249 nir_instr *instr,
1250 bool is_read,
1251 unsigned srcdest,
1252 nir_src *offset,
1253 bool is_shared)
1254 {
1255 /* TODO: types */
1256
1257 midgard_instruction ins;
1258
1259 if (is_read)
1260 ins = m_ld_int4(srcdest, 0);
1261 else
1262 ins = m_st_int4(srcdest, 0);
1263
1264 mir_set_offset(ctx, &ins, offset, is_shared);
1265 mir_set_intr_mask(instr, &ins, is_read);
1266
1267 emit_mir_instruction(ctx, ins);
1268 }
1269
1270 static void
1271 emit_varying_read(
1272 compiler_context *ctx,
1273 unsigned dest, unsigned offset,
1274 unsigned nr_comp, unsigned component,
1275 nir_src *indirect_offset, nir_alu_type type, bool flat)
1276 {
1277 /* XXX: Half-floats? */
1278 /* TODO: swizzle, mask */
1279
1280 midgard_instruction ins = m_ld_vary_32(dest, offset);
1281 ins.mask = mask_of(nr_comp);
1282
1283 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1284 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1285
1286 midgard_varying_parameter p = {
1287 .is_varying = 1,
1288 .interpolation = midgard_interp_default,
1289 .flat = flat,
1290 };
1291
1292 unsigned u;
1293 memcpy(&u, &p, sizeof(p));
1294 ins.load_store.varying_parameters = u;
1295
1296 if (indirect_offset) {
1297 ins.src[2] = nir_src_index(ctx, indirect_offset);
1298 ins.src_types[2] = nir_type_uint32;
1299 } else
1300 ins.load_store.arg_2 = 0x1E;
1301
1302 ins.load_store.arg_1 = 0x9E;
1303
1304 /* Use the type appropriate load */
1305 switch (type) {
1306 case nir_type_uint32:
1307 case nir_type_bool32:
1308 ins.load_store.op = midgard_op_ld_vary_32u;
1309 break;
1310 case nir_type_int32:
1311 ins.load_store.op = midgard_op_ld_vary_32i;
1312 break;
1313 case nir_type_float32:
1314 ins.load_store.op = midgard_op_ld_vary_32;
1315 break;
1316 case nir_type_float16:
1317 ins.load_store.op = midgard_op_ld_vary_16;
1318 break;
1319 default:
1320 unreachable("Attempted to load unknown type");
1321 break;
1322 }
1323
1324 emit_mir_instruction(ctx, ins);
1325 }
1326
1327 static void
1328 emit_attr_read(
1329 compiler_context *ctx,
1330 unsigned dest, unsigned offset,
1331 unsigned nr_comp, nir_alu_type t)
1332 {
1333 midgard_instruction ins = m_ld_attr_32(dest, offset);
1334 ins.load_store.arg_1 = 0x1E;
1335 ins.load_store.arg_2 = 0x1E;
1336 ins.mask = mask_of(nr_comp);
1337
1338 /* Use the type appropriate load */
1339 switch (t) {
1340 case nir_type_uint:
1341 case nir_type_bool:
1342 ins.load_store.op = midgard_op_ld_attr_32u;
1343 break;
1344 case nir_type_int:
1345 ins.load_store.op = midgard_op_ld_attr_32i;
1346 break;
1347 case nir_type_float:
1348 ins.load_store.op = midgard_op_ld_attr_32;
1349 break;
1350 default:
1351 unreachable("Attempted to load unknown type");
1352 break;
1353 }
1354
1355 emit_mir_instruction(ctx, ins);
1356 }
1357
1358 static void
1359 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1360 unsigned nr_components, unsigned offset)
1361 {
1362 nir_dest nir_dest;
1363
1364 /* Figure out which uniform this is */
1365 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1366 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1367
1368 unsigned dest = nir_dest_index(&nir_dest);
1369
1370 /* Sysvals are prefix uniforms */
1371 unsigned uniform = ((uintptr_t) val) - 1;
1372
1373 /* Emit the read itself -- this is never indirect */
1374 midgard_instruction *ins =
1375 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1376
1377 ins->mask = mask_of(nr_components);
1378 }
1379
1380 static unsigned
1381 compute_builtin_arg(nir_op op)
1382 {
1383 switch (op) {
1384 case nir_intrinsic_load_work_group_id:
1385 return 0x14;
1386 case nir_intrinsic_load_local_invocation_id:
1387 return 0x10;
1388 default:
1389 unreachable("Invalid compute paramater loaded");
1390 }
1391 }
1392
1393 static void
1394 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1395 {
1396 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1397
1398 midgard_instruction *br = ctx->writeout_branch[rt];
1399
1400 assert(!br);
1401
1402 emit_explicit_constant(ctx, src, src);
1403
1404 struct midgard_instruction ins =
1405 v_branch(false, false);
1406
1407 ins.writeout = true;
1408
1409 /* Add dependencies */
1410 ins.src[0] = src;
1411 ins.src_types[0] = nir_type_uint32;
1412 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1413 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1414
1415 /* Emit the branch */
1416 br = emit_mir_instruction(ctx, ins);
1417 schedule_barrier(ctx);
1418 ctx->writeout_branch[rt] = br;
1419
1420 /* Push our current location = current block count - 1 = where we'll
1421 * jump to. Maybe a bit too clever for my own good */
1422
1423 br->branch.target_block = ctx->block_count - 1;
1424 }
1425
1426 static void
1427 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1428 {
1429 unsigned reg = nir_dest_index(&instr->dest);
1430 midgard_instruction ins = m_ld_compute_id(reg, 0);
1431 ins.mask = mask_of(3);
1432 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1433 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1434 emit_mir_instruction(ctx, ins);
1435 }
1436
1437 static unsigned
1438 vertex_builtin_arg(nir_op op)
1439 {
1440 switch (op) {
1441 case nir_intrinsic_load_vertex_id:
1442 return PAN_VERTEX_ID;
1443 case nir_intrinsic_load_instance_id:
1444 return PAN_INSTANCE_ID;
1445 default:
1446 unreachable("Invalid vertex builtin");
1447 }
1448 }
1449
1450 static void
1451 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1452 {
1453 unsigned reg = nir_dest_index(&instr->dest);
1454 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1455 }
1456
1457 static void
1458 emit_control_barrier(compiler_context *ctx)
1459 {
1460 midgard_instruction ins = {
1461 .type = TAG_TEXTURE_4,
1462 .dest = ~0,
1463 .src = { ~0, ~0, ~0, ~0 },
1464 .texture = {
1465 .op = TEXTURE_OP_BARRIER,
1466
1467 /* TODO: optimize */
1468 .out_of_order = MIDGARD_BARRIER_BUFFER |
1469 MIDGARD_BARRIER_SHARED ,
1470 }
1471 };
1472
1473 emit_mir_instruction(ctx, ins);
1474 }
1475
1476 static const nir_variable *
1477 search_var(struct exec_list *vars, unsigned driver_loc)
1478 {
1479 nir_foreach_variable(var, vars) {
1480 if (var->data.driver_location == driver_loc)
1481 return var;
1482 }
1483
1484 return NULL;
1485 }
1486
1487 static unsigned
1488 mir_get_branch_cond(nir_src *src, bool *invert)
1489 {
1490 /* Wrap it. No swizzle since it's a scalar */
1491
1492 nir_alu_src alu = {
1493 .src = *src
1494 };
1495
1496 *invert = pan_has_source_mod(&alu, nir_op_inot);
1497 return nir_src_index(NULL, &alu.src);
1498 }
1499
1500 static void
1501 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1502 {
1503 unsigned offset = 0, reg;
1504
1505 switch (instr->intrinsic) {
1506 case nir_intrinsic_discard_if:
1507 case nir_intrinsic_discard: {
1508 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1509 struct midgard_instruction discard = v_branch(conditional, false);
1510 discard.branch.target_type = TARGET_DISCARD;
1511
1512 if (conditional) {
1513 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1514 &discard.branch.invert_conditional);
1515 discard.src_types[0] = nir_type_uint32;
1516 }
1517
1518 emit_mir_instruction(ctx, discard);
1519 schedule_barrier(ctx);
1520
1521 break;
1522 }
1523
1524 case nir_intrinsic_load_uniform:
1525 case nir_intrinsic_load_ubo:
1526 case nir_intrinsic_load_global:
1527 case nir_intrinsic_load_shared:
1528 case nir_intrinsic_load_input:
1529 case nir_intrinsic_load_interpolated_input: {
1530 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1531 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1532 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1533 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1534 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1535 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1536
1537 /* Get the base type of the intrinsic */
1538 /* TODO: Infer type? Does it matter? */
1539 nir_alu_type t =
1540 (is_ubo || is_global || is_shared) ? nir_type_uint :
1541 (is_interp) ? nir_type_float :
1542 nir_intrinsic_type(instr);
1543
1544 t = nir_alu_type_get_base_type(t);
1545
1546 if (!(is_ubo || is_global)) {
1547 offset = nir_intrinsic_base(instr);
1548 }
1549
1550 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1551
1552 nir_src *src_offset = nir_get_io_offset_src(instr);
1553
1554 bool direct = nir_src_is_const(*src_offset);
1555 nir_src *indirect_offset = direct ? NULL : src_offset;
1556
1557 if (direct)
1558 offset += nir_src_as_uint(*src_offset);
1559
1560 /* We may need to apply a fractional offset */
1561 int component = (is_flat || is_interp) ?
1562 nir_intrinsic_component(instr) : 0;
1563 reg = nir_dest_index(&instr->dest);
1564
1565 if (is_uniform && !ctx->is_blend) {
1566 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1567 } else if (is_ubo) {
1568 nir_src index = instr->src[0];
1569
1570 /* TODO: Is indirect block number possible? */
1571 assert(nir_src_is_const(index));
1572
1573 uint32_t uindex = nir_src_as_uint(index) + 1;
1574 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1575 } else if (is_global || is_shared) {
1576 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1577 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1578 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t | nir_dest_bit_size(instr->dest), is_flat);
1579 } else if (ctx->is_blend) {
1580 /* For blend shaders, load the input color, which is
1581 * preloaded to r0 */
1582
1583 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1584 emit_mir_instruction(ctx, move);
1585 schedule_barrier(ctx);
1586 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1587 emit_attr_read(ctx, reg, offset, nr_comp, t);
1588 } else {
1589 DBG("Unknown load\n");
1590 assert(0);
1591 }
1592
1593 break;
1594 }
1595
1596 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1597 case nir_intrinsic_load_barycentric_pixel:
1598 case nir_intrinsic_load_barycentric_centroid:
1599 break;
1600
1601 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1602
1603 case nir_intrinsic_load_raw_output_pan:
1604 case nir_intrinsic_load_output_u8_as_fp16_pan:
1605 reg = nir_dest_index(&instr->dest);
1606 assert(ctx->is_blend);
1607
1608 /* T720 and below use different blend opcodes with slightly
1609 * different semantics than T760 and up */
1610
1611 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1612 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1613
1614 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1615 ld.load_store.op = old_blend ?
1616 midgard_op_ld_color_buffer_as_fp16_old :
1617 midgard_op_ld_color_buffer_as_fp16;
1618
1619 for (unsigned c = 4; c < 16; ++c)
1620 ld.swizzle[0][c] = 0;
1621
1622 ld.dest_type = nir_type_float16;
1623
1624 if (old_blend) {
1625 ld.load_store.address = 1;
1626 ld.load_store.arg_2 = 0x1E;
1627 }
1628 } else if (old_blend) {
1629 ld.load_store.op = midgard_op_ld_color_buffer_32u_old;
1630 ld.load_store.address = 16;
1631 ld.load_store.arg_2 = 0x1E;
1632 }
1633
1634 emit_mir_instruction(ctx, ld);
1635 break;
1636
1637 case nir_intrinsic_load_blend_const_color_rgba: {
1638 assert(ctx->is_blend);
1639 reg = nir_dest_index(&instr->dest);
1640
1641 /* Blend constants are embedded directly in the shader and
1642 * patched in, so we use some magic routing */
1643
1644 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1645 ins.has_constants = true;
1646 ins.has_blend_constant = true;
1647 emit_mir_instruction(ctx, ins);
1648 break;
1649 }
1650
1651 case nir_intrinsic_store_zs_output_pan: {
1652 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1653 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1654 MIDGARD_ZS_RT);
1655
1656 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1657
1658 if (!nir_intrinsic_component(instr))
1659 br->writeout_depth = true;
1660 if (nir_intrinsic_component(instr) ||
1661 instr->num_components)
1662 br->writeout_stencil = true;
1663 assert(br->writeout_depth | br->writeout_stencil);
1664 break;
1665 }
1666
1667 case nir_intrinsic_store_output:
1668 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1669
1670 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1671
1672 reg = nir_src_index(ctx, &instr->src[0]);
1673
1674 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1675 const nir_variable *var;
1676 enum midgard_rt_id rt;
1677
1678 var = search_var(&ctx->nir->outputs,
1679 nir_intrinsic_base(instr));
1680 assert(var);
1681 if (var->data.location == FRAG_RESULT_COLOR)
1682 rt = MIDGARD_COLOR_RT0;
1683 else if (var->data.location >= FRAG_RESULT_DATA0)
1684 rt = MIDGARD_COLOR_RT0 + var->data.location -
1685 FRAG_RESULT_DATA0;
1686 else
1687 assert(0);
1688
1689 emit_fragment_store(ctx, reg, rt);
1690 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1691 /* We should have been vectorized, though we don't
1692 * currently check that st_vary is emitted only once
1693 * per slot (this is relevant, since there's not a mask
1694 * parameter available on the store [set to 0 by the
1695 * blob]). We do respect the component by adjusting the
1696 * swizzle. If this is a constant source, we'll need to
1697 * emit that explicitly. */
1698
1699 emit_explicit_constant(ctx, reg, reg);
1700
1701 unsigned dst_component = nir_intrinsic_component(instr);
1702 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1703
1704 midgard_instruction st = m_st_vary_32(reg, offset);
1705 st.load_store.arg_1 = 0x9E;
1706 st.load_store.arg_2 = 0x1E;
1707
1708 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1709 case nir_type_uint:
1710 case nir_type_bool:
1711 st.load_store.op = midgard_op_st_vary_32u;
1712 break;
1713 case nir_type_int:
1714 st.load_store.op = midgard_op_st_vary_32i;
1715 break;
1716 case nir_type_float:
1717 st.load_store.op = midgard_op_st_vary_32;
1718 break;
1719 default:
1720 unreachable("Attempted to store unknown type");
1721 break;
1722 }
1723
1724 /* nir_intrinsic_component(store_intr) encodes the
1725 * destination component start. Source component offset
1726 * adjustment is taken care of in
1727 * install_registers_instr(), when offset_swizzle() is
1728 * called.
1729 */
1730 unsigned src_component = COMPONENT_X;
1731
1732 assert(nr_comp > 0);
1733 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1734 st.swizzle[0][i] = src_component;
1735 if (i >= dst_component && i < dst_component + nr_comp - 1)
1736 src_component++;
1737 }
1738
1739 emit_mir_instruction(ctx, st);
1740 } else {
1741 DBG("Unknown store\n");
1742 assert(0);
1743 }
1744
1745 break;
1746
1747 /* Special case of store_output for lowered blend shaders */
1748 case nir_intrinsic_store_raw_output_pan:
1749 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1750 reg = nir_src_index(ctx, &instr->src[0]);
1751 emit_fragment_store(ctx, reg, ctx->blend_rt);
1752 break;
1753
1754 case nir_intrinsic_store_global:
1755 case nir_intrinsic_store_shared:
1756 reg = nir_src_index(ctx, &instr->src[0]);
1757 emit_explicit_constant(ctx, reg, reg);
1758
1759 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1760 break;
1761
1762 case nir_intrinsic_load_ssbo_address:
1763 emit_sysval_read(ctx, &instr->instr, 1, 0);
1764 break;
1765
1766 case nir_intrinsic_get_buffer_size:
1767 emit_sysval_read(ctx, &instr->instr, 1, 8);
1768 break;
1769
1770 case nir_intrinsic_load_viewport_scale:
1771 case nir_intrinsic_load_viewport_offset:
1772 case nir_intrinsic_load_num_work_groups:
1773 case nir_intrinsic_load_sampler_lod_parameters_pan:
1774 emit_sysval_read(ctx, &instr->instr, 3, 0);
1775 break;
1776
1777 case nir_intrinsic_load_work_group_id:
1778 case nir_intrinsic_load_local_invocation_id:
1779 emit_compute_builtin(ctx, instr);
1780 break;
1781
1782 case nir_intrinsic_load_vertex_id:
1783 case nir_intrinsic_load_instance_id:
1784 emit_vertex_builtin(ctx, instr);
1785 break;
1786
1787 case nir_intrinsic_memory_barrier_buffer:
1788 case nir_intrinsic_memory_barrier_shared:
1789 break;
1790
1791 case nir_intrinsic_control_barrier:
1792 schedule_barrier(ctx);
1793 emit_control_barrier(ctx);
1794 schedule_barrier(ctx);
1795 break;
1796
1797 default:
1798 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1799 assert(0);
1800 break;
1801 }
1802 }
1803
1804 static unsigned
1805 midgard_tex_format(enum glsl_sampler_dim dim)
1806 {
1807 switch (dim) {
1808 case GLSL_SAMPLER_DIM_1D:
1809 case GLSL_SAMPLER_DIM_BUF:
1810 return MALI_TEX_1D;
1811
1812 case GLSL_SAMPLER_DIM_2D:
1813 case GLSL_SAMPLER_DIM_EXTERNAL:
1814 case GLSL_SAMPLER_DIM_RECT:
1815 return MALI_TEX_2D;
1816
1817 case GLSL_SAMPLER_DIM_3D:
1818 return MALI_TEX_3D;
1819
1820 case GLSL_SAMPLER_DIM_CUBE:
1821 return MALI_TEX_CUBE;
1822
1823 default:
1824 DBG("Unknown sampler dim type\n");
1825 assert(0);
1826 return 0;
1827 }
1828 }
1829
1830 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
1831 * was successful */
1832
1833 static bool
1834 pan_attach_constant_bias(
1835 compiler_context *ctx,
1836 nir_src lod,
1837 midgard_texture_word *word)
1838 {
1839 /* To attach as constant, it has to *be* constant */
1840
1841 if (!nir_src_is_const(lod))
1842 return false;
1843
1844 float f = nir_src_as_float(lod);
1845
1846 /* Break into fixed-point */
1847 signed lod_int = f;
1848 float lod_frac = f - lod_int;
1849
1850 /* Carry over negative fractions */
1851 if (lod_frac < 0.0) {
1852 lod_int--;
1853 lod_frac += 1.0;
1854 }
1855
1856 /* Encode */
1857 word->bias = float_to_ubyte(lod_frac);
1858 word->bias_int = lod_int;
1859
1860 return true;
1861 }
1862
1863 static void
1864 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1865 unsigned midgard_texop)
1866 {
1867 /* TODO */
1868 //assert (!instr->sampler);
1869
1870 int texture_index = instr->texture_index;
1871 int sampler_index = texture_index;
1872
1873 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1874 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1875
1876 midgard_instruction ins = {
1877 .type = TAG_TEXTURE_4,
1878 .mask = 0xF,
1879 .dest = nir_dest_index(&instr->dest),
1880 .src = { ~0, ~0, ~0, ~0 },
1881 .dest_type = dest_type,
1882 .swizzle = SWIZZLE_IDENTITY_4,
1883 .texture = {
1884 .op = midgard_texop,
1885 .format = midgard_tex_format(instr->sampler_dim),
1886 .texture_handle = texture_index,
1887 .sampler_handle = sampler_index,
1888 .shadow = instr->is_shadow,
1889 }
1890 };
1891
1892 if (instr->is_shadow && !instr->is_new_style_shadow)
1893 for (int i = 0; i < 4; ++i)
1894 ins.swizzle[0][i] = COMPONENT_X;
1895
1896 /* We may need a temporary for the coordinate */
1897
1898 bool needs_temp_coord =
1899 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1900 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1901 (instr->is_shadow);
1902
1903 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1904
1905 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1906 int index = nir_src_index(ctx, &instr->src[i].src);
1907 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1908 unsigned sz = nir_src_bit_size(instr->src[i].src);
1909 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1910
1911 switch (instr->src[i].src_type) {
1912 case nir_tex_src_coord: {
1913 emit_explicit_constant(ctx, index, index);
1914
1915 unsigned coord_mask = mask_of(instr->coord_components);
1916
1917 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1918
1919 if (flip_zw)
1920 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1921
1922 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1923 /* texelFetch is undefined on samplerCube */
1924 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1925
1926 /* For cubemaps, we use a special ld/st op to
1927 * select the face and copy the xy into the
1928 * texture register */
1929
1930 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1931 ld.src[1] = index;
1932 ld.src_types[1] = T;
1933 ld.mask = 0x3; /* xy */
1934 ld.load_store.arg_1 = 0x20;
1935 ld.swizzle[1][3] = COMPONENT_X;
1936 emit_mir_instruction(ctx, ld);
1937
1938 /* xyzw -> xyxx */
1939 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1940 ins.swizzle[1][3] = COMPONENT_X;
1941 } else if (needs_temp_coord) {
1942 /* mov coord_temp, coords */
1943 midgard_instruction mov = v_mov(index, coords);
1944 mov.mask = coord_mask;
1945
1946 if (flip_zw)
1947 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1948
1949 emit_mir_instruction(ctx, mov);
1950 } else {
1951 coords = index;
1952 }
1953
1954 ins.src[1] = coords;
1955 ins.src_types[1] = T;
1956
1957 /* Texelfetch coordinates uses all four elements
1958 * (xyz/index) regardless of texture dimensionality,
1959 * which means it's necessary to zero the unused
1960 * components to keep everything happy */
1961
1962 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1963 /* mov index.zw, #0, or generalized */
1964 midgard_instruction mov =
1965 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1966 mov.has_constants = true;
1967 mov.mask = coord_mask ^ 0xF;
1968 emit_mir_instruction(ctx, mov);
1969 }
1970
1971 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1972 /* Array component in w but NIR wants it in z,
1973 * but if we have a temp coord we already fixed
1974 * that up */
1975
1976 if (nr_components == 3) {
1977 ins.swizzle[1][2] = COMPONENT_Z;
1978 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1979 } else if (nr_components == 2) {
1980 ins.swizzle[1][2] =
1981 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1982 ins.swizzle[1][3] = COMPONENT_X;
1983 } else
1984 unreachable("Invalid texture 2D components");
1985 }
1986
1987 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1988 /* We zeroed */
1989 ins.swizzle[1][2] = COMPONENT_Z;
1990 ins.swizzle[1][3] = COMPONENT_W;
1991 }
1992
1993 break;
1994 }
1995
1996 case nir_tex_src_bias:
1997 case nir_tex_src_lod: {
1998 /* Try as a constant if we can */
1999
2000 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
2001 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
2002 break;
2003
2004 ins.texture.lod_register = true;
2005 ins.src[2] = index;
2006 ins.src_types[2] = T;
2007
2008 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2009 ins.swizzle[2][c] = COMPONENT_X;
2010
2011 emit_explicit_constant(ctx, index, index);
2012
2013 break;
2014 };
2015
2016 case nir_tex_src_offset: {
2017 ins.texture.offset_register = true;
2018 ins.src[3] = index;
2019 ins.src_types[3] = T;
2020
2021 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2022 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
2023
2024 emit_explicit_constant(ctx, index, index);
2025 break;
2026 };
2027
2028 case nir_tex_src_comparator: {
2029 unsigned comp = COMPONENT_Z;
2030
2031 /* mov coord_temp.foo, coords */
2032 midgard_instruction mov = v_mov(index, coords);
2033 mov.mask = 1 << comp;
2034
2035 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
2036 mov.swizzle[1][i] = COMPONENT_X;
2037
2038 emit_mir_instruction(ctx, mov);
2039 break;
2040 }
2041
2042 default: {
2043 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
2044 assert(0);
2045 }
2046 }
2047 }
2048
2049 emit_mir_instruction(ctx, ins);
2050 }
2051
2052 static void
2053 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2054 {
2055 switch (instr->op) {
2056 case nir_texop_tex:
2057 case nir_texop_txb:
2058 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2059 break;
2060 case nir_texop_txl:
2061 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2062 break;
2063 case nir_texop_txf:
2064 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2065 break;
2066 case nir_texop_txs:
2067 emit_sysval_read(ctx, &instr->instr, 4, 0);
2068 break;
2069 default: {
2070 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2071 assert(0);
2072 }
2073 }
2074 }
2075
2076 static void
2077 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2078 {
2079 switch (instr->type) {
2080 case nir_jump_break: {
2081 /* Emit a branch out of the loop */
2082 struct midgard_instruction br = v_branch(false, false);
2083 br.branch.target_type = TARGET_BREAK;
2084 br.branch.target_break = ctx->current_loop_depth;
2085 emit_mir_instruction(ctx, br);
2086 break;
2087 }
2088
2089 default:
2090 DBG("Unknown jump type %d\n", instr->type);
2091 break;
2092 }
2093 }
2094
2095 static void
2096 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2097 {
2098 switch (instr->type) {
2099 case nir_instr_type_load_const:
2100 emit_load_const(ctx, nir_instr_as_load_const(instr));
2101 break;
2102
2103 case nir_instr_type_intrinsic:
2104 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2105 break;
2106
2107 case nir_instr_type_alu:
2108 emit_alu(ctx, nir_instr_as_alu(instr));
2109 break;
2110
2111 case nir_instr_type_tex:
2112 emit_tex(ctx, nir_instr_as_tex(instr));
2113 break;
2114
2115 case nir_instr_type_jump:
2116 emit_jump(ctx, nir_instr_as_jump(instr));
2117 break;
2118
2119 case nir_instr_type_ssa_undef:
2120 /* Spurious */
2121 break;
2122
2123 default:
2124 DBG("Unhandled instruction type\n");
2125 break;
2126 }
2127 }
2128
2129
2130 /* ALU instructions can inline or embed constants, which decreases register
2131 * pressure and saves space. */
2132
2133 #define CONDITIONAL_ATTACH(idx) { \
2134 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2135 \
2136 if (entry) { \
2137 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2138 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2139 } \
2140 }
2141
2142 static void
2143 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2144 {
2145 mir_foreach_instr_in_block(block, alu) {
2146 /* Other instructions cannot inline constants */
2147 if (alu->type != TAG_ALU_4) continue;
2148 if (alu->compact_branch) continue;
2149
2150 /* If there is already a constant here, we can do nothing */
2151 if (alu->has_constants) continue;
2152
2153 CONDITIONAL_ATTACH(0);
2154
2155 if (!alu->has_constants) {
2156 CONDITIONAL_ATTACH(1)
2157 } else if (!alu->inline_constant) {
2158 /* Corner case: _two_ vec4 constants, for instance with a
2159 * csel. For this case, we can only use a constant
2160 * register for one, we'll have to emit a move for the
2161 * other. */
2162
2163 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2164 unsigned scratch = make_compiler_temp(ctx);
2165
2166 if (entry) {
2167 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2168 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2169
2170 /* Set the source */
2171 alu->src[1] = scratch;
2172
2173 /* Inject us -before- the last instruction which set r31 */
2174 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2175 }
2176 }
2177 }
2178 }
2179
2180 /* Midgard supports two types of constants, embedded constants (128-bit) and
2181 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2182 * constants can be demoted to inline constants, for space savings and
2183 * sometimes a performance boost */
2184
2185 static void
2186 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2187 {
2188 mir_foreach_instr_in_block(block, ins) {
2189 if (!ins->has_constants) continue;
2190 if (ins->has_inline_constant) continue;
2191
2192 /* Blend constants must not be inlined by definition */
2193 if (ins->has_blend_constant) continue;
2194
2195 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2196 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2197 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2198
2199 if (!(is_16 || is_32))
2200 continue;
2201
2202 /* src1 cannot be an inline constant due to encoding
2203 * restrictions. So, if possible we try to flip the arguments
2204 * in that case */
2205
2206 int op = ins->alu.op;
2207
2208 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2209 alu_opcode_props[op].props & OP_COMMUTES) {
2210 mir_flip(ins);
2211 }
2212
2213 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2214 /* Component is from the swizzle. Take a nonzero component */
2215 assert(ins->mask);
2216 unsigned first_comp = ffs(ins->mask) - 1;
2217 unsigned component = ins->swizzle[1][first_comp];
2218
2219 /* Scale constant appropriately, if we can legally */
2220 uint16_t scaled_constant = 0;
2221
2222 if (is_16) {
2223 scaled_constant = ins->constants.u16[component];
2224 } else if (midgard_is_integer_op(op)) {
2225 scaled_constant = ins->constants.u32[component];
2226
2227 /* Constant overflow after resize */
2228 if (scaled_constant != ins->constants.u32[component])
2229 continue;
2230 } else {
2231 float original = ins->constants.f32[component];
2232 scaled_constant = _mesa_float_to_half(original);
2233
2234 /* Check for loss of precision. If this is
2235 * mediump, we don't care, but for a highp
2236 * shader, we need to pay attention. NIR
2237 * doesn't yet tell us which mode we're in!
2238 * Practically this prevents most constants
2239 * from being inlined, sadly. */
2240
2241 float fp32 = _mesa_half_to_float(scaled_constant);
2242
2243 if (fp32 != original)
2244 continue;
2245 }
2246
2247 /* Should've been const folded */
2248 if (ins->src_abs[1] || ins->src_neg[1])
2249 continue;
2250
2251 /* Make sure that the constant is not itself a vector
2252 * by checking if all accessed values are the same. */
2253
2254 const midgard_constants *cons = &ins->constants;
2255 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2256
2257 bool is_vector = false;
2258 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2259
2260 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2261 /* We only care if this component is actually used */
2262 if (!(mask & (1 << c)))
2263 continue;
2264
2265 uint32_t test = is_16 ?
2266 cons->u16[ins->swizzle[1][c]] :
2267 cons->u32[ins->swizzle[1][c]];
2268
2269 if (test != value) {
2270 is_vector = true;
2271 break;
2272 }
2273 }
2274
2275 if (is_vector)
2276 continue;
2277
2278 /* Get rid of the embedded constant */
2279 ins->has_constants = false;
2280 ins->src[1] = ~0;
2281 ins->has_inline_constant = true;
2282 ins->inline_constant = scaled_constant;
2283 }
2284 }
2285 }
2286
2287 /* Dead code elimination for branches at the end of a block - only one branch
2288 * per block is legal semantically */
2289
2290 static void
2291 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2292 {
2293 bool branched = false;
2294
2295 mir_foreach_instr_in_block_safe(block, ins) {
2296 if (!midgard_is_branch_unit(ins->unit)) continue;
2297
2298 if (branched)
2299 mir_remove_instruction(ins);
2300
2301 branched = true;
2302 }
2303 }
2304
2305 static unsigned
2306 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2307 {
2308 /* Loop to ourselves */
2309 midgard_instruction *br = ctx->writeout_branch[rt];
2310 struct midgard_instruction ins = v_branch(false, false);
2311 ins.writeout = true;
2312 ins.writeout_depth = br->writeout_depth;
2313 ins.writeout_stencil = br->writeout_stencil;
2314 ins.branch.target_block = ctx->block_count - 1;
2315 ins.constants.u32[0] = br->constants.u32[0];
2316 emit_mir_instruction(ctx, ins);
2317
2318 ctx->current_block->epilogue = true;
2319 schedule_barrier(ctx);
2320 return ins.branch.target_block;
2321 }
2322
2323 static midgard_block *
2324 emit_block(compiler_context *ctx, nir_block *block)
2325 {
2326 midgard_block *this_block = ctx->after_block;
2327 ctx->after_block = NULL;
2328
2329 if (!this_block)
2330 this_block = create_empty_block(ctx);
2331
2332 list_addtail(&this_block->base.link, &ctx->blocks);
2333
2334 this_block->scheduled = false;
2335 ++ctx->block_count;
2336
2337 /* Set up current block */
2338 list_inithead(&this_block->base.instructions);
2339 ctx->current_block = this_block;
2340
2341 nir_foreach_instr(instr, block) {
2342 emit_instr(ctx, instr);
2343 ++ctx->instruction_count;
2344 }
2345
2346 return this_block;
2347 }
2348
2349 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2350
2351 static void
2352 emit_if(struct compiler_context *ctx, nir_if *nif)
2353 {
2354 midgard_block *before_block = ctx->current_block;
2355
2356 /* Speculatively emit the branch, but we can't fill it in until later */
2357 bool inv = false;
2358 EMIT(branch, true, true);
2359 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2360 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2361 then_branch->src_types[0] = nir_type_uint32;
2362 then_branch->branch.invert_conditional = !inv;
2363
2364 /* Emit the two subblocks. */
2365 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2366 midgard_block *end_then_block = ctx->current_block;
2367
2368 /* Emit a jump from the end of the then block to the end of the else */
2369 EMIT(branch, false, false);
2370 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2371
2372 /* Emit second block, and check if it's empty */
2373
2374 int else_idx = ctx->block_count;
2375 int count_in = ctx->instruction_count;
2376 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2377 midgard_block *end_else_block = ctx->current_block;
2378 int after_else_idx = ctx->block_count;
2379
2380 /* Now that we have the subblocks emitted, fix up the branches */
2381
2382 assert(then_block);
2383 assert(else_block);
2384
2385 if (ctx->instruction_count == count_in) {
2386 /* The else block is empty, so don't emit an exit jump */
2387 mir_remove_instruction(then_exit);
2388 then_branch->branch.target_block = after_else_idx;
2389 } else {
2390 then_branch->branch.target_block = else_idx;
2391 then_exit->branch.target_block = after_else_idx;
2392 }
2393
2394 /* Wire up the successors */
2395
2396 ctx->after_block = create_empty_block(ctx);
2397
2398 pan_block_add_successor(&before_block->base, &then_block->base);
2399 pan_block_add_successor(&before_block->base, &else_block->base);
2400
2401 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2402 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2403 }
2404
2405 static void
2406 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2407 {
2408 /* Remember where we are */
2409 midgard_block *start_block = ctx->current_block;
2410
2411 /* Allocate a loop number, growing the current inner loop depth */
2412 int loop_idx = ++ctx->current_loop_depth;
2413
2414 /* Get index from before the body so we can loop back later */
2415 int start_idx = ctx->block_count;
2416
2417 /* Emit the body itself */
2418 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2419
2420 /* Branch back to loop back */
2421 struct midgard_instruction br_back = v_branch(false, false);
2422 br_back.branch.target_block = start_idx;
2423 emit_mir_instruction(ctx, br_back);
2424
2425 /* Mark down that branch in the graph. */
2426 pan_block_add_successor(&start_block->base, &loop_block->base);
2427 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2428
2429 /* Find the index of the block about to follow us (note: we don't add
2430 * one; blocks are 0-indexed so we get a fencepost problem) */
2431 int break_block_idx = ctx->block_count;
2432
2433 /* Fix up the break statements we emitted to point to the right place,
2434 * now that we can allocate a block number for them */
2435 ctx->after_block = create_empty_block(ctx);
2436
2437 mir_foreach_block_from(ctx, start_block, _block) {
2438 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2439 if (ins->type != TAG_ALU_4) continue;
2440 if (!ins->compact_branch) continue;
2441
2442 /* We found a branch -- check the type to see if we need to do anything */
2443 if (ins->branch.target_type != TARGET_BREAK) continue;
2444
2445 /* It's a break! Check if it's our break */
2446 if (ins->branch.target_break != loop_idx) continue;
2447
2448 /* Okay, cool, we're breaking out of this loop.
2449 * Rewrite from a break to a goto */
2450
2451 ins->branch.target_type = TARGET_GOTO;
2452 ins->branch.target_block = break_block_idx;
2453
2454 pan_block_add_successor(_block, &ctx->after_block->base);
2455 }
2456 }
2457
2458 /* Now that we've finished emitting the loop, free up the depth again
2459 * so we play nice with recursion amid nested loops */
2460 --ctx->current_loop_depth;
2461
2462 /* Dump loop stats */
2463 ++ctx->loop_count;
2464 }
2465
2466 static midgard_block *
2467 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2468 {
2469 midgard_block *start_block = NULL;
2470
2471 foreach_list_typed(nir_cf_node, node, node, list) {
2472 switch (node->type) {
2473 case nir_cf_node_block: {
2474 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2475
2476 if (!start_block)
2477 start_block = block;
2478
2479 break;
2480 }
2481
2482 case nir_cf_node_if:
2483 emit_if(ctx, nir_cf_node_as_if(node));
2484 break;
2485
2486 case nir_cf_node_loop:
2487 emit_loop(ctx, nir_cf_node_as_loop(node));
2488 break;
2489
2490 case nir_cf_node_function:
2491 assert(0);
2492 break;
2493 }
2494 }
2495
2496 return start_block;
2497 }
2498
2499 /* Due to lookahead, we need to report the first tag executed in the command
2500 * stream and in branch targets. An initial block might be empty, so iterate
2501 * until we find one that 'works' */
2502
2503 static unsigned
2504 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2505 {
2506 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2507
2508 mir_foreach_block_from(ctx, initial_block, _v) {
2509 midgard_block *v = (midgard_block *) _v;
2510 if (v->quadword_count) {
2511 midgard_bundle *initial_bundle =
2512 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2513
2514 return initial_bundle->tag;
2515 }
2516 }
2517
2518 /* Default to a tag 1 which will break from the shader, in case we jump
2519 * to the exit block (i.e. `return` in a compute shader) */
2520
2521 return 1;
2522 }
2523
2524 /* For each fragment writeout instruction, generate a writeout loop to
2525 * associate with it */
2526
2527 static void
2528 mir_add_writeout_loops(compiler_context *ctx)
2529 {
2530 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2531 midgard_instruction *br = ctx->writeout_branch[rt];
2532 if (!br) continue;
2533
2534 unsigned popped = br->branch.target_block;
2535 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2536 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2537 br->branch.target_type = TARGET_GOTO;
2538
2539 /* If we have more RTs, we'll need to restore back after our
2540 * loop terminates */
2541
2542 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2543 midgard_instruction uncond = v_branch(false, false);
2544 uncond.branch.target_block = popped;
2545 uncond.branch.target_type = TARGET_GOTO;
2546 emit_mir_instruction(ctx, uncond);
2547 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2548 schedule_barrier(ctx);
2549 } else {
2550 /* We're last, so we can terminate here */
2551 br->last_writeout = true;
2552 }
2553 }
2554 }
2555
2556 int
2557 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2558 {
2559 struct util_dynarray *compiled = &program->compiled;
2560
2561 midgard_debug = debug_get_option_midgard_debug();
2562
2563 /* TODO: Bound against what? */
2564 compiler_context *ctx = rzalloc(NULL, compiler_context);
2565
2566 ctx->nir = nir;
2567 ctx->stage = nir->info.stage;
2568 ctx->is_blend = is_blend;
2569 ctx->alpha_ref = program->alpha_ref;
2570 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2571 ctx->quirks = midgard_get_quirks(gpu_id);
2572
2573 /* Start off with a safe cutoff, allowing usage of all 16 work
2574 * registers. Later, we'll promote uniform reads to uniform registers
2575 * if we determine it is beneficial to do so */
2576 ctx->uniform_cutoff = 8;
2577
2578 /* Initialize at a global (not block) level hash tables */
2579
2580 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2581 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2582
2583 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2584 * (so we don't accidentally duplicate the epilogue since mesa/st has
2585 * messed with our I/O quite a bit already) */
2586
2587 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2588
2589 if (ctx->stage == MESA_SHADER_VERTEX) {
2590 NIR_PASS_V(nir, nir_lower_viewport_transform);
2591 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2592 }
2593
2594 NIR_PASS_V(nir, nir_lower_var_copies);
2595 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2596 NIR_PASS_V(nir, nir_split_var_copies);
2597 NIR_PASS_V(nir, nir_lower_var_copies);
2598 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2599 NIR_PASS_V(nir, nir_lower_var_copies);
2600 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2601
2602 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2603 NIR_PASS_V(nir, nir_lower_ssbo);
2604 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2605
2606 /* Optimisation passes */
2607
2608 optimise_nir(nir, ctx->quirks, is_blend);
2609
2610 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2611 nir_print_shader(nir, stdout);
2612 }
2613
2614 /* Assign sysvals and counts, now that we're sure
2615 * (post-optimisation) */
2616
2617 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2618 program->sysval_count = ctx->sysvals.sysval_count;
2619 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2620
2621 nir_foreach_function(func, nir) {
2622 if (!func->impl)
2623 continue;
2624
2625 list_inithead(&ctx->blocks);
2626 ctx->block_count = 0;
2627 ctx->func = func;
2628 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2629
2630 emit_cf_list(ctx, &func->impl->body);
2631 free(ctx->already_emitted);
2632 break; /* TODO: Multi-function shaders */
2633 }
2634
2635 util_dynarray_init(compiled, NULL);
2636
2637 /* Per-block lowering before opts */
2638
2639 mir_foreach_block(ctx, _block) {
2640 midgard_block *block = (midgard_block *) _block;
2641 inline_alu_constants(ctx, block);
2642 embedded_to_inline_constant(ctx, block);
2643 }
2644 /* MIR-level optimizations */
2645
2646 bool progress = false;
2647
2648 do {
2649 progress = false;
2650 progress |= midgard_opt_dead_code_eliminate(ctx);
2651
2652 mir_foreach_block(ctx, _block) {
2653 midgard_block *block = (midgard_block *) _block;
2654 progress |= midgard_opt_copy_prop(ctx, block);
2655 progress |= midgard_opt_combine_projection(ctx, block);
2656 progress |= midgard_opt_varying_projection(ctx, block);
2657 }
2658 } while (progress);
2659
2660 mir_foreach_block(ctx, _block) {
2661 midgard_block *block = (midgard_block *) _block;
2662 midgard_lower_derivatives(ctx, block);
2663 midgard_cull_dead_branch(ctx, block);
2664 }
2665
2666 if (ctx->stage == MESA_SHADER_FRAGMENT)
2667 mir_add_writeout_loops(ctx);
2668
2669 /* Analyze now that the code is known but before scheduling creates
2670 * pipeline registers which are harder to track */
2671 mir_analyze_helper_terminate(ctx);
2672 mir_analyze_helper_requirements(ctx);
2673
2674 /* Schedule! */
2675 midgard_schedule_program(ctx);
2676 mir_ra(ctx);
2677
2678 /* Now that all the bundles are scheduled and we can calculate block
2679 * sizes, emit actual branch instructions rather than placeholders */
2680
2681 int br_block_idx = 0;
2682
2683 mir_foreach_block(ctx, _block) {
2684 midgard_block *block = (midgard_block *) _block;
2685 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2686 for (int c = 0; c < bundle->instruction_count; ++c) {
2687 midgard_instruction *ins = bundle->instructions[c];
2688
2689 if (!midgard_is_branch_unit(ins->unit)) continue;
2690
2691 /* Parse some basic branch info */
2692 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2693 bool is_conditional = ins->branch.conditional;
2694 bool is_inverted = ins->branch.invert_conditional;
2695 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2696 bool is_writeout = ins->writeout;
2697
2698 /* Determine the block we're jumping to */
2699 int target_number = ins->branch.target_block;
2700
2701 /* Report the destination tag */
2702 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2703
2704 /* Count up the number of quadwords we're
2705 * jumping over = number of quadwords until
2706 * (br_block_idx, target_number) */
2707
2708 int quadword_offset = 0;
2709
2710 if (is_discard) {
2711 /* Ignored */
2712 } else if (target_number > br_block_idx) {
2713 /* Jump forward */
2714
2715 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2716 midgard_block *blk = mir_get_block(ctx, idx);
2717 assert(blk);
2718
2719 quadword_offset += blk->quadword_count;
2720 }
2721 } else {
2722 /* Jump backwards */
2723
2724 for (int idx = br_block_idx; idx >= target_number; --idx) {
2725 midgard_block *blk = mir_get_block(ctx, idx);
2726 assert(blk);
2727
2728 quadword_offset -= blk->quadword_count;
2729 }
2730 }
2731
2732 /* Unconditional extended branches (far jumps)
2733 * have issues, so we always use a conditional
2734 * branch, setting the condition to always for
2735 * unconditional. For compact unconditional
2736 * branches, cond isn't used so it doesn't
2737 * matter what we pick. */
2738
2739 midgard_condition cond =
2740 !is_conditional ? midgard_condition_always :
2741 is_inverted ? midgard_condition_false :
2742 midgard_condition_true;
2743
2744 midgard_jmp_writeout_op op =
2745 is_discard ? midgard_jmp_writeout_op_discard :
2746 is_writeout ? midgard_jmp_writeout_op_writeout :
2747 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2748 midgard_jmp_writeout_op_branch_cond;
2749
2750 if (!is_compact) {
2751 midgard_branch_extended branch =
2752 midgard_create_branch_extended(
2753 cond, op,
2754 dest_tag,
2755 quadword_offset);
2756
2757 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2758 } else if (is_conditional || is_discard) {
2759 midgard_branch_cond branch = {
2760 .op = op,
2761 .dest_tag = dest_tag,
2762 .offset = quadword_offset,
2763 .cond = cond
2764 };
2765
2766 assert(branch.offset == quadword_offset);
2767
2768 memcpy(&ins->br_compact, &branch, sizeof(branch));
2769 } else {
2770 assert(op == midgard_jmp_writeout_op_branch_uncond);
2771
2772 midgard_branch_uncond branch = {
2773 .op = op,
2774 .dest_tag = dest_tag,
2775 .offset = quadword_offset,
2776 .unknown = 1
2777 };
2778
2779 assert(branch.offset == quadword_offset);
2780
2781 memcpy(&ins->br_compact, &branch, sizeof(branch));
2782 }
2783 }
2784 }
2785
2786 ++br_block_idx;
2787 }
2788
2789 /* Emit flat binary from the instruction arrays. Iterate each block in
2790 * sequence. Save instruction boundaries such that lookahead tags can
2791 * be assigned easily */
2792
2793 /* Cache _all_ bundles in source order for lookahead across failed branches */
2794
2795 int bundle_count = 0;
2796 mir_foreach_block(ctx, _block) {
2797 midgard_block *block = (midgard_block *) _block;
2798 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2799 }
2800 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2801 int bundle_idx = 0;
2802 mir_foreach_block(ctx, _block) {
2803 midgard_block *block = (midgard_block *) _block;
2804 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2805 source_order_bundles[bundle_idx++] = bundle;
2806 }
2807 }
2808
2809 int current_bundle = 0;
2810
2811 /* Midgard prefetches instruction types, so during emission we
2812 * need to lookahead. Unless this is the last instruction, in
2813 * which we return 1. */
2814
2815 mir_foreach_block(ctx, _block) {
2816 midgard_block *block = (midgard_block *) _block;
2817 mir_foreach_bundle_in_block(block, bundle) {
2818 int lookahead = 1;
2819
2820 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2821 lookahead = source_order_bundles[current_bundle + 1]->tag;
2822
2823 emit_binary_bundle(ctx, block, bundle, compiled, lookahead);
2824 ++current_bundle;
2825 }
2826
2827 /* TODO: Free deeper */
2828 //util_dynarray_fini(&block->instructions);
2829 }
2830
2831 free(source_order_bundles);
2832
2833 /* Report the very first tag executed */
2834 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2835
2836 /* Deal with off-by-one related to the fencepost problem */
2837 program->work_register_count = ctx->work_registers + 1;
2838 program->uniform_cutoff = ctx->uniform_cutoff;
2839
2840 program->blend_patch_offset = ctx->blend_constant_offset;
2841 program->tls_size = ctx->tls_size;
2842
2843 if (midgard_debug & MIDGARD_DBG_SHADERS)
2844 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2845
2846 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2847 unsigned nr_bundles = 0, nr_ins = 0;
2848
2849 /* Count instructions and bundles */
2850
2851 mir_foreach_block(ctx, _block) {
2852 midgard_block *block = (midgard_block *) _block;
2853 nr_bundles += util_dynarray_num_elements(
2854 &block->bundles, midgard_bundle);
2855
2856 mir_foreach_bundle_in_block(block, bun)
2857 nr_ins += bun->instruction_count;
2858 }
2859
2860 /* Calculate thread count. There are certain cutoffs by
2861 * register count for thread count */
2862
2863 unsigned nr_registers = program->work_register_count;
2864
2865 unsigned nr_threads =
2866 (nr_registers <= 4) ? 4 :
2867 (nr_registers <= 8) ? 2 :
2868 1;
2869
2870 /* Dump stats */
2871
2872 fprintf(stderr, "shader%d - %s shader: "
2873 "%u inst, %u bundles, %u quadwords, "
2874 "%u registers, %u threads, %u loops, "
2875 "%u:%u spills:fills\n",
2876 SHADER_DB_COUNT++,
2877 ctx->is_blend ? "PAN_SHADER_BLEND" :
2878 gl_shader_stage_name(ctx->stage),
2879 nr_ins, nr_bundles, ctx->quadword_count,
2880 nr_registers, nr_threads,
2881 ctx->loop_count,
2882 ctx->spills, ctx->fills);
2883 }
2884
2885 ralloc_free(ctx);
2886
2887 return 0;
2888 }