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[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 } else { \
121 i.dest = ssa; \
122 i.dest_type = T; \
123 } \
124 return i; \
125 }
126
127 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
128 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
129
130 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
131 * the corresponding Midgard source */
132
133 static midgard_vector_alu_src
134 vector_alu_modifiers(bool abs, bool neg, bool is_int,
135 bool half, bool sext)
136 {
137 /* Figure out how many components there are so we can adjust.
138 * Specifically we want to broadcast the last channel so things like
139 * ball2/3 work.
140 */
141
142 midgard_vector_alu_src alu_src = {
143 .rep_low = 0,
144 .rep_high = 0,
145 .half = half
146 };
147
148 if (is_int) {
149 alu_src.mod = midgard_int_normal;
150
151 /* Sign/zero-extend if needed */
152
153 if (half) {
154 alu_src.mod = sext ?
155 midgard_int_sign_extend
156 : midgard_int_zero_extend;
157 }
158
159 /* These should have been lowered away */
160 assert(!(abs || neg));
161 } else {
162 alu_src.mod = (abs << 0) | (neg << 1);
163 }
164
165 return alu_src;
166 }
167
168 M_LOAD(ld_attr_32, nir_type_uint32);
169 M_LOAD(ld_vary_32, nir_type_uint32);
170 M_LOAD(ld_ubo_int4, nir_type_uint32);
171 M_LOAD(ld_int4, nir_type_uint32);
172 M_STORE(st_int4, nir_type_uint32);
173 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
174 M_STORE(st_vary_32, nir_type_uint32);
175 M_LOAD(ld_cubemap_coords, nir_type_uint32);
176 M_LOAD(ld_compute_id, nir_type_uint32);
177
178 static midgard_instruction
179 v_branch(bool conditional, bool invert)
180 {
181 midgard_instruction ins = {
182 .type = TAG_ALU_4,
183 .unit = ALU_ENAB_BRANCH,
184 .compact_branch = true,
185 .branch = {
186 .conditional = conditional,
187 .invert_conditional = invert
188 },
189 .dest = ~0,
190 .src = { ~0, ~0, ~0, ~0 },
191 };
192
193 return ins;
194 }
195
196 static midgard_branch_extended
197 midgard_create_branch_extended( midgard_condition cond,
198 midgard_jmp_writeout_op op,
199 unsigned dest_tag,
200 signed quadword_offset)
201 {
202 /* The condition code is actually a LUT describing a function to
203 * combine multiple condition codes. However, we only support a single
204 * condition code at the moment, so we just duplicate over a bunch of
205 * times. */
206
207 uint16_t duplicated_cond =
208 (cond << 14) |
209 (cond << 12) |
210 (cond << 10) |
211 (cond << 8) |
212 (cond << 6) |
213 (cond << 4) |
214 (cond << 2) |
215 (cond << 0);
216
217 midgard_branch_extended branch = {
218 .op = op,
219 .dest_tag = dest_tag,
220 .offset = quadword_offset,
221 .cond = duplicated_cond
222 };
223
224 return branch;
225 }
226
227 static void
228 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
229 {
230 ins->has_constants = true;
231 memcpy(&ins->constants, constants, 16);
232 }
233
234 static int
235 glsl_type_size(const struct glsl_type *type, bool bindless)
236 {
237 return glsl_count_attribute_slots(type, false);
238 }
239
240 /* Lower fdot2 to a vector multiplication followed by channel addition */
241 static void
242 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
243 {
244 if (alu->op != nir_op_fdot2)
245 return;
246
247 b->cursor = nir_before_instr(&alu->instr);
248
249 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
250 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
251
252 nir_ssa_def *product = nir_fmul(b, src0, src1);
253
254 nir_ssa_def *sum = nir_fadd(b,
255 nir_channel(b, product, 0),
256 nir_channel(b, product, 1));
257
258 /* Replace the fdot2 with this sum */
259 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
260 }
261
262 static bool
263 midgard_nir_lower_fdot2(nir_shader *shader)
264 {
265 bool progress = false;
266
267 nir_foreach_function(function, shader) {
268 if (!function->impl) continue;
269
270 nir_builder _b;
271 nir_builder *b = &_b;
272 nir_builder_init(b, function->impl);
273
274 nir_foreach_block(block, function->impl) {
275 nir_foreach_instr_safe(instr, block) {
276 if (instr->type != nir_instr_type_alu) continue;
277
278 nir_alu_instr *alu = nir_instr_as_alu(instr);
279 midgard_nir_lower_fdot2_body(b, alu);
280
281 progress |= true;
282 }
283 }
284
285 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
286
287 }
288
289 return progress;
290 }
291
292 /* Midgard can't write depth and stencil separately. It has to happen in a
293 * single store operation containing both. Let's add a panfrost specific
294 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
295 * one.
296 */
297 static bool
298 midgard_nir_lower_zs_store(nir_shader *nir)
299 {
300 if (nir->info.stage != MESA_SHADER_FRAGMENT)
301 return false;
302
303 nir_variable *z_var = NULL, *s_var = NULL;
304
305 nir_foreach_variable(var, &nir->outputs) {
306 if (var->data.location == FRAG_RESULT_DEPTH)
307 z_var = var;
308 else if (var->data.location == FRAG_RESULT_STENCIL)
309 s_var = var;
310 }
311
312 if (!z_var && !s_var)
313 return false;
314
315 bool progress = false;
316
317 nir_foreach_function(function, nir) {
318 if (!function->impl) continue;
319
320 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
321
322 nir_foreach_block(block, function->impl) {
323 nir_foreach_instr_safe(instr, block) {
324 if (instr->type != nir_instr_type_intrinsic)
325 continue;
326
327 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
328 if (intr->intrinsic != nir_intrinsic_store_output)
329 continue;
330
331 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
332 assert(!z_store);
333 z_store = intr;
334 last_store = intr;
335 }
336
337 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
338 assert(!s_store);
339 s_store = intr;
340 last_store = intr;
341 }
342 }
343 }
344
345 if (!z_store && !s_store) continue;
346
347 nir_builder b;
348 nir_builder_init(&b, function->impl);
349
350 b.cursor = nir_before_instr(&last_store->instr);
351
352 nir_ssa_def *zs_store_src;
353
354 if (z_store && s_store) {
355 nir_ssa_def *srcs[2] = {
356 nir_ssa_for_src(&b, z_store->src[0], 1),
357 nir_ssa_for_src(&b, s_store->src[0], 1),
358 };
359
360 zs_store_src = nir_vec(&b, srcs, 2);
361 } else {
362 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
363 }
364
365 nir_intrinsic_instr *zs_store;
366
367 zs_store = nir_intrinsic_instr_create(b.shader,
368 nir_intrinsic_store_zs_output_pan);
369 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
370 zs_store->num_components = z_store && s_store ? 2 : 1;
371 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
372
373 /* Replace the Z and S store by a ZS store */
374 nir_builder_instr_insert(&b, &zs_store->instr);
375
376 if (z_store)
377 nir_instr_remove(&z_store->instr);
378
379 if (s_store)
380 nir_instr_remove(&s_store->instr);
381
382 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
383 progress = true;
384 }
385
386 return progress;
387 }
388
389 /* Flushes undefined values to zero */
390
391 static void
392 optimise_nir(nir_shader *nir, unsigned quirks)
393 {
394 bool progress;
395 unsigned lower_flrp =
396 (nir->options->lower_flrp16 ? 16 : 0) |
397 (nir->options->lower_flrp32 ? 32 : 0) |
398 (nir->options->lower_flrp64 ? 64 : 0);
399
400 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
401 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
402
403 nir_lower_tex_options lower_tex_options = {
404 .lower_txs_lod = true,
405 .lower_txp = ~0,
406 .lower_tex_without_implicit_lod =
407 (quirks & MIDGARD_EXPLICIT_LOD),
408
409 /* TODO: we have native gradient.. */
410 .lower_txd = true,
411 };
412
413 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
414
415 /* Must lower fdot2 after tex is lowered */
416 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
417
418 /* T720 is broken. */
419
420 if (quirks & MIDGARD_BROKEN_LOD)
421 NIR_PASS_V(nir, midgard_nir_lod_errata);
422
423 do {
424 progress = false;
425
426 NIR_PASS(progress, nir, nir_lower_var_copies);
427 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
428
429 NIR_PASS(progress, nir, nir_copy_prop);
430 NIR_PASS(progress, nir, nir_opt_remove_phis);
431 NIR_PASS(progress, nir, nir_opt_dce);
432 NIR_PASS(progress, nir, nir_opt_dead_cf);
433 NIR_PASS(progress, nir, nir_opt_cse);
434 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
435 NIR_PASS(progress, nir, nir_opt_algebraic);
436 NIR_PASS(progress, nir, nir_opt_constant_folding);
437
438 if (lower_flrp != 0) {
439 bool lower_flrp_progress = false;
440 NIR_PASS(lower_flrp_progress,
441 nir,
442 nir_lower_flrp,
443 lower_flrp,
444 false /* always_precise */,
445 nir->options->lower_ffma);
446 if (lower_flrp_progress) {
447 NIR_PASS(progress, nir,
448 nir_opt_constant_folding);
449 progress = true;
450 }
451
452 /* Nothing should rematerialize any flrps, so we only
453 * need to do this lowering once.
454 */
455 lower_flrp = 0;
456 }
457
458 NIR_PASS(progress, nir, nir_opt_undef);
459 NIR_PASS(progress, nir, nir_undef_to_zero);
460
461 NIR_PASS(progress, nir, nir_opt_loop_unroll,
462 nir_var_shader_in |
463 nir_var_shader_out |
464 nir_var_function_temp);
465
466 NIR_PASS(progress, nir, nir_opt_vectorize);
467 } while (progress);
468
469 /* Must be run at the end to prevent creation of fsin/fcos ops */
470 NIR_PASS(progress, nir, midgard_nir_scale_trig);
471
472 do {
473 progress = false;
474
475 NIR_PASS(progress, nir, nir_opt_dce);
476 NIR_PASS(progress, nir, nir_opt_algebraic);
477 NIR_PASS(progress, nir, nir_opt_constant_folding);
478 NIR_PASS(progress, nir, nir_copy_prop);
479 } while (progress);
480
481 NIR_PASS(progress, nir, nir_opt_algebraic_late);
482 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
483
484 /* We implement booleans as 32-bit 0/~0 */
485 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
486
487 /* Now that booleans are lowered, we can run out late opts */
488 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
489 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
490
491 NIR_PASS(progress, nir, nir_copy_prop);
492 NIR_PASS(progress, nir, nir_opt_dce);
493
494 /* Take us out of SSA */
495 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
496 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
497
498 /* We are a vector architecture; write combine where possible */
499 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
500 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
501
502 NIR_PASS(progress, nir, nir_opt_dce);
503 }
504
505 /* Do not actually emit a load; instead, cache the constant for inlining */
506
507 static void
508 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
509 {
510 nir_ssa_def def = instr->def;
511
512 midgard_constants *consts = rzalloc(NULL, midgard_constants);
513
514 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
515
516 #define RAW_CONST_COPY(bits) \
517 nir_const_value_to_array(consts->u##bits, instr->value, \
518 instr->def.num_components, u##bits)
519
520 switch (instr->def.bit_size) {
521 case 64:
522 RAW_CONST_COPY(64);
523 break;
524 case 32:
525 RAW_CONST_COPY(32);
526 break;
527 case 16:
528 RAW_CONST_COPY(16);
529 break;
530 case 8:
531 RAW_CONST_COPY(8);
532 break;
533 default:
534 unreachable("Invalid bit_size for load_const instruction\n");
535 }
536
537 /* Shifted for SSA, +1 for off-by-one */
538 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
539 }
540
541 /* Normally constants are embedded implicitly, but for I/O and such we have to
542 * explicitly emit a move with the constant source */
543
544 static void
545 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
546 {
547 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
548
549 if (constant_value) {
550 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
551 attach_constants(ctx, &ins, constant_value, node + 1);
552 emit_mir_instruction(ctx, ins);
553 }
554 }
555
556 static bool
557 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
558 {
559 unsigned comp = src->swizzle[0];
560
561 for (unsigned c = 1; c < nr_components; ++c) {
562 if (src->swizzle[c] != comp)
563 return true;
564 }
565
566 return false;
567 }
568
569 #define ALU_CASE(nir, _op) \
570 case nir_op_##nir: \
571 op = midgard_alu_op_##_op; \
572 assert(src_bitsize == dst_bitsize); \
573 break;
574
575 #define ALU_CASE_BCAST(nir, _op, count) \
576 case nir_op_##nir: \
577 op = midgard_alu_op_##_op; \
578 broadcast_swizzle = count; \
579 assert(src_bitsize == dst_bitsize); \
580 break;
581 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
582 * special treatment override this anyway. */
583
584 static midgard_reg_mode
585 reg_mode_for_nir(nir_alu_instr *instr)
586 {
587 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
588
589 switch (src_bitsize) {
590 case 8:
591 return midgard_reg_mode_8;
592 case 16:
593 return midgard_reg_mode_16;
594 case 32:
595 return midgard_reg_mode_32;
596 case 64:
597 return midgard_reg_mode_64;
598 default:
599 unreachable("Invalid bit size");
600 }
601 }
602
603 /* Compare mir_lower_invert */
604 static bool
605 nir_accepts_inot(nir_op op, unsigned src)
606 {
607 switch (op) {
608 case nir_op_ior:
609 case nir_op_iand:
610 case nir_op_ixor:
611 return true;
612 case nir_op_b32csel:
613 /* Only the condition */
614 return (src == 0);
615 default:
616 return false;
617 }
618 }
619
620 static bool
621 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
622 {
623 if (pan_has_dest_mod(dest, op)) {
624 assert((*dest)->is_ssa);
625 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
626 return true;
627 }
628
629 return false;
630 }
631
632 static void
633 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, bool is_int, unsigned bcast_count)
634 {
635 nir_alu_src src = instr->src[i];
636
637 if (!is_int) {
638 if (pan_has_source_mod(&src, nir_op_fneg))
639 *neg = !(*neg);
640
641 if (pan_has_source_mod(&src, nir_op_fabs))
642 *abs = true;
643 }
644
645 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
646 *not = true;
647
648 unsigned bits = nir_src_bit_size(src.src);
649
650 ins->src[to] = nir_src_index(NULL, &src.src);
651 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
652
653 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
654 ins->swizzle[to][c] = src.swizzle[
655 (!bcast_count || c < bcast_count) ? c :
656 (bcast_count - 1)];
657 }
658 }
659
660 static void
661 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
662 {
663 nir_dest *dest = &instr->dest.dest;
664
665 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
666 return;
667
668 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
669 * is handled elsewhere */
670
671 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
672 midgard_emit_derivatives(ctx, instr);
673 return;
674 }
675
676 bool is_ssa = dest->is_ssa;
677
678 unsigned nr_components = nir_dest_num_components(*dest);
679 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
680 unsigned op = 0;
681
682 /* Number of components valid to check for the instruction (the rest
683 * will be forced to the last), or 0 to use as-is. Relevant as
684 * ball-type instructions have a channel count in NIR but are all vec4
685 * in Midgard */
686
687 unsigned broadcast_swizzle = 0;
688
689 /* What register mode should we operate in? */
690 midgard_reg_mode reg_mode =
691 reg_mode_for_nir(instr);
692
693 /* Do we need a destination override? Used for inline
694 * type conversion */
695
696 midgard_dest_override dest_override =
697 midgard_dest_override_none;
698
699 /* Should we use a smaller respective source and sign-extend? */
700
701 bool half_1 = false, sext_1 = false;
702 bool half_2 = false, sext_2 = false;
703
704 /* Should we swap arguments? */
705 bool flip_src12 = false;
706
707 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
708 unsigned dst_bitsize = nir_dest_bit_size(*dest);
709
710 switch (instr->op) {
711 ALU_CASE(fadd, fadd);
712 ALU_CASE(fmul, fmul);
713 ALU_CASE(fmin, fmin);
714 ALU_CASE(fmax, fmax);
715 ALU_CASE(imin, imin);
716 ALU_CASE(imax, imax);
717 ALU_CASE(umin, umin);
718 ALU_CASE(umax, umax);
719 ALU_CASE(ffloor, ffloor);
720 ALU_CASE(fround_even, froundeven);
721 ALU_CASE(ftrunc, ftrunc);
722 ALU_CASE(fceil, fceil);
723 ALU_CASE(fdot3, fdot3);
724 ALU_CASE(fdot4, fdot4);
725 ALU_CASE(iadd, iadd);
726 ALU_CASE(isub, isub);
727 ALU_CASE(imul, imul);
728
729 /* Zero shoved as second-arg */
730 ALU_CASE(iabs, iabsdiff);
731
732 ALU_CASE(mov, imov);
733
734 ALU_CASE(feq32, feq);
735 ALU_CASE(fne32, fne);
736 ALU_CASE(flt32, flt);
737 ALU_CASE(ieq32, ieq);
738 ALU_CASE(ine32, ine);
739 ALU_CASE(ilt32, ilt);
740 ALU_CASE(ult32, ult);
741
742 /* We don't have a native b2f32 instruction. Instead, like many
743 * GPUs, we exploit booleans as 0/~0 for false/true, and
744 * correspondingly AND
745 * by 1.0 to do the type conversion. For the moment, prime us
746 * to emit:
747 *
748 * iand [whatever], #0
749 *
750 * At the end of emit_alu (as MIR), we'll fix-up the constant
751 */
752
753 ALU_CASE(b2f32, iand);
754 ALU_CASE(b2i32, iand);
755
756 /* Likewise, we don't have a dedicated f2b32 instruction, but
757 * we can do a "not equal to 0.0" test. */
758
759 ALU_CASE(f2b32, fne);
760 ALU_CASE(i2b32, ine);
761
762 ALU_CASE(frcp, frcp);
763 ALU_CASE(frsq, frsqrt);
764 ALU_CASE(fsqrt, fsqrt);
765 ALU_CASE(fexp2, fexp2);
766 ALU_CASE(flog2, flog2);
767
768 ALU_CASE(f2i64, f2i_rtz);
769 ALU_CASE(f2u64, f2u_rtz);
770 ALU_CASE(i2f64, i2f_rtz);
771 ALU_CASE(u2f64, u2f_rtz);
772
773 ALU_CASE(f2i32, f2i_rtz);
774 ALU_CASE(f2u32, f2u_rtz);
775 ALU_CASE(i2f32, i2f_rtz);
776 ALU_CASE(u2f32, u2f_rtz);
777
778 ALU_CASE(f2i16, f2i_rtz);
779 ALU_CASE(f2u16, f2u_rtz);
780 ALU_CASE(i2f16, i2f_rtz);
781 ALU_CASE(u2f16, u2f_rtz);
782
783 ALU_CASE(fsin, fsin);
784 ALU_CASE(fcos, fcos);
785
786 /* We'll get 0 in the second arg, so:
787 * ~a = ~(a | 0) = nor(a, 0) */
788 ALU_CASE(inot, inor);
789 ALU_CASE(iand, iand);
790 ALU_CASE(ior, ior);
791 ALU_CASE(ixor, ixor);
792 ALU_CASE(ishl, ishl);
793 ALU_CASE(ishr, iasr);
794 ALU_CASE(ushr, ilsr);
795
796 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
797 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
798 ALU_CASE(b32all_fequal4, fball_eq);
799
800 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
801 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
802 ALU_CASE(b32any_fnequal4, fbany_neq);
803
804 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
805 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
806 ALU_CASE(b32all_iequal4, iball_eq);
807
808 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
809 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
810 ALU_CASE(b32any_inequal4, ibany_neq);
811
812 /* Source mods will be shoved in later */
813 ALU_CASE(fabs, fmov);
814 ALU_CASE(fneg, fmov);
815 ALU_CASE(fsat, fmov);
816 ALU_CASE(fsat_signed, fmov);
817 ALU_CASE(fclamp_pos, fmov);
818
819 /* For size conversion, we use a move. Ideally though we would squash
820 * these ops together; maybe that has to happen after in NIR as part of
821 * propagation...? An earlier algebraic pass ensured we step down by
822 * only / exactly one size. If stepping down, we use a dest override to
823 * reduce the size; if stepping up, we use a larger-sized move with a
824 * half source and a sign/zero-extension modifier */
825
826 case nir_op_i2i8:
827 case nir_op_i2i16:
828 case nir_op_i2i32:
829 case nir_op_i2i64:
830 /* If we end up upscale, we'll need a sign-extend on the
831 * operand (the second argument) */
832
833 sext_2 = true;
834 /* fallthrough */
835 case nir_op_u2u8:
836 case nir_op_u2u16:
837 case nir_op_u2u32:
838 case nir_op_u2u64:
839 case nir_op_f2f16:
840 case nir_op_f2f32:
841 case nir_op_f2f64: {
842 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
843 instr->op == nir_op_f2f64)
844 op = midgard_alu_op_fmov;
845 else
846 op = midgard_alu_op_imov;
847
848 if (dst_bitsize == (src_bitsize * 2)) {
849 /* Converting up */
850 half_2 = true;
851
852 /* Use a greater register mode */
853 reg_mode++;
854 } else if (src_bitsize == (dst_bitsize * 2)) {
855 /* Converting down */
856 dest_override = midgard_dest_override_lower;
857 }
858
859 break;
860 }
861
862 /* For greater-or-equal, we lower to less-or-equal and flip the
863 * arguments */
864
865 case nir_op_fge:
866 case nir_op_fge32:
867 case nir_op_ige32:
868 case nir_op_uge32: {
869 op =
870 instr->op == nir_op_fge ? midgard_alu_op_fle :
871 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
872 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
873 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
874 0;
875
876 flip_src12 = true;
877 break;
878 }
879
880 case nir_op_b32csel: {
881 /* Midgard features both fcsel and icsel, depending on
882 * the type of the arguments/output. However, as long
883 * as we're careful we can _always_ use icsel and
884 * _never_ need fcsel, since the latter does additional
885 * floating-point-specific processing whereas the
886 * former just moves bits on the wire. It's not obvious
887 * why these are separate opcodes, save for the ability
888 * to do things like sat/pos/abs/neg for free */
889
890 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
891 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
892
893 break;
894 }
895
896 default:
897 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
898 assert(0);
899 return;
900 }
901
902 /* Midgard can perform certain modifiers on output of an ALU op */
903
904 unsigned outmod = 0;
905
906 bool abs[4] = { false };
907 bool neg[4] = { false };
908 bool is_int = midgard_is_integer_op(op);
909
910 if (midgard_is_integer_out_op(op)) {
911 outmod = midgard_outmod_int_wrap;
912 } else if (instr->op == nir_op_fsat) {
913 outmod = midgard_outmod_sat;
914 } else if (instr->op == nir_op_fsat_signed) {
915 outmod = midgard_outmod_sat_signed;
916 } else if (instr->op == nir_op_fclamp_pos) {
917 outmod = midgard_outmod_pos;
918 }
919
920 /* Fetch unit, quirks, etc information */
921 unsigned opcode_props = alu_opcode_props[op].props;
922 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
923
924 /* Look for floating point mods. We have the mods fsat, fsat_signed,
925 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
926 *
927 * fsat_signed(fpos(x)) = fsat(x)
928 * fsat_signed(fsat(x)) = fsat(x)
929 * fpos(fsat_signed(x)) = fsat(x)
930 * fpos(fsat(x)) = fsat(x)
931 * fsat(fsat_signed(x)) = fsat(x)
932 * fsat(fpos(x)) = fsat(x)
933 *
934 * So by cases any composition of output modifiers is equivalent to
935 * fsat alone.
936 */
937
938 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
939 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
940 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
941 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
942 bool prior = (outmod != midgard_outmod_none);
943 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
944
945 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
946 fpos ? midgard_outmod_pos :
947 ssat ? midgard_outmod_sat_signed :
948 outmod;
949 }
950
951 midgard_instruction ins = {
952 .type = TAG_ALU_4,
953 .dest = nir_dest_index(dest),
954 .dest_type = nir_op_infos[instr->op].output_type
955 | nir_dest_bit_size(*dest),
956 };
957
958 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
959 ins.src[i] = ~0;
960
961 if (quirk_flipped_r24) {
962 ins.src[0] = ~0;
963 mir_copy_src(&ins, instr, 0, 1, &abs[1], &neg[1], &ins.src_invert[1], is_int, broadcast_swizzle);
964 } else {
965 for (unsigned i = 0; i < nr_inputs; ++i) {
966 unsigned to = i;
967
968 if (instr->op == nir_op_b32csel) {
969 /* The condition is the first argument; move
970 * the other arguments up one to be a binary
971 * instruction for Midgard with the condition
972 * last */
973
974 if (i == 0)
975 to = 2;
976 else if (flip_src12)
977 to = 2 - i;
978 else
979 to = i - 1;
980 } else if (flip_src12) {
981 to = 1 - to;
982 }
983
984 mir_copy_src(&ins, instr, i, to, &abs[to], &neg[to], &ins.src_invert[to], is_int, broadcast_swizzle);
985
986 /* (!c) ? a : b = c ? b : a */
987 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
988 ins.src_invert[2] = false;
989 flip_src12 ^= true;
990 }
991 }
992 }
993
994 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
995 /* Lowered to move */
996 if (instr->op == nir_op_fneg)
997 neg[1] = !neg[1];
998
999 if (instr->op == nir_op_fabs)
1000 abs[1] = true;
1001 }
1002
1003 ins.mask = mask_of(nr_components);
1004
1005 midgard_vector_alu alu = {
1006 .op = op,
1007 .reg_mode = reg_mode,
1008 .dest_override = dest_override,
1009 .outmod = outmod,
1010
1011 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[0], neg[0], is_int, half_1, sext_1)),
1012 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[1], neg[1], is_int, half_2, sext_2)),
1013 };
1014
1015 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1016 * components that don't exist. Note modifier => SSA => !reg => no
1017 * writemask, so we don't have to worry about writemasks here.*/
1018
1019 if (!is_ssa)
1020 ins.mask &= instr->dest.write_mask;
1021
1022 ins.alu = alu;
1023
1024 /* Arrange for creation of iandnot/iornot */
1025 if (ins.src_invert[0] && !ins.src_invert[1]) {
1026 mir_flip(&ins);
1027 ins.src_invert[0] = false;
1028 ins.src_invert[1] = true;
1029 }
1030
1031 /* Late fixup for emulated instructions */
1032
1033 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1034 /* Presently, our second argument is an inline #0 constant.
1035 * Switch over to an embedded 1.0 constant (that can't fit
1036 * inline, since we're 32-bit, not 16-bit like the inline
1037 * constants) */
1038
1039 ins.has_inline_constant = false;
1040 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1041 ins.src_types[1] = nir_type_float32;
1042 ins.has_constants = true;
1043
1044 if (instr->op == nir_op_b2f32)
1045 ins.constants.f32[0] = 1.0f;
1046 else
1047 ins.constants.i32[0] = 1;
1048
1049 for (unsigned c = 0; c < 16; ++c)
1050 ins.swizzle[1][c] = 0;
1051 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1052 /* Lots of instructions need a 0 plonked in */
1053 ins.has_inline_constant = false;
1054 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1055 ins.src_types[1] = nir_type_uint32;
1056 ins.has_constants = true;
1057 ins.constants.u32[0] = 0;
1058
1059 for (unsigned c = 0; c < 16; ++c)
1060 ins.swizzle[1][c] = 0;
1061 }
1062
1063 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1064 /* To avoid duplicating the lookup tables (probably), true LUT
1065 * instructions can only operate as if they were scalars. Lower
1066 * them here by changing the component. */
1067
1068 unsigned orig_mask = ins.mask;
1069
1070 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1071 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1072
1073 for (int i = 0; i < nr_components; ++i) {
1074 /* Mask the associated component, dropping the
1075 * instruction if needed */
1076
1077 ins.mask = 1 << i;
1078 ins.mask &= orig_mask;
1079
1080 if (!ins.mask)
1081 continue;
1082
1083 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1084 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1085
1086 emit_mir_instruction(ctx, ins);
1087 }
1088 } else {
1089 emit_mir_instruction(ctx, ins);
1090 }
1091 }
1092
1093 #undef ALU_CASE
1094
1095 static void
1096 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1097 {
1098 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1099 unsigned nir_mask = 0;
1100 unsigned dsize = 0;
1101
1102 if (is_read) {
1103 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1104 dsize = nir_dest_bit_size(intr->dest);
1105 } else {
1106 nir_mask = nir_intrinsic_write_mask(intr);
1107 dsize = 32;
1108 }
1109
1110 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1111 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1112 mir_set_bytemask(ins, bytemask);
1113
1114 if (dsize == 64)
1115 ins->load_64 = true;
1116 }
1117
1118 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1119 * optimized) versions of UBO #0 */
1120
1121 static midgard_instruction *
1122 emit_ubo_read(
1123 compiler_context *ctx,
1124 nir_instr *instr,
1125 unsigned dest,
1126 unsigned offset,
1127 nir_src *indirect_offset,
1128 unsigned indirect_shift,
1129 unsigned index)
1130 {
1131 /* TODO: half-floats */
1132
1133 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1134 ins.constants.u32[0] = offset;
1135
1136 if (instr->type == nir_instr_type_intrinsic)
1137 mir_set_intr_mask(instr, &ins, true);
1138
1139 if (indirect_offset) {
1140 ins.src[2] = nir_src_index(ctx, indirect_offset);
1141 ins.src_types[2] = nir_type_uint32;
1142 ins.load_store.arg_2 = (indirect_shift << 5);
1143 } else {
1144 ins.load_store.arg_2 = 0x1E;
1145 }
1146
1147 ins.load_store.arg_1 = index;
1148
1149 return emit_mir_instruction(ctx, ins);
1150 }
1151
1152 /* Globals are like UBOs if you squint. And shared memory is like globals if
1153 * you squint even harder */
1154
1155 static void
1156 emit_global(
1157 compiler_context *ctx,
1158 nir_instr *instr,
1159 bool is_read,
1160 unsigned srcdest,
1161 nir_src *offset,
1162 bool is_shared)
1163 {
1164 /* TODO: types */
1165
1166 midgard_instruction ins;
1167
1168 if (is_read)
1169 ins = m_ld_int4(srcdest, 0);
1170 else
1171 ins = m_st_int4(srcdest, 0);
1172
1173 mir_set_offset(ctx, &ins, offset, is_shared);
1174 mir_set_intr_mask(instr, &ins, is_read);
1175
1176 emit_mir_instruction(ctx, ins);
1177 }
1178
1179 static void
1180 emit_varying_read(
1181 compiler_context *ctx,
1182 unsigned dest, unsigned offset,
1183 unsigned nr_comp, unsigned component,
1184 nir_src *indirect_offset, nir_alu_type type, bool flat)
1185 {
1186 /* XXX: Half-floats? */
1187 /* TODO: swizzle, mask */
1188
1189 midgard_instruction ins = m_ld_vary_32(dest, offset);
1190 ins.mask = mask_of(nr_comp);
1191
1192 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1193 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1194
1195 midgard_varying_parameter p = {
1196 .is_varying = 1,
1197 .interpolation = midgard_interp_default,
1198 .flat = flat,
1199 };
1200
1201 unsigned u;
1202 memcpy(&u, &p, sizeof(p));
1203 ins.load_store.varying_parameters = u;
1204
1205 if (indirect_offset) {
1206 ins.src[2] = nir_src_index(ctx, indirect_offset);
1207 ins.src_types[2] = nir_type_uint32;
1208 } else
1209 ins.load_store.arg_2 = 0x1E;
1210
1211 ins.load_store.arg_1 = 0x9E;
1212
1213 /* Use the type appropriate load */
1214 switch (type) {
1215 case nir_type_uint:
1216 case nir_type_bool:
1217 ins.load_store.op = midgard_op_ld_vary_32u;
1218 break;
1219 case nir_type_int:
1220 ins.load_store.op = midgard_op_ld_vary_32i;
1221 break;
1222 case nir_type_float:
1223 ins.load_store.op = midgard_op_ld_vary_32;
1224 break;
1225 default:
1226 unreachable("Attempted to load unknown type");
1227 break;
1228 }
1229
1230 emit_mir_instruction(ctx, ins);
1231 }
1232
1233 static void
1234 emit_attr_read(
1235 compiler_context *ctx,
1236 unsigned dest, unsigned offset,
1237 unsigned nr_comp, nir_alu_type t)
1238 {
1239 midgard_instruction ins = m_ld_attr_32(dest, offset);
1240 ins.load_store.arg_1 = 0x1E;
1241 ins.load_store.arg_2 = 0x1E;
1242 ins.mask = mask_of(nr_comp);
1243
1244 /* Use the type appropriate load */
1245 switch (t) {
1246 case nir_type_uint:
1247 case nir_type_bool:
1248 ins.load_store.op = midgard_op_ld_attr_32u;
1249 break;
1250 case nir_type_int:
1251 ins.load_store.op = midgard_op_ld_attr_32i;
1252 break;
1253 case nir_type_float:
1254 ins.load_store.op = midgard_op_ld_attr_32;
1255 break;
1256 default:
1257 unreachable("Attempted to load unknown type");
1258 break;
1259 }
1260
1261 emit_mir_instruction(ctx, ins);
1262 }
1263
1264 static void
1265 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1266 unsigned nr_components, unsigned offset)
1267 {
1268 nir_dest nir_dest;
1269
1270 /* Figure out which uniform this is */
1271 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1272 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1273
1274 unsigned dest = nir_dest_index(&nir_dest);
1275
1276 /* Sysvals are prefix uniforms */
1277 unsigned uniform = ((uintptr_t) val) - 1;
1278
1279 /* Emit the read itself -- this is never indirect */
1280 midgard_instruction *ins =
1281 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1282
1283 ins->mask = mask_of(nr_components);
1284 }
1285
1286 static unsigned
1287 compute_builtin_arg(nir_op op)
1288 {
1289 switch (op) {
1290 case nir_intrinsic_load_work_group_id:
1291 return 0x14;
1292 case nir_intrinsic_load_local_invocation_id:
1293 return 0x10;
1294 default:
1295 unreachable("Invalid compute paramater loaded");
1296 }
1297 }
1298
1299 static void
1300 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1301 {
1302 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1303
1304 midgard_instruction *br = ctx->writeout_branch[rt];
1305
1306 assert(!br);
1307
1308 emit_explicit_constant(ctx, src, src);
1309
1310 struct midgard_instruction ins =
1311 v_branch(false, false);
1312
1313 ins.writeout = true;
1314
1315 /* Add dependencies */
1316 ins.src[0] = src;
1317 ins.src_types[0] = nir_type_uint32;
1318 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1319 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1320
1321 /* Emit the branch */
1322 br = emit_mir_instruction(ctx, ins);
1323 schedule_barrier(ctx);
1324 ctx->writeout_branch[rt] = br;
1325
1326 /* Push our current location = current block count - 1 = where we'll
1327 * jump to. Maybe a bit too clever for my own good */
1328
1329 br->branch.target_block = ctx->block_count - 1;
1330 }
1331
1332 static void
1333 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1334 {
1335 unsigned reg = nir_dest_index(&instr->dest);
1336 midgard_instruction ins = m_ld_compute_id(reg, 0);
1337 ins.mask = mask_of(3);
1338 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1339 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1340 emit_mir_instruction(ctx, ins);
1341 }
1342
1343 static unsigned
1344 vertex_builtin_arg(nir_op op)
1345 {
1346 switch (op) {
1347 case nir_intrinsic_load_vertex_id:
1348 return PAN_VERTEX_ID;
1349 case nir_intrinsic_load_instance_id:
1350 return PAN_INSTANCE_ID;
1351 default:
1352 unreachable("Invalid vertex builtin");
1353 }
1354 }
1355
1356 static void
1357 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1358 {
1359 unsigned reg = nir_dest_index(&instr->dest);
1360 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1361 }
1362
1363 static void
1364 emit_control_barrier(compiler_context *ctx)
1365 {
1366 midgard_instruction ins = {
1367 .type = TAG_TEXTURE_4,
1368 .src = { ~0, ~0, ~0, ~0 },
1369 .texture = {
1370 .op = TEXTURE_OP_BARRIER,
1371
1372 /* TODO: optimize */
1373 .barrier_buffer = 1,
1374 .barrier_shared = 1
1375 }
1376 };
1377
1378 emit_mir_instruction(ctx, ins);
1379 }
1380
1381 static const nir_variable *
1382 search_var(struct exec_list *vars, unsigned driver_loc)
1383 {
1384 nir_foreach_variable(var, vars) {
1385 if (var->data.driver_location == driver_loc)
1386 return var;
1387 }
1388
1389 return NULL;
1390 }
1391
1392 static unsigned
1393 mir_get_branch_cond(nir_src *src, bool *invert)
1394 {
1395 /* Wrap it. No swizzle since it's a scalar */
1396
1397 nir_alu_src alu = {
1398 .src = *src
1399 };
1400
1401 *invert = pan_has_source_mod(&alu, nir_op_inot);
1402 return nir_src_index(NULL, &alu.src);
1403 }
1404
1405 static void
1406 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1407 {
1408 unsigned offset = 0, reg;
1409
1410 switch (instr->intrinsic) {
1411 case nir_intrinsic_discard_if:
1412 case nir_intrinsic_discard: {
1413 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1414 struct midgard_instruction discard = v_branch(conditional, false);
1415 discard.branch.target_type = TARGET_DISCARD;
1416
1417 if (conditional) {
1418 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1419 &discard.branch.invert_conditional);
1420 discard.src_types[0] = nir_type_uint32;
1421 }
1422
1423 emit_mir_instruction(ctx, discard);
1424 schedule_barrier(ctx);
1425
1426 break;
1427 }
1428
1429 case nir_intrinsic_load_uniform:
1430 case nir_intrinsic_load_ubo:
1431 case nir_intrinsic_load_global:
1432 case nir_intrinsic_load_shared:
1433 case nir_intrinsic_load_input:
1434 case nir_intrinsic_load_interpolated_input: {
1435 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1436 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1437 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1438 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1439 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1440 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1441
1442 /* Get the base type of the intrinsic */
1443 /* TODO: Infer type? Does it matter? */
1444 nir_alu_type t =
1445 (is_ubo || is_global || is_shared) ? nir_type_uint :
1446 (is_interp) ? nir_type_float :
1447 nir_intrinsic_type(instr);
1448
1449 t = nir_alu_type_get_base_type(t);
1450
1451 if (!(is_ubo || is_global)) {
1452 offset = nir_intrinsic_base(instr);
1453 }
1454
1455 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1456
1457 nir_src *src_offset = nir_get_io_offset_src(instr);
1458
1459 bool direct = nir_src_is_const(*src_offset);
1460 nir_src *indirect_offset = direct ? NULL : src_offset;
1461
1462 if (direct)
1463 offset += nir_src_as_uint(*src_offset);
1464
1465 /* We may need to apply a fractional offset */
1466 int component = (is_flat || is_interp) ?
1467 nir_intrinsic_component(instr) : 0;
1468 reg = nir_dest_index(&instr->dest);
1469
1470 if (is_uniform && !ctx->is_blend) {
1471 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1472 } else if (is_ubo) {
1473 nir_src index = instr->src[0];
1474
1475 /* TODO: Is indirect block number possible? */
1476 assert(nir_src_is_const(index));
1477
1478 uint32_t uindex = nir_src_as_uint(index) + 1;
1479 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1480 } else if (is_global || is_shared) {
1481 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1482 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1483 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1484 } else if (ctx->is_blend) {
1485 /* For blend shaders, load the input color, which is
1486 * preloaded to r0 */
1487
1488 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1489 emit_mir_instruction(ctx, move);
1490 schedule_barrier(ctx);
1491 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1492 emit_attr_read(ctx, reg, offset, nr_comp, t);
1493 } else {
1494 DBG("Unknown load\n");
1495 assert(0);
1496 }
1497
1498 break;
1499 }
1500
1501 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1502 case nir_intrinsic_load_barycentric_pixel:
1503 case nir_intrinsic_load_barycentric_centroid:
1504 break;
1505
1506 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1507
1508 case nir_intrinsic_load_raw_output_pan:
1509 case nir_intrinsic_load_output_u8_as_fp16_pan:
1510 reg = nir_dest_index(&instr->dest);
1511 assert(ctx->is_blend);
1512
1513 /* T720 and below use different blend opcodes with slightly
1514 * different semantics than T760 and up */
1515
1516 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1517 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1518
1519 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1520 ld.load_store.op = old_blend ?
1521 midgard_op_ld_color_buffer_u8_as_fp16_old :
1522 midgard_op_ld_color_buffer_u8_as_fp16;
1523
1524 if (old_blend) {
1525 ld.load_store.address = 1;
1526 ld.load_store.arg_2 = 0x1E;
1527 }
1528
1529 for (unsigned c = 2; c < 16; ++c)
1530 ld.swizzle[0][c] = 0;
1531 }
1532
1533 emit_mir_instruction(ctx, ld);
1534 break;
1535
1536 case nir_intrinsic_load_blend_const_color_rgba: {
1537 assert(ctx->is_blend);
1538 reg = nir_dest_index(&instr->dest);
1539
1540 /* Blend constants are embedded directly in the shader and
1541 * patched in, so we use some magic routing */
1542
1543 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1544 ins.has_constants = true;
1545 ins.has_blend_constant = true;
1546 emit_mir_instruction(ctx, ins);
1547 break;
1548 }
1549
1550 case nir_intrinsic_store_zs_output_pan: {
1551 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1552 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1553 MIDGARD_ZS_RT);
1554
1555 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1556
1557 if (!nir_intrinsic_component(instr))
1558 br->writeout_depth = true;
1559 if (nir_intrinsic_component(instr) ||
1560 instr->num_components)
1561 br->writeout_stencil = true;
1562 assert(br->writeout_depth | br->writeout_stencil);
1563 break;
1564 }
1565
1566 case nir_intrinsic_store_output:
1567 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1568
1569 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1570
1571 reg = nir_src_index(ctx, &instr->src[0]);
1572
1573 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1574 const nir_variable *var;
1575 enum midgard_rt_id rt;
1576
1577 var = search_var(&ctx->nir->outputs,
1578 nir_intrinsic_base(instr));
1579 assert(var);
1580 if (var->data.location == FRAG_RESULT_COLOR)
1581 rt = MIDGARD_COLOR_RT0;
1582 else if (var->data.location >= FRAG_RESULT_DATA0)
1583 rt = MIDGARD_COLOR_RT0 + var->data.location -
1584 FRAG_RESULT_DATA0;
1585 else
1586 assert(0);
1587
1588 emit_fragment_store(ctx, reg, rt);
1589 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1590 /* We should have been vectorized, though we don't
1591 * currently check that st_vary is emitted only once
1592 * per slot (this is relevant, since there's not a mask
1593 * parameter available on the store [set to 0 by the
1594 * blob]). We do respect the component by adjusting the
1595 * swizzle. If this is a constant source, we'll need to
1596 * emit that explicitly. */
1597
1598 emit_explicit_constant(ctx, reg, reg);
1599
1600 unsigned dst_component = nir_intrinsic_component(instr);
1601 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1602
1603 midgard_instruction st = m_st_vary_32(reg, offset);
1604 st.load_store.arg_1 = 0x9E;
1605 st.load_store.arg_2 = 0x1E;
1606
1607 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1608 case nir_type_uint:
1609 case nir_type_bool:
1610 st.load_store.op = midgard_op_st_vary_32u;
1611 break;
1612 case nir_type_int:
1613 st.load_store.op = midgard_op_st_vary_32i;
1614 break;
1615 case nir_type_float:
1616 st.load_store.op = midgard_op_st_vary_32;
1617 break;
1618 default:
1619 unreachable("Attempted to store unknown type");
1620 break;
1621 }
1622
1623 /* nir_intrinsic_component(store_intr) encodes the
1624 * destination component start. Source component offset
1625 * adjustment is taken care of in
1626 * install_registers_instr(), when offset_swizzle() is
1627 * called.
1628 */
1629 unsigned src_component = COMPONENT_X;
1630
1631 assert(nr_comp > 0);
1632 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1633 st.swizzle[0][i] = src_component;
1634 if (i >= dst_component && i < dst_component + nr_comp - 1)
1635 src_component++;
1636 }
1637
1638 emit_mir_instruction(ctx, st);
1639 } else {
1640 DBG("Unknown store\n");
1641 assert(0);
1642 }
1643
1644 break;
1645
1646 /* Special case of store_output for lowered blend shaders */
1647 case nir_intrinsic_store_raw_output_pan:
1648 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1649 reg = nir_src_index(ctx, &instr->src[0]);
1650
1651 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1652 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1653 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1654 * of:
1655 *
1656 * imov r0.xyzw, r0.xxxx
1657 */
1658
1659 unsigned expanded = make_compiler_temp(ctx);
1660
1661 midgard_instruction splatter = v_mov(reg, expanded);
1662
1663 for (unsigned c = 0; c < 16; ++c)
1664 splatter.swizzle[1][c] = 0;
1665
1666 emit_mir_instruction(ctx, splatter);
1667 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1668 } else
1669 emit_fragment_store(ctx, reg, ctx->blend_rt);
1670
1671 break;
1672
1673 case nir_intrinsic_store_global:
1674 case nir_intrinsic_store_shared:
1675 reg = nir_src_index(ctx, &instr->src[0]);
1676 emit_explicit_constant(ctx, reg, reg);
1677
1678 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1679 break;
1680
1681 case nir_intrinsic_load_ssbo_address:
1682 emit_sysval_read(ctx, &instr->instr, 1, 0);
1683 break;
1684
1685 case nir_intrinsic_get_buffer_size:
1686 emit_sysval_read(ctx, &instr->instr, 1, 8);
1687 break;
1688
1689 case nir_intrinsic_load_viewport_scale:
1690 case nir_intrinsic_load_viewport_offset:
1691 case nir_intrinsic_load_num_work_groups:
1692 case nir_intrinsic_load_sampler_lod_parameters_pan:
1693 emit_sysval_read(ctx, &instr->instr, 3, 0);
1694 break;
1695
1696 case nir_intrinsic_load_work_group_id:
1697 case nir_intrinsic_load_local_invocation_id:
1698 emit_compute_builtin(ctx, instr);
1699 break;
1700
1701 case nir_intrinsic_load_vertex_id:
1702 case nir_intrinsic_load_instance_id:
1703 emit_vertex_builtin(ctx, instr);
1704 break;
1705
1706 case nir_intrinsic_memory_barrier_buffer:
1707 case nir_intrinsic_memory_barrier_shared:
1708 break;
1709
1710 case nir_intrinsic_control_barrier:
1711 schedule_barrier(ctx);
1712 emit_control_barrier(ctx);
1713 schedule_barrier(ctx);
1714 break;
1715
1716 default:
1717 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1718 assert(0);
1719 break;
1720 }
1721 }
1722
1723 static unsigned
1724 midgard_tex_format(enum glsl_sampler_dim dim)
1725 {
1726 switch (dim) {
1727 case GLSL_SAMPLER_DIM_1D:
1728 case GLSL_SAMPLER_DIM_BUF:
1729 return MALI_TEX_1D;
1730
1731 case GLSL_SAMPLER_DIM_2D:
1732 case GLSL_SAMPLER_DIM_EXTERNAL:
1733 case GLSL_SAMPLER_DIM_RECT:
1734 return MALI_TEX_2D;
1735
1736 case GLSL_SAMPLER_DIM_3D:
1737 return MALI_TEX_3D;
1738
1739 case GLSL_SAMPLER_DIM_CUBE:
1740 return MALI_TEX_CUBE;
1741
1742 default:
1743 DBG("Unknown sampler dim type\n");
1744 assert(0);
1745 return 0;
1746 }
1747 }
1748
1749 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1750 * was successful */
1751
1752 static bool
1753 pan_attach_constant_bias(
1754 compiler_context *ctx,
1755 nir_src lod,
1756 midgard_texture_word *word)
1757 {
1758 /* To attach as constant, it has to *be* constant */
1759
1760 if (!nir_src_is_const(lod))
1761 return false;
1762
1763 float f = nir_src_as_float(lod);
1764
1765 /* Break into fixed-point */
1766 signed lod_int = f;
1767 float lod_frac = f - lod_int;
1768
1769 /* Carry over negative fractions */
1770 if (lod_frac < 0.0) {
1771 lod_int--;
1772 lod_frac += 1.0;
1773 }
1774
1775 /* Encode */
1776 word->bias = float_to_ubyte(lod_frac);
1777 word->bias_int = lod_int;
1778
1779 return true;
1780 }
1781
1782 static void
1783 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1784 unsigned midgard_texop)
1785 {
1786 /* TODO */
1787 //assert (!instr->sampler);
1788
1789 int texture_index = instr->texture_index;
1790 int sampler_index = texture_index;
1791
1792 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1793 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1794
1795 midgard_instruction ins = {
1796 .type = TAG_TEXTURE_4,
1797 .mask = 0xF,
1798 .dest = nir_dest_index(&instr->dest),
1799 .src = { ~0, ~0, ~0, ~0 },
1800 .dest_type = dest_type,
1801 .swizzle = SWIZZLE_IDENTITY_4,
1802 .texture = {
1803 .op = midgard_texop,
1804 .format = midgard_tex_format(instr->sampler_dim),
1805 .texture_handle = texture_index,
1806 .sampler_handle = sampler_index,
1807 .shadow = instr->is_shadow,
1808 }
1809 };
1810
1811 if (instr->is_shadow && !instr->is_new_style_shadow)
1812 for (int i = 0; i < 4; ++i)
1813 ins.swizzle[0][i] = COMPONENT_X;
1814
1815 /* We may need a temporary for the coordinate */
1816
1817 bool needs_temp_coord =
1818 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1819 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1820 (instr->is_shadow);
1821
1822 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1823
1824 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1825 int index = nir_src_index(ctx, &instr->src[i].src);
1826 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1827 unsigned sz = nir_src_bit_size(instr->src[i].src);
1828 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1829
1830 switch (instr->src[i].src_type) {
1831 case nir_tex_src_coord: {
1832 emit_explicit_constant(ctx, index, index);
1833
1834 unsigned coord_mask = mask_of(instr->coord_components);
1835
1836 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1837
1838 if (flip_zw)
1839 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1840
1841 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1842 /* texelFetch is undefined on samplerCube */
1843 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1844
1845 /* For cubemaps, we use a special ld/st op to
1846 * select the face and copy the xy into the
1847 * texture register */
1848
1849 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1850 ld.src[1] = index;
1851 ld.src_types[1] = T;
1852 ld.mask = 0x3; /* xy */
1853 ld.load_store.arg_1 = 0x20;
1854 ld.swizzle[1][3] = COMPONENT_X;
1855 emit_mir_instruction(ctx, ld);
1856
1857 /* xyzw -> xyxx */
1858 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1859 ins.swizzle[1][3] = COMPONENT_X;
1860 } else if (needs_temp_coord) {
1861 /* mov coord_temp, coords */
1862 midgard_instruction mov = v_mov(index, coords);
1863 mov.mask = coord_mask;
1864
1865 if (flip_zw)
1866 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1867
1868 emit_mir_instruction(ctx, mov);
1869 } else {
1870 coords = index;
1871 }
1872
1873 ins.src[1] = coords;
1874 ins.src_types[1] = T;
1875
1876 /* Texelfetch coordinates uses all four elements
1877 * (xyz/index) regardless of texture dimensionality,
1878 * which means it's necessary to zero the unused
1879 * components to keep everything happy */
1880
1881 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1882 /* mov index.zw, #0, or generalized */
1883 midgard_instruction mov =
1884 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1885 mov.has_constants = true;
1886 mov.mask = coord_mask ^ 0xF;
1887 emit_mir_instruction(ctx, mov);
1888 }
1889
1890 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1891 /* Array component in w but NIR wants it in z,
1892 * but if we have a temp coord we already fixed
1893 * that up */
1894
1895 if (nr_components == 3) {
1896 ins.swizzle[1][2] = COMPONENT_Z;
1897 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1898 } else if (nr_components == 2) {
1899 ins.swizzle[1][2] =
1900 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1901 ins.swizzle[1][3] = COMPONENT_X;
1902 } else
1903 unreachable("Invalid texture 2D components");
1904 }
1905
1906 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1907 /* We zeroed */
1908 ins.swizzle[1][2] = COMPONENT_Z;
1909 ins.swizzle[1][3] = COMPONENT_W;
1910 }
1911
1912 break;
1913 }
1914
1915 case nir_tex_src_bias:
1916 case nir_tex_src_lod: {
1917 /* Try as a constant if we can */
1918
1919 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1920 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1921 break;
1922
1923 ins.texture.lod_register = true;
1924 ins.src[2] = index;
1925 ins.src_types[2] = T;
1926
1927 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1928 ins.swizzle[2][c] = COMPONENT_X;
1929
1930 emit_explicit_constant(ctx, index, index);
1931
1932 break;
1933 };
1934
1935 case nir_tex_src_offset: {
1936 ins.texture.offset_register = true;
1937 ins.src[3] = index;
1938 ins.src_types[3] = T;
1939
1940 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1941 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1942
1943 emit_explicit_constant(ctx, index, index);
1944 break;
1945 };
1946
1947 case nir_tex_src_comparator: {
1948 unsigned comp = COMPONENT_Z;
1949
1950 /* mov coord_temp.foo, coords */
1951 midgard_instruction mov = v_mov(index, coords);
1952 mov.mask = 1 << comp;
1953
1954 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1955 mov.swizzle[1][i] = COMPONENT_X;
1956
1957 emit_mir_instruction(ctx, mov);
1958 break;
1959 }
1960
1961 default: {
1962 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1963 assert(0);
1964 }
1965 }
1966 }
1967
1968 emit_mir_instruction(ctx, ins);
1969 }
1970
1971 static void
1972 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1973 {
1974 switch (instr->op) {
1975 case nir_texop_tex:
1976 case nir_texop_txb:
1977 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1978 break;
1979 case nir_texop_txl:
1980 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1981 break;
1982 case nir_texop_txf:
1983 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1984 break;
1985 case nir_texop_txs:
1986 emit_sysval_read(ctx, &instr->instr, 4, 0);
1987 break;
1988 default: {
1989 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1990 assert(0);
1991 }
1992 }
1993 }
1994
1995 static void
1996 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1997 {
1998 switch (instr->type) {
1999 case nir_jump_break: {
2000 /* Emit a branch out of the loop */
2001 struct midgard_instruction br = v_branch(false, false);
2002 br.branch.target_type = TARGET_BREAK;
2003 br.branch.target_break = ctx->current_loop_depth;
2004 emit_mir_instruction(ctx, br);
2005 break;
2006 }
2007
2008 default:
2009 DBG("Unknown jump type %d\n", instr->type);
2010 break;
2011 }
2012 }
2013
2014 static void
2015 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2016 {
2017 switch (instr->type) {
2018 case nir_instr_type_load_const:
2019 emit_load_const(ctx, nir_instr_as_load_const(instr));
2020 break;
2021
2022 case nir_instr_type_intrinsic:
2023 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2024 break;
2025
2026 case nir_instr_type_alu:
2027 emit_alu(ctx, nir_instr_as_alu(instr));
2028 break;
2029
2030 case nir_instr_type_tex:
2031 emit_tex(ctx, nir_instr_as_tex(instr));
2032 break;
2033
2034 case nir_instr_type_jump:
2035 emit_jump(ctx, nir_instr_as_jump(instr));
2036 break;
2037
2038 case nir_instr_type_ssa_undef:
2039 /* Spurious */
2040 break;
2041
2042 default:
2043 DBG("Unhandled instruction type\n");
2044 break;
2045 }
2046 }
2047
2048
2049 /* ALU instructions can inline or embed constants, which decreases register
2050 * pressure and saves space. */
2051
2052 #define CONDITIONAL_ATTACH(idx) { \
2053 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2054 \
2055 if (entry) { \
2056 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2057 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2058 } \
2059 }
2060
2061 static void
2062 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2063 {
2064 mir_foreach_instr_in_block(block, alu) {
2065 /* Other instructions cannot inline constants */
2066 if (alu->type != TAG_ALU_4) continue;
2067 if (alu->compact_branch) continue;
2068
2069 /* If there is already a constant here, we can do nothing */
2070 if (alu->has_constants) continue;
2071
2072 CONDITIONAL_ATTACH(0);
2073
2074 if (!alu->has_constants) {
2075 CONDITIONAL_ATTACH(1)
2076 } else if (!alu->inline_constant) {
2077 /* Corner case: _two_ vec4 constants, for instance with a
2078 * csel. For this case, we can only use a constant
2079 * register for one, we'll have to emit a move for the
2080 * other. */
2081
2082 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2083 unsigned scratch = make_compiler_temp(ctx);
2084
2085 if (entry) {
2086 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2087 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2088
2089 /* Set the source */
2090 alu->src[1] = scratch;
2091
2092 /* Inject us -before- the last instruction which set r31 */
2093 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2094 }
2095 }
2096 }
2097 }
2098
2099 /* Midgard supports two types of constants, embedded constants (128-bit) and
2100 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2101 * constants can be demoted to inline constants, for space savings and
2102 * sometimes a performance boost */
2103
2104 static void
2105 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2106 {
2107 mir_foreach_instr_in_block(block, ins) {
2108 if (!ins->has_constants) continue;
2109 if (ins->has_inline_constant) continue;
2110
2111 /* Blend constants must not be inlined by definition */
2112 if (ins->has_blend_constant) continue;
2113
2114 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2115 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2116 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2117
2118 if (!(is_16 || is_32))
2119 continue;
2120
2121 /* src1 cannot be an inline constant due to encoding
2122 * restrictions. So, if possible we try to flip the arguments
2123 * in that case */
2124
2125 int op = ins->alu.op;
2126
2127 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2128 alu_opcode_props[op].props & OP_COMMUTES) {
2129 mir_flip(ins);
2130 }
2131
2132 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2133 /* Extract the source information */
2134
2135 midgard_vector_alu_src *src;
2136 int q = ins->alu.src2;
2137 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2138 src = m;
2139
2140 /* Component is from the swizzle. Take a nonzero component */
2141 assert(ins->mask);
2142 unsigned first_comp = ffs(ins->mask) - 1;
2143 unsigned component = ins->swizzle[1][first_comp];
2144
2145 /* Scale constant appropriately, if we can legally */
2146 uint16_t scaled_constant = 0;
2147
2148 if (is_16) {
2149 scaled_constant = ins->constants.u16[component];
2150 } else if (midgard_is_integer_op(op)) {
2151 scaled_constant = ins->constants.u32[component];
2152
2153 /* Constant overflow after resize */
2154 if (scaled_constant != ins->constants.u32[component])
2155 continue;
2156 } else {
2157 float original = ins->constants.f32[component];
2158 scaled_constant = _mesa_float_to_half(original);
2159
2160 /* Check for loss of precision. If this is
2161 * mediump, we don't care, but for a highp
2162 * shader, we need to pay attention. NIR
2163 * doesn't yet tell us which mode we're in!
2164 * Practically this prevents most constants
2165 * from being inlined, sadly. */
2166
2167 float fp32 = _mesa_half_to_float(scaled_constant);
2168
2169 if (fp32 != original)
2170 continue;
2171 }
2172
2173 /* We don't know how to handle these with a constant */
2174
2175 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2176 DBG("Bailing inline constant...\n");
2177 continue;
2178 }
2179
2180 /* Make sure that the constant is not itself a vector
2181 * by checking if all accessed values are the same. */
2182
2183 const midgard_constants *cons = &ins->constants;
2184 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2185
2186 bool is_vector = false;
2187 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2188
2189 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2190 /* We only care if this component is actually used */
2191 if (!(mask & (1 << c)))
2192 continue;
2193
2194 uint32_t test = is_16 ?
2195 cons->u16[ins->swizzle[1][c]] :
2196 cons->u32[ins->swizzle[1][c]];
2197
2198 if (test != value) {
2199 is_vector = true;
2200 break;
2201 }
2202 }
2203
2204 if (is_vector)
2205 continue;
2206
2207 /* Get rid of the embedded constant */
2208 ins->has_constants = false;
2209 ins->src[1] = ~0;
2210 ins->has_inline_constant = true;
2211 ins->inline_constant = scaled_constant;
2212 }
2213 }
2214 }
2215
2216 /* Dead code elimination for branches at the end of a block - only one branch
2217 * per block is legal semantically */
2218
2219 static void
2220 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2221 {
2222 bool branched = false;
2223
2224 mir_foreach_instr_in_block_safe(block, ins) {
2225 if (!midgard_is_branch_unit(ins->unit)) continue;
2226
2227 if (branched)
2228 mir_remove_instruction(ins);
2229
2230 branched = true;
2231 }
2232 }
2233
2234 static unsigned
2235 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2236 {
2237 /* Loop to ourselves */
2238 midgard_instruction *br = ctx->writeout_branch[rt];
2239 struct midgard_instruction ins = v_branch(false, false);
2240 ins.writeout = true;
2241 ins.writeout_depth = br->writeout_depth;
2242 ins.writeout_stencil = br->writeout_stencil;
2243 ins.branch.target_block = ctx->block_count - 1;
2244 ins.constants.u32[0] = br->constants.u32[0];
2245 emit_mir_instruction(ctx, ins);
2246
2247 ctx->current_block->epilogue = true;
2248 schedule_barrier(ctx);
2249 return ins.branch.target_block;
2250 }
2251
2252 static midgard_block *
2253 emit_block(compiler_context *ctx, nir_block *block)
2254 {
2255 midgard_block *this_block = ctx->after_block;
2256 ctx->after_block = NULL;
2257
2258 if (!this_block)
2259 this_block = create_empty_block(ctx);
2260
2261 list_addtail(&this_block->base.link, &ctx->blocks);
2262
2263 this_block->scheduled = false;
2264 ++ctx->block_count;
2265
2266 /* Set up current block */
2267 list_inithead(&this_block->base.instructions);
2268 ctx->current_block = this_block;
2269
2270 nir_foreach_instr(instr, block) {
2271 emit_instr(ctx, instr);
2272 ++ctx->instruction_count;
2273 }
2274
2275 return this_block;
2276 }
2277
2278 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2279
2280 static void
2281 emit_if(struct compiler_context *ctx, nir_if *nif)
2282 {
2283 midgard_block *before_block = ctx->current_block;
2284
2285 /* Speculatively emit the branch, but we can't fill it in until later */
2286 bool inv = false;
2287 EMIT(branch, true, true);
2288 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2289 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2290 then_branch->src_types[0] = nir_type_uint32;
2291 then_branch->branch.invert_conditional = !inv;
2292
2293 /* Emit the two subblocks. */
2294 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2295 midgard_block *end_then_block = ctx->current_block;
2296
2297 /* Emit a jump from the end of the then block to the end of the else */
2298 EMIT(branch, false, false);
2299 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2300
2301 /* Emit second block, and check if it's empty */
2302
2303 int else_idx = ctx->block_count;
2304 int count_in = ctx->instruction_count;
2305 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2306 midgard_block *end_else_block = ctx->current_block;
2307 int after_else_idx = ctx->block_count;
2308
2309 /* Now that we have the subblocks emitted, fix up the branches */
2310
2311 assert(then_block);
2312 assert(else_block);
2313
2314 if (ctx->instruction_count == count_in) {
2315 /* The else block is empty, so don't emit an exit jump */
2316 mir_remove_instruction(then_exit);
2317 then_branch->branch.target_block = after_else_idx;
2318 } else {
2319 then_branch->branch.target_block = else_idx;
2320 then_exit->branch.target_block = after_else_idx;
2321 }
2322
2323 /* Wire up the successors */
2324
2325 ctx->after_block = create_empty_block(ctx);
2326
2327 pan_block_add_successor(&before_block->base, &then_block->base);
2328 pan_block_add_successor(&before_block->base, &else_block->base);
2329
2330 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2331 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2332 }
2333
2334 static void
2335 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2336 {
2337 /* Remember where we are */
2338 midgard_block *start_block = ctx->current_block;
2339
2340 /* Allocate a loop number, growing the current inner loop depth */
2341 int loop_idx = ++ctx->current_loop_depth;
2342
2343 /* Get index from before the body so we can loop back later */
2344 int start_idx = ctx->block_count;
2345
2346 /* Emit the body itself */
2347 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2348
2349 /* Branch back to loop back */
2350 struct midgard_instruction br_back = v_branch(false, false);
2351 br_back.branch.target_block = start_idx;
2352 emit_mir_instruction(ctx, br_back);
2353
2354 /* Mark down that branch in the graph. */
2355 pan_block_add_successor(&start_block->base, &loop_block->base);
2356 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2357
2358 /* Find the index of the block about to follow us (note: we don't add
2359 * one; blocks are 0-indexed so we get a fencepost problem) */
2360 int break_block_idx = ctx->block_count;
2361
2362 /* Fix up the break statements we emitted to point to the right place,
2363 * now that we can allocate a block number for them */
2364 ctx->after_block = create_empty_block(ctx);
2365
2366 mir_foreach_block_from(ctx, start_block, _block) {
2367 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2368 if (ins->type != TAG_ALU_4) continue;
2369 if (!ins->compact_branch) continue;
2370
2371 /* We found a branch -- check the type to see if we need to do anything */
2372 if (ins->branch.target_type != TARGET_BREAK) continue;
2373
2374 /* It's a break! Check if it's our break */
2375 if (ins->branch.target_break != loop_idx) continue;
2376
2377 /* Okay, cool, we're breaking out of this loop.
2378 * Rewrite from a break to a goto */
2379
2380 ins->branch.target_type = TARGET_GOTO;
2381 ins->branch.target_block = break_block_idx;
2382
2383 pan_block_add_successor(_block, &ctx->after_block->base);
2384 }
2385 }
2386
2387 /* Now that we've finished emitting the loop, free up the depth again
2388 * so we play nice with recursion amid nested loops */
2389 --ctx->current_loop_depth;
2390
2391 /* Dump loop stats */
2392 ++ctx->loop_count;
2393 }
2394
2395 static midgard_block *
2396 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2397 {
2398 midgard_block *start_block = NULL;
2399
2400 foreach_list_typed(nir_cf_node, node, node, list) {
2401 switch (node->type) {
2402 case nir_cf_node_block: {
2403 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2404
2405 if (!start_block)
2406 start_block = block;
2407
2408 break;
2409 }
2410
2411 case nir_cf_node_if:
2412 emit_if(ctx, nir_cf_node_as_if(node));
2413 break;
2414
2415 case nir_cf_node_loop:
2416 emit_loop(ctx, nir_cf_node_as_loop(node));
2417 break;
2418
2419 case nir_cf_node_function:
2420 assert(0);
2421 break;
2422 }
2423 }
2424
2425 return start_block;
2426 }
2427
2428 /* Due to lookahead, we need to report the first tag executed in the command
2429 * stream and in branch targets. An initial block might be empty, so iterate
2430 * until we find one that 'works' */
2431
2432 static unsigned
2433 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2434 {
2435 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2436
2437 mir_foreach_block_from(ctx, initial_block, _v) {
2438 midgard_block *v = (midgard_block *) _v;
2439 if (v->quadword_count) {
2440 midgard_bundle *initial_bundle =
2441 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2442
2443 return initial_bundle->tag;
2444 }
2445 }
2446
2447 /* Default to a tag 1 which will break from the shader, in case we jump
2448 * to the exit block (i.e. `return` in a compute shader) */
2449
2450 return 1;
2451 }
2452
2453 /* For each fragment writeout instruction, generate a writeout loop to
2454 * associate with it */
2455
2456 static void
2457 mir_add_writeout_loops(compiler_context *ctx)
2458 {
2459 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2460 midgard_instruction *br = ctx->writeout_branch[rt];
2461 if (!br) continue;
2462
2463 unsigned popped = br->branch.target_block;
2464 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2465 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2466 br->branch.target_type = TARGET_GOTO;
2467
2468 /* If we have more RTs, we'll need to restore back after our
2469 * loop terminates */
2470
2471 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2472 midgard_instruction uncond = v_branch(false, false);
2473 uncond.branch.target_block = popped;
2474 uncond.branch.target_type = TARGET_GOTO;
2475 emit_mir_instruction(ctx, uncond);
2476 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2477 schedule_barrier(ctx);
2478 } else {
2479 /* We're last, so we can terminate here */
2480 br->last_writeout = true;
2481 }
2482 }
2483 }
2484
2485 int
2486 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2487 {
2488 struct util_dynarray *compiled = &program->compiled;
2489
2490 midgard_debug = debug_get_option_midgard_debug();
2491
2492 /* TODO: Bound against what? */
2493 compiler_context *ctx = rzalloc(NULL, compiler_context);
2494
2495 ctx->nir = nir;
2496 ctx->stage = nir->info.stage;
2497 ctx->is_blend = is_blend;
2498 ctx->alpha_ref = program->alpha_ref;
2499 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2500 ctx->quirks = midgard_get_quirks(gpu_id);
2501
2502 /* Start off with a safe cutoff, allowing usage of all 16 work
2503 * registers. Later, we'll promote uniform reads to uniform registers
2504 * if we determine it is beneficial to do so */
2505 ctx->uniform_cutoff = 8;
2506
2507 /* Initialize at a global (not block) level hash tables */
2508
2509 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2510 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2511
2512 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2513 * (so we don't accidentally duplicate the epilogue since mesa/st has
2514 * messed with our I/O quite a bit already) */
2515
2516 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2517
2518 if (ctx->stage == MESA_SHADER_VERTEX) {
2519 NIR_PASS_V(nir, nir_lower_viewport_transform);
2520 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2521 }
2522
2523 NIR_PASS_V(nir, nir_lower_var_copies);
2524 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2525 NIR_PASS_V(nir, nir_split_var_copies);
2526 NIR_PASS_V(nir, nir_lower_var_copies);
2527 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2528 NIR_PASS_V(nir, nir_lower_var_copies);
2529 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2530
2531 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2532 NIR_PASS_V(nir, nir_lower_ssbo);
2533 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2534
2535 /* Optimisation passes */
2536
2537 optimise_nir(nir, ctx->quirks);
2538
2539 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2540 nir_print_shader(nir, stdout);
2541 }
2542
2543 /* Assign sysvals and counts, now that we're sure
2544 * (post-optimisation) */
2545
2546 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2547 program->sysval_count = ctx->sysvals.sysval_count;
2548 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2549
2550 nir_foreach_function(func, nir) {
2551 if (!func->impl)
2552 continue;
2553
2554 list_inithead(&ctx->blocks);
2555 ctx->block_count = 0;
2556 ctx->func = func;
2557 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2558
2559 emit_cf_list(ctx, &func->impl->body);
2560 free(ctx->already_emitted);
2561 break; /* TODO: Multi-function shaders */
2562 }
2563
2564 util_dynarray_init(compiled, NULL);
2565
2566 /* Per-block lowering before opts */
2567
2568 mir_foreach_block(ctx, _block) {
2569 midgard_block *block = (midgard_block *) _block;
2570 inline_alu_constants(ctx, block);
2571 midgard_opt_promote_fmov(ctx, block);
2572 embedded_to_inline_constant(ctx, block);
2573 }
2574 /* MIR-level optimizations */
2575
2576 bool progress = false;
2577
2578 do {
2579 progress = false;
2580
2581 mir_foreach_block(ctx, _block) {
2582 midgard_block *block = (midgard_block *) _block;
2583 progress |= midgard_opt_copy_prop(ctx, block);
2584 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2585 progress |= midgard_opt_combine_projection(ctx, block);
2586 progress |= midgard_opt_varying_projection(ctx, block);
2587 }
2588 } while (progress);
2589
2590 mir_foreach_block(ctx, _block) {
2591 midgard_block *block = (midgard_block *) _block;
2592 midgard_lower_derivatives(ctx, block);
2593 midgard_cull_dead_branch(ctx, block);
2594 }
2595
2596 if (ctx->stage == MESA_SHADER_FRAGMENT)
2597 mir_add_writeout_loops(ctx);
2598
2599 /* Analyze now that the code is known but before scheduling creates
2600 * pipeline registers which are harder to track */
2601 mir_analyze_helper_terminate(ctx);
2602 mir_analyze_helper_requirements(ctx);
2603
2604 /* Schedule! */
2605 midgard_schedule_program(ctx);
2606 mir_ra(ctx);
2607
2608 /* Now that all the bundles are scheduled and we can calculate block
2609 * sizes, emit actual branch instructions rather than placeholders */
2610
2611 int br_block_idx = 0;
2612
2613 mir_foreach_block(ctx, _block) {
2614 midgard_block *block = (midgard_block *) _block;
2615 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2616 for (int c = 0; c < bundle->instruction_count; ++c) {
2617 midgard_instruction *ins = bundle->instructions[c];
2618
2619 if (!midgard_is_branch_unit(ins->unit)) continue;
2620
2621 /* Parse some basic branch info */
2622 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2623 bool is_conditional = ins->branch.conditional;
2624 bool is_inverted = ins->branch.invert_conditional;
2625 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2626 bool is_writeout = ins->writeout;
2627
2628 /* Determine the block we're jumping to */
2629 int target_number = ins->branch.target_block;
2630
2631 /* Report the destination tag */
2632 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2633
2634 /* Count up the number of quadwords we're
2635 * jumping over = number of quadwords until
2636 * (br_block_idx, target_number) */
2637
2638 int quadword_offset = 0;
2639
2640 if (is_discard) {
2641 /* Ignored */
2642 } else if (target_number > br_block_idx) {
2643 /* Jump forward */
2644
2645 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2646 midgard_block *blk = mir_get_block(ctx, idx);
2647 assert(blk);
2648
2649 quadword_offset += blk->quadword_count;
2650 }
2651 } else {
2652 /* Jump backwards */
2653
2654 for (int idx = br_block_idx; idx >= target_number; --idx) {
2655 midgard_block *blk = mir_get_block(ctx, idx);
2656 assert(blk);
2657
2658 quadword_offset -= blk->quadword_count;
2659 }
2660 }
2661
2662 /* Unconditional extended branches (far jumps)
2663 * have issues, so we always use a conditional
2664 * branch, setting the condition to always for
2665 * unconditional. For compact unconditional
2666 * branches, cond isn't used so it doesn't
2667 * matter what we pick. */
2668
2669 midgard_condition cond =
2670 !is_conditional ? midgard_condition_always :
2671 is_inverted ? midgard_condition_false :
2672 midgard_condition_true;
2673
2674 midgard_jmp_writeout_op op =
2675 is_discard ? midgard_jmp_writeout_op_discard :
2676 is_writeout ? midgard_jmp_writeout_op_writeout :
2677 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2678 midgard_jmp_writeout_op_branch_cond;
2679
2680 if (!is_compact) {
2681 midgard_branch_extended branch =
2682 midgard_create_branch_extended(
2683 cond, op,
2684 dest_tag,
2685 quadword_offset);
2686
2687 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2688 } else if (is_conditional || is_discard) {
2689 midgard_branch_cond branch = {
2690 .op = op,
2691 .dest_tag = dest_tag,
2692 .offset = quadword_offset,
2693 .cond = cond
2694 };
2695
2696 assert(branch.offset == quadword_offset);
2697
2698 memcpy(&ins->br_compact, &branch, sizeof(branch));
2699 } else {
2700 assert(op == midgard_jmp_writeout_op_branch_uncond);
2701
2702 midgard_branch_uncond branch = {
2703 .op = op,
2704 .dest_tag = dest_tag,
2705 .offset = quadword_offset,
2706 .unknown = 1
2707 };
2708
2709 assert(branch.offset == quadword_offset);
2710
2711 memcpy(&ins->br_compact, &branch, sizeof(branch));
2712 }
2713 }
2714 }
2715
2716 ++br_block_idx;
2717 }
2718
2719 /* Emit flat binary from the instruction arrays. Iterate each block in
2720 * sequence. Save instruction boundaries such that lookahead tags can
2721 * be assigned easily */
2722
2723 /* Cache _all_ bundles in source order for lookahead across failed branches */
2724
2725 int bundle_count = 0;
2726 mir_foreach_block(ctx, _block) {
2727 midgard_block *block = (midgard_block *) _block;
2728 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2729 }
2730 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2731 int bundle_idx = 0;
2732 mir_foreach_block(ctx, _block) {
2733 midgard_block *block = (midgard_block *) _block;
2734 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2735 source_order_bundles[bundle_idx++] = bundle;
2736 }
2737 }
2738
2739 int current_bundle = 0;
2740
2741 /* Midgard prefetches instruction types, so during emission we
2742 * need to lookahead. Unless this is the last instruction, in
2743 * which we return 1. */
2744
2745 mir_foreach_block(ctx, _block) {
2746 midgard_block *block = (midgard_block *) _block;
2747 mir_foreach_bundle_in_block(block, bundle) {
2748 int lookahead = 1;
2749
2750 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2751 lookahead = source_order_bundles[current_bundle + 1]->tag;
2752
2753 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2754 ++current_bundle;
2755 }
2756
2757 /* TODO: Free deeper */
2758 //util_dynarray_fini(&block->instructions);
2759 }
2760
2761 free(source_order_bundles);
2762
2763 /* Report the very first tag executed */
2764 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2765
2766 /* Deal with off-by-one related to the fencepost problem */
2767 program->work_register_count = ctx->work_registers + 1;
2768 program->uniform_cutoff = ctx->uniform_cutoff;
2769
2770 program->blend_patch_offset = ctx->blend_constant_offset;
2771 program->tls_size = ctx->tls_size;
2772
2773 if (midgard_debug & MIDGARD_DBG_SHADERS)
2774 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2775
2776 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2777 unsigned nr_bundles = 0, nr_ins = 0;
2778
2779 /* Count instructions and bundles */
2780
2781 mir_foreach_block(ctx, _block) {
2782 midgard_block *block = (midgard_block *) _block;
2783 nr_bundles += util_dynarray_num_elements(
2784 &block->bundles, midgard_bundle);
2785
2786 mir_foreach_bundle_in_block(block, bun)
2787 nr_ins += bun->instruction_count;
2788 }
2789
2790 /* Calculate thread count. There are certain cutoffs by
2791 * register count for thread count */
2792
2793 unsigned nr_registers = program->work_register_count;
2794
2795 unsigned nr_threads =
2796 (nr_registers <= 4) ? 4 :
2797 (nr_registers <= 8) ? 2 :
2798 1;
2799
2800 /* Dump stats */
2801
2802 fprintf(stderr, "shader%d - %s shader: "
2803 "%u inst, %u bundles, %u quadwords, "
2804 "%u registers, %u threads, %u loops, "
2805 "%u:%u spills:fills\n",
2806 SHADER_DB_COUNT++,
2807 gl_shader_stage_name(ctx->stage),
2808 nr_ins, nr_bundles, ctx->quadword_count,
2809 nr_registers, nr_threads,
2810 ctx->loop_count,
2811 ctx->spills, ctx->fills);
2812 }
2813
2814 ralloc_free(ctx);
2815
2816 return 0;
2817 }