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pan/mdg: Ensure ld_vary_16 is aligned
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 M_LOAD(ld_attr_32, nir_type_uint32);
132 M_LOAD(ld_vary_32, nir_type_uint32);
133 M_LOAD(ld_ubo_int4, nir_type_uint32);
134 M_LOAD(ld_int4, nir_type_uint32);
135 M_STORE(st_int4, nir_type_uint32);
136 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
137 M_LOAD(ld_color_buffer_as_fp16, nir_type_float16);
138 M_STORE(st_vary_32, nir_type_uint32);
139 M_LOAD(ld_cubemap_coords, nir_type_uint32);
140 M_LOAD(ld_compute_id, nir_type_uint32);
141
142 static midgard_instruction
143 v_branch(bool conditional, bool invert)
144 {
145 midgard_instruction ins = {
146 .type = TAG_ALU_4,
147 .unit = ALU_ENAB_BRANCH,
148 .compact_branch = true,
149 .branch = {
150 .conditional = conditional,
151 .invert_conditional = invert
152 },
153 .dest = ~0,
154 .src = { ~0, ~0, ~0, ~0 },
155 };
156
157 return ins;
158 }
159
160 static midgard_branch_extended
161 midgard_create_branch_extended( midgard_condition cond,
162 midgard_jmp_writeout_op op,
163 unsigned dest_tag,
164 signed quadword_offset)
165 {
166 /* The condition code is actually a LUT describing a function to
167 * combine multiple condition codes. However, we only support a single
168 * condition code at the moment, so we just duplicate over a bunch of
169 * times. */
170
171 uint16_t duplicated_cond =
172 (cond << 14) |
173 (cond << 12) |
174 (cond << 10) |
175 (cond << 8) |
176 (cond << 6) |
177 (cond << 4) |
178 (cond << 2) |
179 (cond << 0);
180
181 midgard_branch_extended branch = {
182 .op = op,
183 .dest_tag = dest_tag,
184 .offset = quadword_offset,
185 .cond = duplicated_cond
186 };
187
188 return branch;
189 }
190
191 static void
192 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
193 {
194 ins->has_constants = true;
195 memcpy(&ins->constants, constants, 16);
196 }
197
198 static int
199 glsl_type_size(const struct glsl_type *type, bool bindless)
200 {
201 return glsl_count_attribute_slots(type, false);
202 }
203
204 /* Lower fdot2 to a vector multiplication followed by channel addition */
205 static void
206 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
207 {
208 if (alu->op != nir_op_fdot2)
209 return;
210
211 b->cursor = nir_before_instr(&alu->instr);
212
213 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
214 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
215
216 nir_ssa_def *product = nir_fmul(b, src0, src1);
217
218 nir_ssa_def *sum = nir_fadd(b,
219 nir_channel(b, product, 0),
220 nir_channel(b, product, 1));
221
222 /* Replace the fdot2 with this sum */
223 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
224 }
225
226 static bool
227 midgard_nir_lower_fdot2(nir_shader *shader)
228 {
229 bool progress = false;
230
231 nir_foreach_function(function, shader) {
232 if (!function->impl) continue;
233
234 nir_builder _b;
235 nir_builder *b = &_b;
236 nir_builder_init(b, function->impl);
237
238 nir_foreach_block(block, function->impl) {
239 nir_foreach_instr_safe(instr, block) {
240 if (instr->type != nir_instr_type_alu) continue;
241
242 nir_alu_instr *alu = nir_instr_as_alu(instr);
243 midgard_nir_lower_fdot2_body(b, alu);
244
245 progress |= true;
246 }
247 }
248
249 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
250
251 }
252
253 return progress;
254 }
255
256 /* Midgard can't write depth and stencil separately. It has to happen in a
257 * single store operation containing both. Let's add a panfrost specific
258 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
259 * one.
260 */
261 static bool
262 midgard_nir_lower_zs_store(nir_shader *nir)
263 {
264 if (nir->info.stage != MESA_SHADER_FRAGMENT)
265 return false;
266
267 nir_variable *z_var = NULL, *s_var = NULL;
268
269 nir_foreach_variable(var, &nir->outputs) {
270 if (var->data.location == FRAG_RESULT_DEPTH)
271 z_var = var;
272 else if (var->data.location == FRAG_RESULT_STENCIL)
273 s_var = var;
274 }
275
276 if (!z_var && !s_var)
277 return false;
278
279 bool progress = false;
280
281 nir_foreach_function(function, nir) {
282 if (!function->impl) continue;
283
284 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
285
286 nir_foreach_block(block, function->impl) {
287 nir_foreach_instr_safe(instr, block) {
288 if (instr->type != nir_instr_type_intrinsic)
289 continue;
290
291 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
292 if (intr->intrinsic != nir_intrinsic_store_output)
293 continue;
294
295 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
296 assert(!z_store);
297 z_store = intr;
298 last_store = intr;
299 }
300
301 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
302 assert(!s_store);
303 s_store = intr;
304 last_store = intr;
305 }
306 }
307 }
308
309 if (!z_store && !s_store) continue;
310
311 nir_builder b;
312 nir_builder_init(&b, function->impl);
313
314 b.cursor = nir_before_instr(&last_store->instr);
315
316 nir_ssa_def *zs_store_src;
317
318 if (z_store && s_store) {
319 nir_ssa_def *srcs[2] = {
320 nir_ssa_for_src(&b, z_store->src[0], 1),
321 nir_ssa_for_src(&b, s_store->src[0], 1),
322 };
323
324 zs_store_src = nir_vec(&b, srcs, 2);
325 } else {
326 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
327 }
328
329 nir_intrinsic_instr *zs_store;
330
331 zs_store = nir_intrinsic_instr_create(b.shader,
332 nir_intrinsic_store_zs_output_pan);
333 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
334 zs_store->num_components = z_store && s_store ? 2 : 1;
335 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
336
337 /* Replace the Z and S store by a ZS store */
338 nir_builder_instr_insert(&b, &zs_store->instr);
339
340 if (z_store)
341 nir_instr_remove(&z_store->instr);
342
343 if (s_store)
344 nir_instr_remove(&s_store->instr);
345
346 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
347 progress = true;
348 }
349
350 return progress;
351 }
352
353 /* Flushes undefined values to zero */
354
355 static void
356 optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
357 {
358 bool progress;
359 unsigned lower_flrp =
360 (nir->options->lower_flrp16 ? 16 : 0) |
361 (nir->options->lower_flrp32 ? 32 : 0) |
362 (nir->options->lower_flrp64 ? 64 : 0);
363
364 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
365 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
366
367 nir_lower_tex_options lower_tex_options = {
368 .lower_txs_lod = true,
369 .lower_txp = ~0,
370 .lower_tex_without_implicit_lod =
371 (quirks & MIDGARD_EXPLICIT_LOD),
372
373 /* TODO: we have native gradient.. */
374 .lower_txd = true,
375 };
376
377 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
378
379 /* Must lower fdot2 after tex is lowered */
380 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
381
382 /* T720 is broken. */
383
384 if (quirks & MIDGARD_BROKEN_LOD)
385 NIR_PASS_V(nir, midgard_nir_lod_errata);
386
387 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_early);
388
389 if (!is_blend)
390 NIR_PASS(progress, nir, nir_fuse_io_16);
391
392 do {
393 progress = false;
394
395 NIR_PASS(progress, nir, nir_lower_var_copies);
396 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
397
398 NIR_PASS(progress, nir, nir_copy_prop);
399 NIR_PASS(progress, nir, nir_opt_remove_phis);
400 NIR_PASS(progress, nir, nir_opt_dce);
401 NIR_PASS(progress, nir, nir_opt_dead_cf);
402 NIR_PASS(progress, nir, nir_opt_cse);
403 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
404 NIR_PASS(progress, nir, nir_opt_algebraic);
405 NIR_PASS(progress, nir, nir_opt_constant_folding);
406
407 if (lower_flrp != 0) {
408 bool lower_flrp_progress = false;
409 NIR_PASS(lower_flrp_progress,
410 nir,
411 nir_lower_flrp,
412 lower_flrp,
413 false /* always_precise */,
414 nir->options->lower_ffma);
415 if (lower_flrp_progress) {
416 NIR_PASS(progress, nir,
417 nir_opt_constant_folding);
418 progress = true;
419 }
420
421 /* Nothing should rematerialize any flrps, so we only
422 * need to do this lowering once.
423 */
424 lower_flrp = 0;
425 }
426
427 NIR_PASS(progress, nir, nir_opt_undef);
428 NIR_PASS(progress, nir, nir_undef_to_zero);
429
430 NIR_PASS(progress, nir, nir_opt_loop_unroll,
431 nir_var_shader_in |
432 nir_var_shader_out |
433 nir_var_function_temp);
434
435 NIR_PASS(progress, nir, nir_opt_vectorize);
436 } while (progress);
437
438 /* Must be run at the end to prevent creation of fsin/fcos ops */
439 NIR_PASS(progress, nir, midgard_nir_scale_trig);
440
441 do {
442 progress = false;
443
444 NIR_PASS(progress, nir, nir_opt_dce);
445 NIR_PASS(progress, nir, nir_opt_algebraic);
446 NIR_PASS(progress, nir, nir_opt_constant_folding);
447 NIR_PASS(progress, nir, nir_copy_prop);
448 } while (progress);
449
450 NIR_PASS(progress, nir, nir_opt_algebraic_late);
451 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
452
453 /* We implement booleans as 32-bit 0/~0 */
454 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
455
456 /* Now that booleans are lowered, we can run out late opts */
457 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
458 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
459
460 NIR_PASS(progress, nir, nir_copy_prop);
461 NIR_PASS(progress, nir, nir_opt_dce);
462
463 /* Take us out of SSA */
464 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
465 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
466
467 /* We are a vector architecture; write combine where possible */
468 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
469 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
470
471 NIR_PASS(progress, nir, nir_opt_dce);
472 }
473
474 /* Do not actually emit a load; instead, cache the constant for inlining */
475
476 static void
477 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
478 {
479 nir_ssa_def def = instr->def;
480
481 midgard_constants *consts = rzalloc(NULL, midgard_constants);
482
483 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
484
485 #define RAW_CONST_COPY(bits) \
486 nir_const_value_to_array(consts->u##bits, instr->value, \
487 instr->def.num_components, u##bits)
488
489 switch (instr->def.bit_size) {
490 case 64:
491 RAW_CONST_COPY(64);
492 break;
493 case 32:
494 RAW_CONST_COPY(32);
495 break;
496 case 16:
497 RAW_CONST_COPY(16);
498 break;
499 case 8:
500 RAW_CONST_COPY(8);
501 break;
502 default:
503 unreachable("Invalid bit_size for load_const instruction\n");
504 }
505
506 /* Shifted for SSA, +1 for off-by-one */
507 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
508 }
509
510 /* Normally constants are embedded implicitly, but for I/O and such we have to
511 * explicitly emit a move with the constant source */
512
513 static void
514 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
515 {
516 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
517
518 if (constant_value) {
519 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
520 attach_constants(ctx, &ins, constant_value, node + 1);
521 emit_mir_instruction(ctx, ins);
522 }
523 }
524
525 static bool
526 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
527 {
528 unsigned comp = src->swizzle[0];
529
530 for (unsigned c = 1; c < nr_components; ++c) {
531 if (src->swizzle[c] != comp)
532 return true;
533 }
534
535 return false;
536 }
537
538 #define ALU_CASE(nir, _op) \
539 case nir_op_##nir: \
540 op = midgard_alu_op_##_op; \
541 assert(src_bitsize == dst_bitsize); \
542 break;
543
544 #define ALU_CASE_RTZ(nir, _op) \
545 case nir_op_##nir: \
546 op = midgard_alu_op_##_op; \
547 roundmode = MIDGARD_RTZ; \
548 break;
549
550 #define ALU_CHECK_CMP(sext) \
551 assert(src_bitsize == 16 || src_bitsize == 32); \
552 assert(dst_bitsize == 16 || dst_bitsize == 32); \
553
554 #define ALU_CASE_BCAST(nir, _op, count) \
555 case nir_op_##nir: \
556 op = midgard_alu_op_##_op; \
557 broadcast_swizzle = count; \
558 ALU_CHECK_CMP(true); \
559 break;
560
561 #define ALU_CASE_CMP(nir, _op, sext) \
562 case nir_op_##nir: \
563 op = midgard_alu_op_##_op; \
564 ALU_CHECK_CMP(sext); \
565 break;
566
567 /* Analyze the sizes of the dest and inputs to determine reg mode. */
568
569 static midgard_reg_mode
570 reg_mode_for_nir(nir_alu_instr *instr)
571 {
572 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
573 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
574 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
575
576 /* We don't have fp16 LUTs, so we'll want to emit code like:
577 *
578 * vlut.fsinr hr0, hr0
579 *
580 * where both input and output are 16-bit but the operation is carried
581 * out in 32-bit
582 */
583
584 switch (instr->op) {
585 case nir_op_fsqrt:
586 case nir_op_frcp:
587 case nir_op_frsq:
588 case nir_op_fsin:
589 case nir_op_fcos:
590 case nir_op_fexp2:
591 case nir_op_flog2:
592 max_bitsize = MAX2(max_bitsize, 32);
593 break;
594
595 /* These get lowered to moves */
596 case nir_op_pack_32_4x8:
597 max_bitsize = 8;
598 break;
599 case nir_op_pack_32_2x16:
600 max_bitsize = 16;
601 break;
602 default:
603 break;
604 }
605
606
607 switch (max_bitsize) {
608 /* Use 16 pipe for 8 since we don't support vec16 yet */
609 case 8:
610 case 16:
611 return midgard_reg_mode_16;
612 case 32:
613 return midgard_reg_mode_32;
614 case 64:
615 return midgard_reg_mode_64;
616 default:
617 unreachable("Invalid bit size");
618 }
619 }
620
621 /* Compare mir_lower_invert */
622 static bool
623 nir_accepts_inot(nir_op op, unsigned src)
624 {
625 switch (op) {
626 case nir_op_ior:
627 case nir_op_iand: /* TODO: b2f16 */
628 case nir_op_ixor:
629 return true;
630 case nir_op_b32csel:
631 /* Only the condition */
632 return (src == 0);
633 default:
634 return false;
635 }
636 }
637
638 static bool
639 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
640 {
641 if (pan_has_dest_mod(dest, op)) {
642 assert((*dest)->is_ssa);
643 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
644 return true;
645 }
646
647 return false;
648 }
649
650 static void
651 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, enum midgard_roundmode *roundmode, bool is_int, unsigned bcast_count)
652 {
653 nir_alu_src src = instr->src[i];
654
655 if (!is_int) {
656 if (pan_has_source_mod(&src, nir_op_fneg))
657 *neg = !(*neg);
658
659 if (pan_has_source_mod(&src, nir_op_fabs))
660 *abs = true;
661 }
662
663 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
664 *not = true;
665
666 if (roundmode) {
667 if (pan_has_source_mod(&src, nir_op_fround_even))
668 *roundmode = MIDGARD_RTE;
669
670 if (pan_has_source_mod(&src, nir_op_ftrunc))
671 *roundmode = MIDGARD_RTZ;
672
673 if (pan_has_source_mod(&src, nir_op_ffloor))
674 *roundmode = MIDGARD_RTN;
675
676 if (pan_has_source_mod(&src, nir_op_fceil))
677 *roundmode = MIDGARD_RTP;
678 }
679
680 unsigned bits = nir_src_bit_size(src.src);
681
682 ins->src[to] = nir_src_index(NULL, &src.src);
683 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
684
685 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
686 ins->swizzle[to][c] = src.swizzle[
687 (!bcast_count || c < bcast_count) ? c :
688 (bcast_count - 1)];
689 }
690 }
691
692 /* Midgard features both fcsel and icsel, depending on whether you want int or
693 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
694 * we should emit an int or float csel depending on what modifiers could be
695 * placed. In the absense of modifiers, this is probably arbitrary. */
696
697 static bool
698 mir_is_bcsel_float(nir_alu_instr *instr)
699 {
700 nir_op intmods[] = {
701 nir_op_i2i8, nir_op_i2i16,
702 nir_op_i2i32, nir_op_i2i64
703 };
704
705 nir_op floatmods[] = {
706 nir_op_fabs, nir_op_fneg,
707 nir_op_f2f16, nir_op_f2f32,
708 nir_op_f2f64
709 };
710
711 nir_op floatdestmods[] = {
712 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
713 nir_op_f2f16, nir_op_f2f32
714 };
715
716 signed score = 0;
717
718 for (unsigned i = 1; i < 3; ++i) {
719 nir_alu_src s = instr->src[i];
720 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
721 if (pan_has_source_mod(&s, intmods[q]))
722 score--;
723 }
724 }
725
726 for (unsigned i = 1; i < 3; ++i) {
727 nir_alu_src s = instr->src[i];
728 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
729 if (pan_has_source_mod(&s, floatmods[q]))
730 score++;
731 }
732 }
733
734 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
735 nir_dest *dest = &instr->dest.dest;
736 if (pan_has_dest_mod(&dest, floatdestmods[q]))
737 score++;
738 }
739
740 return (score > 0);
741 }
742
743 static void
744 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
745 {
746 nir_dest *dest = &instr->dest.dest;
747
748 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
749 return;
750
751 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
752 * is handled elsewhere */
753
754 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
755 midgard_emit_derivatives(ctx, instr);
756 return;
757 }
758
759 bool is_ssa = dest->is_ssa;
760
761 unsigned nr_components = nir_dest_num_components(*dest);
762 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
763 unsigned op = 0;
764
765 /* Number of components valid to check for the instruction (the rest
766 * will be forced to the last), or 0 to use as-is. Relevant as
767 * ball-type instructions have a channel count in NIR but are all vec4
768 * in Midgard */
769
770 unsigned broadcast_swizzle = 0;
771
772 /* What register mode should we operate in? */
773 midgard_reg_mode reg_mode =
774 reg_mode_for_nir(instr);
775
776 /* Should we swap arguments? */
777 bool flip_src12 = false;
778
779 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
780 unsigned dst_bitsize = nir_dest_bit_size(*dest);
781
782 enum midgard_roundmode roundmode = MIDGARD_RTE;
783
784 switch (instr->op) {
785 ALU_CASE(fadd, fadd);
786 ALU_CASE(fmul, fmul);
787 ALU_CASE(fmin, fmin);
788 ALU_CASE(fmax, fmax);
789 ALU_CASE(imin, imin);
790 ALU_CASE(imax, imax);
791 ALU_CASE(umin, umin);
792 ALU_CASE(umax, umax);
793 ALU_CASE(ffloor, ffloor);
794 ALU_CASE(fround_even, froundeven);
795 ALU_CASE(ftrunc, ftrunc);
796 ALU_CASE(fceil, fceil);
797 ALU_CASE(fdot3, fdot3);
798 ALU_CASE(fdot4, fdot4);
799 ALU_CASE(iadd, iadd);
800 ALU_CASE(isub, isub);
801 ALU_CASE(imul, imul);
802
803 /* Zero shoved as second-arg */
804 ALU_CASE(iabs, iabsdiff);
805
806 ALU_CASE(mov, imov);
807
808 ALU_CASE_CMP(feq32, feq, false);
809 ALU_CASE_CMP(fne32, fne, false);
810 ALU_CASE_CMP(flt32, flt, false);
811 ALU_CASE_CMP(ieq32, ieq, true);
812 ALU_CASE_CMP(ine32, ine, true);
813 ALU_CASE_CMP(ilt32, ilt, true);
814 ALU_CASE_CMP(ult32, ult, false);
815
816 /* We don't have a native b2f32 instruction. Instead, like many
817 * GPUs, we exploit booleans as 0/~0 for false/true, and
818 * correspondingly AND
819 * by 1.0 to do the type conversion. For the moment, prime us
820 * to emit:
821 *
822 * iand [whatever], #0
823 *
824 * At the end of emit_alu (as MIR), we'll fix-up the constant
825 */
826
827 ALU_CASE_CMP(b2f32, iand, true);
828 ALU_CASE_CMP(b2f16, iand, true);
829 ALU_CASE_CMP(b2i32, iand, true);
830
831 /* Likewise, we don't have a dedicated f2b32 instruction, but
832 * we can do a "not equal to 0.0" test. */
833
834 ALU_CASE_CMP(f2b32, fne, false);
835 ALU_CASE_CMP(i2b32, ine, true);
836
837 ALU_CASE(frcp, frcp);
838 ALU_CASE(frsq, frsqrt);
839 ALU_CASE(fsqrt, fsqrt);
840 ALU_CASE(fexp2, fexp2);
841 ALU_CASE(flog2, flog2);
842
843 ALU_CASE_RTZ(f2i64, f2i_rte);
844 ALU_CASE_RTZ(f2u64, f2u_rte);
845 ALU_CASE_RTZ(i2f64, i2f_rte);
846 ALU_CASE_RTZ(u2f64, u2f_rte);
847
848 ALU_CASE_RTZ(f2i32, f2i_rte);
849 ALU_CASE_RTZ(f2u32, f2u_rte);
850 ALU_CASE_RTZ(i2f32, i2f_rte);
851 ALU_CASE_RTZ(u2f32, u2f_rte);
852
853 ALU_CASE_RTZ(f2i8, f2i_rte);
854 ALU_CASE_RTZ(f2u8, f2u_rte);
855
856 ALU_CASE_RTZ(f2i16, f2i_rte);
857 ALU_CASE_RTZ(f2u16, f2u_rte);
858 ALU_CASE_RTZ(i2f16, i2f_rte);
859 ALU_CASE_RTZ(u2f16, u2f_rte);
860
861 ALU_CASE(fsin, fsin);
862 ALU_CASE(fcos, fcos);
863
864 /* We'll get 0 in the second arg, so:
865 * ~a = ~(a | 0) = nor(a, 0) */
866 ALU_CASE(inot, inor);
867 ALU_CASE(iand, iand);
868 ALU_CASE(ior, ior);
869 ALU_CASE(ixor, ixor);
870 ALU_CASE(ishl, ishl);
871 ALU_CASE(ishr, iasr);
872 ALU_CASE(ushr, ilsr);
873
874 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
875 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
876 ALU_CASE_CMP(b32all_fequal4, fball_eq, true);
877
878 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
879 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
880 ALU_CASE_CMP(b32any_fnequal4, fbany_neq, true);
881
882 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
883 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
884 ALU_CASE_CMP(b32all_iequal4, iball_eq, true);
885
886 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
887 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
888 ALU_CASE_CMP(b32any_inequal4, ibany_neq, true);
889
890 /* Source mods will be shoved in later */
891 ALU_CASE(fabs, fmov);
892 ALU_CASE(fneg, fmov);
893 ALU_CASE(fsat, fmov);
894 ALU_CASE(fsat_signed, fmov);
895 ALU_CASE(fclamp_pos, fmov);
896
897 /* For size conversion, we use a move. Ideally though we would squash
898 * these ops together; maybe that has to happen after in NIR as part of
899 * propagation...? An earlier algebraic pass ensured we step down by
900 * only / exactly one size. If stepping down, we use a dest override to
901 * reduce the size; if stepping up, we use a larger-sized move with a
902 * half source and a sign/zero-extension modifier */
903
904 case nir_op_i2i8:
905 case nir_op_i2i16:
906 case nir_op_i2i32:
907 case nir_op_i2i64:
908 case nir_op_u2u8:
909 case nir_op_u2u16:
910 case nir_op_u2u32:
911 case nir_op_u2u64:
912 case nir_op_f2f16:
913 case nir_op_f2f32:
914 case nir_op_f2f64: {
915 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
916 instr->op == nir_op_f2f64)
917 op = midgard_alu_op_fmov;
918 else
919 op = midgard_alu_op_imov;
920
921 break;
922 }
923
924 /* For greater-or-equal, we lower to less-or-equal and flip the
925 * arguments */
926
927 case nir_op_fge:
928 case nir_op_fge32:
929 case nir_op_ige32:
930 case nir_op_uge32: {
931 op =
932 instr->op == nir_op_fge ? midgard_alu_op_fle :
933 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
934 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
935 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
936 0;
937
938 flip_src12 = true;
939 ALU_CHECK_CMP(false);
940 break;
941 }
942
943 case nir_op_b32csel: {
944 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
945 bool is_float = mir_is_bcsel_float(instr);
946 op = is_float ?
947 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
948 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
949
950 break;
951 }
952
953 case nir_op_unpack_32_2x16:
954 case nir_op_unpack_32_4x8:
955 case nir_op_pack_32_2x16:
956 case nir_op_pack_32_4x8: {
957 op = midgard_alu_op_imov;
958 break;
959 }
960
961 default:
962 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
963 assert(0);
964 return;
965 }
966
967 /* Promote imov to fmov if it might help inline a constant */
968 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
969 && nir_src_bit_size(instr->src[0].src) == 32
970 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
971 nir_src_num_components(instr->src[0].src))) {
972 op = midgard_alu_op_fmov;
973 }
974
975 /* Midgard can perform certain modifiers on output of an ALU op */
976
977 unsigned outmod = 0;
978 bool is_int = midgard_is_integer_op(op);
979
980 if (midgard_is_integer_out_op(op)) {
981 outmod = midgard_outmod_int_wrap;
982 } else if (instr->op == nir_op_fsat) {
983 outmod = midgard_outmod_sat;
984 } else if (instr->op == nir_op_fsat_signed) {
985 outmod = midgard_outmod_sat_signed;
986 } else if (instr->op == nir_op_fclamp_pos) {
987 outmod = midgard_outmod_pos;
988 }
989
990 /* Fetch unit, quirks, etc information */
991 unsigned opcode_props = alu_opcode_props[op].props;
992 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
993
994 /* Look for floating point mods. We have the mods fsat, fsat_signed,
995 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
996 *
997 * fsat_signed(fpos(x)) = fsat(x)
998 * fsat_signed(fsat(x)) = fsat(x)
999 * fpos(fsat_signed(x)) = fsat(x)
1000 * fpos(fsat(x)) = fsat(x)
1001 * fsat(fsat_signed(x)) = fsat(x)
1002 * fsat(fpos(x)) = fsat(x)
1003 *
1004 * So by cases any composition of output modifiers is equivalent to
1005 * fsat alone.
1006 */
1007
1008 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
1009 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
1010 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
1011 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
1012 bool prior = (outmod != midgard_outmod_none);
1013 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
1014
1015 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
1016 fpos ? midgard_outmod_pos :
1017 ssat ? midgard_outmod_sat_signed :
1018 outmod;
1019 }
1020
1021 midgard_instruction ins = {
1022 .type = TAG_ALU_4,
1023 .dest = nir_dest_index(dest),
1024 .dest_type = nir_op_infos[instr->op].output_type
1025 | nir_dest_bit_size(*dest),
1026 .roundmode = roundmode,
1027 };
1028
1029 enum midgard_roundmode *roundptr = (opcode_props & MIDGARD_ROUNDS) ?
1030 &ins.roundmode : NULL;
1031
1032 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
1033 ins.src[i] = ~0;
1034
1035 if (quirk_flipped_r24) {
1036 ins.src[0] = ~0;
1037 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], roundptr, is_int, broadcast_swizzle);
1038 } else {
1039 for (unsigned i = 0; i < nr_inputs; ++i) {
1040 unsigned to = i;
1041
1042 if (instr->op == nir_op_b32csel) {
1043 /* The condition is the first argument; move
1044 * the other arguments up one to be a binary
1045 * instruction for Midgard with the condition
1046 * last */
1047
1048 if (i == 0)
1049 to = 2;
1050 else if (flip_src12)
1051 to = 2 - i;
1052 else
1053 to = i - 1;
1054 } else if (flip_src12) {
1055 to = 1 - to;
1056 }
1057
1058 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], roundptr, is_int, broadcast_swizzle);
1059
1060 /* (!c) ? a : b = c ? b : a */
1061 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1062 ins.src_invert[2] = false;
1063 flip_src12 ^= true;
1064 }
1065 }
1066 }
1067
1068 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1069 /* Lowered to move */
1070 if (instr->op == nir_op_fneg)
1071 ins.src_neg[1] ^= true;
1072
1073 if (instr->op == nir_op_fabs)
1074 ins.src_abs[1] = true;
1075 }
1076
1077 ins.mask = mask_of(nr_components);
1078
1079 midgard_vector_alu alu = {
1080 .op = op,
1081 .reg_mode = reg_mode,
1082 .outmod = outmod,
1083 };
1084
1085 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1086 * components that don't exist. Note modifier => SSA => !reg => no
1087 * writemask, so we don't have to worry about writemasks here.*/
1088
1089 if (!is_ssa)
1090 ins.mask &= instr->dest.write_mask;
1091
1092 ins.alu = alu;
1093
1094 /* Late fixup for emulated instructions */
1095
1096 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1097 /* Presently, our second argument is an inline #0 constant.
1098 * Switch over to an embedded 1.0 constant (that can't fit
1099 * inline, since we're 32-bit, not 16-bit like the inline
1100 * constants) */
1101
1102 ins.has_inline_constant = false;
1103 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1104 ins.src_types[1] = nir_type_float32;
1105 ins.has_constants = true;
1106
1107 if (instr->op == nir_op_b2f32)
1108 ins.constants.f32[0] = 1.0f;
1109 else
1110 ins.constants.i32[0] = 1;
1111
1112 for (unsigned c = 0; c < 16; ++c)
1113 ins.swizzle[1][c] = 0;
1114 } else if (instr->op == nir_op_b2f16) {
1115 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1116 ins.src_types[1] = nir_type_float16;
1117 ins.has_constants = true;
1118 ins.constants.i16[0] = _mesa_float_to_half(1.0);
1119
1120 for (unsigned c = 0; c < 16; ++c)
1121 ins.swizzle[1][c] = 0;
1122 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1123 /* Lots of instructions need a 0 plonked in */
1124 ins.has_inline_constant = false;
1125 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1126 ins.src_types[1] = nir_type_uint32;
1127 ins.has_constants = true;
1128 ins.constants.u32[0] = 0;
1129
1130 for (unsigned c = 0; c < 16; ++c)
1131 ins.swizzle[1][c] = 0;
1132 } else if (instr->op == nir_op_pack_32_2x16) {
1133 ins.dest_type = nir_type_uint16;
1134 ins.mask = mask_of(nr_components * 2);
1135 ins.is_pack = true;
1136 } else if (instr->op == nir_op_pack_32_4x8) {
1137 ins.dest_type = nir_type_uint8;
1138 ins.mask = mask_of(nr_components * 4);
1139 ins.is_pack = true;
1140 } else if (instr->op == nir_op_unpack_32_2x16) {
1141 ins.dest_type = nir_type_uint32;
1142 ins.mask = mask_of(nr_components >> 1);
1143 ins.is_pack = true;
1144 } else if (instr->op == nir_op_unpack_32_4x8) {
1145 ins.dest_type = nir_type_uint32;
1146 ins.mask = mask_of(nr_components >> 2);
1147 ins.is_pack = true;
1148 }
1149
1150 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1151 /* To avoid duplicating the lookup tables (probably), true LUT
1152 * instructions can only operate as if they were scalars. Lower
1153 * them here by changing the component. */
1154
1155 unsigned orig_mask = ins.mask;
1156
1157 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1158 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1159
1160 for (int i = 0; i < nr_components; ++i) {
1161 /* Mask the associated component, dropping the
1162 * instruction if needed */
1163
1164 ins.mask = 1 << i;
1165 ins.mask &= orig_mask;
1166
1167 if (!ins.mask)
1168 continue;
1169
1170 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1171 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1172
1173 emit_mir_instruction(ctx, ins);
1174 }
1175 } else {
1176 emit_mir_instruction(ctx, ins);
1177 }
1178 }
1179
1180 #undef ALU_CASE
1181
1182 static void
1183 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1184 {
1185 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1186 unsigned nir_mask = 0;
1187 unsigned dsize = 0;
1188
1189 if (is_read) {
1190 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1191 dsize = nir_dest_bit_size(intr->dest);
1192 } else {
1193 nir_mask = nir_intrinsic_write_mask(intr);
1194 dsize = 32;
1195 }
1196
1197 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1198 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1199 mir_set_bytemask(ins, bytemask);
1200 ins->dest_type = nir_type_uint | dsize;
1201 }
1202
1203 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1204 * optimized) versions of UBO #0 */
1205
1206 static midgard_instruction *
1207 emit_ubo_read(
1208 compiler_context *ctx,
1209 nir_instr *instr,
1210 unsigned dest,
1211 unsigned offset,
1212 nir_src *indirect_offset,
1213 unsigned indirect_shift,
1214 unsigned index)
1215 {
1216 /* TODO: half-floats */
1217
1218 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1219 ins.constants.u32[0] = offset;
1220
1221 if (instr->type == nir_instr_type_intrinsic)
1222 mir_set_intr_mask(instr, &ins, true);
1223
1224 if (indirect_offset) {
1225 ins.src[2] = nir_src_index(ctx, indirect_offset);
1226 ins.src_types[2] = nir_type_uint32;
1227 ins.load_store.arg_2 = (indirect_shift << 5);
1228 } else {
1229 ins.load_store.arg_2 = 0x1E;
1230 }
1231
1232 ins.load_store.arg_1 = index;
1233
1234 return emit_mir_instruction(ctx, ins);
1235 }
1236
1237 /* Globals are like UBOs if you squint. And shared memory is like globals if
1238 * you squint even harder */
1239
1240 static void
1241 emit_global(
1242 compiler_context *ctx,
1243 nir_instr *instr,
1244 bool is_read,
1245 unsigned srcdest,
1246 nir_src *offset,
1247 bool is_shared)
1248 {
1249 /* TODO: types */
1250
1251 midgard_instruction ins;
1252
1253 if (is_read)
1254 ins = m_ld_int4(srcdest, 0);
1255 else
1256 ins = m_st_int4(srcdest, 0);
1257
1258 mir_set_offset(ctx, &ins, offset, is_shared);
1259 mir_set_intr_mask(instr, &ins, is_read);
1260
1261 emit_mir_instruction(ctx, ins);
1262 }
1263
1264 static void
1265 emit_varying_read(
1266 compiler_context *ctx,
1267 unsigned dest, unsigned offset,
1268 unsigned nr_comp, unsigned component,
1269 nir_src *indirect_offset, nir_alu_type type, bool flat)
1270 {
1271 /* XXX: Half-floats? */
1272 /* TODO: swizzle, mask */
1273
1274 midgard_instruction ins = m_ld_vary_32(dest, offset);
1275 ins.mask = mask_of(nr_comp);
1276 ins.dest_type = type;
1277
1278 if (type == nir_type_float16) {
1279 /* Ensure we are aligned so we can pack it later */
1280 ins.mask = mask_of(ALIGN_POT(nr_comp, 2));
1281 }
1282
1283 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1284 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1285
1286 midgard_varying_parameter p = {
1287 .is_varying = 1,
1288 .interpolation = midgard_interp_default,
1289 .flat = flat,
1290 };
1291
1292 unsigned u;
1293 memcpy(&u, &p, sizeof(p));
1294 ins.load_store.varying_parameters = u;
1295
1296 if (indirect_offset) {
1297 ins.src[2] = nir_src_index(ctx, indirect_offset);
1298 ins.src_types[2] = nir_type_uint32;
1299 } else
1300 ins.load_store.arg_2 = 0x1E;
1301
1302 ins.load_store.arg_1 = 0x9E;
1303
1304 /* Use the type appropriate load */
1305 switch (type) {
1306 case nir_type_uint32:
1307 case nir_type_bool32:
1308 ins.load_store.op = midgard_op_ld_vary_32u;
1309 break;
1310 case nir_type_int32:
1311 ins.load_store.op = midgard_op_ld_vary_32i;
1312 break;
1313 case nir_type_float32:
1314 ins.load_store.op = midgard_op_ld_vary_32;
1315 break;
1316 case nir_type_float16:
1317 ins.load_store.op = midgard_op_ld_vary_16;
1318 break;
1319 default:
1320 unreachable("Attempted to load unknown type");
1321 break;
1322 }
1323
1324 emit_mir_instruction(ctx, ins);
1325 }
1326
1327 static void
1328 emit_attr_read(
1329 compiler_context *ctx,
1330 unsigned dest, unsigned offset,
1331 unsigned nr_comp, nir_alu_type t)
1332 {
1333 midgard_instruction ins = m_ld_attr_32(dest, offset);
1334 ins.load_store.arg_1 = 0x1E;
1335 ins.load_store.arg_2 = 0x1E;
1336 ins.mask = mask_of(nr_comp);
1337
1338 /* Use the type appropriate load */
1339 switch (t) {
1340 case nir_type_uint:
1341 case nir_type_bool:
1342 ins.load_store.op = midgard_op_ld_attr_32u;
1343 break;
1344 case nir_type_int:
1345 ins.load_store.op = midgard_op_ld_attr_32i;
1346 break;
1347 case nir_type_float:
1348 ins.load_store.op = midgard_op_ld_attr_32;
1349 break;
1350 default:
1351 unreachable("Attempted to load unknown type");
1352 break;
1353 }
1354
1355 emit_mir_instruction(ctx, ins);
1356 }
1357
1358 static void
1359 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1360 unsigned nr_components, unsigned offset)
1361 {
1362 nir_dest nir_dest;
1363
1364 /* Figure out which uniform this is */
1365 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1366 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1367
1368 unsigned dest = nir_dest_index(&nir_dest);
1369
1370 /* Sysvals are prefix uniforms */
1371 unsigned uniform = ((uintptr_t) val) - 1;
1372
1373 /* Emit the read itself -- this is never indirect */
1374 midgard_instruction *ins =
1375 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1376
1377 ins->mask = mask_of(nr_components);
1378 }
1379
1380 static unsigned
1381 compute_builtin_arg(nir_op op)
1382 {
1383 switch (op) {
1384 case nir_intrinsic_load_work_group_id:
1385 return 0x14;
1386 case nir_intrinsic_load_local_invocation_id:
1387 return 0x10;
1388 default:
1389 unreachable("Invalid compute paramater loaded");
1390 }
1391 }
1392
1393 static void
1394 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1395 {
1396 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1397
1398 midgard_instruction *br = ctx->writeout_branch[rt];
1399
1400 assert(!br);
1401
1402 emit_explicit_constant(ctx, src, src);
1403
1404 struct midgard_instruction ins =
1405 v_branch(false, false);
1406
1407 ins.writeout = true;
1408
1409 /* Add dependencies */
1410 ins.src[0] = src;
1411 ins.src_types[0] = nir_type_uint32;
1412 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1413 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1414
1415 /* Emit the branch */
1416 br = emit_mir_instruction(ctx, ins);
1417 schedule_barrier(ctx);
1418 ctx->writeout_branch[rt] = br;
1419
1420 /* Push our current location = current block count - 1 = where we'll
1421 * jump to. Maybe a bit too clever for my own good */
1422
1423 br->branch.target_block = ctx->block_count - 1;
1424 }
1425
1426 static void
1427 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1428 {
1429 unsigned reg = nir_dest_index(&instr->dest);
1430 midgard_instruction ins = m_ld_compute_id(reg, 0);
1431 ins.mask = mask_of(3);
1432 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1433 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1434 emit_mir_instruction(ctx, ins);
1435 }
1436
1437 static unsigned
1438 vertex_builtin_arg(nir_op op)
1439 {
1440 switch (op) {
1441 case nir_intrinsic_load_vertex_id:
1442 return PAN_VERTEX_ID;
1443 case nir_intrinsic_load_instance_id:
1444 return PAN_INSTANCE_ID;
1445 default:
1446 unreachable("Invalid vertex builtin");
1447 }
1448 }
1449
1450 static void
1451 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1452 {
1453 unsigned reg = nir_dest_index(&instr->dest);
1454 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1455 }
1456
1457 static void
1458 emit_control_barrier(compiler_context *ctx)
1459 {
1460 midgard_instruction ins = {
1461 .type = TAG_TEXTURE_4,
1462 .dest = ~0,
1463 .src = { ~0, ~0, ~0, ~0 },
1464 .texture = {
1465 .op = TEXTURE_OP_BARRIER,
1466
1467 /* TODO: optimize */
1468 .out_of_order = MIDGARD_BARRIER_BUFFER |
1469 MIDGARD_BARRIER_SHARED ,
1470 }
1471 };
1472
1473 emit_mir_instruction(ctx, ins);
1474 }
1475
1476 static const nir_variable *
1477 search_var(struct exec_list *vars, unsigned driver_loc)
1478 {
1479 nir_foreach_variable(var, vars) {
1480 if (var->data.driver_location == driver_loc)
1481 return var;
1482 }
1483
1484 return NULL;
1485 }
1486
1487 static unsigned
1488 mir_get_branch_cond(nir_src *src, bool *invert)
1489 {
1490 /* Wrap it. No swizzle since it's a scalar */
1491
1492 nir_alu_src alu = {
1493 .src = *src
1494 };
1495
1496 *invert = pan_has_source_mod(&alu, nir_op_inot);
1497 return nir_src_index(NULL, &alu.src);
1498 }
1499
1500 static void
1501 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1502 {
1503 unsigned offset = 0, reg;
1504
1505 switch (instr->intrinsic) {
1506 case nir_intrinsic_discard_if:
1507 case nir_intrinsic_discard: {
1508 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1509 struct midgard_instruction discard = v_branch(conditional, false);
1510 discard.branch.target_type = TARGET_DISCARD;
1511
1512 if (conditional) {
1513 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1514 &discard.branch.invert_conditional);
1515 discard.src_types[0] = nir_type_uint32;
1516 }
1517
1518 emit_mir_instruction(ctx, discard);
1519 schedule_barrier(ctx);
1520
1521 break;
1522 }
1523
1524 case nir_intrinsic_load_uniform:
1525 case nir_intrinsic_load_ubo:
1526 case nir_intrinsic_load_global:
1527 case nir_intrinsic_load_shared:
1528 case nir_intrinsic_load_input:
1529 case nir_intrinsic_load_interpolated_input: {
1530 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1531 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1532 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1533 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1534 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1535 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1536
1537 /* Get the base type of the intrinsic */
1538 /* TODO: Infer type? Does it matter? */
1539 nir_alu_type t =
1540 (is_ubo || is_global || is_shared) ? nir_type_uint :
1541 (is_interp) ? nir_type_float :
1542 nir_intrinsic_type(instr);
1543
1544 t = nir_alu_type_get_base_type(t);
1545
1546 if (!(is_ubo || is_global)) {
1547 offset = nir_intrinsic_base(instr);
1548 }
1549
1550 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1551
1552 nir_src *src_offset = nir_get_io_offset_src(instr);
1553
1554 bool direct = nir_src_is_const(*src_offset);
1555 nir_src *indirect_offset = direct ? NULL : src_offset;
1556
1557 if (direct)
1558 offset += nir_src_as_uint(*src_offset);
1559
1560 /* We may need to apply a fractional offset */
1561 int component = (is_flat || is_interp) ?
1562 nir_intrinsic_component(instr) : 0;
1563 reg = nir_dest_index(&instr->dest);
1564
1565 if (is_uniform && !ctx->is_blend) {
1566 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1567 } else if (is_ubo) {
1568 nir_src index = instr->src[0];
1569
1570 /* TODO: Is indirect block number possible? */
1571 assert(nir_src_is_const(index));
1572
1573 uint32_t uindex = nir_src_as_uint(index) + 1;
1574 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1575 } else if (is_global || is_shared) {
1576 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1577 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1578 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t | nir_dest_bit_size(instr->dest), is_flat);
1579 } else if (ctx->is_blend) {
1580 /* For blend shaders, load the input color, which is
1581 * preloaded to r0 */
1582
1583 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1584 emit_mir_instruction(ctx, move);
1585 schedule_barrier(ctx);
1586 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1587 emit_attr_read(ctx, reg, offset, nr_comp, t);
1588 } else {
1589 DBG("Unknown load\n");
1590 assert(0);
1591 }
1592
1593 break;
1594 }
1595
1596 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1597 case nir_intrinsic_load_barycentric_pixel:
1598 case nir_intrinsic_load_barycentric_centroid:
1599 break;
1600
1601 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1602
1603 case nir_intrinsic_load_raw_output_pan: {
1604 reg = nir_dest_index(&instr->dest);
1605 assert(ctx->is_blend);
1606
1607 /* T720 and below use different blend opcodes with slightly
1608 * different semantics than T760 and up */
1609
1610 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1611
1612 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1613 ld.load_store.op = midgard_op_ld_color_buffer_32u_old;
1614 ld.load_store.address = 16;
1615 ld.load_store.arg_2 = 0x1E;
1616 }
1617
1618 emit_mir_instruction(ctx, ld);
1619 break;
1620 }
1621
1622 case nir_intrinsic_load_output: {
1623 reg = nir_dest_index(&instr->dest);
1624 assert(ctx->is_blend);
1625
1626 midgard_instruction ld = m_ld_color_buffer_as_fp16(reg, 0);
1627
1628 for (unsigned c = 4; c < 16; ++c)
1629 ld.swizzle[0][c] = 0;
1630
1631 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1632 ld.load_store.op = midgard_op_ld_color_buffer_as_fp16_old;
1633 ld.load_store.address = 1;
1634 ld.load_store.arg_2 = 0x1E;
1635 }
1636
1637 emit_mir_instruction(ctx, ld);
1638 break;
1639 }
1640
1641 case nir_intrinsic_load_blend_const_color_rgba: {
1642 assert(ctx->is_blend);
1643 reg = nir_dest_index(&instr->dest);
1644
1645 /* Blend constants are embedded directly in the shader and
1646 * patched in, so we use some magic routing */
1647
1648 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1649 ins.has_constants = true;
1650 ins.has_blend_constant = true;
1651 emit_mir_instruction(ctx, ins);
1652 break;
1653 }
1654
1655 case nir_intrinsic_store_zs_output_pan: {
1656 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1657 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1658 MIDGARD_ZS_RT);
1659
1660 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1661
1662 if (!nir_intrinsic_component(instr))
1663 br->writeout_depth = true;
1664 if (nir_intrinsic_component(instr) ||
1665 instr->num_components)
1666 br->writeout_stencil = true;
1667 assert(br->writeout_depth | br->writeout_stencil);
1668 break;
1669 }
1670
1671 case nir_intrinsic_store_output:
1672 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1673
1674 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1675
1676 reg = nir_src_index(ctx, &instr->src[0]);
1677
1678 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1679 const nir_variable *var;
1680 enum midgard_rt_id rt;
1681
1682 var = search_var(&ctx->nir->outputs,
1683 nir_intrinsic_base(instr));
1684 assert(var);
1685 if (var->data.location == FRAG_RESULT_COLOR)
1686 rt = MIDGARD_COLOR_RT0;
1687 else if (var->data.location >= FRAG_RESULT_DATA0)
1688 rt = MIDGARD_COLOR_RT0 + var->data.location -
1689 FRAG_RESULT_DATA0;
1690 else
1691 assert(0);
1692
1693 emit_fragment_store(ctx, reg, rt);
1694 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1695 /* We should have been vectorized, though we don't
1696 * currently check that st_vary is emitted only once
1697 * per slot (this is relevant, since there's not a mask
1698 * parameter available on the store [set to 0 by the
1699 * blob]). We do respect the component by adjusting the
1700 * swizzle. If this is a constant source, we'll need to
1701 * emit that explicitly. */
1702
1703 emit_explicit_constant(ctx, reg, reg);
1704
1705 unsigned dst_component = nir_intrinsic_component(instr);
1706 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1707
1708 midgard_instruction st = m_st_vary_32(reg, offset);
1709 st.load_store.arg_1 = 0x9E;
1710 st.load_store.arg_2 = 0x1E;
1711
1712 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1713 case nir_type_uint:
1714 case nir_type_bool:
1715 st.load_store.op = midgard_op_st_vary_32u;
1716 break;
1717 case nir_type_int:
1718 st.load_store.op = midgard_op_st_vary_32i;
1719 break;
1720 case nir_type_float:
1721 st.load_store.op = midgard_op_st_vary_32;
1722 break;
1723 default:
1724 unreachable("Attempted to store unknown type");
1725 break;
1726 }
1727
1728 /* nir_intrinsic_component(store_intr) encodes the
1729 * destination component start. Source component offset
1730 * adjustment is taken care of in
1731 * install_registers_instr(), when offset_swizzle() is
1732 * called.
1733 */
1734 unsigned src_component = COMPONENT_X;
1735
1736 assert(nr_comp > 0);
1737 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1738 st.swizzle[0][i] = src_component;
1739 if (i >= dst_component && i < dst_component + nr_comp - 1)
1740 src_component++;
1741 }
1742
1743 emit_mir_instruction(ctx, st);
1744 } else {
1745 DBG("Unknown store\n");
1746 assert(0);
1747 }
1748
1749 break;
1750
1751 /* Special case of store_output for lowered blend shaders */
1752 case nir_intrinsic_store_raw_output_pan:
1753 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1754 reg = nir_src_index(ctx, &instr->src[0]);
1755 emit_fragment_store(ctx, reg, ctx->blend_rt);
1756 break;
1757
1758 case nir_intrinsic_store_global:
1759 case nir_intrinsic_store_shared:
1760 reg = nir_src_index(ctx, &instr->src[0]);
1761 emit_explicit_constant(ctx, reg, reg);
1762
1763 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1764 break;
1765
1766 case nir_intrinsic_load_ssbo_address:
1767 emit_sysval_read(ctx, &instr->instr, 1, 0);
1768 break;
1769
1770 case nir_intrinsic_get_buffer_size:
1771 emit_sysval_read(ctx, &instr->instr, 1, 8);
1772 break;
1773
1774 case nir_intrinsic_load_viewport_scale:
1775 case nir_intrinsic_load_viewport_offset:
1776 case nir_intrinsic_load_num_work_groups:
1777 case nir_intrinsic_load_sampler_lod_parameters_pan:
1778 emit_sysval_read(ctx, &instr->instr, 3, 0);
1779 break;
1780
1781 case nir_intrinsic_load_work_group_id:
1782 case nir_intrinsic_load_local_invocation_id:
1783 emit_compute_builtin(ctx, instr);
1784 break;
1785
1786 case nir_intrinsic_load_vertex_id:
1787 case nir_intrinsic_load_instance_id:
1788 emit_vertex_builtin(ctx, instr);
1789 break;
1790
1791 case nir_intrinsic_memory_barrier_buffer:
1792 case nir_intrinsic_memory_barrier_shared:
1793 break;
1794
1795 case nir_intrinsic_control_barrier:
1796 schedule_barrier(ctx);
1797 emit_control_barrier(ctx);
1798 schedule_barrier(ctx);
1799 break;
1800
1801 default:
1802 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1803 assert(0);
1804 break;
1805 }
1806 }
1807
1808 static unsigned
1809 midgard_tex_format(enum glsl_sampler_dim dim)
1810 {
1811 switch (dim) {
1812 case GLSL_SAMPLER_DIM_1D:
1813 case GLSL_SAMPLER_DIM_BUF:
1814 return MALI_TEX_1D;
1815
1816 case GLSL_SAMPLER_DIM_2D:
1817 case GLSL_SAMPLER_DIM_EXTERNAL:
1818 case GLSL_SAMPLER_DIM_RECT:
1819 return MALI_TEX_2D;
1820
1821 case GLSL_SAMPLER_DIM_3D:
1822 return MALI_TEX_3D;
1823
1824 case GLSL_SAMPLER_DIM_CUBE:
1825 return MALI_TEX_CUBE;
1826
1827 default:
1828 DBG("Unknown sampler dim type\n");
1829 assert(0);
1830 return 0;
1831 }
1832 }
1833
1834 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
1835 * was successful */
1836
1837 static bool
1838 pan_attach_constant_bias(
1839 compiler_context *ctx,
1840 nir_src lod,
1841 midgard_texture_word *word)
1842 {
1843 /* To attach as constant, it has to *be* constant */
1844
1845 if (!nir_src_is_const(lod))
1846 return false;
1847
1848 float f = nir_src_as_float(lod);
1849
1850 /* Break into fixed-point */
1851 signed lod_int = f;
1852 float lod_frac = f - lod_int;
1853
1854 /* Carry over negative fractions */
1855 if (lod_frac < 0.0) {
1856 lod_int--;
1857 lod_frac += 1.0;
1858 }
1859
1860 /* Encode */
1861 word->bias = float_to_ubyte(lod_frac);
1862 word->bias_int = lod_int;
1863
1864 return true;
1865 }
1866
1867 static void
1868 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1869 unsigned midgard_texop)
1870 {
1871 /* TODO */
1872 //assert (!instr->sampler);
1873
1874 int texture_index = instr->texture_index;
1875 int sampler_index = texture_index;
1876
1877 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1878 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1879
1880 midgard_instruction ins = {
1881 .type = TAG_TEXTURE_4,
1882 .mask = 0xF,
1883 .dest = nir_dest_index(&instr->dest),
1884 .src = { ~0, ~0, ~0, ~0 },
1885 .dest_type = dest_type,
1886 .swizzle = SWIZZLE_IDENTITY_4,
1887 .texture = {
1888 .op = midgard_texop,
1889 .format = midgard_tex_format(instr->sampler_dim),
1890 .texture_handle = texture_index,
1891 .sampler_handle = sampler_index,
1892 .shadow = instr->is_shadow,
1893 }
1894 };
1895
1896 if (instr->is_shadow && !instr->is_new_style_shadow)
1897 for (int i = 0; i < 4; ++i)
1898 ins.swizzle[0][i] = COMPONENT_X;
1899
1900 /* We may need a temporary for the coordinate */
1901
1902 bool needs_temp_coord =
1903 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1904 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1905 (instr->is_shadow);
1906
1907 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1908
1909 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1910 int index = nir_src_index(ctx, &instr->src[i].src);
1911 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1912 unsigned sz = nir_src_bit_size(instr->src[i].src);
1913 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1914
1915 switch (instr->src[i].src_type) {
1916 case nir_tex_src_coord: {
1917 emit_explicit_constant(ctx, index, index);
1918
1919 unsigned coord_mask = mask_of(instr->coord_components);
1920
1921 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1922
1923 if (flip_zw)
1924 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1925
1926 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1927 /* texelFetch is undefined on samplerCube */
1928 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1929
1930 /* For cubemaps, we use a special ld/st op to
1931 * select the face and copy the xy into the
1932 * texture register */
1933
1934 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1935 ld.src[1] = index;
1936 ld.src_types[1] = T;
1937 ld.mask = 0x3; /* xy */
1938 ld.load_store.arg_1 = 0x20;
1939 ld.swizzle[1][3] = COMPONENT_X;
1940 emit_mir_instruction(ctx, ld);
1941
1942 /* xyzw -> xyxx */
1943 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1944 ins.swizzle[1][3] = COMPONENT_X;
1945 } else if (needs_temp_coord) {
1946 /* mov coord_temp, coords */
1947 midgard_instruction mov = v_mov(index, coords);
1948 mov.mask = coord_mask;
1949
1950 if (flip_zw)
1951 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1952
1953 emit_mir_instruction(ctx, mov);
1954 } else {
1955 coords = index;
1956 }
1957
1958 ins.src[1] = coords;
1959 ins.src_types[1] = T;
1960
1961 /* Texelfetch coordinates uses all four elements
1962 * (xyz/index) regardless of texture dimensionality,
1963 * which means it's necessary to zero the unused
1964 * components to keep everything happy */
1965
1966 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1967 /* mov index.zw, #0, or generalized */
1968 midgard_instruction mov =
1969 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1970 mov.has_constants = true;
1971 mov.mask = coord_mask ^ 0xF;
1972 emit_mir_instruction(ctx, mov);
1973 }
1974
1975 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1976 /* Array component in w but NIR wants it in z,
1977 * but if we have a temp coord we already fixed
1978 * that up */
1979
1980 if (nr_components == 3) {
1981 ins.swizzle[1][2] = COMPONENT_Z;
1982 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1983 } else if (nr_components == 2) {
1984 ins.swizzle[1][2] =
1985 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1986 ins.swizzle[1][3] = COMPONENT_X;
1987 } else
1988 unreachable("Invalid texture 2D components");
1989 }
1990
1991 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1992 /* We zeroed */
1993 ins.swizzle[1][2] = COMPONENT_Z;
1994 ins.swizzle[1][3] = COMPONENT_W;
1995 }
1996
1997 break;
1998 }
1999
2000 case nir_tex_src_bias:
2001 case nir_tex_src_lod: {
2002 /* Try as a constant if we can */
2003
2004 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
2005 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
2006 break;
2007
2008 ins.texture.lod_register = true;
2009 ins.src[2] = index;
2010 ins.src_types[2] = T;
2011
2012 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2013 ins.swizzle[2][c] = COMPONENT_X;
2014
2015 emit_explicit_constant(ctx, index, index);
2016
2017 break;
2018 };
2019
2020 case nir_tex_src_offset: {
2021 ins.texture.offset_register = true;
2022 ins.src[3] = index;
2023 ins.src_types[3] = T;
2024
2025 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2026 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
2027
2028 emit_explicit_constant(ctx, index, index);
2029 break;
2030 };
2031
2032 case nir_tex_src_comparator: {
2033 unsigned comp = COMPONENT_Z;
2034
2035 /* mov coord_temp.foo, coords */
2036 midgard_instruction mov = v_mov(index, coords);
2037 mov.mask = 1 << comp;
2038
2039 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
2040 mov.swizzle[1][i] = COMPONENT_X;
2041
2042 emit_mir_instruction(ctx, mov);
2043 break;
2044 }
2045
2046 default: {
2047 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
2048 assert(0);
2049 }
2050 }
2051 }
2052
2053 emit_mir_instruction(ctx, ins);
2054 }
2055
2056 static void
2057 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2058 {
2059 switch (instr->op) {
2060 case nir_texop_tex:
2061 case nir_texop_txb:
2062 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2063 break;
2064 case nir_texop_txl:
2065 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2066 break;
2067 case nir_texop_txf:
2068 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2069 break;
2070 case nir_texop_txs:
2071 emit_sysval_read(ctx, &instr->instr, 4, 0);
2072 break;
2073 default: {
2074 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2075 assert(0);
2076 }
2077 }
2078 }
2079
2080 static void
2081 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2082 {
2083 switch (instr->type) {
2084 case nir_jump_break: {
2085 /* Emit a branch out of the loop */
2086 struct midgard_instruction br = v_branch(false, false);
2087 br.branch.target_type = TARGET_BREAK;
2088 br.branch.target_break = ctx->current_loop_depth;
2089 emit_mir_instruction(ctx, br);
2090 break;
2091 }
2092
2093 default:
2094 DBG("Unknown jump type %d\n", instr->type);
2095 break;
2096 }
2097 }
2098
2099 static void
2100 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2101 {
2102 switch (instr->type) {
2103 case nir_instr_type_load_const:
2104 emit_load_const(ctx, nir_instr_as_load_const(instr));
2105 break;
2106
2107 case nir_instr_type_intrinsic:
2108 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2109 break;
2110
2111 case nir_instr_type_alu:
2112 emit_alu(ctx, nir_instr_as_alu(instr));
2113 break;
2114
2115 case nir_instr_type_tex:
2116 emit_tex(ctx, nir_instr_as_tex(instr));
2117 break;
2118
2119 case nir_instr_type_jump:
2120 emit_jump(ctx, nir_instr_as_jump(instr));
2121 break;
2122
2123 case nir_instr_type_ssa_undef:
2124 /* Spurious */
2125 break;
2126
2127 default:
2128 DBG("Unhandled instruction type\n");
2129 break;
2130 }
2131 }
2132
2133
2134 /* ALU instructions can inline or embed constants, which decreases register
2135 * pressure and saves space. */
2136
2137 #define CONDITIONAL_ATTACH(idx) { \
2138 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2139 \
2140 if (entry) { \
2141 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2142 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2143 } \
2144 }
2145
2146 static void
2147 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2148 {
2149 mir_foreach_instr_in_block(block, alu) {
2150 /* Other instructions cannot inline constants */
2151 if (alu->type != TAG_ALU_4) continue;
2152 if (alu->compact_branch) continue;
2153
2154 /* If there is already a constant here, we can do nothing */
2155 if (alu->has_constants) continue;
2156
2157 CONDITIONAL_ATTACH(0);
2158
2159 if (!alu->has_constants) {
2160 CONDITIONAL_ATTACH(1)
2161 } else if (!alu->inline_constant) {
2162 /* Corner case: _two_ vec4 constants, for instance with a
2163 * csel. For this case, we can only use a constant
2164 * register for one, we'll have to emit a move for the
2165 * other. */
2166
2167 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2168 unsigned scratch = make_compiler_temp(ctx);
2169
2170 if (entry) {
2171 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2172 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2173
2174 /* Set the source */
2175 alu->src[1] = scratch;
2176
2177 /* Inject us -before- the last instruction which set r31 */
2178 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2179 }
2180 }
2181 }
2182 }
2183
2184 /* Midgard supports two types of constants, embedded constants (128-bit) and
2185 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2186 * constants can be demoted to inline constants, for space savings and
2187 * sometimes a performance boost */
2188
2189 static void
2190 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2191 {
2192 mir_foreach_instr_in_block(block, ins) {
2193 if (!ins->has_constants) continue;
2194 if (ins->has_inline_constant) continue;
2195
2196 /* Blend constants must not be inlined by definition */
2197 if (ins->has_blend_constant) continue;
2198
2199 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2200 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2201 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2202
2203 if (!(is_16 || is_32))
2204 continue;
2205
2206 /* src1 cannot be an inline constant due to encoding
2207 * restrictions. So, if possible we try to flip the arguments
2208 * in that case */
2209
2210 int op = ins->alu.op;
2211
2212 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2213 alu_opcode_props[op].props & OP_COMMUTES) {
2214 mir_flip(ins);
2215 }
2216
2217 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2218 /* Component is from the swizzle. Take a nonzero component */
2219 assert(ins->mask);
2220 unsigned first_comp = ffs(ins->mask) - 1;
2221 unsigned component = ins->swizzle[1][first_comp];
2222
2223 /* Scale constant appropriately, if we can legally */
2224 uint16_t scaled_constant = 0;
2225
2226 if (is_16) {
2227 scaled_constant = ins->constants.u16[component];
2228 } else if (midgard_is_integer_op(op)) {
2229 scaled_constant = ins->constants.u32[component];
2230
2231 /* Constant overflow after resize */
2232 if (scaled_constant != ins->constants.u32[component])
2233 continue;
2234 } else {
2235 float original = ins->constants.f32[component];
2236 scaled_constant = _mesa_float_to_half(original);
2237
2238 /* Check for loss of precision. If this is
2239 * mediump, we don't care, but for a highp
2240 * shader, we need to pay attention. NIR
2241 * doesn't yet tell us which mode we're in!
2242 * Practically this prevents most constants
2243 * from being inlined, sadly. */
2244
2245 float fp32 = _mesa_half_to_float(scaled_constant);
2246
2247 if (fp32 != original)
2248 continue;
2249 }
2250
2251 /* Should've been const folded */
2252 if (ins->src_abs[1] || ins->src_neg[1])
2253 continue;
2254
2255 /* Make sure that the constant is not itself a vector
2256 * by checking if all accessed values are the same. */
2257
2258 const midgard_constants *cons = &ins->constants;
2259 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2260
2261 bool is_vector = false;
2262 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2263
2264 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2265 /* We only care if this component is actually used */
2266 if (!(mask & (1 << c)))
2267 continue;
2268
2269 uint32_t test = is_16 ?
2270 cons->u16[ins->swizzle[1][c]] :
2271 cons->u32[ins->swizzle[1][c]];
2272
2273 if (test != value) {
2274 is_vector = true;
2275 break;
2276 }
2277 }
2278
2279 if (is_vector)
2280 continue;
2281
2282 /* Get rid of the embedded constant */
2283 ins->has_constants = false;
2284 ins->src[1] = ~0;
2285 ins->has_inline_constant = true;
2286 ins->inline_constant = scaled_constant;
2287 }
2288 }
2289 }
2290
2291 /* Dead code elimination for branches at the end of a block - only one branch
2292 * per block is legal semantically */
2293
2294 static void
2295 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2296 {
2297 bool branched = false;
2298
2299 mir_foreach_instr_in_block_safe(block, ins) {
2300 if (!midgard_is_branch_unit(ins->unit)) continue;
2301
2302 if (branched)
2303 mir_remove_instruction(ins);
2304
2305 branched = true;
2306 }
2307 }
2308
2309 /* We want to force the invert on AND/OR to the second slot to legalize into
2310 * iandnot/iornot. The relevant patterns are for AND (and OR respectively)
2311 *
2312 * ~a & #b = ~a & ~(#~b)
2313 * ~a & b = b & ~a
2314 */
2315
2316 static void
2317 midgard_legalize_invert(compiler_context *ctx, midgard_block *block)
2318 {
2319 mir_foreach_instr_in_block(block, ins) {
2320 if (ins->type != TAG_ALU_4) continue;
2321
2322 if (ins->alu.op != midgard_alu_op_iand &&
2323 ins->alu.op != midgard_alu_op_ior) continue;
2324
2325 if (ins->src_invert[1] || !ins->src_invert[0]) continue;
2326
2327 if (ins->has_inline_constant) {
2328 /* ~(#~a) = ~(~#a) = a, so valid, and forces both
2329 * inverts on */
2330 ins->inline_constant = ~ins->inline_constant;
2331 ins->src_invert[1] = true;
2332 } else {
2333 /* Flip to the right invert order. Note
2334 * has_inline_constant false by assumption on the
2335 * branch, so flipping makes sense. */
2336 mir_flip(ins);
2337 }
2338 }
2339 }
2340
2341 static unsigned
2342 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2343 {
2344 /* Loop to ourselves */
2345 midgard_instruction *br = ctx->writeout_branch[rt];
2346 struct midgard_instruction ins = v_branch(false, false);
2347 ins.writeout = true;
2348 ins.writeout_depth = br->writeout_depth;
2349 ins.writeout_stencil = br->writeout_stencil;
2350 ins.branch.target_block = ctx->block_count - 1;
2351 ins.constants.u32[0] = br->constants.u32[0];
2352 emit_mir_instruction(ctx, ins);
2353
2354 ctx->current_block->epilogue = true;
2355 schedule_barrier(ctx);
2356 return ins.branch.target_block;
2357 }
2358
2359 static midgard_block *
2360 emit_block(compiler_context *ctx, nir_block *block)
2361 {
2362 midgard_block *this_block = ctx->after_block;
2363 ctx->after_block = NULL;
2364
2365 if (!this_block)
2366 this_block = create_empty_block(ctx);
2367
2368 list_addtail(&this_block->base.link, &ctx->blocks);
2369
2370 this_block->scheduled = false;
2371 ++ctx->block_count;
2372
2373 /* Set up current block */
2374 list_inithead(&this_block->base.instructions);
2375 ctx->current_block = this_block;
2376
2377 nir_foreach_instr(instr, block) {
2378 emit_instr(ctx, instr);
2379 ++ctx->instruction_count;
2380 }
2381
2382 return this_block;
2383 }
2384
2385 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2386
2387 static void
2388 emit_if(struct compiler_context *ctx, nir_if *nif)
2389 {
2390 midgard_block *before_block = ctx->current_block;
2391
2392 /* Speculatively emit the branch, but we can't fill it in until later */
2393 bool inv = false;
2394 EMIT(branch, true, true);
2395 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2396 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2397 then_branch->src_types[0] = nir_type_uint32;
2398 then_branch->branch.invert_conditional = !inv;
2399
2400 /* Emit the two subblocks. */
2401 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2402 midgard_block *end_then_block = ctx->current_block;
2403
2404 /* Emit a jump from the end of the then block to the end of the else */
2405 EMIT(branch, false, false);
2406 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2407
2408 /* Emit second block, and check if it's empty */
2409
2410 int else_idx = ctx->block_count;
2411 int count_in = ctx->instruction_count;
2412 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2413 midgard_block *end_else_block = ctx->current_block;
2414 int after_else_idx = ctx->block_count;
2415
2416 /* Now that we have the subblocks emitted, fix up the branches */
2417
2418 assert(then_block);
2419 assert(else_block);
2420
2421 if (ctx->instruction_count == count_in) {
2422 /* The else block is empty, so don't emit an exit jump */
2423 mir_remove_instruction(then_exit);
2424 then_branch->branch.target_block = after_else_idx;
2425 } else {
2426 then_branch->branch.target_block = else_idx;
2427 then_exit->branch.target_block = after_else_idx;
2428 }
2429
2430 /* Wire up the successors */
2431
2432 ctx->after_block = create_empty_block(ctx);
2433
2434 pan_block_add_successor(&before_block->base, &then_block->base);
2435 pan_block_add_successor(&before_block->base, &else_block->base);
2436
2437 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2438 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2439 }
2440
2441 static void
2442 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2443 {
2444 /* Remember where we are */
2445 midgard_block *start_block = ctx->current_block;
2446
2447 /* Allocate a loop number, growing the current inner loop depth */
2448 int loop_idx = ++ctx->current_loop_depth;
2449
2450 /* Get index from before the body so we can loop back later */
2451 int start_idx = ctx->block_count;
2452
2453 /* Emit the body itself */
2454 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2455
2456 /* Branch back to loop back */
2457 struct midgard_instruction br_back = v_branch(false, false);
2458 br_back.branch.target_block = start_idx;
2459 emit_mir_instruction(ctx, br_back);
2460
2461 /* Mark down that branch in the graph. */
2462 pan_block_add_successor(&start_block->base, &loop_block->base);
2463 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2464
2465 /* Find the index of the block about to follow us (note: we don't add
2466 * one; blocks are 0-indexed so we get a fencepost problem) */
2467 int break_block_idx = ctx->block_count;
2468
2469 /* Fix up the break statements we emitted to point to the right place,
2470 * now that we can allocate a block number for them */
2471 ctx->after_block = create_empty_block(ctx);
2472
2473 mir_foreach_block_from(ctx, start_block, _block) {
2474 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2475 if (ins->type != TAG_ALU_4) continue;
2476 if (!ins->compact_branch) continue;
2477
2478 /* We found a branch -- check the type to see if we need to do anything */
2479 if (ins->branch.target_type != TARGET_BREAK) continue;
2480
2481 /* It's a break! Check if it's our break */
2482 if (ins->branch.target_break != loop_idx) continue;
2483
2484 /* Okay, cool, we're breaking out of this loop.
2485 * Rewrite from a break to a goto */
2486
2487 ins->branch.target_type = TARGET_GOTO;
2488 ins->branch.target_block = break_block_idx;
2489
2490 pan_block_add_successor(_block, &ctx->after_block->base);
2491 }
2492 }
2493
2494 /* Now that we've finished emitting the loop, free up the depth again
2495 * so we play nice with recursion amid nested loops */
2496 --ctx->current_loop_depth;
2497
2498 /* Dump loop stats */
2499 ++ctx->loop_count;
2500 }
2501
2502 static midgard_block *
2503 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2504 {
2505 midgard_block *start_block = NULL;
2506
2507 foreach_list_typed(nir_cf_node, node, node, list) {
2508 switch (node->type) {
2509 case nir_cf_node_block: {
2510 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2511
2512 if (!start_block)
2513 start_block = block;
2514
2515 break;
2516 }
2517
2518 case nir_cf_node_if:
2519 emit_if(ctx, nir_cf_node_as_if(node));
2520 break;
2521
2522 case nir_cf_node_loop:
2523 emit_loop(ctx, nir_cf_node_as_loop(node));
2524 break;
2525
2526 case nir_cf_node_function:
2527 assert(0);
2528 break;
2529 }
2530 }
2531
2532 return start_block;
2533 }
2534
2535 /* Due to lookahead, we need to report the first tag executed in the command
2536 * stream and in branch targets. An initial block might be empty, so iterate
2537 * until we find one that 'works' */
2538
2539 static unsigned
2540 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2541 {
2542 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2543
2544 mir_foreach_block_from(ctx, initial_block, _v) {
2545 midgard_block *v = (midgard_block *) _v;
2546 if (v->quadword_count) {
2547 midgard_bundle *initial_bundle =
2548 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2549
2550 return initial_bundle->tag;
2551 }
2552 }
2553
2554 /* Default to a tag 1 which will break from the shader, in case we jump
2555 * to the exit block (i.e. `return` in a compute shader) */
2556
2557 return 1;
2558 }
2559
2560 /* For each fragment writeout instruction, generate a writeout loop to
2561 * associate with it */
2562
2563 static void
2564 mir_add_writeout_loops(compiler_context *ctx)
2565 {
2566 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2567 midgard_instruction *br = ctx->writeout_branch[rt];
2568 if (!br) continue;
2569
2570 unsigned popped = br->branch.target_block;
2571 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2572 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2573 br->branch.target_type = TARGET_GOTO;
2574
2575 /* If we have more RTs, we'll need to restore back after our
2576 * loop terminates */
2577
2578 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2579 midgard_instruction uncond = v_branch(false, false);
2580 uncond.branch.target_block = popped;
2581 uncond.branch.target_type = TARGET_GOTO;
2582 emit_mir_instruction(ctx, uncond);
2583 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2584 schedule_barrier(ctx);
2585 } else {
2586 /* We're last, so we can terminate here */
2587 br->last_writeout = true;
2588 }
2589 }
2590 }
2591
2592 int
2593 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2594 {
2595 struct util_dynarray *compiled = &program->compiled;
2596
2597 midgard_debug = debug_get_option_midgard_debug();
2598
2599 /* TODO: Bound against what? */
2600 compiler_context *ctx = rzalloc(NULL, compiler_context);
2601
2602 ctx->nir = nir;
2603 ctx->stage = nir->info.stage;
2604 ctx->is_blend = is_blend;
2605 ctx->alpha_ref = program->alpha_ref;
2606 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2607 ctx->quirks = midgard_get_quirks(gpu_id);
2608
2609 /* Start off with a safe cutoff, allowing usage of all 16 work
2610 * registers. Later, we'll promote uniform reads to uniform registers
2611 * if we determine it is beneficial to do so */
2612 ctx->uniform_cutoff = 8;
2613
2614 /* Initialize at a global (not block) level hash tables */
2615
2616 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2617 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2618
2619 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2620 * (so we don't accidentally duplicate the epilogue since mesa/st has
2621 * messed with our I/O quite a bit already) */
2622
2623 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2624
2625 if (ctx->stage == MESA_SHADER_VERTEX) {
2626 NIR_PASS_V(nir, nir_lower_viewport_transform);
2627 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2628 }
2629
2630 NIR_PASS_V(nir, nir_lower_var_copies);
2631 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2632 NIR_PASS_V(nir, nir_split_var_copies);
2633 NIR_PASS_V(nir, nir_lower_var_copies);
2634 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2635 NIR_PASS_V(nir, nir_lower_var_copies);
2636 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2637
2638 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2639 NIR_PASS_V(nir, nir_lower_ssbo);
2640 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2641
2642 /* Optimisation passes */
2643
2644 optimise_nir(nir, ctx->quirks, is_blend);
2645
2646 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2647 nir_print_shader(nir, stdout);
2648 }
2649
2650 /* Assign sysvals and counts, now that we're sure
2651 * (post-optimisation) */
2652
2653 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2654 program->sysval_count = ctx->sysvals.sysval_count;
2655 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2656
2657 nir_foreach_function(func, nir) {
2658 if (!func->impl)
2659 continue;
2660
2661 list_inithead(&ctx->blocks);
2662 ctx->block_count = 0;
2663 ctx->func = func;
2664 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2665
2666 emit_cf_list(ctx, &func->impl->body);
2667 free(ctx->already_emitted);
2668 break; /* TODO: Multi-function shaders */
2669 }
2670
2671 util_dynarray_init(compiled, NULL);
2672
2673 /* Per-block lowering before opts */
2674
2675 mir_foreach_block(ctx, _block) {
2676 midgard_block *block = (midgard_block *) _block;
2677 inline_alu_constants(ctx, block);
2678 embedded_to_inline_constant(ctx, block);
2679 }
2680 /* MIR-level optimizations */
2681
2682 bool progress = false;
2683
2684 do {
2685 progress = false;
2686 progress |= midgard_opt_dead_code_eliminate(ctx);
2687
2688 mir_foreach_block(ctx, _block) {
2689 midgard_block *block = (midgard_block *) _block;
2690 progress |= midgard_opt_copy_prop(ctx, block);
2691 progress |= midgard_opt_combine_projection(ctx, block);
2692 progress |= midgard_opt_varying_projection(ctx, block);
2693 }
2694 } while (progress);
2695
2696 mir_foreach_block(ctx, _block) {
2697 midgard_block *block = (midgard_block *) _block;
2698 midgard_lower_derivatives(ctx, block);
2699 midgard_legalize_invert(ctx, block);
2700 midgard_cull_dead_branch(ctx, block);
2701 }
2702
2703 if (ctx->stage == MESA_SHADER_FRAGMENT)
2704 mir_add_writeout_loops(ctx);
2705
2706 /* Analyze now that the code is known but before scheduling creates
2707 * pipeline registers which are harder to track */
2708 mir_analyze_helper_terminate(ctx);
2709 mir_analyze_helper_requirements(ctx);
2710
2711 /* Schedule! */
2712 midgard_schedule_program(ctx);
2713 mir_ra(ctx);
2714
2715 /* Now that all the bundles are scheduled and we can calculate block
2716 * sizes, emit actual branch instructions rather than placeholders */
2717
2718 int br_block_idx = 0;
2719
2720 mir_foreach_block(ctx, _block) {
2721 midgard_block *block = (midgard_block *) _block;
2722 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2723 for (int c = 0; c < bundle->instruction_count; ++c) {
2724 midgard_instruction *ins = bundle->instructions[c];
2725
2726 if (!midgard_is_branch_unit(ins->unit)) continue;
2727
2728 /* Parse some basic branch info */
2729 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2730 bool is_conditional = ins->branch.conditional;
2731 bool is_inverted = ins->branch.invert_conditional;
2732 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2733 bool is_writeout = ins->writeout;
2734
2735 /* Determine the block we're jumping to */
2736 int target_number = ins->branch.target_block;
2737
2738 /* Report the destination tag */
2739 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2740
2741 /* Count up the number of quadwords we're
2742 * jumping over = number of quadwords until
2743 * (br_block_idx, target_number) */
2744
2745 int quadword_offset = 0;
2746
2747 if (is_discard) {
2748 /* Ignored */
2749 } else if (target_number > br_block_idx) {
2750 /* Jump forward */
2751
2752 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2753 midgard_block *blk = mir_get_block(ctx, idx);
2754 assert(blk);
2755
2756 quadword_offset += blk->quadword_count;
2757 }
2758 } else {
2759 /* Jump backwards */
2760
2761 for (int idx = br_block_idx; idx >= target_number; --idx) {
2762 midgard_block *blk = mir_get_block(ctx, idx);
2763 assert(blk);
2764
2765 quadword_offset -= blk->quadword_count;
2766 }
2767 }
2768
2769 /* Unconditional extended branches (far jumps)
2770 * have issues, so we always use a conditional
2771 * branch, setting the condition to always for
2772 * unconditional. For compact unconditional
2773 * branches, cond isn't used so it doesn't
2774 * matter what we pick. */
2775
2776 midgard_condition cond =
2777 !is_conditional ? midgard_condition_always :
2778 is_inverted ? midgard_condition_false :
2779 midgard_condition_true;
2780
2781 midgard_jmp_writeout_op op =
2782 is_discard ? midgard_jmp_writeout_op_discard :
2783 is_writeout ? midgard_jmp_writeout_op_writeout :
2784 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2785 midgard_jmp_writeout_op_branch_cond;
2786
2787 if (!is_compact) {
2788 midgard_branch_extended branch =
2789 midgard_create_branch_extended(
2790 cond, op,
2791 dest_tag,
2792 quadword_offset);
2793
2794 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2795 } else if (is_conditional || is_discard) {
2796 midgard_branch_cond branch = {
2797 .op = op,
2798 .dest_tag = dest_tag,
2799 .offset = quadword_offset,
2800 .cond = cond
2801 };
2802
2803 assert(branch.offset == quadword_offset);
2804
2805 memcpy(&ins->br_compact, &branch, sizeof(branch));
2806 } else {
2807 assert(op == midgard_jmp_writeout_op_branch_uncond);
2808
2809 midgard_branch_uncond branch = {
2810 .op = op,
2811 .dest_tag = dest_tag,
2812 .offset = quadword_offset,
2813 .unknown = 1
2814 };
2815
2816 assert(branch.offset == quadword_offset);
2817
2818 memcpy(&ins->br_compact, &branch, sizeof(branch));
2819 }
2820 }
2821 }
2822
2823 ++br_block_idx;
2824 }
2825
2826 /* Emit flat binary from the instruction arrays. Iterate each block in
2827 * sequence. Save instruction boundaries such that lookahead tags can
2828 * be assigned easily */
2829
2830 /* Cache _all_ bundles in source order for lookahead across failed branches */
2831
2832 int bundle_count = 0;
2833 mir_foreach_block(ctx, _block) {
2834 midgard_block *block = (midgard_block *) _block;
2835 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2836 }
2837 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2838 int bundle_idx = 0;
2839 mir_foreach_block(ctx, _block) {
2840 midgard_block *block = (midgard_block *) _block;
2841 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2842 source_order_bundles[bundle_idx++] = bundle;
2843 }
2844 }
2845
2846 int current_bundle = 0;
2847
2848 /* Midgard prefetches instruction types, so during emission we
2849 * need to lookahead. Unless this is the last instruction, in
2850 * which we return 1. */
2851
2852 mir_foreach_block(ctx, _block) {
2853 midgard_block *block = (midgard_block *) _block;
2854 mir_foreach_bundle_in_block(block, bundle) {
2855 int lookahead = 1;
2856
2857 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2858 lookahead = source_order_bundles[current_bundle + 1]->tag;
2859
2860 emit_binary_bundle(ctx, block, bundle, compiled, lookahead);
2861 ++current_bundle;
2862 }
2863
2864 /* TODO: Free deeper */
2865 //util_dynarray_fini(&block->instructions);
2866 }
2867
2868 free(source_order_bundles);
2869
2870 /* Report the very first tag executed */
2871 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2872
2873 /* Deal with off-by-one related to the fencepost problem */
2874 program->work_register_count = ctx->work_registers + 1;
2875 program->uniform_cutoff = ctx->uniform_cutoff;
2876
2877 program->blend_patch_offset = ctx->blend_constant_offset;
2878 program->tls_size = ctx->tls_size;
2879
2880 if (midgard_debug & MIDGARD_DBG_SHADERS)
2881 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2882
2883 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2884 unsigned nr_bundles = 0, nr_ins = 0;
2885
2886 /* Count instructions and bundles */
2887
2888 mir_foreach_block(ctx, _block) {
2889 midgard_block *block = (midgard_block *) _block;
2890 nr_bundles += util_dynarray_num_elements(
2891 &block->bundles, midgard_bundle);
2892
2893 mir_foreach_bundle_in_block(block, bun)
2894 nr_ins += bun->instruction_count;
2895 }
2896
2897 /* Calculate thread count. There are certain cutoffs by
2898 * register count for thread count */
2899
2900 unsigned nr_registers = program->work_register_count;
2901
2902 unsigned nr_threads =
2903 (nr_registers <= 4) ? 4 :
2904 (nr_registers <= 8) ? 2 :
2905 1;
2906
2907 /* Dump stats */
2908
2909 fprintf(stderr, "shader%d - %s shader: "
2910 "%u inst, %u bundles, %u quadwords, "
2911 "%u registers, %u threads, %u loops, "
2912 "%u:%u spills:fills\n",
2913 SHADER_DB_COUNT++,
2914 ctx->is_blend ? "PAN_SHADER_BLEND" :
2915 gl_shader_stage_name(ctx->stage),
2916 nr_ins, nr_bundles, ctx->quadword_count,
2917 nr_registers, nr_threads,
2918 ctx->loop_count,
2919 ctx->spills, ctx->fills);
2920 }
2921
2922 ralloc_free(ctx);
2923
2924 return 0;
2925 }