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pan/mdg: Handle regular nir_intrinsic_load_output
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 M_LOAD(ld_attr_32, nir_type_uint32);
132 M_LOAD(ld_vary_32, nir_type_uint32);
133 M_LOAD(ld_ubo_int4, nir_type_uint32);
134 M_LOAD(ld_int4, nir_type_uint32);
135 M_STORE(st_int4, nir_type_uint32);
136 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
137 M_LOAD(ld_color_buffer_as_fp16, nir_type_float16);
138 M_STORE(st_vary_32, nir_type_uint32);
139 M_LOAD(ld_cubemap_coords, nir_type_uint32);
140 M_LOAD(ld_compute_id, nir_type_uint32);
141
142 static midgard_instruction
143 v_branch(bool conditional, bool invert)
144 {
145 midgard_instruction ins = {
146 .type = TAG_ALU_4,
147 .unit = ALU_ENAB_BRANCH,
148 .compact_branch = true,
149 .branch = {
150 .conditional = conditional,
151 .invert_conditional = invert
152 },
153 .dest = ~0,
154 .src = { ~0, ~0, ~0, ~0 },
155 };
156
157 return ins;
158 }
159
160 static midgard_branch_extended
161 midgard_create_branch_extended( midgard_condition cond,
162 midgard_jmp_writeout_op op,
163 unsigned dest_tag,
164 signed quadword_offset)
165 {
166 /* The condition code is actually a LUT describing a function to
167 * combine multiple condition codes. However, we only support a single
168 * condition code at the moment, so we just duplicate over a bunch of
169 * times. */
170
171 uint16_t duplicated_cond =
172 (cond << 14) |
173 (cond << 12) |
174 (cond << 10) |
175 (cond << 8) |
176 (cond << 6) |
177 (cond << 4) |
178 (cond << 2) |
179 (cond << 0);
180
181 midgard_branch_extended branch = {
182 .op = op,
183 .dest_tag = dest_tag,
184 .offset = quadword_offset,
185 .cond = duplicated_cond
186 };
187
188 return branch;
189 }
190
191 static void
192 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
193 {
194 ins->has_constants = true;
195 memcpy(&ins->constants, constants, 16);
196 }
197
198 static int
199 glsl_type_size(const struct glsl_type *type, bool bindless)
200 {
201 return glsl_count_attribute_slots(type, false);
202 }
203
204 /* Lower fdot2 to a vector multiplication followed by channel addition */
205 static void
206 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
207 {
208 if (alu->op != nir_op_fdot2)
209 return;
210
211 b->cursor = nir_before_instr(&alu->instr);
212
213 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
214 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
215
216 nir_ssa_def *product = nir_fmul(b, src0, src1);
217
218 nir_ssa_def *sum = nir_fadd(b,
219 nir_channel(b, product, 0),
220 nir_channel(b, product, 1));
221
222 /* Replace the fdot2 with this sum */
223 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
224 }
225
226 static bool
227 midgard_nir_lower_fdot2(nir_shader *shader)
228 {
229 bool progress = false;
230
231 nir_foreach_function(function, shader) {
232 if (!function->impl) continue;
233
234 nir_builder _b;
235 nir_builder *b = &_b;
236 nir_builder_init(b, function->impl);
237
238 nir_foreach_block(block, function->impl) {
239 nir_foreach_instr_safe(instr, block) {
240 if (instr->type != nir_instr_type_alu) continue;
241
242 nir_alu_instr *alu = nir_instr_as_alu(instr);
243 midgard_nir_lower_fdot2_body(b, alu);
244
245 progress |= true;
246 }
247 }
248
249 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
250
251 }
252
253 return progress;
254 }
255
256 /* Midgard can't write depth and stencil separately. It has to happen in a
257 * single store operation containing both. Let's add a panfrost specific
258 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
259 * one.
260 */
261 static bool
262 midgard_nir_lower_zs_store(nir_shader *nir)
263 {
264 if (nir->info.stage != MESA_SHADER_FRAGMENT)
265 return false;
266
267 nir_variable *z_var = NULL, *s_var = NULL;
268
269 nir_foreach_variable(var, &nir->outputs) {
270 if (var->data.location == FRAG_RESULT_DEPTH)
271 z_var = var;
272 else if (var->data.location == FRAG_RESULT_STENCIL)
273 s_var = var;
274 }
275
276 if (!z_var && !s_var)
277 return false;
278
279 bool progress = false;
280
281 nir_foreach_function(function, nir) {
282 if (!function->impl) continue;
283
284 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
285
286 nir_foreach_block(block, function->impl) {
287 nir_foreach_instr_safe(instr, block) {
288 if (instr->type != nir_instr_type_intrinsic)
289 continue;
290
291 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
292 if (intr->intrinsic != nir_intrinsic_store_output)
293 continue;
294
295 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
296 assert(!z_store);
297 z_store = intr;
298 last_store = intr;
299 }
300
301 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
302 assert(!s_store);
303 s_store = intr;
304 last_store = intr;
305 }
306 }
307 }
308
309 if (!z_store && !s_store) continue;
310
311 nir_builder b;
312 nir_builder_init(&b, function->impl);
313
314 b.cursor = nir_before_instr(&last_store->instr);
315
316 nir_ssa_def *zs_store_src;
317
318 if (z_store && s_store) {
319 nir_ssa_def *srcs[2] = {
320 nir_ssa_for_src(&b, z_store->src[0], 1),
321 nir_ssa_for_src(&b, s_store->src[0], 1),
322 };
323
324 zs_store_src = nir_vec(&b, srcs, 2);
325 } else {
326 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
327 }
328
329 nir_intrinsic_instr *zs_store;
330
331 zs_store = nir_intrinsic_instr_create(b.shader,
332 nir_intrinsic_store_zs_output_pan);
333 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
334 zs_store->num_components = z_store && s_store ? 2 : 1;
335 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
336
337 /* Replace the Z and S store by a ZS store */
338 nir_builder_instr_insert(&b, &zs_store->instr);
339
340 if (z_store)
341 nir_instr_remove(&z_store->instr);
342
343 if (s_store)
344 nir_instr_remove(&s_store->instr);
345
346 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
347 progress = true;
348 }
349
350 return progress;
351 }
352
353 /* Flushes undefined values to zero */
354
355 static void
356 optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
357 {
358 bool progress;
359 unsigned lower_flrp =
360 (nir->options->lower_flrp16 ? 16 : 0) |
361 (nir->options->lower_flrp32 ? 32 : 0) |
362 (nir->options->lower_flrp64 ? 64 : 0);
363
364 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
365 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
366
367 nir_lower_tex_options lower_tex_options = {
368 .lower_txs_lod = true,
369 .lower_txp = ~0,
370 .lower_tex_without_implicit_lod =
371 (quirks & MIDGARD_EXPLICIT_LOD),
372
373 /* TODO: we have native gradient.. */
374 .lower_txd = true,
375 };
376
377 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
378
379 /* Must lower fdot2 after tex is lowered */
380 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
381
382 /* T720 is broken. */
383
384 if (quirks & MIDGARD_BROKEN_LOD)
385 NIR_PASS_V(nir, midgard_nir_lod_errata);
386
387 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_early);
388
389 if (!is_blend)
390 NIR_PASS(progress, nir, nir_fuse_io_16);
391
392 do {
393 progress = false;
394
395 NIR_PASS(progress, nir, nir_lower_var_copies);
396 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
397
398 NIR_PASS(progress, nir, nir_copy_prop);
399 NIR_PASS(progress, nir, nir_opt_remove_phis);
400 NIR_PASS(progress, nir, nir_opt_dce);
401 NIR_PASS(progress, nir, nir_opt_dead_cf);
402 NIR_PASS(progress, nir, nir_opt_cse);
403 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
404 NIR_PASS(progress, nir, nir_opt_algebraic);
405 NIR_PASS(progress, nir, nir_opt_constant_folding);
406
407 if (lower_flrp != 0) {
408 bool lower_flrp_progress = false;
409 NIR_PASS(lower_flrp_progress,
410 nir,
411 nir_lower_flrp,
412 lower_flrp,
413 false /* always_precise */,
414 nir->options->lower_ffma);
415 if (lower_flrp_progress) {
416 NIR_PASS(progress, nir,
417 nir_opt_constant_folding);
418 progress = true;
419 }
420
421 /* Nothing should rematerialize any flrps, so we only
422 * need to do this lowering once.
423 */
424 lower_flrp = 0;
425 }
426
427 NIR_PASS(progress, nir, nir_opt_undef);
428 NIR_PASS(progress, nir, nir_undef_to_zero);
429
430 NIR_PASS(progress, nir, nir_opt_loop_unroll,
431 nir_var_shader_in |
432 nir_var_shader_out |
433 nir_var_function_temp);
434
435 NIR_PASS(progress, nir, nir_opt_vectorize);
436 } while (progress);
437
438 /* Must be run at the end to prevent creation of fsin/fcos ops */
439 NIR_PASS(progress, nir, midgard_nir_scale_trig);
440
441 do {
442 progress = false;
443
444 NIR_PASS(progress, nir, nir_opt_dce);
445 NIR_PASS(progress, nir, nir_opt_algebraic);
446 NIR_PASS(progress, nir, nir_opt_constant_folding);
447 NIR_PASS(progress, nir, nir_copy_prop);
448 } while (progress);
449
450 NIR_PASS(progress, nir, nir_opt_algebraic_late);
451 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
452
453 /* We implement booleans as 32-bit 0/~0 */
454 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
455
456 /* Now that booleans are lowered, we can run out late opts */
457 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
458 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
459
460 NIR_PASS(progress, nir, nir_copy_prop);
461 NIR_PASS(progress, nir, nir_opt_dce);
462
463 /* Take us out of SSA */
464 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
465 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
466
467 /* We are a vector architecture; write combine where possible */
468 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
469 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
470
471 NIR_PASS(progress, nir, nir_opt_dce);
472 }
473
474 /* Do not actually emit a load; instead, cache the constant for inlining */
475
476 static void
477 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
478 {
479 nir_ssa_def def = instr->def;
480
481 midgard_constants *consts = rzalloc(NULL, midgard_constants);
482
483 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
484
485 #define RAW_CONST_COPY(bits) \
486 nir_const_value_to_array(consts->u##bits, instr->value, \
487 instr->def.num_components, u##bits)
488
489 switch (instr->def.bit_size) {
490 case 64:
491 RAW_CONST_COPY(64);
492 break;
493 case 32:
494 RAW_CONST_COPY(32);
495 break;
496 case 16:
497 RAW_CONST_COPY(16);
498 break;
499 case 8:
500 RAW_CONST_COPY(8);
501 break;
502 default:
503 unreachable("Invalid bit_size for load_const instruction\n");
504 }
505
506 /* Shifted for SSA, +1 for off-by-one */
507 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
508 }
509
510 /* Normally constants are embedded implicitly, but for I/O and such we have to
511 * explicitly emit a move with the constant source */
512
513 static void
514 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
515 {
516 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
517
518 if (constant_value) {
519 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
520 attach_constants(ctx, &ins, constant_value, node + 1);
521 emit_mir_instruction(ctx, ins);
522 }
523 }
524
525 static bool
526 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
527 {
528 unsigned comp = src->swizzle[0];
529
530 for (unsigned c = 1; c < nr_components; ++c) {
531 if (src->swizzle[c] != comp)
532 return true;
533 }
534
535 return false;
536 }
537
538 #define ALU_CASE(nir, _op) \
539 case nir_op_##nir: \
540 op = midgard_alu_op_##_op; \
541 assert(src_bitsize == dst_bitsize); \
542 break;
543
544 #define ALU_CASE_RTZ(nir, _op) \
545 case nir_op_##nir: \
546 op = midgard_alu_op_##_op; \
547 roundmode = MIDGARD_RTZ; \
548 break;
549
550 #define ALU_CHECK_CMP(sext) \
551 assert(src_bitsize == 16 || src_bitsize == 32); \
552 assert(dst_bitsize == 16 || dst_bitsize == 32); \
553
554 #define ALU_CASE_BCAST(nir, _op, count) \
555 case nir_op_##nir: \
556 op = midgard_alu_op_##_op; \
557 broadcast_swizzle = count; \
558 ALU_CHECK_CMP(true); \
559 break;
560
561 #define ALU_CASE_CMP(nir, _op, sext) \
562 case nir_op_##nir: \
563 op = midgard_alu_op_##_op; \
564 ALU_CHECK_CMP(sext); \
565 break;
566
567 /* Analyze the sizes of the dest and inputs to determine reg mode. */
568
569 static midgard_reg_mode
570 reg_mode_for_nir(nir_alu_instr *instr)
571 {
572 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
573 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
574 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
575
576 /* We don't have fp16 LUTs, so we'll want to emit code like:
577 *
578 * vlut.fsinr hr0, hr0
579 *
580 * where both input and output are 16-bit but the operation is carried
581 * out in 32-bit
582 */
583
584 switch (instr->op) {
585 case nir_op_fsqrt:
586 case nir_op_frcp:
587 case nir_op_frsq:
588 case nir_op_fsin:
589 case nir_op_fcos:
590 case nir_op_fexp2:
591 case nir_op_flog2:
592 max_bitsize = MAX2(max_bitsize, 32);
593 break;
594
595 /* These get lowered to moves */
596 case nir_op_pack_32_4x8:
597 max_bitsize = 8;
598 break;
599 case nir_op_pack_32_2x16:
600 max_bitsize = 16;
601 break;
602 default:
603 break;
604 }
605
606
607 switch (max_bitsize) {
608 /* Use 16 pipe for 8 since we don't support vec16 yet */
609 case 8:
610 case 16:
611 return midgard_reg_mode_16;
612 case 32:
613 return midgard_reg_mode_32;
614 case 64:
615 return midgard_reg_mode_64;
616 default:
617 unreachable("Invalid bit size");
618 }
619 }
620
621 /* Compare mir_lower_invert */
622 static bool
623 nir_accepts_inot(nir_op op, unsigned src)
624 {
625 switch (op) {
626 case nir_op_ior:
627 case nir_op_iand: /* TODO: b2f16 */
628 case nir_op_ixor:
629 return true;
630 case nir_op_b32csel:
631 /* Only the condition */
632 return (src == 0);
633 default:
634 return false;
635 }
636 }
637
638 static bool
639 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
640 {
641 if (pan_has_dest_mod(dest, op)) {
642 assert((*dest)->is_ssa);
643 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
644 return true;
645 }
646
647 return false;
648 }
649
650 static void
651 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, enum midgard_roundmode *roundmode, bool is_int, unsigned bcast_count)
652 {
653 nir_alu_src src = instr->src[i];
654
655 if (!is_int) {
656 if (pan_has_source_mod(&src, nir_op_fneg))
657 *neg = !(*neg);
658
659 if (pan_has_source_mod(&src, nir_op_fabs))
660 *abs = true;
661 }
662
663 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
664 *not = true;
665
666 if (roundmode) {
667 if (pan_has_source_mod(&src, nir_op_fround_even))
668 *roundmode = MIDGARD_RTE;
669
670 if (pan_has_source_mod(&src, nir_op_ftrunc))
671 *roundmode = MIDGARD_RTZ;
672
673 if (pan_has_source_mod(&src, nir_op_ffloor))
674 *roundmode = MIDGARD_RTN;
675
676 if (pan_has_source_mod(&src, nir_op_fceil))
677 *roundmode = MIDGARD_RTP;
678 }
679
680 unsigned bits = nir_src_bit_size(src.src);
681
682 ins->src[to] = nir_src_index(NULL, &src.src);
683 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
684
685 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
686 ins->swizzle[to][c] = src.swizzle[
687 (!bcast_count || c < bcast_count) ? c :
688 (bcast_count - 1)];
689 }
690 }
691
692 /* Midgard features both fcsel and icsel, depending on whether you want int or
693 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
694 * we should emit an int or float csel depending on what modifiers could be
695 * placed. In the absense of modifiers, this is probably arbitrary. */
696
697 static bool
698 mir_is_bcsel_float(nir_alu_instr *instr)
699 {
700 nir_op intmods[] = {
701 nir_op_i2i8, nir_op_i2i16,
702 nir_op_i2i32, nir_op_i2i64
703 };
704
705 nir_op floatmods[] = {
706 nir_op_fabs, nir_op_fneg,
707 nir_op_f2f16, nir_op_f2f32,
708 nir_op_f2f64
709 };
710
711 nir_op floatdestmods[] = {
712 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
713 nir_op_f2f16, nir_op_f2f32
714 };
715
716 signed score = 0;
717
718 for (unsigned i = 1; i < 3; ++i) {
719 nir_alu_src s = instr->src[i];
720 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
721 if (pan_has_source_mod(&s, intmods[q]))
722 score--;
723 }
724 }
725
726 for (unsigned i = 1; i < 3; ++i) {
727 nir_alu_src s = instr->src[i];
728 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
729 if (pan_has_source_mod(&s, floatmods[q]))
730 score++;
731 }
732 }
733
734 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
735 nir_dest *dest = &instr->dest.dest;
736 if (pan_has_dest_mod(&dest, floatdestmods[q]))
737 score++;
738 }
739
740 return (score > 0);
741 }
742
743 static void
744 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
745 {
746 nir_dest *dest = &instr->dest.dest;
747
748 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
749 return;
750
751 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
752 * is handled elsewhere */
753
754 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
755 midgard_emit_derivatives(ctx, instr);
756 return;
757 }
758
759 bool is_ssa = dest->is_ssa;
760
761 unsigned nr_components = nir_dest_num_components(*dest);
762 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
763 unsigned op = 0;
764
765 /* Number of components valid to check for the instruction (the rest
766 * will be forced to the last), or 0 to use as-is. Relevant as
767 * ball-type instructions have a channel count in NIR but are all vec4
768 * in Midgard */
769
770 unsigned broadcast_swizzle = 0;
771
772 /* What register mode should we operate in? */
773 midgard_reg_mode reg_mode =
774 reg_mode_for_nir(instr);
775
776 /* Should we swap arguments? */
777 bool flip_src12 = false;
778
779 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
780 unsigned dst_bitsize = nir_dest_bit_size(*dest);
781
782 enum midgard_roundmode roundmode = MIDGARD_RTE;
783
784 switch (instr->op) {
785 ALU_CASE(fadd, fadd);
786 ALU_CASE(fmul, fmul);
787 ALU_CASE(fmin, fmin);
788 ALU_CASE(fmax, fmax);
789 ALU_CASE(imin, imin);
790 ALU_CASE(imax, imax);
791 ALU_CASE(umin, umin);
792 ALU_CASE(umax, umax);
793 ALU_CASE(ffloor, ffloor);
794 ALU_CASE(fround_even, froundeven);
795 ALU_CASE(ftrunc, ftrunc);
796 ALU_CASE(fceil, fceil);
797 ALU_CASE(fdot3, fdot3);
798 ALU_CASE(fdot4, fdot4);
799 ALU_CASE(iadd, iadd);
800 ALU_CASE(isub, isub);
801 ALU_CASE(imul, imul);
802
803 /* Zero shoved as second-arg */
804 ALU_CASE(iabs, iabsdiff);
805
806 ALU_CASE(mov, imov);
807
808 ALU_CASE_CMP(feq32, feq, false);
809 ALU_CASE_CMP(fne32, fne, false);
810 ALU_CASE_CMP(flt32, flt, false);
811 ALU_CASE_CMP(ieq32, ieq, true);
812 ALU_CASE_CMP(ine32, ine, true);
813 ALU_CASE_CMP(ilt32, ilt, true);
814 ALU_CASE_CMP(ult32, ult, false);
815
816 /* We don't have a native b2f32 instruction. Instead, like many
817 * GPUs, we exploit booleans as 0/~0 for false/true, and
818 * correspondingly AND
819 * by 1.0 to do the type conversion. For the moment, prime us
820 * to emit:
821 *
822 * iand [whatever], #0
823 *
824 * At the end of emit_alu (as MIR), we'll fix-up the constant
825 */
826
827 ALU_CASE_CMP(b2f32, iand, true);
828 ALU_CASE_CMP(b2f16, iand, true);
829 ALU_CASE_CMP(b2i32, iand, true);
830
831 /* Likewise, we don't have a dedicated f2b32 instruction, but
832 * we can do a "not equal to 0.0" test. */
833
834 ALU_CASE_CMP(f2b32, fne, false);
835 ALU_CASE_CMP(i2b32, ine, true);
836
837 ALU_CASE(frcp, frcp);
838 ALU_CASE(frsq, frsqrt);
839 ALU_CASE(fsqrt, fsqrt);
840 ALU_CASE(fexp2, fexp2);
841 ALU_CASE(flog2, flog2);
842
843 ALU_CASE_RTZ(f2i64, f2i_rte);
844 ALU_CASE_RTZ(f2u64, f2u_rte);
845 ALU_CASE_RTZ(i2f64, i2f_rte);
846 ALU_CASE_RTZ(u2f64, u2f_rte);
847
848 ALU_CASE_RTZ(f2i32, f2i_rte);
849 ALU_CASE_RTZ(f2u32, f2u_rte);
850 ALU_CASE_RTZ(i2f32, i2f_rte);
851 ALU_CASE_RTZ(u2f32, u2f_rte);
852
853 ALU_CASE_RTZ(f2i8, f2i_rte);
854 ALU_CASE_RTZ(f2u8, f2u_rte);
855
856 ALU_CASE_RTZ(f2i16, f2i_rte);
857 ALU_CASE_RTZ(f2u16, f2u_rte);
858 ALU_CASE_RTZ(i2f16, i2f_rte);
859 ALU_CASE_RTZ(u2f16, u2f_rte);
860
861 ALU_CASE(fsin, fsin);
862 ALU_CASE(fcos, fcos);
863
864 /* We'll get 0 in the second arg, so:
865 * ~a = ~(a | 0) = nor(a, 0) */
866 ALU_CASE(inot, inor);
867 ALU_CASE(iand, iand);
868 ALU_CASE(ior, ior);
869 ALU_CASE(ixor, ixor);
870 ALU_CASE(ishl, ishl);
871 ALU_CASE(ishr, iasr);
872 ALU_CASE(ushr, ilsr);
873
874 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
875 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
876 ALU_CASE_CMP(b32all_fequal4, fball_eq, true);
877
878 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
879 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
880 ALU_CASE_CMP(b32any_fnequal4, fbany_neq, true);
881
882 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
883 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
884 ALU_CASE_CMP(b32all_iequal4, iball_eq, true);
885
886 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
887 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
888 ALU_CASE_CMP(b32any_inequal4, ibany_neq, true);
889
890 /* Source mods will be shoved in later */
891 ALU_CASE(fabs, fmov);
892 ALU_CASE(fneg, fmov);
893 ALU_CASE(fsat, fmov);
894 ALU_CASE(fsat_signed, fmov);
895 ALU_CASE(fclamp_pos, fmov);
896
897 /* For size conversion, we use a move. Ideally though we would squash
898 * these ops together; maybe that has to happen after in NIR as part of
899 * propagation...? An earlier algebraic pass ensured we step down by
900 * only / exactly one size. If stepping down, we use a dest override to
901 * reduce the size; if stepping up, we use a larger-sized move with a
902 * half source and a sign/zero-extension modifier */
903
904 case nir_op_i2i8:
905 case nir_op_i2i16:
906 case nir_op_i2i32:
907 case nir_op_i2i64:
908 case nir_op_u2u8:
909 case nir_op_u2u16:
910 case nir_op_u2u32:
911 case nir_op_u2u64:
912 case nir_op_f2f16:
913 case nir_op_f2f32:
914 case nir_op_f2f64: {
915 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
916 instr->op == nir_op_f2f64)
917 op = midgard_alu_op_fmov;
918 else
919 op = midgard_alu_op_imov;
920
921 break;
922 }
923
924 /* For greater-or-equal, we lower to less-or-equal and flip the
925 * arguments */
926
927 case nir_op_fge:
928 case nir_op_fge32:
929 case nir_op_ige32:
930 case nir_op_uge32: {
931 op =
932 instr->op == nir_op_fge ? midgard_alu_op_fle :
933 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
934 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
935 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
936 0;
937
938 flip_src12 = true;
939 ALU_CHECK_CMP(false);
940 break;
941 }
942
943 case nir_op_b32csel: {
944 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
945 bool is_float = mir_is_bcsel_float(instr);
946 op = is_float ?
947 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
948 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
949
950 break;
951 }
952
953 case nir_op_unpack_32_2x16:
954 case nir_op_unpack_32_4x8:
955 case nir_op_pack_32_2x16:
956 case nir_op_pack_32_4x8: {
957 op = midgard_alu_op_imov;
958 break;
959 }
960
961 default:
962 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
963 assert(0);
964 return;
965 }
966
967 /* Promote imov to fmov if it might help inline a constant */
968 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
969 && nir_src_bit_size(instr->src[0].src) == 32
970 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
971 nir_src_num_components(instr->src[0].src))) {
972 op = midgard_alu_op_fmov;
973 }
974
975 /* Midgard can perform certain modifiers on output of an ALU op */
976
977 unsigned outmod = 0;
978 bool is_int = midgard_is_integer_op(op);
979
980 if (midgard_is_integer_out_op(op)) {
981 outmod = midgard_outmod_int_wrap;
982 } else if (instr->op == nir_op_fsat) {
983 outmod = midgard_outmod_sat;
984 } else if (instr->op == nir_op_fsat_signed) {
985 outmod = midgard_outmod_sat_signed;
986 } else if (instr->op == nir_op_fclamp_pos) {
987 outmod = midgard_outmod_pos;
988 }
989
990 /* Fetch unit, quirks, etc information */
991 unsigned opcode_props = alu_opcode_props[op].props;
992 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
993
994 /* Look for floating point mods. We have the mods fsat, fsat_signed,
995 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
996 *
997 * fsat_signed(fpos(x)) = fsat(x)
998 * fsat_signed(fsat(x)) = fsat(x)
999 * fpos(fsat_signed(x)) = fsat(x)
1000 * fpos(fsat(x)) = fsat(x)
1001 * fsat(fsat_signed(x)) = fsat(x)
1002 * fsat(fpos(x)) = fsat(x)
1003 *
1004 * So by cases any composition of output modifiers is equivalent to
1005 * fsat alone.
1006 */
1007
1008 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
1009 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
1010 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
1011 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
1012 bool prior = (outmod != midgard_outmod_none);
1013 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
1014
1015 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
1016 fpos ? midgard_outmod_pos :
1017 ssat ? midgard_outmod_sat_signed :
1018 outmod;
1019 }
1020
1021 midgard_instruction ins = {
1022 .type = TAG_ALU_4,
1023 .dest = nir_dest_index(dest),
1024 .dest_type = nir_op_infos[instr->op].output_type
1025 | nir_dest_bit_size(*dest),
1026 .roundmode = roundmode,
1027 };
1028
1029 enum midgard_roundmode *roundptr = (opcode_props & MIDGARD_ROUNDS) ?
1030 &ins.roundmode : NULL;
1031
1032 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
1033 ins.src[i] = ~0;
1034
1035 if (quirk_flipped_r24) {
1036 ins.src[0] = ~0;
1037 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], roundptr, is_int, broadcast_swizzle);
1038 } else {
1039 for (unsigned i = 0; i < nr_inputs; ++i) {
1040 unsigned to = i;
1041
1042 if (instr->op == nir_op_b32csel) {
1043 /* The condition is the first argument; move
1044 * the other arguments up one to be a binary
1045 * instruction for Midgard with the condition
1046 * last */
1047
1048 if (i == 0)
1049 to = 2;
1050 else if (flip_src12)
1051 to = 2 - i;
1052 else
1053 to = i - 1;
1054 } else if (flip_src12) {
1055 to = 1 - to;
1056 }
1057
1058 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], roundptr, is_int, broadcast_swizzle);
1059
1060 /* (!c) ? a : b = c ? b : a */
1061 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1062 ins.src_invert[2] = false;
1063 flip_src12 ^= true;
1064 }
1065 }
1066 }
1067
1068 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1069 /* Lowered to move */
1070 if (instr->op == nir_op_fneg)
1071 ins.src_neg[1] ^= true;
1072
1073 if (instr->op == nir_op_fabs)
1074 ins.src_abs[1] = true;
1075 }
1076
1077 ins.mask = mask_of(nr_components);
1078
1079 midgard_vector_alu alu = {
1080 .op = op,
1081 .reg_mode = reg_mode,
1082 .outmod = outmod,
1083 };
1084
1085 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1086 * components that don't exist. Note modifier => SSA => !reg => no
1087 * writemask, so we don't have to worry about writemasks here.*/
1088
1089 if (!is_ssa)
1090 ins.mask &= instr->dest.write_mask;
1091
1092 ins.alu = alu;
1093
1094 /* Late fixup for emulated instructions */
1095
1096 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1097 /* Presently, our second argument is an inline #0 constant.
1098 * Switch over to an embedded 1.0 constant (that can't fit
1099 * inline, since we're 32-bit, not 16-bit like the inline
1100 * constants) */
1101
1102 ins.has_inline_constant = false;
1103 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1104 ins.src_types[1] = nir_type_float32;
1105 ins.has_constants = true;
1106
1107 if (instr->op == nir_op_b2f32)
1108 ins.constants.f32[0] = 1.0f;
1109 else
1110 ins.constants.i32[0] = 1;
1111
1112 for (unsigned c = 0; c < 16; ++c)
1113 ins.swizzle[1][c] = 0;
1114 } else if (instr->op == nir_op_b2f16) {
1115 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1116 ins.src_types[1] = nir_type_float16;
1117 ins.has_constants = true;
1118 ins.constants.i16[0] = _mesa_float_to_half(1.0);
1119
1120 for (unsigned c = 0; c < 16; ++c)
1121 ins.swizzle[1][c] = 0;
1122 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1123 /* Lots of instructions need a 0 plonked in */
1124 ins.has_inline_constant = false;
1125 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1126 ins.src_types[1] = nir_type_uint32;
1127 ins.has_constants = true;
1128 ins.constants.u32[0] = 0;
1129
1130 for (unsigned c = 0; c < 16; ++c)
1131 ins.swizzle[1][c] = 0;
1132 } else if (instr->op == nir_op_pack_32_2x16) {
1133 ins.dest_type = nir_type_uint16;
1134 ins.mask = mask_of(nr_components * 2);
1135 ins.is_pack = true;
1136 } else if (instr->op == nir_op_pack_32_4x8) {
1137 ins.dest_type = nir_type_uint8;
1138 ins.mask = mask_of(nr_components * 4);
1139 ins.is_pack = true;
1140 } else if (instr->op == nir_op_unpack_32_2x16) {
1141 ins.dest_type = nir_type_uint32;
1142 ins.mask = mask_of(nr_components >> 1);
1143 ins.is_pack = true;
1144 } else if (instr->op == nir_op_unpack_32_4x8) {
1145 ins.dest_type = nir_type_uint32;
1146 ins.mask = mask_of(nr_components >> 2);
1147 ins.is_pack = true;
1148 }
1149
1150 /* Arrange for creation of iandnot/iornot */
1151 if (ins.src_invert[0] && !ins.src_invert[1]) {
1152 mir_flip(&ins);
1153 ins.src_invert[0] = false;
1154 ins.src_invert[1] = true;
1155 }
1156
1157 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1158 /* To avoid duplicating the lookup tables (probably), true LUT
1159 * instructions can only operate as if they were scalars. Lower
1160 * them here by changing the component. */
1161
1162 unsigned orig_mask = ins.mask;
1163
1164 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1165 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1166
1167 for (int i = 0; i < nr_components; ++i) {
1168 /* Mask the associated component, dropping the
1169 * instruction if needed */
1170
1171 ins.mask = 1 << i;
1172 ins.mask &= orig_mask;
1173
1174 if (!ins.mask)
1175 continue;
1176
1177 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1178 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1179
1180 emit_mir_instruction(ctx, ins);
1181 }
1182 } else {
1183 emit_mir_instruction(ctx, ins);
1184 }
1185 }
1186
1187 #undef ALU_CASE
1188
1189 static void
1190 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1191 {
1192 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1193 unsigned nir_mask = 0;
1194 unsigned dsize = 0;
1195
1196 if (is_read) {
1197 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1198 dsize = nir_dest_bit_size(intr->dest);
1199 } else {
1200 nir_mask = nir_intrinsic_write_mask(intr);
1201 dsize = 32;
1202 }
1203
1204 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1205 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1206 mir_set_bytemask(ins, bytemask);
1207 ins->dest_type = nir_type_uint | dsize;
1208 }
1209
1210 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1211 * optimized) versions of UBO #0 */
1212
1213 static midgard_instruction *
1214 emit_ubo_read(
1215 compiler_context *ctx,
1216 nir_instr *instr,
1217 unsigned dest,
1218 unsigned offset,
1219 nir_src *indirect_offset,
1220 unsigned indirect_shift,
1221 unsigned index)
1222 {
1223 /* TODO: half-floats */
1224
1225 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1226 ins.constants.u32[0] = offset;
1227
1228 if (instr->type == nir_instr_type_intrinsic)
1229 mir_set_intr_mask(instr, &ins, true);
1230
1231 if (indirect_offset) {
1232 ins.src[2] = nir_src_index(ctx, indirect_offset);
1233 ins.src_types[2] = nir_type_uint32;
1234 ins.load_store.arg_2 = (indirect_shift << 5);
1235 } else {
1236 ins.load_store.arg_2 = 0x1E;
1237 }
1238
1239 ins.load_store.arg_1 = index;
1240
1241 return emit_mir_instruction(ctx, ins);
1242 }
1243
1244 /* Globals are like UBOs if you squint. And shared memory is like globals if
1245 * you squint even harder */
1246
1247 static void
1248 emit_global(
1249 compiler_context *ctx,
1250 nir_instr *instr,
1251 bool is_read,
1252 unsigned srcdest,
1253 nir_src *offset,
1254 bool is_shared)
1255 {
1256 /* TODO: types */
1257
1258 midgard_instruction ins;
1259
1260 if (is_read)
1261 ins = m_ld_int4(srcdest, 0);
1262 else
1263 ins = m_st_int4(srcdest, 0);
1264
1265 mir_set_offset(ctx, &ins, offset, is_shared);
1266 mir_set_intr_mask(instr, &ins, is_read);
1267
1268 emit_mir_instruction(ctx, ins);
1269 }
1270
1271 static void
1272 emit_varying_read(
1273 compiler_context *ctx,
1274 unsigned dest, unsigned offset,
1275 unsigned nr_comp, unsigned component,
1276 nir_src *indirect_offset, nir_alu_type type, bool flat)
1277 {
1278 /* XXX: Half-floats? */
1279 /* TODO: swizzle, mask */
1280
1281 midgard_instruction ins = m_ld_vary_32(dest, offset);
1282 ins.mask = mask_of(nr_comp);
1283
1284 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1285 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1286
1287 midgard_varying_parameter p = {
1288 .is_varying = 1,
1289 .interpolation = midgard_interp_default,
1290 .flat = flat,
1291 };
1292
1293 unsigned u;
1294 memcpy(&u, &p, sizeof(p));
1295 ins.load_store.varying_parameters = u;
1296
1297 if (indirect_offset) {
1298 ins.src[2] = nir_src_index(ctx, indirect_offset);
1299 ins.src_types[2] = nir_type_uint32;
1300 } else
1301 ins.load_store.arg_2 = 0x1E;
1302
1303 ins.load_store.arg_1 = 0x9E;
1304
1305 /* Use the type appropriate load */
1306 switch (type) {
1307 case nir_type_uint32:
1308 case nir_type_bool32:
1309 ins.load_store.op = midgard_op_ld_vary_32u;
1310 break;
1311 case nir_type_int32:
1312 ins.load_store.op = midgard_op_ld_vary_32i;
1313 break;
1314 case nir_type_float32:
1315 ins.load_store.op = midgard_op_ld_vary_32;
1316 break;
1317 case nir_type_float16:
1318 ins.load_store.op = midgard_op_ld_vary_16;
1319 break;
1320 default:
1321 unreachable("Attempted to load unknown type");
1322 break;
1323 }
1324
1325 emit_mir_instruction(ctx, ins);
1326 }
1327
1328 static void
1329 emit_attr_read(
1330 compiler_context *ctx,
1331 unsigned dest, unsigned offset,
1332 unsigned nr_comp, nir_alu_type t)
1333 {
1334 midgard_instruction ins = m_ld_attr_32(dest, offset);
1335 ins.load_store.arg_1 = 0x1E;
1336 ins.load_store.arg_2 = 0x1E;
1337 ins.mask = mask_of(nr_comp);
1338
1339 /* Use the type appropriate load */
1340 switch (t) {
1341 case nir_type_uint:
1342 case nir_type_bool:
1343 ins.load_store.op = midgard_op_ld_attr_32u;
1344 break;
1345 case nir_type_int:
1346 ins.load_store.op = midgard_op_ld_attr_32i;
1347 break;
1348 case nir_type_float:
1349 ins.load_store.op = midgard_op_ld_attr_32;
1350 break;
1351 default:
1352 unreachable("Attempted to load unknown type");
1353 break;
1354 }
1355
1356 emit_mir_instruction(ctx, ins);
1357 }
1358
1359 static void
1360 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1361 unsigned nr_components, unsigned offset)
1362 {
1363 nir_dest nir_dest;
1364
1365 /* Figure out which uniform this is */
1366 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1367 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1368
1369 unsigned dest = nir_dest_index(&nir_dest);
1370
1371 /* Sysvals are prefix uniforms */
1372 unsigned uniform = ((uintptr_t) val) - 1;
1373
1374 /* Emit the read itself -- this is never indirect */
1375 midgard_instruction *ins =
1376 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1377
1378 ins->mask = mask_of(nr_components);
1379 }
1380
1381 static unsigned
1382 compute_builtin_arg(nir_op op)
1383 {
1384 switch (op) {
1385 case nir_intrinsic_load_work_group_id:
1386 return 0x14;
1387 case nir_intrinsic_load_local_invocation_id:
1388 return 0x10;
1389 default:
1390 unreachable("Invalid compute paramater loaded");
1391 }
1392 }
1393
1394 static void
1395 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1396 {
1397 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1398
1399 midgard_instruction *br = ctx->writeout_branch[rt];
1400
1401 assert(!br);
1402
1403 emit_explicit_constant(ctx, src, src);
1404
1405 struct midgard_instruction ins =
1406 v_branch(false, false);
1407
1408 ins.writeout = true;
1409
1410 /* Add dependencies */
1411 ins.src[0] = src;
1412 ins.src_types[0] = nir_type_uint32;
1413 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1414 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1415
1416 /* Emit the branch */
1417 br = emit_mir_instruction(ctx, ins);
1418 schedule_barrier(ctx);
1419 ctx->writeout_branch[rt] = br;
1420
1421 /* Push our current location = current block count - 1 = where we'll
1422 * jump to. Maybe a bit too clever for my own good */
1423
1424 br->branch.target_block = ctx->block_count - 1;
1425 }
1426
1427 static void
1428 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1429 {
1430 unsigned reg = nir_dest_index(&instr->dest);
1431 midgard_instruction ins = m_ld_compute_id(reg, 0);
1432 ins.mask = mask_of(3);
1433 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1434 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1435 emit_mir_instruction(ctx, ins);
1436 }
1437
1438 static unsigned
1439 vertex_builtin_arg(nir_op op)
1440 {
1441 switch (op) {
1442 case nir_intrinsic_load_vertex_id:
1443 return PAN_VERTEX_ID;
1444 case nir_intrinsic_load_instance_id:
1445 return PAN_INSTANCE_ID;
1446 default:
1447 unreachable("Invalid vertex builtin");
1448 }
1449 }
1450
1451 static void
1452 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1453 {
1454 unsigned reg = nir_dest_index(&instr->dest);
1455 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1456 }
1457
1458 static void
1459 emit_control_barrier(compiler_context *ctx)
1460 {
1461 midgard_instruction ins = {
1462 .type = TAG_TEXTURE_4,
1463 .dest = ~0,
1464 .src = { ~0, ~0, ~0, ~0 },
1465 .texture = {
1466 .op = TEXTURE_OP_BARRIER,
1467
1468 /* TODO: optimize */
1469 .out_of_order = MIDGARD_BARRIER_BUFFER |
1470 MIDGARD_BARRIER_SHARED ,
1471 }
1472 };
1473
1474 emit_mir_instruction(ctx, ins);
1475 }
1476
1477 static const nir_variable *
1478 search_var(struct exec_list *vars, unsigned driver_loc)
1479 {
1480 nir_foreach_variable(var, vars) {
1481 if (var->data.driver_location == driver_loc)
1482 return var;
1483 }
1484
1485 return NULL;
1486 }
1487
1488 static unsigned
1489 mir_get_branch_cond(nir_src *src, bool *invert)
1490 {
1491 /* Wrap it. No swizzle since it's a scalar */
1492
1493 nir_alu_src alu = {
1494 .src = *src
1495 };
1496
1497 *invert = pan_has_source_mod(&alu, nir_op_inot);
1498 return nir_src_index(NULL, &alu.src);
1499 }
1500
1501 static void
1502 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1503 {
1504 unsigned offset = 0, reg;
1505
1506 switch (instr->intrinsic) {
1507 case nir_intrinsic_discard_if:
1508 case nir_intrinsic_discard: {
1509 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1510 struct midgard_instruction discard = v_branch(conditional, false);
1511 discard.branch.target_type = TARGET_DISCARD;
1512
1513 if (conditional) {
1514 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1515 &discard.branch.invert_conditional);
1516 discard.src_types[0] = nir_type_uint32;
1517 }
1518
1519 emit_mir_instruction(ctx, discard);
1520 schedule_barrier(ctx);
1521
1522 break;
1523 }
1524
1525 case nir_intrinsic_load_uniform:
1526 case nir_intrinsic_load_ubo:
1527 case nir_intrinsic_load_global:
1528 case nir_intrinsic_load_shared:
1529 case nir_intrinsic_load_input:
1530 case nir_intrinsic_load_interpolated_input: {
1531 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1532 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1533 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1534 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1535 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1536 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1537
1538 /* Get the base type of the intrinsic */
1539 /* TODO: Infer type? Does it matter? */
1540 nir_alu_type t =
1541 (is_ubo || is_global || is_shared) ? nir_type_uint :
1542 (is_interp) ? nir_type_float :
1543 nir_intrinsic_type(instr);
1544
1545 t = nir_alu_type_get_base_type(t);
1546
1547 if (!(is_ubo || is_global)) {
1548 offset = nir_intrinsic_base(instr);
1549 }
1550
1551 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1552
1553 nir_src *src_offset = nir_get_io_offset_src(instr);
1554
1555 bool direct = nir_src_is_const(*src_offset);
1556 nir_src *indirect_offset = direct ? NULL : src_offset;
1557
1558 if (direct)
1559 offset += nir_src_as_uint(*src_offset);
1560
1561 /* We may need to apply a fractional offset */
1562 int component = (is_flat || is_interp) ?
1563 nir_intrinsic_component(instr) : 0;
1564 reg = nir_dest_index(&instr->dest);
1565
1566 if (is_uniform && !ctx->is_blend) {
1567 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1568 } else if (is_ubo) {
1569 nir_src index = instr->src[0];
1570
1571 /* TODO: Is indirect block number possible? */
1572 assert(nir_src_is_const(index));
1573
1574 uint32_t uindex = nir_src_as_uint(index) + 1;
1575 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1576 } else if (is_global || is_shared) {
1577 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1578 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1579 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t | nir_dest_bit_size(instr->dest), is_flat);
1580 } else if (ctx->is_blend) {
1581 /* For blend shaders, load the input color, which is
1582 * preloaded to r0 */
1583
1584 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1585 emit_mir_instruction(ctx, move);
1586 schedule_barrier(ctx);
1587 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1588 emit_attr_read(ctx, reg, offset, nr_comp, t);
1589 } else {
1590 DBG("Unknown load\n");
1591 assert(0);
1592 }
1593
1594 break;
1595 }
1596
1597 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1598 case nir_intrinsic_load_barycentric_pixel:
1599 case nir_intrinsic_load_barycentric_centroid:
1600 break;
1601
1602 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1603
1604 case nir_intrinsic_load_raw_output_pan: {
1605 reg = nir_dest_index(&instr->dest);
1606 assert(ctx->is_blend);
1607
1608 /* T720 and below use different blend opcodes with slightly
1609 * different semantics than T760 and up */
1610
1611 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1612
1613 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1614 ld.load_store.op = midgard_op_ld_color_buffer_32u_old;
1615 ld.load_store.address = 16;
1616 ld.load_store.arg_2 = 0x1E;
1617 }
1618
1619 emit_mir_instruction(ctx, ld);
1620 break;
1621 }
1622
1623 case nir_intrinsic_load_output: {
1624 reg = nir_dest_index(&instr->dest);
1625 assert(ctx->is_blend);
1626
1627 midgard_instruction ld = m_ld_color_buffer_as_fp16(reg, 0);
1628
1629 for (unsigned c = 4; c < 16; ++c)
1630 ld.swizzle[0][c] = 0;
1631
1632 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1633 ld.load_store.op = midgard_op_ld_color_buffer_as_fp16_old;
1634 ld.load_store.address = 1;
1635 ld.load_store.arg_2 = 0x1E;
1636 }
1637
1638 emit_mir_instruction(ctx, ld);
1639 break;
1640 }
1641
1642 case nir_intrinsic_load_blend_const_color_rgba: {
1643 assert(ctx->is_blend);
1644 reg = nir_dest_index(&instr->dest);
1645
1646 /* Blend constants are embedded directly in the shader and
1647 * patched in, so we use some magic routing */
1648
1649 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1650 ins.has_constants = true;
1651 ins.has_blend_constant = true;
1652 emit_mir_instruction(ctx, ins);
1653 break;
1654 }
1655
1656 case nir_intrinsic_store_zs_output_pan: {
1657 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1658 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1659 MIDGARD_ZS_RT);
1660
1661 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1662
1663 if (!nir_intrinsic_component(instr))
1664 br->writeout_depth = true;
1665 if (nir_intrinsic_component(instr) ||
1666 instr->num_components)
1667 br->writeout_stencil = true;
1668 assert(br->writeout_depth | br->writeout_stencil);
1669 break;
1670 }
1671
1672 case nir_intrinsic_store_output:
1673 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1674
1675 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1676
1677 reg = nir_src_index(ctx, &instr->src[0]);
1678
1679 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1680 const nir_variable *var;
1681 enum midgard_rt_id rt;
1682
1683 var = search_var(&ctx->nir->outputs,
1684 nir_intrinsic_base(instr));
1685 assert(var);
1686 if (var->data.location == FRAG_RESULT_COLOR)
1687 rt = MIDGARD_COLOR_RT0;
1688 else if (var->data.location >= FRAG_RESULT_DATA0)
1689 rt = MIDGARD_COLOR_RT0 + var->data.location -
1690 FRAG_RESULT_DATA0;
1691 else
1692 assert(0);
1693
1694 emit_fragment_store(ctx, reg, rt);
1695 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1696 /* We should have been vectorized, though we don't
1697 * currently check that st_vary is emitted only once
1698 * per slot (this is relevant, since there's not a mask
1699 * parameter available on the store [set to 0 by the
1700 * blob]). We do respect the component by adjusting the
1701 * swizzle. If this is a constant source, we'll need to
1702 * emit that explicitly. */
1703
1704 emit_explicit_constant(ctx, reg, reg);
1705
1706 unsigned dst_component = nir_intrinsic_component(instr);
1707 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1708
1709 midgard_instruction st = m_st_vary_32(reg, offset);
1710 st.load_store.arg_1 = 0x9E;
1711 st.load_store.arg_2 = 0x1E;
1712
1713 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1714 case nir_type_uint:
1715 case nir_type_bool:
1716 st.load_store.op = midgard_op_st_vary_32u;
1717 break;
1718 case nir_type_int:
1719 st.load_store.op = midgard_op_st_vary_32i;
1720 break;
1721 case nir_type_float:
1722 st.load_store.op = midgard_op_st_vary_32;
1723 break;
1724 default:
1725 unreachable("Attempted to store unknown type");
1726 break;
1727 }
1728
1729 /* nir_intrinsic_component(store_intr) encodes the
1730 * destination component start. Source component offset
1731 * adjustment is taken care of in
1732 * install_registers_instr(), when offset_swizzle() is
1733 * called.
1734 */
1735 unsigned src_component = COMPONENT_X;
1736
1737 assert(nr_comp > 0);
1738 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1739 st.swizzle[0][i] = src_component;
1740 if (i >= dst_component && i < dst_component + nr_comp - 1)
1741 src_component++;
1742 }
1743
1744 emit_mir_instruction(ctx, st);
1745 } else {
1746 DBG("Unknown store\n");
1747 assert(0);
1748 }
1749
1750 break;
1751
1752 /* Special case of store_output for lowered blend shaders */
1753 case nir_intrinsic_store_raw_output_pan:
1754 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1755 reg = nir_src_index(ctx, &instr->src[0]);
1756 emit_fragment_store(ctx, reg, ctx->blend_rt);
1757 break;
1758
1759 case nir_intrinsic_store_global:
1760 case nir_intrinsic_store_shared:
1761 reg = nir_src_index(ctx, &instr->src[0]);
1762 emit_explicit_constant(ctx, reg, reg);
1763
1764 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1765 break;
1766
1767 case nir_intrinsic_load_ssbo_address:
1768 emit_sysval_read(ctx, &instr->instr, 1, 0);
1769 break;
1770
1771 case nir_intrinsic_get_buffer_size:
1772 emit_sysval_read(ctx, &instr->instr, 1, 8);
1773 break;
1774
1775 case nir_intrinsic_load_viewport_scale:
1776 case nir_intrinsic_load_viewport_offset:
1777 case nir_intrinsic_load_num_work_groups:
1778 case nir_intrinsic_load_sampler_lod_parameters_pan:
1779 emit_sysval_read(ctx, &instr->instr, 3, 0);
1780 break;
1781
1782 case nir_intrinsic_load_work_group_id:
1783 case nir_intrinsic_load_local_invocation_id:
1784 emit_compute_builtin(ctx, instr);
1785 break;
1786
1787 case nir_intrinsic_load_vertex_id:
1788 case nir_intrinsic_load_instance_id:
1789 emit_vertex_builtin(ctx, instr);
1790 break;
1791
1792 case nir_intrinsic_memory_barrier_buffer:
1793 case nir_intrinsic_memory_barrier_shared:
1794 break;
1795
1796 case nir_intrinsic_control_barrier:
1797 schedule_barrier(ctx);
1798 emit_control_barrier(ctx);
1799 schedule_barrier(ctx);
1800 break;
1801
1802 default:
1803 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1804 assert(0);
1805 break;
1806 }
1807 }
1808
1809 static unsigned
1810 midgard_tex_format(enum glsl_sampler_dim dim)
1811 {
1812 switch (dim) {
1813 case GLSL_SAMPLER_DIM_1D:
1814 case GLSL_SAMPLER_DIM_BUF:
1815 return MALI_TEX_1D;
1816
1817 case GLSL_SAMPLER_DIM_2D:
1818 case GLSL_SAMPLER_DIM_EXTERNAL:
1819 case GLSL_SAMPLER_DIM_RECT:
1820 return MALI_TEX_2D;
1821
1822 case GLSL_SAMPLER_DIM_3D:
1823 return MALI_TEX_3D;
1824
1825 case GLSL_SAMPLER_DIM_CUBE:
1826 return MALI_TEX_CUBE;
1827
1828 default:
1829 DBG("Unknown sampler dim type\n");
1830 assert(0);
1831 return 0;
1832 }
1833 }
1834
1835 /* Tries to attach an explicit LOD or bias as a constant. Returns whether this
1836 * was successful */
1837
1838 static bool
1839 pan_attach_constant_bias(
1840 compiler_context *ctx,
1841 nir_src lod,
1842 midgard_texture_word *word)
1843 {
1844 /* To attach as constant, it has to *be* constant */
1845
1846 if (!nir_src_is_const(lod))
1847 return false;
1848
1849 float f = nir_src_as_float(lod);
1850
1851 /* Break into fixed-point */
1852 signed lod_int = f;
1853 float lod_frac = f - lod_int;
1854
1855 /* Carry over negative fractions */
1856 if (lod_frac < 0.0) {
1857 lod_int--;
1858 lod_frac += 1.0;
1859 }
1860
1861 /* Encode */
1862 word->bias = float_to_ubyte(lod_frac);
1863 word->bias_int = lod_int;
1864
1865 return true;
1866 }
1867
1868 static void
1869 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1870 unsigned midgard_texop)
1871 {
1872 /* TODO */
1873 //assert (!instr->sampler);
1874
1875 int texture_index = instr->texture_index;
1876 int sampler_index = texture_index;
1877
1878 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1879 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1880
1881 midgard_instruction ins = {
1882 .type = TAG_TEXTURE_4,
1883 .mask = 0xF,
1884 .dest = nir_dest_index(&instr->dest),
1885 .src = { ~0, ~0, ~0, ~0 },
1886 .dest_type = dest_type,
1887 .swizzle = SWIZZLE_IDENTITY_4,
1888 .texture = {
1889 .op = midgard_texop,
1890 .format = midgard_tex_format(instr->sampler_dim),
1891 .texture_handle = texture_index,
1892 .sampler_handle = sampler_index,
1893 .shadow = instr->is_shadow,
1894 }
1895 };
1896
1897 if (instr->is_shadow && !instr->is_new_style_shadow)
1898 for (int i = 0; i < 4; ++i)
1899 ins.swizzle[0][i] = COMPONENT_X;
1900
1901 /* We may need a temporary for the coordinate */
1902
1903 bool needs_temp_coord =
1904 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1905 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1906 (instr->is_shadow);
1907
1908 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1909
1910 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1911 int index = nir_src_index(ctx, &instr->src[i].src);
1912 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1913 unsigned sz = nir_src_bit_size(instr->src[i].src);
1914 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1915
1916 switch (instr->src[i].src_type) {
1917 case nir_tex_src_coord: {
1918 emit_explicit_constant(ctx, index, index);
1919
1920 unsigned coord_mask = mask_of(instr->coord_components);
1921
1922 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1923
1924 if (flip_zw)
1925 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1926
1927 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1928 /* texelFetch is undefined on samplerCube */
1929 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1930
1931 /* For cubemaps, we use a special ld/st op to
1932 * select the face and copy the xy into the
1933 * texture register */
1934
1935 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1936 ld.src[1] = index;
1937 ld.src_types[1] = T;
1938 ld.mask = 0x3; /* xy */
1939 ld.load_store.arg_1 = 0x20;
1940 ld.swizzle[1][3] = COMPONENT_X;
1941 emit_mir_instruction(ctx, ld);
1942
1943 /* xyzw -> xyxx */
1944 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1945 ins.swizzle[1][3] = COMPONENT_X;
1946 } else if (needs_temp_coord) {
1947 /* mov coord_temp, coords */
1948 midgard_instruction mov = v_mov(index, coords);
1949 mov.mask = coord_mask;
1950
1951 if (flip_zw)
1952 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1953
1954 emit_mir_instruction(ctx, mov);
1955 } else {
1956 coords = index;
1957 }
1958
1959 ins.src[1] = coords;
1960 ins.src_types[1] = T;
1961
1962 /* Texelfetch coordinates uses all four elements
1963 * (xyz/index) regardless of texture dimensionality,
1964 * which means it's necessary to zero the unused
1965 * components to keep everything happy */
1966
1967 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1968 /* mov index.zw, #0, or generalized */
1969 midgard_instruction mov =
1970 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1971 mov.has_constants = true;
1972 mov.mask = coord_mask ^ 0xF;
1973 emit_mir_instruction(ctx, mov);
1974 }
1975
1976 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1977 /* Array component in w but NIR wants it in z,
1978 * but if we have a temp coord we already fixed
1979 * that up */
1980
1981 if (nr_components == 3) {
1982 ins.swizzle[1][2] = COMPONENT_Z;
1983 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1984 } else if (nr_components == 2) {
1985 ins.swizzle[1][2] =
1986 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1987 ins.swizzle[1][3] = COMPONENT_X;
1988 } else
1989 unreachable("Invalid texture 2D components");
1990 }
1991
1992 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1993 /* We zeroed */
1994 ins.swizzle[1][2] = COMPONENT_Z;
1995 ins.swizzle[1][3] = COMPONENT_W;
1996 }
1997
1998 break;
1999 }
2000
2001 case nir_tex_src_bias:
2002 case nir_tex_src_lod: {
2003 /* Try as a constant if we can */
2004
2005 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
2006 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
2007 break;
2008
2009 ins.texture.lod_register = true;
2010 ins.src[2] = index;
2011 ins.src_types[2] = T;
2012
2013 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2014 ins.swizzle[2][c] = COMPONENT_X;
2015
2016 emit_explicit_constant(ctx, index, index);
2017
2018 break;
2019 };
2020
2021 case nir_tex_src_offset: {
2022 ins.texture.offset_register = true;
2023 ins.src[3] = index;
2024 ins.src_types[3] = T;
2025
2026 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2027 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
2028
2029 emit_explicit_constant(ctx, index, index);
2030 break;
2031 };
2032
2033 case nir_tex_src_comparator: {
2034 unsigned comp = COMPONENT_Z;
2035
2036 /* mov coord_temp.foo, coords */
2037 midgard_instruction mov = v_mov(index, coords);
2038 mov.mask = 1 << comp;
2039
2040 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
2041 mov.swizzle[1][i] = COMPONENT_X;
2042
2043 emit_mir_instruction(ctx, mov);
2044 break;
2045 }
2046
2047 default: {
2048 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
2049 assert(0);
2050 }
2051 }
2052 }
2053
2054 emit_mir_instruction(ctx, ins);
2055 }
2056
2057 static void
2058 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2059 {
2060 switch (instr->op) {
2061 case nir_texop_tex:
2062 case nir_texop_txb:
2063 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2064 break;
2065 case nir_texop_txl:
2066 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2067 break;
2068 case nir_texop_txf:
2069 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2070 break;
2071 case nir_texop_txs:
2072 emit_sysval_read(ctx, &instr->instr, 4, 0);
2073 break;
2074 default: {
2075 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2076 assert(0);
2077 }
2078 }
2079 }
2080
2081 static void
2082 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2083 {
2084 switch (instr->type) {
2085 case nir_jump_break: {
2086 /* Emit a branch out of the loop */
2087 struct midgard_instruction br = v_branch(false, false);
2088 br.branch.target_type = TARGET_BREAK;
2089 br.branch.target_break = ctx->current_loop_depth;
2090 emit_mir_instruction(ctx, br);
2091 break;
2092 }
2093
2094 default:
2095 DBG("Unknown jump type %d\n", instr->type);
2096 break;
2097 }
2098 }
2099
2100 static void
2101 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2102 {
2103 switch (instr->type) {
2104 case nir_instr_type_load_const:
2105 emit_load_const(ctx, nir_instr_as_load_const(instr));
2106 break;
2107
2108 case nir_instr_type_intrinsic:
2109 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2110 break;
2111
2112 case nir_instr_type_alu:
2113 emit_alu(ctx, nir_instr_as_alu(instr));
2114 break;
2115
2116 case nir_instr_type_tex:
2117 emit_tex(ctx, nir_instr_as_tex(instr));
2118 break;
2119
2120 case nir_instr_type_jump:
2121 emit_jump(ctx, nir_instr_as_jump(instr));
2122 break;
2123
2124 case nir_instr_type_ssa_undef:
2125 /* Spurious */
2126 break;
2127
2128 default:
2129 DBG("Unhandled instruction type\n");
2130 break;
2131 }
2132 }
2133
2134
2135 /* ALU instructions can inline or embed constants, which decreases register
2136 * pressure and saves space. */
2137
2138 #define CONDITIONAL_ATTACH(idx) { \
2139 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2140 \
2141 if (entry) { \
2142 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2143 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2144 } \
2145 }
2146
2147 static void
2148 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2149 {
2150 mir_foreach_instr_in_block(block, alu) {
2151 /* Other instructions cannot inline constants */
2152 if (alu->type != TAG_ALU_4) continue;
2153 if (alu->compact_branch) continue;
2154
2155 /* If there is already a constant here, we can do nothing */
2156 if (alu->has_constants) continue;
2157
2158 CONDITIONAL_ATTACH(0);
2159
2160 if (!alu->has_constants) {
2161 CONDITIONAL_ATTACH(1)
2162 } else if (!alu->inline_constant) {
2163 /* Corner case: _two_ vec4 constants, for instance with a
2164 * csel. For this case, we can only use a constant
2165 * register for one, we'll have to emit a move for the
2166 * other. */
2167
2168 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2169 unsigned scratch = make_compiler_temp(ctx);
2170
2171 if (entry) {
2172 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2173 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2174
2175 /* Set the source */
2176 alu->src[1] = scratch;
2177
2178 /* Inject us -before- the last instruction which set r31 */
2179 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2180 }
2181 }
2182 }
2183 }
2184
2185 /* Midgard supports two types of constants, embedded constants (128-bit) and
2186 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2187 * constants can be demoted to inline constants, for space savings and
2188 * sometimes a performance boost */
2189
2190 static void
2191 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2192 {
2193 mir_foreach_instr_in_block(block, ins) {
2194 if (!ins->has_constants) continue;
2195 if (ins->has_inline_constant) continue;
2196
2197 /* Blend constants must not be inlined by definition */
2198 if (ins->has_blend_constant) continue;
2199
2200 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2201 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2202 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2203
2204 if (!(is_16 || is_32))
2205 continue;
2206
2207 /* src1 cannot be an inline constant due to encoding
2208 * restrictions. So, if possible we try to flip the arguments
2209 * in that case */
2210
2211 int op = ins->alu.op;
2212
2213 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2214 alu_opcode_props[op].props & OP_COMMUTES) {
2215 mir_flip(ins);
2216 }
2217
2218 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2219 /* Component is from the swizzle. Take a nonzero component */
2220 assert(ins->mask);
2221 unsigned first_comp = ffs(ins->mask) - 1;
2222 unsigned component = ins->swizzle[1][first_comp];
2223
2224 /* Scale constant appropriately, if we can legally */
2225 uint16_t scaled_constant = 0;
2226
2227 if (is_16) {
2228 scaled_constant = ins->constants.u16[component];
2229 } else if (midgard_is_integer_op(op)) {
2230 scaled_constant = ins->constants.u32[component];
2231
2232 /* Constant overflow after resize */
2233 if (scaled_constant != ins->constants.u32[component])
2234 continue;
2235 } else {
2236 float original = ins->constants.f32[component];
2237 scaled_constant = _mesa_float_to_half(original);
2238
2239 /* Check for loss of precision. If this is
2240 * mediump, we don't care, but for a highp
2241 * shader, we need to pay attention. NIR
2242 * doesn't yet tell us which mode we're in!
2243 * Practically this prevents most constants
2244 * from being inlined, sadly. */
2245
2246 float fp32 = _mesa_half_to_float(scaled_constant);
2247
2248 if (fp32 != original)
2249 continue;
2250 }
2251
2252 /* Should've been const folded */
2253 if (ins->src_abs[1] || ins->src_neg[1])
2254 continue;
2255
2256 /* Make sure that the constant is not itself a vector
2257 * by checking if all accessed values are the same. */
2258
2259 const midgard_constants *cons = &ins->constants;
2260 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2261
2262 bool is_vector = false;
2263 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2264
2265 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2266 /* We only care if this component is actually used */
2267 if (!(mask & (1 << c)))
2268 continue;
2269
2270 uint32_t test = is_16 ?
2271 cons->u16[ins->swizzle[1][c]] :
2272 cons->u32[ins->swizzle[1][c]];
2273
2274 if (test != value) {
2275 is_vector = true;
2276 break;
2277 }
2278 }
2279
2280 if (is_vector)
2281 continue;
2282
2283 /* Get rid of the embedded constant */
2284 ins->has_constants = false;
2285 ins->src[1] = ~0;
2286 ins->has_inline_constant = true;
2287 ins->inline_constant = scaled_constant;
2288 }
2289 }
2290 }
2291
2292 /* Dead code elimination for branches at the end of a block - only one branch
2293 * per block is legal semantically */
2294
2295 static void
2296 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2297 {
2298 bool branched = false;
2299
2300 mir_foreach_instr_in_block_safe(block, ins) {
2301 if (!midgard_is_branch_unit(ins->unit)) continue;
2302
2303 if (branched)
2304 mir_remove_instruction(ins);
2305
2306 branched = true;
2307 }
2308 }
2309
2310 static unsigned
2311 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2312 {
2313 /* Loop to ourselves */
2314 midgard_instruction *br = ctx->writeout_branch[rt];
2315 struct midgard_instruction ins = v_branch(false, false);
2316 ins.writeout = true;
2317 ins.writeout_depth = br->writeout_depth;
2318 ins.writeout_stencil = br->writeout_stencil;
2319 ins.branch.target_block = ctx->block_count - 1;
2320 ins.constants.u32[0] = br->constants.u32[0];
2321 emit_mir_instruction(ctx, ins);
2322
2323 ctx->current_block->epilogue = true;
2324 schedule_barrier(ctx);
2325 return ins.branch.target_block;
2326 }
2327
2328 static midgard_block *
2329 emit_block(compiler_context *ctx, nir_block *block)
2330 {
2331 midgard_block *this_block = ctx->after_block;
2332 ctx->after_block = NULL;
2333
2334 if (!this_block)
2335 this_block = create_empty_block(ctx);
2336
2337 list_addtail(&this_block->base.link, &ctx->blocks);
2338
2339 this_block->scheduled = false;
2340 ++ctx->block_count;
2341
2342 /* Set up current block */
2343 list_inithead(&this_block->base.instructions);
2344 ctx->current_block = this_block;
2345
2346 nir_foreach_instr(instr, block) {
2347 emit_instr(ctx, instr);
2348 ++ctx->instruction_count;
2349 }
2350
2351 return this_block;
2352 }
2353
2354 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2355
2356 static void
2357 emit_if(struct compiler_context *ctx, nir_if *nif)
2358 {
2359 midgard_block *before_block = ctx->current_block;
2360
2361 /* Speculatively emit the branch, but we can't fill it in until later */
2362 bool inv = false;
2363 EMIT(branch, true, true);
2364 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2365 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2366 then_branch->src_types[0] = nir_type_uint32;
2367 then_branch->branch.invert_conditional = !inv;
2368
2369 /* Emit the two subblocks. */
2370 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2371 midgard_block *end_then_block = ctx->current_block;
2372
2373 /* Emit a jump from the end of the then block to the end of the else */
2374 EMIT(branch, false, false);
2375 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2376
2377 /* Emit second block, and check if it's empty */
2378
2379 int else_idx = ctx->block_count;
2380 int count_in = ctx->instruction_count;
2381 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2382 midgard_block *end_else_block = ctx->current_block;
2383 int after_else_idx = ctx->block_count;
2384
2385 /* Now that we have the subblocks emitted, fix up the branches */
2386
2387 assert(then_block);
2388 assert(else_block);
2389
2390 if (ctx->instruction_count == count_in) {
2391 /* The else block is empty, so don't emit an exit jump */
2392 mir_remove_instruction(then_exit);
2393 then_branch->branch.target_block = after_else_idx;
2394 } else {
2395 then_branch->branch.target_block = else_idx;
2396 then_exit->branch.target_block = after_else_idx;
2397 }
2398
2399 /* Wire up the successors */
2400
2401 ctx->after_block = create_empty_block(ctx);
2402
2403 pan_block_add_successor(&before_block->base, &then_block->base);
2404 pan_block_add_successor(&before_block->base, &else_block->base);
2405
2406 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2407 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2408 }
2409
2410 static void
2411 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2412 {
2413 /* Remember where we are */
2414 midgard_block *start_block = ctx->current_block;
2415
2416 /* Allocate a loop number, growing the current inner loop depth */
2417 int loop_idx = ++ctx->current_loop_depth;
2418
2419 /* Get index from before the body so we can loop back later */
2420 int start_idx = ctx->block_count;
2421
2422 /* Emit the body itself */
2423 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2424
2425 /* Branch back to loop back */
2426 struct midgard_instruction br_back = v_branch(false, false);
2427 br_back.branch.target_block = start_idx;
2428 emit_mir_instruction(ctx, br_back);
2429
2430 /* Mark down that branch in the graph. */
2431 pan_block_add_successor(&start_block->base, &loop_block->base);
2432 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2433
2434 /* Find the index of the block about to follow us (note: we don't add
2435 * one; blocks are 0-indexed so we get a fencepost problem) */
2436 int break_block_idx = ctx->block_count;
2437
2438 /* Fix up the break statements we emitted to point to the right place,
2439 * now that we can allocate a block number for them */
2440 ctx->after_block = create_empty_block(ctx);
2441
2442 mir_foreach_block_from(ctx, start_block, _block) {
2443 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2444 if (ins->type != TAG_ALU_4) continue;
2445 if (!ins->compact_branch) continue;
2446
2447 /* We found a branch -- check the type to see if we need to do anything */
2448 if (ins->branch.target_type != TARGET_BREAK) continue;
2449
2450 /* It's a break! Check if it's our break */
2451 if (ins->branch.target_break != loop_idx) continue;
2452
2453 /* Okay, cool, we're breaking out of this loop.
2454 * Rewrite from a break to a goto */
2455
2456 ins->branch.target_type = TARGET_GOTO;
2457 ins->branch.target_block = break_block_idx;
2458
2459 pan_block_add_successor(_block, &ctx->after_block->base);
2460 }
2461 }
2462
2463 /* Now that we've finished emitting the loop, free up the depth again
2464 * so we play nice with recursion amid nested loops */
2465 --ctx->current_loop_depth;
2466
2467 /* Dump loop stats */
2468 ++ctx->loop_count;
2469 }
2470
2471 static midgard_block *
2472 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2473 {
2474 midgard_block *start_block = NULL;
2475
2476 foreach_list_typed(nir_cf_node, node, node, list) {
2477 switch (node->type) {
2478 case nir_cf_node_block: {
2479 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2480
2481 if (!start_block)
2482 start_block = block;
2483
2484 break;
2485 }
2486
2487 case nir_cf_node_if:
2488 emit_if(ctx, nir_cf_node_as_if(node));
2489 break;
2490
2491 case nir_cf_node_loop:
2492 emit_loop(ctx, nir_cf_node_as_loop(node));
2493 break;
2494
2495 case nir_cf_node_function:
2496 assert(0);
2497 break;
2498 }
2499 }
2500
2501 return start_block;
2502 }
2503
2504 /* Due to lookahead, we need to report the first tag executed in the command
2505 * stream and in branch targets. An initial block might be empty, so iterate
2506 * until we find one that 'works' */
2507
2508 static unsigned
2509 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2510 {
2511 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2512
2513 mir_foreach_block_from(ctx, initial_block, _v) {
2514 midgard_block *v = (midgard_block *) _v;
2515 if (v->quadword_count) {
2516 midgard_bundle *initial_bundle =
2517 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2518
2519 return initial_bundle->tag;
2520 }
2521 }
2522
2523 /* Default to a tag 1 which will break from the shader, in case we jump
2524 * to the exit block (i.e. `return` in a compute shader) */
2525
2526 return 1;
2527 }
2528
2529 /* For each fragment writeout instruction, generate a writeout loop to
2530 * associate with it */
2531
2532 static void
2533 mir_add_writeout_loops(compiler_context *ctx)
2534 {
2535 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2536 midgard_instruction *br = ctx->writeout_branch[rt];
2537 if (!br) continue;
2538
2539 unsigned popped = br->branch.target_block;
2540 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2541 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2542 br->branch.target_type = TARGET_GOTO;
2543
2544 /* If we have more RTs, we'll need to restore back after our
2545 * loop terminates */
2546
2547 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2548 midgard_instruction uncond = v_branch(false, false);
2549 uncond.branch.target_block = popped;
2550 uncond.branch.target_type = TARGET_GOTO;
2551 emit_mir_instruction(ctx, uncond);
2552 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2553 schedule_barrier(ctx);
2554 } else {
2555 /* We're last, so we can terminate here */
2556 br->last_writeout = true;
2557 }
2558 }
2559 }
2560
2561 int
2562 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2563 {
2564 struct util_dynarray *compiled = &program->compiled;
2565
2566 midgard_debug = debug_get_option_midgard_debug();
2567
2568 /* TODO: Bound against what? */
2569 compiler_context *ctx = rzalloc(NULL, compiler_context);
2570
2571 ctx->nir = nir;
2572 ctx->stage = nir->info.stage;
2573 ctx->is_blend = is_blend;
2574 ctx->alpha_ref = program->alpha_ref;
2575 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2576 ctx->quirks = midgard_get_quirks(gpu_id);
2577
2578 /* Start off with a safe cutoff, allowing usage of all 16 work
2579 * registers. Later, we'll promote uniform reads to uniform registers
2580 * if we determine it is beneficial to do so */
2581 ctx->uniform_cutoff = 8;
2582
2583 /* Initialize at a global (not block) level hash tables */
2584
2585 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2586 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2587
2588 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2589 * (so we don't accidentally duplicate the epilogue since mesa/st has
2590 * messed with our I/O quite a bit already) */
2591
2592 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2593
2594 if (ctx->stage == MESA_SHADER_VERTEX) {
2595 NIR_PASS_V(nir, nir_lower_viewport_transform);
2596 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2597 }
2598
2599 NIR_PASS_V(nir, nir_lower_var_copies);
2600 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2601 NIR_PASS_V(nir, nir_split_var_copies);
2602 NIR_PASS_V(nir, nir_lower_var_copies);
2603 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2604 NIR_PASS_V(nir, nir_lower_var_copies);
2605 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2606
2607 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2608 NIR_PASS_V(nir, nir_lower_ssbo);
2609 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2610
2611 /* Optimisation passes */
2612
2613 optimise_nir(nir, ctx->quirks, is_blend);
2614
2615 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2616 nir_print_shader(nir, stdout);
2617 }
2618
2619 /* Assign sysvals and counts, now that we're sure
2620 * (post-optimisation) */
2621
2622 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2623 program->sysval_count = ctx->sysvals.sysval_count;
2624 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2625
2626 nir_foreach_function(func, nir) {
2627 if (!func->impl)
2628 continue;
2629
2630 list_inithead(&ctx->blocks);
2631 ctx->block_count = 0;
2632 ctx->func = func;
2633 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2634
2635 emit_cf_list(ctx, &func->impl->body);
2636 free(ctx->already_emitted);
2637 break; /* TODO: Multi-function shaders */
2638 }
2639
2640 util_dynarray_init(compiled, NULL);
2641
2642 /* Per-block lowering before opts */
2643
2644 mir_foreach_block(ctx, _block) {
2645 midgard_block *block = (midgard_block *) _block;
2646 inline_alu_constants(ctx, block);
2647 embedded_to_inline_constant(ctx, block);
2648 }
2649 /* MIR-level optimizations */
2650
2651 bool progress = false;
2652
2653 do {
2654 progress = false;
2655 progress |= midgard_opt_dead_code_eliminate(ctx);
2656
2657 mir_foreach_block(ctx, _block) {
2658 midgard_block *block = (midgard_block *) _block;
2659 progress |= midgard_opt_copy_prop(ctx, block);
2660 progress |= midgard_opt_combine_projection(ctx, block);
2661 progress |= midgard_opt_varying_projection(ctx, block);
2662 }
2663 } while (progress);
2664
2665 mir_foreach_block(ctx, _block) {
2666 midgard_block *block = (midgard_block *) _block;
2667 midgard_lower_derivatives(ctx, block);
2668 midgard_cull_dead_branch(ctx, block);
2669 }
2670
2671 if (ctx->stage == MESA_SHADER_FRAGMENT)
2672 mir_add_writeout_loops(ctx);
2673
2674 /* Analyze now that the code is known but before scheduling creates
2675 * pipeline registers which are harder to track */
2676 mir_analyze_helper_terminate(ctx);
2677 mir_analyze_helper_requirements(ctx);
2678
2679 /* Schedule! */
2680 midgard_schedule_program(ctx);
2681 mir_ra(ctx);
2682
2683 /* Now that all the bundles are scheduled and we can calculate block
2684 * sizes, emit actual branch instructions rather than placeholders */
2685
2686 int br_block_idx = 0;
2687
2688 mir_foreach_block(ctx, _block) {
2689 midgard_block *block = (midgard_block *) _block;
2690 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2691 for (int c = 0; c < bundle->instruction_count; ++c) {
2692 midgard_instruction *ins = bundle->instructions[c];
2693
2694 if (!midgard_is_branch_unit(ins->unit)) continue;
2695
2696 /* Parse some basic branch info */
2697 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2698 bool is_conditional = ins->branch.conditional;
2699 bool is_inverted = ins->branch.invert_conditional;
2700 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2701 bool is_writeout = ins->writeout;
2702
2703 /* Determine the block we're jumping to */
2704 int target_number = ins->branch.target_block;
2705
2706 /* Report the destination tag */
2707 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2708
2709 /* Count up the number of quadwords we're
2710 * jumping over = number of quadwords until
2711 * (br_block_idx, target_number) */
2712
2713 int quadword_offset = 0;
2714
2715 if (is_discard) {
2716 /* Ignored */
2717 } else if (target_number > br_block_idx) {
2718 /* Jump forward */
2719
2720 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2721 midgard_block *blk = mir_get_block(ctx, idx);
2722 assert(blk);
2723
2724 quadword_offset += blk->quadword_count;
2725 }
2726 } else {
2727 /* Jump backwards */
2728
2729 for (int idx = br_block_idx; idx >= target_number; --idx) {
2730 midgard_block *blk = mir_get_block(ctx, idx);
2731 assert(blk);
2732
2733 quadword_offset -= blk->quadword_count;
2734 }
2735 }
2736
2737 /* Unconditional extended branches (far jumps)
2738 * have issues, so we always use a conditional
2739 * branch, setting the condition to always for
2740 * unconditional. For compact unconditional
2741 * branches, cond isn't used so it doesn't
2742 * matter what we pick. */
2743
2744 midgard_condition cond =
2745 !is_conditional ? midgard_condition_always :
2746 is_inverted ? midgard_condition_false :
2747 midgard_condition_true;
2748
2749 midgard_jmp_writeout_op op =
2750 is_discard ? midgard_jmp_writeout_op_discard :
2751 is_writeout ? midgard_jmp_writeout_op_writeout :
2752 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2753 midgard_jmp_writeout_op_branch_cond;
2754
2755 if (!is_compact) {
2756 midgard_branch_extended branch =
2757 midgard_create_branch_extended(
2758 cond, op,
2759 dest_tag,
2760 quadword_offset);
2761
2762 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2763 } else if (is_conditional || is_discard) {
2764 midgard_branch_cond branch = {
2765 .op = op,
2766 .dest_tag = dest_tag,
2767 .offset = quadword_offset,
2768 .cond = cond
2769 };
2770
2771 assert(branch.offset == quadword_offset);
2772
2773 memcpy(&ins->br_compact, &branch, sizeof(branch));
2774 } else {
2775 assert(op == midgard_jmp_writeout_op_branch_uncond);
2776
2777 midgard_branch_uncond branch = {
2778 .op = op,
2779 .dest_tag = dest_tag,
2780 .offset = quadword_offset,
2781 .unknown = 1
2782 };
2783
2784 assert(branch.offset == quadword_offset);
2785
2786 memcpy(&ins->br_compact, &branch, sizeof(branch));
2787 }
2788 }
2789 }
2790
2791 ++br_block_idx;
2792 }
2793
2794 /* Emit flat binary from the instruction arrays. Iterate each block in
2795 * sequence. Save instruction boundaries such that lookahead tags can
2796 * be assigned easily */
2797
2798 /* Cache _all_ bundles in source order for lookahead across failed branches */
2799
2800 int bundle_count = 0;
2801 mir_foreach_block(ctx, _block) {
2802 midgard_block *block = (midgard_block *) _block;
2803 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2804 }
2805 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2806 int bundle_idx = 0;
2807 mir_foreach_block(ctx, _block) {
2808 midgard_block *block = (midgard_block *) _block;
2809 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2810 source_order_bundles[bundle_idx++] = bundle;
2811 }
2812 }
2813
2814 int current_bundle = 0;
2815
2816 /* Midgard prefetches instruction types, so during emission we
2817 * need to lookahead. Unless this is the last instruction, in
2818 * which we return 1. */
2819
2820 mir_foreach_block(ctx, _block) {
2821 midgard_block *block = (midgard_block *) _block;
2822 mir_foreach_bundle_in_block(block, bundle) {
2823 int lookahead = 1;
2824
2825 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2826 lookahead = source_order_bundles[current_bundle + 1]->tag;
2827
2828 emit_binary_bundle(ctx, block, bundle, compiled, lookahead);
2829 ++current_bundle;
2830 }
2831
2832 /* TODO: Free deeper */
2833 //util_dynarray_fini(&block->instructions);
2834 }
2835
2836 free(source_order_bundles);
2837
2838 /* Report the very first tag executed */
2839 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2840
2841 /* Deal with off-by-one related to the fencepost problem */
2842 program->work_register_count = ctx->work_registers + 1;
2843 program->uniform_cutoff = ctx->uniform_cutoff;
2844
2845 program->blend_patch_offset = ctx->blend_constant_offset;
2846 program->tls_size = ctx->tls_size;
2847
2848 if (midgard_debug & MIDGARD_DBG_SHADERS)
2849 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2850
2851 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2852 unsigned nr_bundles = 0, nr_ins = 0;
2853
2854 /* Count instructions and bundles */
2855
2856 mir_foreach_block(ctx, _block) {
2857 midgard_block *block = (midgard_block *) _block;
2858 nr_bundles += util_dynarray_num_elements(
2859 &block->bundles, midgard_bundle);
2860
2861 mir_foreach_bundle_in_block(block, bun)
2862 nr_ins += bun->instruction_count;
2863 }
2864
2865 /* Calculate thread count. There are certain cutoffs by
2866 * register count for thread count */
2867
2868 unsigned nr_registers = program->work_register_count;
2869
2870 unsigned nr_threads =
2871 (nr_registers <= 4) ? 4 :
2872 (nr_registers <= 8) ? 2 :
2873 1;
2874
2875 /* Dump stats */
2876
2877 fprintf(stderr, "shader%d - %s shader: "
2878 "%u inst, %u bundles, %u quadwords, "
2879 "%u registers, %u threads, %u loops, "
2880 "%u:%u spills:fills\n",
2881 SHADER_DB_COUNT++,
2882 ctx->is_blend ? "PAN_SHADER_BLEND" :
2883 gl_shader_stage_name(ctx->stage),
2884 nr_ins, nr_bundles, ctx->quadword_count,
2885 nr_registers, nr_threads,
2886 ctx->loop_count,
2887 ctx->spills, ctx->fills);
2888 }
2889
2890 ralloc_free(ctx);
2891
2892 return 0;
2893 }