2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
63 unsigned SHADER_DB_COUNT
= 0;
65 int midgard_debug
= 0;
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 midgard_is_branch_unit(unsigned unit
)
75 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
79 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
85 for (unsigned i
= 0; i
< block
->nr_successors
; ++i
) {
86 if (block
->successors
[i
] == successor
)
90 block
->successors
[block
->nr_successors
++] = successor
;
91 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
94 /* Helpers to generate midgard_instruction's using macro magic, since every
95 * driver seems to do it that way */
97 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
99 #define M_LOAD_STORE(name, store) \
100 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
101 midgard_instruction i = { \
102 .type = TAG_LOAD_STORE_4, \
106 .src = { -1, -1, -1 }, \
109 .op = midgard_op_##name, \
110 .swizzle = SWIZZLE_XYZW, \
116 i.ssa_args.src[0] = ssa; \
118 i.ssa_args.dest = ssa; \
123 #define M_LOAD(name) M_LOAD_STORE(name, false)
124 #define M_STORE(name) M_LOAD_STORE(name, true)
126 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
127 * the corresponding Midgard source */
129 static midgard_vector_alu_src
130 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
131 bool half
, bool sext
)
133 if (!src
) return blank_alu_src
;
135 /* Figure out how many components there are so we can adjust the
136 * swizzle. Specifically we want to broadcast the last channel so
137 * things like ball2/3 work
140 if (broadcast_count
) {
141 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
143 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
144 src
->swizzle
[c
] = last_component
;
148 midgard_vector_alu_src alu_src
= {
152 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
156 alu_src
.mod
= midgard_int_normal
;
158 /* Sign/zero-extend if needed */
162 midgard_int_sign_extend
163 : midgard_int_zero_extend
;
166 /* These should have been lowered away */
167 assert(!(src
->abs
|| src
->negate
));
169 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
175 /* load/store instructions have both 32-bit and 16-bit variants, depending on
176 * whether we are using vectors composed of highp or mediump. At the moment, we
177 * don't support half-floats -- this requires changes in other parts of the
178 * compiler -- therefore the 16-bit versions are commented out. */
180 //M_LOAD(ld_attr_16);
182 //M_LOAD(ld_vary_16);
187 M_LOAD(ld_color_buffer_8
);
188 //M_STORE(st_vary_16);
190 M_LOAD(st_cubemap_coords
);
191 M_LOAD(ld_compute_id
);
193 static midgard_instruction
194 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
196 midgard_branch_cond branch
= {
204 memcpy(&compact
, &branch
, sizeof(branch
));
206 midgard_instruction ins
= {
208 .unit
= ALU_ENAB_BR_COMPACT
,
209 .prepacked_branch
= true,
210 .compact_branch
= true,
211 .br_compact
= compact
,
214 .src
= { -1, -1, -1 },
218 if (op
== midgard_jmp_writeout_op_writeout
)
224 static midgard_instruction
225 v_branch(bool conditional
, bool invert
)
227 midgard_instruction ins
= {
229 .unit
= ALU_ENAB_BRANCH
,
230 .compact_branch
= true,
232 .conditional
= conditional
,
233 .invert_conditional
= invert
237 .src
= { -1, -1, -1 },
244 static midgard_branch_extended
245 midgard_create_branch_extended( midgard_condition cond
,
246 midgard_jmp_writeout_op op
,
248 signed quadword_offset
)
250 /* The condition code is actually a LUT describing a function to
251 * combine multiple condition codes. However, we only support a single
252 * condition code at the moment, so we just duplicate over a bunch of
255 uint16_t duplicated_cond
=
265 midgard_branch_extended branch
= {
267 .dest_tag
= dest_tag
,
268 .offset
= quadword_offset
,
269 .cond
= duplicated_cond
276 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
278 ins
->has_constants
= true;
279 memcpy(&ins
->constants
, constants
, 16);
283 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
285 return glsl_count_attribute_slots(type
, false);
288 /* Lower fdot2 to a vector multiplication followed by channel addition */
290 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
292 if (alu
->op
!= nir_op_fdot2
)
295 b
->cursor
= nir_before_instr(&alu
->instr
);
297 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
298 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
300 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
302 nir_ssa_def
*sum
= nir_fadd(b
,
303 nir_channel(b
, product
, 0),
304 nir_channel(b
, product
, 1));
306 /* Replace the fdot2 with this sum */
307 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
311 midgard_sysval_for_ssbo(nir_intrinsic_instr
*instr
)
313 /* This is way too meta */
314 bool is_store
= instr
->intrinsic
== nir_intrinsic_store_ssbo
;
315 unsigned idx_idx
= is_store
? 1 : 0;
317 nir_src index
= instr
->src
[idx_idx
];
318 assert(nir_src_is_const(index
));
319 uint32_t uindex
= nir_src_as_uint(index
);
321 return PAN_SYSVAL(SSBO
, uindex
);
325 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
327 switch (instr
->intrinsic
) {
328 case nir_intrinsic_load_viewport_scale
:
329 return PAN_SYSVAL_VIEWPORT_SCALE
;
330 case nir_intrinsic_load_viewport_offset
:
331 return PAN_SYSVAL_VIEWPORT_OFFSET
;
332 case nir_intrinsic_load_num_work_groups
:
333 return PAN_SYSVAL_NUM_WORK_GROUPS
;
334 case nir_intrinsic_load_ssbo
:
335 case nir_intrinsic_store_ssbo
:
336 return midgard_sysval_for_ssbo(instr
);
342 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
345 nir_intrinsic_instr
*intr
;
346 nir_dest
*dst
= NULL
;
350 bool is_store
= false;
352 switch (instr
->type
) {
353 case nir_instr_type_intrinsic
:
354 intr
= nir_instr_as_intrinsic(instr
);
355 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
357 is_store
|= intr
->intrinsic
== nir_intrinsic_store_ssbo
;
359 case nir_instr_type_tex
:
360 tex
= nir_instr_as_tex(instr
);
361 if (tex
->op
!= nir_texop_txs
)
364 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
365 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
366 nir_tex_instr_dest_size(tex
) -
367 (tex
->is_array
? 1 : 0),
375 if (dest
&& dst
&& !is_store
)
376 *dest
= nir_dest_index(ctx
, dst
);
382 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
386 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
390 /* We have a sysval load; check if it's already been assigned */
392 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
395 /* It hasn't -- so assign it now! */
397 unsigned id
= ctx
->sysval_count
++;
398 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
399 ctx
->sysvals
[id
] = sysval
;
403 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
405 ctx
->sysval_count
= 0;
407 nir_foreach_function(function
, shader
) {
408 if (!function
->impl
) continue;
410 nir_foreach_block(block
, function
->impl
) {
411 nir_foreach_instr_safe(instr
, block
) {
412 midgard_nir_assign_sysval_body(ctx
, instr
);
419 midgard_nir_lower_fdot2(nir_shader
*shader
)
421 bool progress
= false;
423 nir_foreach_function(function
, shader
) {
424 if (!function
->impl
) continue;
427 nir_builder
*b
= &_b
;
428 nir_builder_init(b
, function
->impl
);
430 nir_foreach_block(block
, function
->impl
) {
431 nir_foreach_instr_safe(instr
, block
) {
432 if (instr
->type
!= nir_instr_type_alu
) continue;
434 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
435 midgard_nir_lower_fdot2_body(b
, alu
);
441 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
448 /* Flushes undefined values to zero */
451 optimise_nir(nir_shader
*nir
)
454 unsigned lower_flrp
=
455 (nir
->options
->lower_flrp16
? 16 : 0) |
456 (nir
->options
->lower_flrp32
? 32 : 0) |
457 (nir
->options
->lower_flrp64
? 64 : 0);
459 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
460 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
461 NIR_PASS(progress
, nir
, nir_lower_idiv
);
463 nir_lower_tex_options lower_tex_options
= {
464 .lower_txs_lod
= true,
468 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
473 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
474 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
476 NIR_PASS(progress
, nir
, nir_copy_prop
);
477 NIR_PASS(progress
, nir
, nir_opt_dce
);
478 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
479 NIR_PASS(progress
, nir
, nir_opt_cse
);
480 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
481 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
482 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
484 if (lower_flrp
!= 0) {
485 bool lower_flrp_progress
= false;
486 NIR_PASS(lower_flrp_progress
,
490 false /* always_precise */,
491 nir
->options
->lower_ffma
);
492 if (lower_flrp_progress
) {
493 NIR_PASS(progress
, nir
,
494 nir_opt_constant_folding
);
498 /* Nothing should rematerialize any flrps, so we only
499 * need to do this lowering once.
504 NIR_PASS(progress
, nir
, nir_opt_undef
);
505 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
507 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
510 nir_var_function_temp
);
512 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
515 /* Must be run at the end to prevent creation of fsin/fcos ops */
516 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
521 NIR_PASS(progress
, nir
, nir_opt_dce
);
522 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
523 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
524 NIR_PASS(progress
, nir
, nir_copy_prop
);
527 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
529 /* We implement booleans as 32-bit 0/~0 */
530 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
532 /* Now that booleans are lowered, we can run out late opts */
533 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
535 /* Lower mods for float ops only. Integer ops don't support modifiers
536 * (saturate doesn't make sense on integers, neg/abs require dedicated
539 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
540 NIR_PASS(progress
, nir
, nir_copy_prop
);
541 NIR_PASS(progress
, nir
, nir_opt_dce
);
543 /* Take us out of SSA */
544 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
545 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
547 /* We are a vector architecture; write combine where possible */
548 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
549 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
551 NIR_PASS(progress
, nir
, nir_opt_dce
);
554 /* Do not actually emit a load; instead, cache the constant for inlining */
557 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
559 nir_ssa_def def
= instr
->def
;
561 float *v
= rzalloc_array(NULL
, float, 4);
562 nir_const_load_to_arr(v
, instr
, f32
);
564 /* Shifted for SSA, +1 for off-by-one */
565 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, v
);
568 /* Normally constants are embedded implicitly, but for I/O and such we have to
569 * explicitly emit a move with the constant source */
572 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
574 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
576 if (constant_value
) {
577 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, to
);
578 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
579 emit_mir_instruction(ctx
, ins
);
584 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
586 unsigned comp
= src
->swizzle
[0];
588 for (unsigned c
= 1; c
< nr_components
; ++c
) {
589 if (src
->swizzle
[c
] != comp
)
596 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
597 * output of a conditional test) into that register */
600 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
602 int condition
= nir_src_index(ctx
, src
);
604 /* Source to swizzle the desired component into w */
606 const midgard_vector_alu_src alu_src
= {
607 .swizzle
= SWIZZLE(component
, component
, component
, component
),
610 /* There is no boolean move instruction. Instead, we simulate a move by
611 * ANDing the condition with itself to get it into r31.w */
613 midgard_instruction ins
= {
616 /* We need to set the conditional as close as possible */
617 .precede_break
= true,
618 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
619 .mask
= 1 << COMPONENT_W
,
622 .src
= { condition
, condition
, -1 },
623 .dest
= SSA_FIXED_REGISTER(31),
627 .op
= midgard_alu_op_iand
,
628 .outmod
= midgard_outmod_int_wrap
,
629 .reg_mode
= midgard_reg_mode_32
,
630 .dest_override
= midgard_dest_override_none
,
631 .src1
= vector_alu_srco_unsigned(alu_src
),
632 .src2
= vector_alu_srco_unsigned(alu_src
)
636 emit_mir_instruction(ctx
, ins
);
639 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
643 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
645 int condition
= nir_src_index(ctx
, &src
->src
);
647 /* Source to swizzle the desired component into w */
649 const midgard_vector_alu_src alu_src
= {
650 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
653 /* There is no boolean move instruction. Instead, we simulate a move by
654 * ANDing the condition with itself to get it into r31.w */
656 midgard_instruction ins
= {
658 .precede_break
= true,
659 .mask
= mask_of(nr_comp
),
661 .src
= { condition
, condition
, -1 },
662 .dest
= SSA_FIXED_REGISTER(31),
665 .op
= midgard_alu_op_iand
,
666 .outmod
= midgard_outmod_int_wrap
,
667 .reg_mode
= midgard_reg_mode_32
,
668 .dest_override
= midgard_dest_override_none
,
669 .src1
= vector_alu_srco_unsigned(alu_src
),
670 .src2
= vector_alu_srco_unsigned(alu_src
)
674 emit_mir_instruction(ctx
, ins
);
677 #define ALU_CASE(nir, _op) \
679 op = midgard_alu_op_##_op; \
680 assert(src_bitsize == dst_bitsize); \
683 #define ALU_CASE_BCAST(nir, _op, count) \
685 op = midgard_alu_op_##_op; \
686 broadcast_swizzle = count; \
687 assert(src_bitsize == dst_bitsize); \
690 nir_is_fzero_constant(nir_src src
)
692 if (!nir_src_is_const(src
))
695 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
696 if (nir_src_comp_as_float(src
, c
) != 0.0)
703 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
704 * special treatment override this anyway. */
706 static midgard_reg_mode
707 reg_mode_for_nir(nir_alu_instr
*instr
)
709 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
711 switch (src_bitsize
) {
713 return midgard_reg_mode_8
;
715 return midgard_reg_mode_16
;
717 return midgard_reg_mode_32
;
719 return midgard_reg_mode_64
;
721 unreachable("Invalid bit size");
726 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
728 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
729 * is handled elsewhere */
731 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
732 midgard_emit_derivatives(ctx
, instr
);
736 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
738 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
739 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
740 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
742 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
743 * supported. A few do not and are commented for now. Also, there are a
744 * number of NIR ops which Midgard does not support and need to be
745 * lowered, also TODO. This switch block emits the opcode and calling
746 * convention of the Midgard instruction; actual packing is done in
751 /* Number of components valid to check for the instruction (the rest
752 * will be forced to the last), or 0 to use as-is. Relevant as
753 * ball-type instructions have a channel count in NIR but are all vec4
756 unsigned broadcast_swizzle
= 0;
758 /* What register mode should we operate in? */
759 midgard_reg_mode reg_mode
=
760 reg_mode_for_nir(instr
);
762 /* Do we need a destination override? Used for inline
765 midgard_dest_override dest_override
=
766 midgard_dest_override_none
;
768 /* Should we use a smaller respective source and sign-extend? */
770 bool half_1
= false, sext_1
= false;
771 bool half_2
= false, sext_2
= false;
773 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
774 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
777 ALU_CASE(fadd
, fadd
);
778 ALU_CASE(fmul
, fmul
);
779 ALU_CASE(fmin
, fmin
);
780 ALU_CASE(fmax
, fmax
);
781 ALU_CASE(imin
, imin
);
782 ALU_CASE(imax
, imax
);
783 ALU_CASE(umin
, umin
);
784 ALU_CASE(umax
, umax
);
785 ALU_CASE(ffloor
, ffloor
);
786 ALU_CASE(fround_even
, froundeven
);
787 ALU_CASE(ftrunc
, ftrunc
);
788 ALU_CASE(fceil
, fceil
);
789 ALU_CASE(fdot3
, fdot3
);
790 ALU_CASE(fdot4
, fdot4
);
791 ALU_CASE(iadd
, iadd
);
792 ALU_CASE(isub
, isub
);
793 ALU_CASE(imul
, imul
);
795 /* Zero shoved as second-arg */
796 ALU_CASE(iabs
, iabsdiff
);
800 ALU_CASE(feq32
, feq
);
801 ALU_CASE(fne32
, fne
);
802 ALU_CASE(flt32
, flt
);
803 ALU_CASE(ieq32
, ieq
);
804 ALU_CASE(ine32
, ine
);
805 ALU_CASE(ilt32
, ilt
);
806 ALU_CASE(ult32
, ult
);
808 /* We don't have a native b2f32 instruction. Instead, like many
809 * GPUs, we exploit booleans as 0/~0 for false/true, and
810 * correspondingly AND
811 * by 1.0 to do the type conversion. For the moment, prime us
814 * iand [whatever], #0
816 * At the end of emit_alu (as MIR), we'll fix-up the constant
819 ALU_CASE(b2f32
, iand
);
820 ALU_CASE(b2i32
, iand
);
822 /* Likewise, we don't have a dedicated f2b32 instruction, but
823 * we can do a "not equal to 0.0" test. */
825 ALU_CASE(f2b32
, fne
);
826 ALU_CASE(i2b32
, ine
);
828 ALU_CASE(frcp
, frcp
);
829 ALU_CASE(frsq
, frsqrt
);
830 ALU_CASE(fsqrt
, fsqrt
);
831 ALU_CASE(fexp2
, fexp2
);
832 ALU_CASE(flog2
, flog2
);
834 ALU_CASE(f2i32
, f2i_rtz
);
835 ALU_CASE(f2u32
, f2u_rtz
);
836 ALU_CASE(i2f32
, i2f_rtz
);
837 ALU_CASE(u2f32
, u2f_rtz
);
839 ALU_CASE(f2i16
, f2i_rtz
);
840 ALU_CASE(f2u16
, f2u_rtz
);
841 ALU_CASE(i2f16
, i2f_rtz
);
842 ALU_CASE(u2f16
, u2f_rtz
);
844 ALU_CASE(fsin
, fsin
);
845 ALU_CASE(fcos
, fcos
);
847 /* We'll set invert */
848 ALU_CASE(inot
, imov
);
849 ALU_CASE(iand
, iand
);
851 ALU_CASE(ixor
, ixor
);
852 ALU_CASE(ishl
, ishl
);
853 ALU_CASE(ishr
, iasr
);
854 ALU_CASE(ushr
, ilsr
);
856 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
857 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
858 ALU_CASE(b32all_fequal4
, fball_eq
);
860 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
861 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
862 ALU_CASE(b32any_fnequal4
, fbany_neq
);
864 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
865 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
866 ALU_CASE(b32all_iequal4
, iball_eq
);
868 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
869 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
870 ALU_CASE(b32any_inequal4
, ibany_neq
);
872 /* Source mods will be shoved in later */
873 ALU_CASE(fabs
, fmov
);
874 ALU_CASE(fneg
, fmov
);
875 ALU_CASE(fsat
, fmov
);
877 /* For size conversion, we use a move. Ideally though we would squash
878 * these ops together; maybe that has to happen after in NIR as part of
879 * propagation...? An earlier algebraic pass ensured we step down by
880 * only / exactly one size. If stepping down, we use a dest override to
881 * reduce the size; if stepping up, we use a larger-sized move with a
882 * half source and a sign/zero-extension modifier */
887 /* If we end up upscale, we'll need a sign-extend on the
888 * operand (the second argument) */
894 op
= midgard_alu_op_imov
;
896 if (dst_bitsize
== (src_bitsize
* 2)) {
900 /* Use a greater register mode */
902 } else if (src_bitsize
== (dst_bitsize
* 2)) {
903 /* Converting down */
904 dest_override
= midgard_dest_override_lower
;
911 assert(src_bitsize
== 32);
913 op
= midgard_alu_op_fmov
;
914 dest_override
= midgard_dest_override_lower
;
919 assert(src_bitsize
== 16);
921 op
= midgard_alu_op_fmov
;
928 /* For greater-or-equal, we lower to less-or-equal and flip the
936 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
937 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
938 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
939 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
942 /* Swap via temporary */
943 nir_alu_src temp
= instr
->src
[1];
944 instr
->src
[1] = instr
->src
[0];
945 instr
->src
[0] = temp
;
950 case nir_op_b32csel
: {
951 /* Midgard features both fcsel and icsel, depending on
952 * the type of the arguments/output. However, as long
953 * as we're careful we can _always_ use icsel and
954 * _never_ need fcsel, since the latter does additional
955 * floating-point-specific processing whereas the
956 * former just moves bits on the wire. It's not obvious
957 * why these are separate opcodes, save for the ability
958 * to do things like sat/pos/abs/neg for free */
960 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
961 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
963 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
966 /* Emit the condition into r31 */
969 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
971 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
973 /* The condition is the first argument; move the other
974 * arguments up one to be a binary instruction for
977 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
982 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
987 /* Midgard can perform certain modifiers on output of an ALU op */
990 if (midgard_is_integer_out_op(op
)) {
991 outmod
= midgard_outmod_int_wrap
;
993 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
994 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
997 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
999 if (instr
->op
== nir_op_fmax
) {
1000 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
1001 op
= midgard_alu_op_fmov
;
1003 outmod
= midgard_outmod_pos
;
1004 instr
->src
[0] = instr
->src
[1];
1005 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1006 op
= midgard_alu_op_fmov
;
1008 outmod
= midgard_outmod_pos
;
1012 /* Fetch unit, quirks, etc information */
1013 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1014 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1016 /* src0 will always exist afaik, but src1 will not for 1-argument
1017 * instructions. The latter can only be fetched if the instruction
1018 * needs it, or else we may segfault. */
1020 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1021 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1023 /* Rather than use the instruction generation helpers, we do it
1024 * ourselves here to avoid the mess */
1026 midgard_instruction ins
= {
1030 quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1031 quirk_flipped_r24
? src0
: src1
,
1038 nir_alu_src
*nirmods
[2] = { NULL
};
1040 if (nr_inputs
== 2) {
1041 nirmods
[0] = &instr
->src
[0];
1042 nirmods
[1] = &instr
->src
[1];
1043 } else if (nr_inputs
== 1) {
1044 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1049 /* These were lowered to a move, so apply the corresponding mod */
1051 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1052 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
1054 if (instr
->op
== nir_op_fneg
)
1055 s
->negate
= !s
->negate
;
1057 if (instr
->op
== nir_op_fabs
)
1061 bool is_int
= midgard_is_integer_op(op
);
1063 ins
.mask
= mask_of(nr_components
);
1065 midgard_vector_alu alu
= {
1067 .reg_mode
= reg_mode
,
1068 .dest_override
= dest_override
,
1071 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1072 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1075 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1078 ins
.mask
&= instr
->dest
.write_mask
;
1082 /* Late fixup for emulated instructions */
1084 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1085 /* Presently, our second argument is an inline #0 constant.
1086 * Switch over to an embedded 1.0 constant (that can't fit
1087 * inline, since we're 32-bit, not 16-bit like the inline
1090 ins
.ssa_args
.inline_constant
= false;
1091 ins
.ssa_args
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1092 ins
.has_constants
= true;
1094 if (instr
->op
== nir_op_b2f32
) {
1095 ins
.constants
[0] = 1.0f
;
1097 /* Type pun it into place */
1099 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1102 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1103 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1104 /* Lots of instructions need a 0 plonked in */
1105 ins
.ssa_args
.inline_constant
= false;
1106 ins
.ssa_args
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1107 ins
.has_constants
= true;
1108 ins
.constants
[0] = 0.0f
;
1109 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1110 } else if (instr
->op
== nir_op_inot
) {
1114 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1115 /* To avoid duplicating the lookup tables (probably), true LUT
1116 * instructions can only operate as if they were scalars. Lower
1117 * them here by changing the component. */
1119 uint8_t original_swizzle
[4];
1120 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1121 unsigned orig_mask
= ins
.mask
;
1123 for (int i
= 0; i
< nr_components
; ++i
) {
1124 /* Mask the associated component, dropping the
1125 * instruction if needed */
1128 ins
.mask
&= orig_mask
;
1133 for (int j
= 0; j
< 4; ++j
)
1134 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1136 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, false));
1137 emit_mir_instruction(ctx
, ins
);
1140 emit_mir_instruction(ctx
, ins
);
1147 mir_mask_for_intr(nir_instr
*instr
, bool is_read
)
1149 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1152 return mask_of(nir_intrinsic_dest_components(intr
));
1154 return nir_intrinsic_write_mask(intr
);
1157 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1158 * optimized) versions of UBO #0 */
1160 midgard_instruction
*
1162 compiler_context
*ctx
,
1166 nir_src
*indirect_offset
,
1169 /* TODO: half-floats */
1171 midgard_instruction ins
= m_ld_ubo_int4(dest
, offset
);
1173 assert((offset
& 0xF) == 0);
1176 /* TODO: Don't split */
1177 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1178 ins
.load_store
.address
= offset
>> 3;
1179 ins
.mask
= mir_mask_for_intr(instr
, true);
1181 if (indirect_offset
) {
1182 ins
.ssa_args
.src
[1] = nir_src_index(ctx
, indirect_offset
);
1183 ins
.load_store
.arg_2
= 0x80;
1185 ins
.load_store
.arg_2
= 0x1E;
1188 ins
.load_store
.arg_1
= index
;
1190 return emit_mir_instruction(ctx
, ins
);
1193 /* SSBO reads are like UBO reads if you squint */
1197 compiler_context
*ctx
,
1202 nir_src
*indirect_offset
,
1207 midgard_instruction ins
;
1210 ins
= m_ld_int4(srcdest
, offset
);
1212 ins
= m_st_int4(srcdest
, offset
);
1214 /* SSBO reads use a generic memory read interface, so we need the
1215 * address of the SSBO as the first argument. This is a sysval. */
1217 unsigned addr
= make_compiler_temp(ctx
);
1218 emit_sysval_read(ctx
, instr
, addr
, 2);
1220 /* The source array is a bit of a leaky abstraction for SSBOs.
1221 * Nevertheless, for loads:
1227 * Whereas for stores:
1233 * We would like arg_1 = the address and
1234 * arg_2 = the offset.
1237 ins
.ssa_args
.src
[is_read
? 0 : 1] = addr
;
1239 /* TODO: What is this? It looks superficially like a shift << 5, but
1240 * arg_1 doesn't take a shift Should it be E0 or A0? */
1241 if (indirect_offset
)
1242 ins
.load_store
.arg_1
|= 0xE0;
1244 /* We also need to emit the indirect offset */
1246 if (indirect_offset
)
1247 ins
.ssa_args
.src
[is_read
? 1 : 2] = nir_src_index(ctx
, indirect_offset
);
1249 ins
.load_store
.arg_2
= 0x7E;
1251 /* TODO: Bounds check */
1253 /* Finally, we emit the direct offset */
1255 ins
.load_store
.varying_parameters
= (offset
& 0x1FF) << 1;
1256 ins
.load_store
.address
= (offset
>> 9);
1257 ins
.mask
= mir_mask_for_intr(instr
, is_read
);
1259 emit_mir_instruction(ctx
, ins
);
1264 compiler_context
*ctx
,
1265 unsigned dest
, unsigned offset
,
1266 unsigned nr_comp
, unsigned component
,
1267 nir_src
*indirect_offset
, nir_alu_type type
)
1269 /* XXX: Half-floats? */
1270 /* TODO: swizzle, mask */
1272 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1273 ins
.mask
= mask_of(nr_comp
);
1274 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1276 midgard_varying_parameter p
= {
1278 .interpolation
= midgard_interp_default
,
1279 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1283 memcpy(&u
, &p
, sizeof(p
));
1284 ins
.load_store
.varying_parameters
= u
;
1286 if (indirect_offset
)
1287 ins
.ssa_args
.src
[1] = nir_src_index(ctx
, indirect_offset
);
1289 ins
.load_store
.arg_2
= 0x1E;
1291 ins
.load_store
.arg_1
= 0x9E;
1293 /* Use the type appropriate load */
1297 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1300 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1302 case nir_type_float
:
1303 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1306 unreachable("Attempted to load unknown type");
1310 emit_mir_instruction(ctx
, ins
);
1314 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
, signed dest_override
,
1315 unsigned nr_components
)
1319 /* Figure out which uniform this is */
1320 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1321 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1323 if (dest_override
>= 0)
1324 dest
= dest_override
;
1326 /* Sysvals are prefix uniforms */
1327 unsigned uniform
= ((uintptr_t) val
) - 1;
1329 /* Emit the read itself -- this is never indirect */
1330 midgard_instruction
*ins
=
1331 emit_ubo_read(ctx
, instr
, dest
, uniform
* 16, NULL
, 0);
1333 ins
->mask
= mask_of(nr_components
);
1337 compute_builtin_arg(nir_op op
)
1340 case nir_intrinsic_load_work_group_id
:
1342 case nir_intrinsic_load_local_invocation_id
:
1345 unreachable("Invalid compute paramater loaded");
1349 /* Emit store for a fragment shader, which is encoded via a fancy branch. TODO:
1350 * Handle MRT here */
1353 emit_fragment_store(compiler_context
*ctx
, unsigned src
, unsigned rt
)
1355 /* First, move in whatever we're outputting */
1356 midgard_instruction move
= v_mov(src
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1358 /* Force a tight schedule. TODO: Make the scheduler MRT aware */
1359 move
.unit
= UNIT_VMUL
;
1360 move
.precede_break
= true;
1361 move
.dont_eliminate
= true;
1364 emit_mir_instruction(ctx
, move
);
1366 /* If we're doing MRT, we need to specify the render target */
1368 midgard_instruction rt_move
= {
1375 /* We'll write to r1.z */
1376 rt_move
= v_mov(-1, blank_alu_src
, SSA_FIXED_REGISTER(1));
1377 rt_move
.mask
= 1 << COMPONENT_Z
;
1378 rt_move
.unit
= UNIT_SADD
;
1380 /* r1.z = (rt * 0x100) */
1381 rt_move
.ssa_args
.inline_constant
= true;
1382 rt_move
.inline_constant
= (rt
* 0x100);
1385 ctx
->work_registers
= MAX2(ctx
->work_registers
, 1);
1388 emit_mir_instruction(ctx
, rt_move
);
1391 /* Next, generate the branch. For R render targets in the writeout, the
1392 * i'th render target jumps to pseudo-offset [2(R-1) + i] */
1394 unsigned offset
= (2 * (ctx
->nir
->num_outputs
- 1)) + rt
;
1396 struct midgard_instruction ins
=
1397 v_alu_br_compact_cond(midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, offset
, midgard_condition_always
);
1399 /* Add dependencies */
1400 ins
.ssa_args
.src
[0] = move
.ssa_args
.dest
;
1401 ins
.ssa_args
.src
[1] = rt_move
.ssa_args
.dest
;
1403 /* Emit the branch */
1404 emit_mir_instruction(ctx
, ins
);
1408 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1410 unsigned reg
= nir_dest_index(ctx
, &instr
->dest
);
1411 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1412 ins
.mask
= mask_of(3);
1413 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1414 emit_mir_instruction(ctx
, ins
);
1417 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1419 unsigned offset
= 0, reg
;
1421 switch (instr
->intrinsic
) {
1422 case nir_intrinsic_discard_if
:
1423 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1427 case nir_intrinsic_discard
: {
1428 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1429 struct midgard_instruction discard
= v_branch(conditional
, false);
1430 discard
.branch
.target_type
= TARGET_DISCARD
;
1431 emit_mir_instruction(ctx
, discard
);
1435 case nir_intrinsic_load_uniform
:
1436 case nir_intrinsic_load_ubo
:
1437 case nir_intrinsic_load_ssbo
:
1438 case nir_intrinsic_load_input
: {
1439 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1440 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1441 bool is_ssbo
= instr
->intrinsic
== nir_intrinsic_load_ssbo
;
1443 /* Get the base type of the intrinsic */
1444 /* TODO: Infer type? Does it matter? */
1446 (is_ubo
|| is_ssbo
) ? nir_type_uint
: nir_intrinsic_type(instr
);
1447 t
= nir_alu_type_get_base_type(t
);
1449 if (!(is_ubo
|| is_ssbo
)) {
1450 offset
= nir_intrinsic_base(instr
);
1453 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1455 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1457 bool direct
= nir_src_is_const(*src_offset
);
1458 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1461 offset
+= nir_src_as_uint(*src_offset
);
1463 /* We may need to apply a fractional offset */
1464 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1465 nir_intrinsic_component(instr
) : 0;
1466 reg
= nir_dest_index(ctx
, &instr
->dest
);
1468 if (is_uniform
&& !ctx
->is_blend
) {
1469 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysval_count
+ offset
) * 16, indirect_offset
, 0);
1470 } else if (is_ubo
) {
1471 nir_src index
= instr
->src
[0];
1473 /* We don't yet support indirect UBOs. For indirect
1474 * block numbers (if that's possible), we don't know
1475 * enough about the hardware yet. For indirect sources,
1476 * we know what we need but we need to add some NIR
1477 * support for lowering correctly with respect to
1480 assert(nir_src_is_const(index
));
1481 assert(nir_src_is_const(*src_offset
));
1483 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1484 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, NULL
, uindex
);
1485 } else if (is_ssbo
) {
1486 nir_src index
= instr
->src
[0];
1487 assert(nir_src_is_const(index
));
1488 uint32_t uindex
= nir_src_as_uint(index
);
1490 emit_ssbo_access(ctx
, &instr
->instr
, true, reg
, offset
, indirect_offset
, uindex
);
1491 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1492 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
, t
);
1493 } else if (ctx
->is_blend
) {
1494 /* For blend shaders, load the input color, which is
1495 * preloaded to r0 */
1497 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), blank_alu_src
, reg
);
1498 emit_mir_instruction(ctx
, move
);
1499 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1500 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1501 ins
.load_store
.arg_1
= 0x1E;
1502 ins
.load_store
.arg_2
= 0x1E;
1503 ins
.mask
= mask_of(nr_comp
);
1505 /* Use the type appropriate load */
1509 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1512 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1514 case nir_type_float
:
1515 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1518 unreachable("Attempted to load unknown type");
1522 emit_mir_instruction(ctx
, ins
);
1524 DBG("Unknown load\n");
1531 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1533 case nir_intrinsic_load_raw_output_pan
:
1534 reg
= nir_dest_index(ctx
, &instr
->dest
);
1535 assert(ctx
->is_blend
);
1537 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1538 emit_mir_instruction(ctx
, ins
);
1541 case nir_intrinsic_load_blend_const_color_rgba
: {
1542 assert(ctx
->is_blend
);
1543 reg
= nir_dest_index(ctx
, &instr
->dest
);
1545 /* Blend constants are embedded directly in the shader and
1546 * patched in, so we use some magic routing */
1548 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1549 ins
.has_constants
= true;
1550 ins
.has_blend_constant
= true;
1551 emit_mir_instruction(ctx
, ins
);
1555 case nir_intrinsic_store_output
:
1556 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1558 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1560 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1562 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1563 /* Determine number of render targets */
1564 emit_fragment_store(ctx
, reg
, offset
);
1565 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1566 /* We should have been vectorized, though we don't
1567 * currently check that st_vary is emitted only once
1568 * per slot (this is relevant, since there's not a mask
1569 * parameter available on the store [set to 0 by the
1570 * blob]). We do respect the component by adjusting the
1571 * swizzle. If this is a constant source, we'll need to
1572 * emit that explicitly. */
1574 emit_explicit_constant(ctx
, reg
, reg
);
1576 unsigned component
= nir_intrinsic_component(instr
);
1578 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1579 st
.load_store
.arg_1
= 0x9E;
1580 st
.load_store
.arg_2
= 0x1E;
1581 st
.load_store
.swizzle
= SWIZZLE_XYZW
<< (2*component
);
1582 emit_mir_instruction(ctx
, st
);
1584 DBG("Unknown store\n");
1590 /* Special case of store_output for lowered blend shaders */
1591 case nir_intrinsic_store_raw_output_pan
:
1592 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1593 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1594 emit_fragment_store(ctx
, reg
, 0);
1598 case nir_intrinsic_store_ssbo
:
1599 assert(nir_src_is_const(instr
->src
[1]));
1601 bool direct_offset
= nir_src_is_const(instr
->src
[2]);
1602 offset
= direct_offset
? nir_src_as_uint(instr
->src
[2]) : 0;
1603 nir_src
*indirect_offset
= direct_offset
? NULL
: &instr
->src
[2];
1604 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1606 uint32_t uindex
= nir_src_as_uint(instr
->src
[1]);
1608 emit_explicit_constant(ctx
, reg
, reg
);
1609 emit_ssbo_access(ctx
, &instr
->instr
, false, reg
, offset
, indirect_offset
, uindex
);
1612 case nir_intrinsic_load_alpha_ref_float
:
1613 assert(instr
->dest
.is_ssa
);
1615 float ref_value
= ctx
->alpha_ref
;
1617 /* See emit_load_const */
1618 float *v
= ralloc_array(NULL
, float, 4);
1619 memcpy(v
, &ref_value
, sizeof(float));
1620 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (instr
->dest
.ssa
.index
<< 1) + 1, v
);
1623 case nir_intrinsic_load_viewport_scale
:
1624 case nir_intrinsic_load_viewport_offset
:
1625 case nir_intrinsic_load_num_work_groups
:
1626 emit_sysval_read(ctx
, &instr
->instr
, -1, 3);
1629 case nir_intrinsic_load_work_group_id
:
1630 case nir_intrinsic_load_local_invocation_id
:
1631 emit_compute_builtin(ctx
, instr
);
1635 printf ("Unhandled intrinsic\n");
1642 midgard_tex_format(enum glsl_sampler_dim dim
)
1645 case GLSL_SAMPLER_DIM_1D
:
1646 case GLSL_SAMPLER_DIM_BUF
:
1649 case GLSL_SAMPLER_DIM_2D
:
1650 case GLSL_SAMPLER_DIM_EXTERNAL
:
1651 case GLSL_SAMPLER_DIM_RECT
:
1654 case GLSL_SAMPLER_DIM_3D
:
1657 case GLSL_SAMPLER_DIM_CUBE
:
1658 return MALI_TEX_CUBE
;
1661 DBG("Unknown sampler dim type\n");
1667 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1671 pan_attach_constant_bias(
1672 compiler_context
*ctx
,
1674 midgard_texture_word
*word
)
1676 /* To attach as constant, it has to *be* constant */
1678 if (!nir_src_is_const(lod
))
1681 float f
= nir_src_as_float(lod
);
1683 /* Break into fixed-point */
1685 float lod_frac
= f
- lod_int
;
1687 /* Carry over negative fractions */
1688 if (lod_frac
< 0.0) {
1694 word
->bias
= float_to_ubyte(lod_frac
);
1695 word
->bias_int
= lod_int
;
1700 static enum mali_sampler_type
1701 midgard_sampler_type(nir_alu_type t
) {
1702 switch (nir_alu_type_get_base_type(t
))
1704 case nir_type_float
:
1705 return MALI_SAMPLER_FLOAT
;
1707 return MALI_SAMPLER_SIGNED
;
1709 return MALI_SAMPLER_UNSIGNED
;
1711 unreachable("Unknown sampler type");
1716 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1717 unsigned midgard_texop
)
1720 //assert (!instr->sampler);
1721 //assert (!instr->texture_array_size);
1723 int texture_index
= instr
->texture_index
;
1724 int sampler_index
= texture_index
;
1726 /* No helper to build texture words -- we do it all here */
1727 midgard_instruction ins
= {
1728 .type
= TAG_TEXTURE_4
,
1731 .dest
= nir_dest_index(ctx
, &instr
->dest
),
1732 .src
= { -1, -1, -1 },
1735 .op
= midgard_texop
,
1736 .format
= midgard_tex_format(instr
->sampler_dim
),
1737 .texture_handle
= texture_index
,
1738 .sampler_handle
= sampler_index
,
1739 .swizzle
= SWIZZLE_XYZW
,
1740 .in_reg_swizzle
= SWIZZLE_XYZW
,
1746 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1750 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1751 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1752 midgard_vector_alu_src alu_src
= blank_alu_src
;
1754 switch (instr
->src
[i
].src_type
) {
1755 case nir_tex_src_coord
: {
1756 emit_explicit_constant(ctx
, index
, index
);
1758 /* Texelfetch coordinates uses all four elements
1759 * (xyz/index) regardless of texture dimensionality,
1760 * which means it's necessary to zero the unused
1761 * components to keep everything happy */
1763 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1764 unsigned old_index
= index
;
1766 index
= make_compiler_temp(ctx
);
1768 /* mov index, old_index */
1769 midgard_instruction mov
= v_mov(old_index
, blank_alu_src
, index
);
1771 emit_mir_instruction(ctx
, mov
);
1773 /* mov index.zw, #0 */
1774 mov
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
),
1775 blank_alu_src
, index
);
1776 mov
.has_constants
= true;
1777 mov
.mask
= (1 << COMPONENT_Z
) | (1 << COMPONENT_W
);
1778 emit_mir_instruction(ctx
, mov
);
1781 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1782 /* texelFetch is undefined on samplerCube */
1783 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1785 /* For cubemaps, we use a special ld/st op to
1786 * select the face and copy the xy into the
1787 * texture register */
1789 unsigned temp
= make_compiler_temp(ctx
);
1790 midgard_instruction st
= m_st_cubemap_coords(temp
, 0);
1791 st
.ssa_args
.src
[0] = index
;
1792 st
.mask
= 0x3; /* xy */
1793 st
.load_store
.arg_1
= 0x20;
1794 st
.load_store
.swizzle
= alu_src
.swizzle
;
1795 emit_mir_instruction(ctx
, st
);
1797 ins
.ssa_args
.src
[0] = temp
;
1799 ins
.ssa_args
.src
[0] = index
;
1802 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1803 /* Array component in w but NIR wants it in z */
1804 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYZZ
;
1810 case nir_tex_src_bias
:
1811 case nir_tex_src_lod
: {
1812 /* Try as a constant if we can */
1814 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1815 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1818 ins
.texture
.lod_register
= true;
1819 ins
.ssa_args
.src
[1] = index
;
1820 emit_explicit_constant(ctx
, index
, index
);
1826 unreachable("Unknown texture source type\n");
1830 emit_mir_instruction(ctx
, ins
);
1832 /* Used for .cont and .last hinting */
1833 ctx
->texture_op_count
++;
1837 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1839 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1840 * generic tex in some cases (which confuses the hardware) */
1842 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1844 if (is_vertex
&& instr
->op
== nir_texop_tex
)
1845 instr
->op
= nir_texop_txl
;
1847 switch (instr
->op
) {
1850 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1853 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1856 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1859 emit_sysval_read(ctx
, &instr
->instr
, -1, 4);
1862 unreachable("Unhanlded texture op");
1867 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1869 switch (instr
->type
) {
1870 case nir_jump_break
: {
1871 /* Emit a branch out of the loop */
1872 struct midgard_instruction br
= v_branch(false, false);
1873 br
.branch
.target_type
= TARGET_BREAK
;
1874 br
.branch
.target_break
= ctx
->current_loop_depth
;
1875 emit_mir_instruction(ctx
, br
);
1880 DBG("Unknown jump type %d\n", instr
->type
);
1886 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1888 switch (instr
->type
) {
1889 case nir_instr_type_load_const
:
1890 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1893 case nir_instr_type_intrinsic
:
1894 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1897 case nir_instr_type_alu
:
1898 emit_alu(ctx
, nir_instr_as_alu(instr
));
1901 case nir_instr_type_tex
:
1902 emit_tex(ctx
, nir_instr_as_tex(instr
));
1905 case nir_instr_type_jump
:
1906 emit_jump(ctx
, nir_instr_as_jump(instr
));
1909 case nir_instr_type_ssa_undef
:
1914 DBG("Unhandled instruction type\n");
1920 /* ALU instructions can inline or embed constants, which decreases register
1921 * pressure and saves space. */
1923 #define CONDITIONAL_ATTACH(src) { \
1924 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1927 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1928 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1933 inline_alu_constants(compiler_context
*ctx
)
1935 mir_foreach_instr(ctx
, alu
) {
1936 /* Other instructions cannot inline constants */
1937 if (alu
->type
!= TAG_ALU_4
) continue;
1939 /* If there is already a constant here, we can do nothing */
1940 if (alu
->has_constants
) continue;
1942 CONDITIONAL_ATTACH(src
[0]);
1944 if (!alu
->has_constants
) {
1945 CONDITIONAL_ATTACH(src
[1])
1946 } else if (!alu
->inline_constant
) {
1947 /* Corner case: _two_ vec4 constants, for instance with a
1948 * csel. For this case, we can only use a constant
1949 * register for one, we'll have to emit a move for the
1950 * other. Note, if both arguments are constants, then
1951 * necessarily neither argument depends on the value of
1952 * any particular register. As the destination register
1953 * will be wiped, that means we can spill the constant
1954 * to the destination register.
1957 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src
[1] + 1);
1958 unsigned scratch
= alu
->ssa_args
.dest
;
1961 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1962 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src
[1] + 1);
1964 /* Force a break XXX Defer r31 writes */
1965 ins
.unit
= UNIT_VLUT
;
1967 /* Set the source */
1968 alu
->ssa_args
.src
[1] = scratch
;
1970 /* Inject us -before- the last instruction which set r31 */
1971 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1977 /* Being a little silly with the names, but returns the op that is the bitwise
1978 * inverse of the op with the argument switched. I.e. (f and g are
1981 * f(a, b) = ~g(b, a)
1983 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
1985 * f(a, b) = ~g(b, a)
1986 * ~f(a, b) = g(b, a)
1987 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
1990 * Thus we define this function in pairs.
1993 static inline midgard_alu_op
1994 mir_contrapositive(midgard_alu_op op
)
1997 case midgard_alu_op_flt
:
1998 return midgard_alu_op_fle
;
1999 case midgard_alu_op_fle
:
2000 return midgard_alu_op_flt
;
2002 case midgard_alu_op_ilt
:
2003 return midgard_alu_op_ile
;
2004 case midgard_alu_op_ile
:
2005 return midgard_alu_op_ilt
;
2008 unreachable("No known contrapositive");
2012 /* Midgard supports two types of constants, embedded constants (128-bit) and
2013 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2014 * constants can be demoted to inline constants, for space savings and
2015 * sometimes a performance boost */
2018 embedded_to_inline_constant(compiler_context
*ctx
)
2020 mir_foreach_instr(ctx
, ins
) {
2021 if (!ins
->has_constants
) continue;
2023 if (ins
->ssa_args
.inline_constant
) continue;
2025 /* Blend constants must not be inlined by definition */
2026 if (ins
->has_blend_constant
) continue;
2028 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2029 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
2030 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
2032 if (!(is_16
|| is_32
))
2035 /* src1 cannot be an inline constant due to encoding
2036 * restrictions. So, if possible we try to flip the arguments
2039 int op
= ins
->alu
.op
;
2041 if (ins
->ssa_args
.src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2042 bool flip
= alu_opcode_props
[op
].props
& OP_COMMUTES
;
2045 /* Conditionals can be inverted */
2046 case midgard_alu_op_flt
:
2047 case midgard_alu_op_ilt
:
2048 case midgard_alu_op_fle
:
2049 case midgard_alu_op_ile
:
2050 ins
->alu
.op
= mir_contrapositive(ins
->alu
.op
);
2055 case midgard_alu_op_fcsel
:
2056 case midgard_alu_op_icsel
:
2057 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
2063 /* Flip the SSA numbers */
2064 ins
->ssa_args
.src
[0] = ins
->ssa_args
.src
[1];
2065 ins
->ssa_args
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2067 /* And flip the modifiers */
2071 src_temp
= ins
->alu
.src2
;
2072 ins
->alu
.src2
= ins
->alu
.src1
;
2073 ins
->alu
.src1
= src_temp
;
2077 if (ins
->ssa_args
.src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2078 /* Extract the source information */
2080 midgard_vector_alu_src
*src
;
2081 int q
= ins
->alu
.src2
;
2082 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2085 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2086 int component
= src
->swizzle
& 3;
2088 /* Scale constant appropriately, if we can legally */
2089 uint16_t scaled_constant
= 0;
2091 if (midgard_is_integer_op(op
) || is_16
) {
2092 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2093 scaled_constant
= (uint16_t) iconstants
[component
];
2095 /* Constant overflow after resize */
2096 if (scaled_constant
!= iconstants
[component
])
2099 float original
= (float) ins
->constants
[component
];
2100 scaled_constant
= _mesa_float_to_half(original
);
2102 /* Check for loss of precision. If this is
2103 * mediump, we don't care, but for a highp
2104 * shader, we need to pay attention. NIR
2105 * doesn't yet tell us which mode we're in!
2106 * Practically this prevents most constants
2107 * from being inlined, sadly. */
2109 float fp32
= _mesa_half_to_float(scaled_constant
);
2111 if (fp32
!= original
)
2115 /* We don't know how to handle these with a constant */
2117 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
2118 DBG("Bailing inline constant...\n");
2122 /* Make sure that the constant is not itself a
2123 * vector by checking if all accessed values
2124 * (by the swizzle) are the same. */
2126 uint32_t *cons
= (uint32_t *) ins
->constants
;
2127 uint32_t value
= cons
[component
];
2129 bool is_vector
= false;
2130 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2132 for (int c
= 1; c
< 4; ++c
) {
2133 /* We only care if this component is actually used */
2134 if (!(mask
& (1 << c
)))
2137 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2139 if (test
!= value
) {
2148 /* Get rid of the embedded constant */
2149 ins
->has_constants
= false;
2150 ins
->ssa_args
.src
[1] = -1;
2151 ins
->ssa_args
.inline_constant
= true;
2152 ins
->inline_constant
= scaled_constant
;
2157 /* Dead code elimination for branches at the end of a block - only one branch
2158 * per block is legal semantically */
2161 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2163 bool branched
= false;
2165 mir_foreach_instr_in_block_safe(block
, ins
) {
2166 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2168 /* We ignore prepacked branches since the fragment epilogue is
2169 * just generally special */
2170 if (ins
->prepacked_branch
) continue;
2172 /* Discards are similarly special and may not correspond to the
2175 if (ins
->branch
.target_type
== TARGET_DISCARD
) continue;
2178 /* We already branched, so this is dead */
2179 mir_remove_instruction(ins
);
2186 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2187 * the move can be propagated away entirely */
2190 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2193 if (comp
== midgard_outmod_none
)
2196 if (*outmod
== midgard_outmod_none
) {
2201 /* TODO: Compose rules */
2206 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2208 bool progress
= false;
2210 mir_foreach_instr_in_block_safe(block
, ins
) {
2211 if (ins
->type
!= TAG_ALU_4
) continue;
2212 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2213 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2215 /* TODO: Registers? */
2216 unsigned src
= ins
->ssa_args
.src
[1];
2217 if (src
& IS_REG
) continue;
2218 assert(!mir_has_multiple_writes(ctx
, src
));
2220 /* There might be a source modifier, too */
2221 if (mir_nontrivial_source2_mod(ins
)) continue;
2223 /* Backpropagate the modifier */
2224 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2225 if (v
->type
!= TAG_ALU_4
) continue;
2226 if (v
->ssa_args
.dest
!= src
) continue;
2228 /* Can we even take a float outmod? */
2229 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2231 midgard_outmod_float temp
= v
->alu
.outmod
;
2232 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2234 /* Throw in the towel.. */
2235 if (!progress
) break;
2237 /* Otherwise, transfer the modifier */
2238 v
->alu
.outmod
= temp
;
2239 ins
->alu
.outmod
= midgard_outmod_none
;
2249 emit_fragment_epilogue(compiler_context
*ctx
)
2251 /* Just emit the last chunk with the branch */
2252 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2255 static midgard_block
*
2256 emit_block(compiler_context
*ctx
, nir_block
*block
)
2258 midgard_block
*this_block
= ctx
->after_block
;
2259 ctx
->after_block
= NULL
;
2262 this_block
= rzalloc(ctx
, midgard_block
);
2264 list_addtail(&this_block
->link
, &ctx
->blocks
);
2266 this_block
->is_scheduled
= false;
2269 ctx
->texture_index
[0] = -1;
2270 ctx
->texture_index
[1] = -1;
2272 /* Set up current block */
2273 list_inithead(&this_block
->instructions
);
2274 ctx
->current_block
= this_block
;
2276 nir_foreach_instr(instr
, block
) {
2277 emit_instr(ctx
, instr
);
2278 ++ctx
->instruction_count
;
2281 inline_alu_constants(ctx
);
2282 embedded_to_inline_constant(ctx
);
2284 /* Append fragment shader epilogue (value writeout) */
2285 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2286 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2287 emit_fragment_epilogue(ctx
);
2291 /* Allow the next control flow to access us retroactively, for
2293 ctx
->current_block
= this_block
;
2298 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2301 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2303 midgard_block
*before_block
= ctx
->current_block
;
2305 /* Conditional branches expect the condition in r31.w; emit a move for
2306 * that in the _previous_ block (which is the current block). */
2307 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2309 /* Speculatively emit the branch, but we can't fill it in until later */
2310 EMIT(branch
, true, true);
2311 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2313 /* Emit the two subblocks. */
2314 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2315 midgard_block
*end_then_block
= ctx
->current_block
;
2317 /* Emit a jump from the end of the then block to the end of the else */
2318 EMIT(branch
, false, false);
2319 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2321 /* Emit second block, and check if it's empty */
2323 int else_idx
= ctx
->block_count
;
2324 int count_in
= ctx
->instruction_count
;
2325 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2326 midgard_block
*end_else_block
= ctx
->current_block
;
2327 int after_else_idx
= ctx
->block_count
;
2329 /* Now that we have the subblocks emitted, fix up the branches */
2334 if (ctx
->instruction_count
== count_in
) {
2335 /* The else block is empty, so don't emit an exit jump */
2336 mir_remove_instruction(then_exit
);
2337 then_branch
->branch
.target_block
= after_else_idx
;
2339 then_branch
->branch
.target_block
= else_idx
;
2340 then_exit
->branch
.target_block
= after_else_idx
;
2343 /* Wire up the successors */
2345 ctx
->after_block
= rzalloc(ctx
, midgard_block
);
2347 midgard_block_add_successor(before_block
, then_block
);
2348 midgard_block_add_successor(before_block
, else_block
);
2350 midgard_block_add_successor(end_then_block
, ctx
->after_block
);
2351 midgard_block_add_successor(end_else_block
, ctx
->after_block
);
2355 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2357 /* Remember where we are */
2358 midgard_block
*start_block
= ctx
->current_block
;
2360 /* Allocate a loop number, growing the current inner loop depth */
2361 int loop_idx
= ++ctx
->current_loop_depth
;
2363 /* Get index from before the body so we can loop back later */
2364 int start_idx
= ctx
->block_count
;
2366 /* Emit the body itself */
2367 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2369 /* Branch back to loop back */
2370 struct midgard_instruction br_back
= v_branch(false, false);
2371 br_back
.branch
.target_block
= start_idx
;
2372 emit_mir_instruction(ctx
, br_back
);
2374 /* Mark down that branch in the graph. */
2375 midgard_block_add_successor(start_block
, loop_block
);
2376 midgard_block_add_successor(ctx
->current_block
, loop_block
);
2378 /* Find the index of the block about to follow us (note: we don't add
2379 * one; blocks are 0-indexed so we get a fencepost problem) */
2380 int break_block_idx
= ctx
->block_count
;
2382 /* Fix up the break statements we emitted to point to the right place,
2383 * now that we can allocate a block number for them */
2384 ctx
->after_block
= rzalloc(ctx
, midgard_block
);
2386 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2387 mir_foreach_instr_in_block(block
, ins
) {
2388 if (ins
->type
!= TAG_ALU_4
) continue;
2389 if (!ins
->compact_branch
) continue;
2390 if (ins
->prepacked_branch
) continue;
2392 /* We found a branch -- check the type to see if we need to do anything */
2393 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2395 /* It's a break! Check if it's our break */
2396 if (ins
->branch
.target_break
!= loop_idx
) continue;
2398 /* Okay, cool, we're breaking out of this loop.
2399 * Rewrite from a break to a goto */
2401 ins
->branch
.target_type
= TARGET_GOTO
;
2402 ins
->branch
.target_block
= break_block_idx
;
2404 midgard_block_add_successor(block
, ctx
->after_block
);
2408 /* Now that we've finished emitting the loop, free up the depth again
2409 * so we play nice with recursion amid nested loops */
2410 --ctx
->current_loop_depth
;
2412 /* Dump loop stats */
2416 static midgard_block
*
2417 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2419 midgard_block
*start_block
= NULL
;
2421 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2422 switch (node
->type
) {
2423 case nir_cf_node_block
: {
2424 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2427 start_block
= block
;
2432 case nir_cf_node_if
:
2433 emit_if(ctx
, nir_cf_node_as_if(node
));
2436 case nir_cf_node_loop
:
2437 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2440 case nir_cf_node_function
:
2449 /* Due to lookahead, we need to report the first tag executed in the command
2450 * stream and in branch targets. An initial block might be empty, so iterate
2451 * until we find one that 'works' */
2454 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2456 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2458 unsigned first_tag
= 0;
2460 mir_foreach_block_from(ctx
, initial_block
, v
) {
2461 midgard_bundle
*initial_bundle
=
2462 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2464 if (initial_bundle
) {
2465 first_tag
= initial_bundle
->tag
;
2474 midgard_compile_shader_nir(struct midgard_screen
*screen
, nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2476 struct util_dynarray
*compiled
= &program
->compiled
;
2478 midgard_debug
= debug_get_option_midgard_debug();
2480 /* TODO: Bound against what? */
2481 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2484 ctx
->screen
= screen
;
2485 ctx
->stage
= nir
->info
.stage
;
2486 ctx
->is_blend
= is_blend
;
2487 ctx
->alpha_ref
= program
->alpha_ref
;
2489 /* Start off with a safe cutoff, allowing usage of all 16 work
2490 * registers. Later, we'll promote uniform reads to uniform registers
2491 * if we determine it is beneficial to do so */
2492 ctx
->uniform_cutoff
= 8;
2494 /* Initialize at a global (not block) level hash tables */
2496 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2497 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2498 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2500 /* Record the varying mapping for the command stream's bookkeeping */
2502 struct exec_list
*varyings
=
2503 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2505 unsigned max_varying
= 0;
2506 nir_foreach_variable(var
, varyings
) {
2507 unsigned loc
= var
->data
.driver_location
;
2508 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2510 for (int c
= 0; c
< sz
; ++c
) {
2511 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2512 max_varying
= MAX2(max_varying
, loc
+ c
);
2516 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2517 * (so we don't accidentally duplicate the epilogue since mesa/st has
2518 * messed with our I/O quite a bit already) */
2520 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2522 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2523 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2524 NIR_PASS_V(nir
, nir_clamp_psiz
, 1.0, 1024.0);
2527 NIR_PASS_V(nir
, nir_lower_var_copies
);
2528 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2529 NIR_PASS_V(nir
, nir_split_var_copies
);
2530 NIR_PASS_V(nir
, nir_lower_var_copies
);
2531 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2532 NIR_PASS_V(nir
, nir_lower_var_copies
);
2533 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2535 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2537 /* Optimisation passes */
2541 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2542 nir_print_shader(nir
, stdout
);
2545 /* Assign sysvals and counts, now that we're sure
2546 * (post-optimisation) */
2548 midgard_nir_assign_sysvals(ctx
, nir
);
2550 program
->uniform_count
= nir
->num_uniforms
;
2551 program
->sysval_count
= ctx
->sysval_count
;
2552 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2554 nir_foreach_function(func
, nir
) {
2558 list_inithead(&ctx
->blocks
);
2559 ctx
->block_count
= 0;
2562 emit_cf_list(ctx
, &func
->impl
->body
);
2563 emit_block(ctx
, func
->impl
->end_block
);
2565 break; /* TODO: Multi-function shaders */
2568 util_dynarray_init(compiled
, NULL
);
2570 /* MIR-level optimizations */
2572 bool progress
= false;
2577 mir_foreach_block(ctx
, block
) {
2578 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2579 progress
|= midgard_opt_copy_prop(ctx
, block
);
2580 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2581 progress
|= midgard_opt_combine_projection(ctx
, block
);
2582 progress
|= midgard_opt_varying_projection(ctx
, block
);
2583 progress
|= midgard_opt_not_propagate(ctx
, block
);
2584 progress
|= midgard_opt_fuse_src_invert(ctx
, block
);
2585 progress
|= midgard_opt_fuse_dest_invert(ctx
, block
);
2589 mir_foreach_block(ctx
, block
) {
2590 midgard_lower_invert(ctx
, block
);
2591 midgard_lower_derivatives(ctx
, block
);
2594 /* Nested control-flow can result in dead branches at the end of the
2595 * block. This messes with our analysis and is just dead code, so cull
2597 mir_foreach_block(ctx
, block
) {
2598 midgard_opt_cull_dead_branch(ctx
, block
);
2601 /* Ensure we were lowered */
2602 mir_foreach_instr_global(ctx
, ins
) {
2603 assert(!ins
->invert
);
2607 schedule_program(ctx
);
2609 /* Now that all the bundles are scheduled and we can calculate block
2610 * sizes, emit actual branch instructions rather than placeholders */
2612 int br_block_idx
= 0;
2614 mir_foreach_block(ctx
, block
) {
2615 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2616 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2617 midgard_instruction
*ins
= bundle
->instructions
[c
];
2619 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2621 if (ins
->prepacked_branch
) continue;
2623 /* Parse some basic branch info */
2624 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2625 bool is_conditional
= ins
->branch
.conditional
;
2626 bool is_inverted
= ins
->branch
.invert_conditional
;
2627 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2629 /* Determine the block we're jumping to */
2630 int target_number
= ins
->branch
.target_block
;
2632 /* Report the destination tag */
2633 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2635 /* Count up the number of quadwords we're
2636 * jumping over = number of quadwords until
2637 * (br_block_idx, target_number) */
2639 int quadword_offset
= 0;
2643 } else if (target_number
> br_block_idx
) {
2646 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2647 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2650 quadword_offset
+= blk
->quadword_count
;
2653 /* Jump backwards */
2655 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2656 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2659 quadword_offset
-= blk
->quadword_count
;
2663 /* Unconditional extended branches (far jumps)
2664 * have issues, so we always use a conditional
2665 * branch, setting the condition to always for
2666 * unconditional. For compact unconditional
2667 * branches, cond isn't used so it doesn't
2668 * matter what we pick. */
2670 midgard_condition cond
=
2671 !is_conditional
? midgard_condition_always
:
2672 is_inverted
? midgard_condition_false
:
2673 midgard_condition_true
;
2675 midgard_jmp_writeout_op op
=
2676 is_discard
? midgard_jmp_writeout_op_discard
:
2677 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2678 midgard_jmp_writeout_op_branch_cond
;
2681 midgard_branch_extended branch
=
2682 midgard_create_branch_extended(
2687 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2688 } else if (is_conditional
|| is_discard
) {
2689 midgard_branch_cond branch
= {
2691 .dest_tag
= dest_tag
,
2692 .offset
= quadword_offset
,
2696 assert(branch
.offset
== quadword_offset
);
2698 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2700 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2702 midgard_branch_uncond branch
= {
2704 .dest_tag
= dest_tag
,
2705 .offset
= quadword_offset
,
2709 assert(branch
.offset
== quadword_offset
);
2711 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2719 /* Emit flat binary from the instruction arrays. Iterate each block in
2720 * sequence. Save instruction boundaries such that lookahead tags can
2721 * be assigned easily */
2723 /* Cache _all_ bundles in source order for lookahead across failed branches */
2725 int bundle_count
= 0;
2726 mir_foreach_block(ctx
, block
) {
2727 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2729 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2731 mir_foreach_block(ctx
, block
) {
2732 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2733 source_order_bundles
[bundle_idx
++] = bundle
;
2737 int current_bundle
= 0;
2739 /* Midgard prefetches instruction types, so during emission we
2740 * need to lookahead. Unless this is the last instruction, in
2741 * which we return 1. Or if this is the second to last and the
2742 * last is an ALU, then it's also 1... */
2744 mir_foreach_block(ctx
, block
) {
2745 mir_foreach_bundle_in_block(block
, bundle
) {
2748 if (current_bundle
+ 1 < bundle_count
) {
2749 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2751 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2758 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2762 /* TODO: Free deeper */
2763 //util_dynarray_fini(&block->instructions);
2766 free(source_order_bundles
);
2768 /* Report the very first tag executed */
2769 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2771 /* Deal with off-by-one related to the fencepost problem */
2772 program
->work_register_count
= ctx
->work_registers
+ 1;
2773 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2775 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2776 program
->tls_size
= ctx
->tls_size
;
2778 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2779 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
, false, 0, "");
2781 if (midgard_debug
& MIDGARD_DBG_SHADERDB
) {
2782 unsigned nr_bundles
= 0, nr_ins
= 0, nr_quadwords
= 0;
2784 /* Count instructions and bundles */
2786 mir_foreach_instr_global(ctx
, ins
) {
2790 mir_foreach_block(ctx
, block
) {
2791 nr_bundles
+= util_dynarray_num_elements(
2792 &block
->bundles
, midgard_bundle
);
2794 nr_quadwords
+= block
->quadword_count
;
2797 /* Calculate thread count. There are certain cutoffs by
2798 * register count for thread count */
2800 unsigned nr_registers
= program
->work_register_count
;
2802 unsigned nr_threads
=
2803 (nr_registers
<= 4) ? 4 :
2804 (nr_registers
<= 8) ? 2 :
2809 fprintf(stderr
, "shader%d - %s shader: "
2810 "%u inst, %u bundles, %u quadwords, "
2811 "%u registers, %u threads, %u loops, "
2812 "%d:%d spills:fills\n",
2814 gl_shader_stage_name(ctx
->stage
),
2815 nr_ins
, nr_bundles
, nr_quadwords
,
2816 nr_registers
, nr_threads
,
2818 ctx
->spills
, ctx
->fills
);