2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
63 unsigned SHADER_DB_COUNT
= 0;
65 int midgard_debug
= 0;
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 midgard_is_branch_unit(unsigned unit
)
75 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
79 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
81 block
->successors
[block
->nr_successors
++] = successor
;
82 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
85 /* Helpers to generate midgard_instruction's using macro magic, since every
86 * driver seems to do it that way */
88 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
90 #define M_LOAD_STORE(name, rname, uname) \
91 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
92 midgard_instruction i = { \
93 .type = TAG_LOAD_STORE_4, \
101 .op = midgard_op_##name, \
102 .swizzle = SWIZZLE_XYZW, \
110 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
111 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
113 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
114 * the corresponding Midgard source */
116 static midgard_vector_alu_src
117 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
118 bool half
, bool sext
)
120 if (!src
) return blank_alu_src
;
122 /* Figure out how many components there are so we can adjust the
123 * swizzle. Specifically we want to broadcast the last channel so
124 * things like ball2/3 work
127 if (broadcast_count
) {
128 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
130 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
131 src
->swizzle
[c
] = last_component
;
135 midgard_vector_alu_src alu_src
= {
139 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
143 alu_src
.mod
= midgard_int_normal
;
145 /* Sign/zero-extend if needed */
149 midgard_int_sign_extend
150 : midgard_int_zero_extend
;
153 /* These should have been lowered away */
154 assert(!(src
->abs
|| src
->negate
));
156 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
162 /* load/store instructions have both 32-bit and 16-bit variants, depending on
163 * whether we are using vectors composed of highp or mediump. At the moment, we
164 * don't support half-floats -- this requires changes in other parts of the
165 * compiler -- therefore the 16-bit versions are commented out. */
167 //M_LOAD(ld_attr_16);
169 //M_LOAD(ld_vary_16);
171 //M_LOAD(ld_uniform_16);
172 M_LOAD(ld_uniform_32
);
173 M_LOAD(ld_color_buffer_8
);
174 //M_STORE(st_vary_16);
176 M_STORE(st_cubemap_coords
);
178 static midgard_instruction
179 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
181 midgard_branch_cond branch
= {
189 memcpy(&compact
, &branch
, sizeof(branch
));
191 midgard_instruction ins
= {
193 .unit
= ALU_ENAB_BR_COMPACT
,
194 .prepacked_branch
= true,
195 .compact_branch
= true,
196 .br_compact
= compact
199 if (op
== midgard_jmp_writeout_op_writeout
)
205 static midgard_instruction
206 v_branch(bool conditional
, bool invert
)
208 midgard_instruction ins
= {
210 .unit
= ALU_ENAB_BRANCH
,
211 .compact_branch
= true,
213 .conditional
= conditional
,
214 .invert_conditional
= invert
221 static midgard_branch_extended
222 midgard_create_branch_extended( midgard_condition cond
,
223 midgard_jmp_writeout_op op
,
225 signed quadword_offset
)
227 /* For unclear reasons, the condition code is repeated 8 times */
228 uint16_t duplicated_cond
=
238 midgard_branch_extended branch
= {
240 .dest_tag
= dest_tag
,
241 .offset
= quadword_offset
,
242 .cond
= duplicated_cond
249 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
251 ins
->has_constants
= true;
252 memcpy(&ins
->constants
, constants
, 16);
256 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
258 return glsl_count_attribute_slots(type
, false);
261 /* Lower fdot2 to a vector multiplication followed by channel addition */
263 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
265 if (alu
->op
!= nir_op_fdot2
)
268 b
->cursor
= nir_before_instr(&alu
->instr
);
270 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
271 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
273 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
275 nir_ssa_def
*sum
= nir_fadd(b
,
276 nir_channel(b
, product
, 0),
277 nir_channel(b
, product
, 1));
279 /* Replace the fdot2 with this sum */
280 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
284 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
286 switch (instr
->intrinsic
) {
287 case nir_intrinsic_load_viewport_scale
:
288 return PAN_SYSVAL_VIEWPORT_SCALE
;
289 case nir_intrinsic_load_viewport_offset
:
290 return PAN_SYSVAL_VIEWPORT_OFFSET
;
297 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
300 return dst
->ssa
.index
;
302 assert(!dst
->reg
.indirect
);
303 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
307 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
310 nir_intrinsic_instr
*intr
;
311 nir_dest
*dst
= NULL
;
315 switch (instr
->type
) {
316 case nir_instr_type_intrinsic
:
317 intr
= nir_instr_as_intrinsic(instr
);
318 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
321 case nir_instr_type_tex
:
322 tex
= nir_instr_as_tex(instr
);
323 if (tex
->op
!= nir_texop_txs
)
326 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
327 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
328 nir_tex_instr_dest_size(tex
) -
329 (tex
->is_array
? 1 : 0),
338 *dest
= nir_dest_index(ctx
, dst
);
344 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
348 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
352 /* We have a sysval load; check if it's already been assigned */
354 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
357 /* It hasn't -- so assign it now! */
359 unsigned id
= ctx
->sysval_count
++;
360 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
361 ctx
->sysvals
[id
] = sysval
;
365 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
367 ctx
->sysval_count
= 0;
369 nir_foreach_function(function
, shader
) {
370 if (!function
->impl
) continue;
372 nir_foreach_block(block
, function
->impl
) {
373 nir_foreach_instr_safe(instr
, block
) {
374 midgard_nir_assign_sysval_body(ctx
, instr
);
381 midgard_nir_lower_fdot2(nir_shader
*shader
)
383 bool progress
= false;
385 nir_foreach_function(function
, shader
) {
386 if (!function
->impl
) continue;
389 nir_builder
*b
= &_b
;
390 nir_builder_init(b
, function
->impl
);
392 nir_foreach_block(block
, function
->impl
) {
393 nir_foreach_instr_safe(instr
, block
) {
394 if (instr
->type
!= nir_instr_type_alu
) continue;
396 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
397 midgard_nir_lower_fdot2_body(b
, alu
);
403 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
410 /* Flushes undefined values to zero */
413 optimise_nir(nir_shader
*nir
)
416 unsigned lower_flrp
=
417 (nir
->options
->lower_flrp16
? 16 : 0) |
418 (nir
->options
->lower_flrp32
? 32 : 0) |
419 (nir
->options
->lower_flrp64
? 64 : 0);
421 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
422 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
423 NIR_PASS(progress
, nir
, nir_lower_idiv
);
425 nir_lower_tex_options lower_tex_1st_pass_options
= {
430 nir_lower_tex_options lower_tex_2nd_pass_options
= {
431 .lower_txs_lod
= true,
434 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_1st_pass_options
);
435 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_2nd_pass_options
);
440 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
441 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
443 NIR_PASS(progress
, nir
, nir_copy_prop
);
444 NIR_PASS(progress
, nir
, nir_opt_dce
);
445 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
446 NIR_PASS(progress
, nir
, nir_opt_cse
);
447 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
448 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
449 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
451 if (lower_flrp
!= 0) {
452 bool lower_flrp_progress
= false;
453 NIR_PASS(lower_flrp_progress
,
457 false /* always_precise */,
458 nir
->options
->lower_ffma
);
459 if (lower_flrp_progress
) {
460 NIR_PASS(progress
, nir
,
461 nir_opt_constant_folding
);
465 /* Nothing should rematerialize any flrps, so we only
466 * need to do this lowering once.
471 NIR_PASS(progress
, nir
, nir_opt_undef
);
472 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
474 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
477 nir_var_function_temp
);
479 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
482 /* Must be run at the end to prevent creation of fsin/fcos ops */
483 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
488 NIR_PASS(progress
, nir
, nir_opt_dce
);
489 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
490 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
491 NIR_PASS(progress
, nir
, nir_copy_prop
);
494 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
496 /* We implement booleans as 32-bit 0/~0 */
497 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
499 /* Now that booleans are lowered, we can run out late opts */
500 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
502 /* Lower mods for float ops only. Integer ops don't support modifiers
503 * (saturate doesn't make sense on integers, neg/abs require dedicated
506 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
507 NIR_PASS(progress
, nir
, nir_copy_prop
);
508 NIR_PASS(progress
, nir
, nir_opt_dce
);
510 /* Take us out of SSA */
511 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
512 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
514 /* We are a vector architecture; write combine where possible */
515 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
516 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
518 NIR_PASS(progress
, nir
, nir_opt_dce
);
521 /* Do not actually emit a load; instead, cache the constant for inlining */
524 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
526 nir_ssa_def def
= instr
->def
;
528 float *v
= rzalloc_array(NULL
, float, 4);
529 nir_const_load_to_arr(v
, instr
, f32
);
530 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
534 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
537 return src
->ssa
->index
;
539 assert(!src
->reg
.indirect
);
540 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
545 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
547 return nir_src_index(ctx
, &src
->src
);
551 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
553 unsigned comp
= src
->swizzle
[0];
555 for (unsigned c
= 1; c
< nr_components
; ++c
) {
556 if (src
->swizzle
[c
] != comp
)
563 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
564 * output of a conditional test) into that register */
567 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
569 int condition
= nir_src_index(ctx
, src
);
571 /* Source to swizzle the desired component into w */
573 const midgard_vector_alu_src alu_src
= {
574 .swizzle
= SWIZZLE(component
, component
, component
, component
),
577 /* There is no boolean move instruction. Instead, we simulate a move by
578 * ANDing the condition with itself to get it into r31.w */
580 midgard_instruction ins
= {
583 /* We need to set the conditional as close as possible */
584 .precede_break
= true,
585 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
586 .mask
= 1 << COMPONENT_W
,
591 .dest
= SSA_FIXED_REGISTER(31),
595 .op
= midgard_alu_op_iand
,
596 .outmod
= midgard_outmod_int_wrap
,
597 .reg_mode
= midgard_reg_mode_32
,
598 .dest_override
= midgard_dest_override_none
,
599 .src1
= vector_alu_srco_unsigned(alu_src
),
600 .src2
= vector_alu_srco_unsigned(alu_src
)
604 emit_mir_instruction(ctx
, ins
);
607 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
611 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
613 int condition
= nir_src_index(ctx
, &src
->src
);
615 /* Source to swizzle the desired component into w */
617 const midgard_vector_alu_src alu_src
= {
618 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
621 /* There is no boolean move instruction. Instead, we simulate a move by
622 * ANDing the condition with itself to get it into r31.w */
624 midgard_instruction ins
= {
626 .precede_break
= true,
627 .mask
= mask_of(nr_comp
),
631 .dest
= SSA_FIXED_REGISTER(31),
634 .op
= midgard_alu_op_iand
,
635 .outmod
= midgard_outmod_int_wrap
,
636 .reg_mode
= midgard_reg_mode_32
,
637 .dest_override
= midgard_dest_override_none
,
638 .src1
= vector_alu_srco_unsigned(alu_src
),
639 .src2
= vector_alu_srco_unsigned(alu_src
)
643 emit_mir_instruction(ctx
, ins
);
648 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
649 * pinning to eliminate this move in all known cases */
652 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
654 int offset
= nir_src_index(ctx
, src
);
656 midgard_instruction ins
= {
658 .mask
= 1 << COMPONENT_W
,
660 .src0
= SSA_UNUSED_1
,
662 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
665 .op
= midgard_alu_op_imov
,
666 .outmod
= midgard_outmod_int_wrap
,
667 .reg_mode
= midgard_reg_mode_32
,
668 .dest_override
= midgard_dest_override_none
,
669 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
670 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
674 emit_mir_instruction(ctx
, ins
);
677 #define ALU_CASE(nir, _op) \
679 op = midgard_alu_op_##_op; \
680 assert(src_bitsize == dst_bitsize); \
683 #define ALU_CASE_BCAST(nir, _op, count) \
685 op = midgard_alu_op_##_op; \
686 broadcast_swizzle = count; \
687 assert(src_bitsize == dst_bitsize); \
690 nir_is_fzero_constant(nir_src src
)
692 if (!nir_src_is_const(src
))
695 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
696 if (nir_src_comp_as_float(src
, c
) != 0.0)
703 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
704 * special treatment override this anyway. */
706 static midgard_reg_mode
707 reg_mode_for_nir(nir_alu_instr
*instr
)
709 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
711 switch (src_bitsize
) {
713 return midgard_reg_mode_8
;
715 return midgard_reg_mode_16
;
717 return midgard_reg_mode_32
;
719 return midgard_reg_mode_64
;
721 unreachable("Invalid bit size");
726 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
728 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
730 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
731 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
732 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
734 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
735 * supported. A few do not and are commented for now. Also, there are a
736 * number of NIR ops which Midgard does not support and need to be
737 * lowered, also TODO. This switch block emits the opcode and calling
738 * convention of the Midgard instruction; actual packing is done in
743 /* Number of components valid to check for the instruction (the rest
744 * will be forced to the last), or 0 to use as-is. Relevant as
745 * ball-type instructions have a channel count in NIR but are all vec4
748 unsigned broadcast_swizzle
= 0;
750 /* What register mode should we operate in? */
751 midgard_reg_mode reg_mode
=
752 reg_mode_for_nir(instr
);
754 /* Do we need a destination override? Used for inline
757 midgard_dest_override dest_override
=
758 midgard_dest_override_none
;
760 /* Should we use a smaller respective source and sign-extend? */
762 bool half_1
= false, sext_1
= false;
763 bool half_2
= false, sext_2
= false;
765 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
766 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
769 ALU_CASE(fadd
, fadd
);
770 ALU_CASE(fmul
, fmul
);
771 ALU_CASE(fmin
, fmin
);
772 ALU_CASE(fmax
, fmax
);
773 ALU_CASE(imin
, imin
);
774 ALU_CASE(imax
, imax
);
775 ALU_CASE(umin
, umin
);
776 ALU_CASE(umax
, umax
);
777 ALU_CASE(ffloor
, ffloor
);
778 ALU_CASE(fround_even
, froundeven
);
779 ALU_CASE(ftrunc
, ftrunc
);
780 ALU_CASE(fceil
, fceil
);
781 ALU_CASE(fdot3
, fdot3
);
782 ALU_CASE(fdot4
, fdot4
);
783 ALU_CASE(iadd
, iadd
);
784 ALU_CASE(isub
, isub
);
785 ALU_CASE(imul
, imul
);
787 /* Zero shoved as second-arg */
788 ALU_CASE(iabs
, iabsdiff
);
792 ALU_CASE(feq32
, feq
);
793 ALU_CASE(fne32
, fne
);
794 ALU_CASE(flt32
, flt
);
795 ALU_CASE(ieq32
, ieq
);
796 ALU_CASE(ine32
, ine
);
797 ALU_CASE(ilt32
, ilt
);
798 ALU_CASE(ult32
, ult
);
800 /* We don't have a native b2f32 instruction. Instead, like many
801 * GPUs, we exploit booleans as 0/~0 for false/true, and
802 * correspondingly AND
803 * by 1.0 to do the type conversion. For the moment, prime us
806 * iand [whatever], #0
808 * At the end of emit_alu (as MIR), we'll fix-up the constant
811 ALU_CASE(b2f32
, iand
);
812 ALU_CASE(b2i32
, iand
);
814 /* Likewise, we don't have a dedicated f2b32 instruction, but
815 * we can do a "not equal to 0.0" test. */
817 ALU_CASE(f2b32
, fne
);
818 ALU_CASE(i2b32
, ine
);
820 ALU_CASE(frcp
, frcp
);
821 ALU_CASE(frsq
, frsqrt
);
822 ALU_CASE(fsqrt
, fsqrt
);
823 ALU_CASE(fexp2
, fexp2
);
824 ALU_CASE(flog2
, flog2
);
826 ALU_CASE(f2i32
, f2i_rtz
);
827 ALU_CASE(f2u32
, f2u_rtz
);
828 ALU_CASE(i2f32
, i2f_rtz
);
829 ALU_CASE(u2f32
, u2f_rtz
);
831 ALU_CASE(f2i16
, f2i_rtz
);
832 ALU_CASE(f2u16
, f2u_rtz
);
833 ALU_CASE(i2f16
, i2f_rtz
);
834 ALU_CASE(u2f16
, u2f_rtz
);
836 ALU_CASE(fsin
, fsin
);
837 ALU_CASE(fcos
, fcos
);
839 /* Second op implicit #0 */
840 ALU_CASE(inot
, inor
);
841 ALU_CASE(iand
, iand
);
843 ALU_CASE(ixor
, ixor
);
844 ALU_CASE(ishl
, ishl
);
845 ALU_CASE(ishr
, iasr
);
846 ALU_CASE(ushr
, ilsr
);
848 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
849 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
850 ALU_CASE(b32all_fequal4
, fball_eq
);
852 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
853 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
854 ALU_CASE(b32any_fnequal4
, fbany_neq
);
856 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
857 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
858 ALU_CASE(b32all_iequal4
, iball_eq
);
860 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
861 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
862 ALU_CASE(b32any_inequal4
, ibany_neq
);
864 /* Source mods will be shoved in later */
865 ALU_CASE(fabs
, fmov
);
866 ALU_CASE(fneg
, fmov
);
867 ALU_CASE(fsat
, fmov
);
869 /* For size conversion, we use a move. Ideally though we would squash
870 * these ops together; maybe that has to happen after in NIR as part of
871 * propagation...? An earlier algebraic pass ensured we step down by
872 * only / exactly one size. If stepping down, we use a dest override to
873 * reduce the size; if stepping up, we use a larger-sized move with a
874 * half source and a sign/zero-extension modifier */
879 /* If we end up upscale, we'll need a sign-extend on the
880 * operand (the second argument) */
886 op
= midgard_alu_op_imov
;
888 if (dst_bitsize
== (src_bitsize
* 2)) {
892 /* Use a greater register mode */
894 } else if (src_bitsize
== (dst_bitsize
* 2)) {
895 /* Converting down */
896 dest_override
= midgard_dest_override_lower
;
903 assert(src_bitsize
== 32);
905 op
= midgard_alu_op_fmov
;
906 dest_override
= midgard_dest_override_lower
;
911 assert(src_bitsize
== 16);
913 op
= midgard_alu_op_fmov
;
920 /* For greater-or-equal, we lower to less-or-equal and flip the
928 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
929 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
930 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
931 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
934 /* Swap via temporary */
935 nir_alu_src temp
= instr
->src
[1];
936 instr
->src
[1] = instr
->src
[0];
937 instr
->src
[0] = temp
;
942 case nir_op_b32csel
: {
943 /* Midgard features both fcsel and icsel, depending on
944 * the type of the arguments/output. However, as long
945 * as we're careful we can _always_ use icsel and
946 * _never_ need fcsel, since the latter does additional
947 * floating-point-specific processing whereas the
948 * former just moves bits on the wire. It's not obvious
949 * why these are separate opcodes, save for the ability
950 * to do things like sat/pos/abs/neg for free */
952 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
953 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
955 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
958 /* Emit the condition into r31 */
961 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
963 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
965 /* The condition is the first argument; move the other
966 * arguments up one to be a binary instruction for
969 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
974 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
979 /* Midgard can perform certain modifiers on output of an ALU op */
982 if (midgard_is_integer_out_op(op
)) {
983 outmod
= midgard_outmod_int_wrap
;
985 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
986 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
989 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
991 if (instr
->op
== nir_op_fmax
) {
992 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
993 op
= midgard_alu_op_fmov
;
995 outmod
= midgard_outmod_pos
;
996 instr
->src
[0] = instr
->src
[1];
997 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
998 op
= midgard_alu_op_fmov
;
1000 outmod
= midgard_outmod_pos
;
1004 /* Fetch unit, quirks, etc information */
1005 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1006 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1008 /* src0 will always exist afaik, but src1 will not for 1-argument
1009 * instructions. The latter can only be fetched if the instruction
1010 * needs it, or else we may segfault. */
1012 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1013 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1015 /* Rather than use the instruction generation helpers, we do it
1016 * ourselves here to avoid the mess */
1018 midgard_instruction ins
= {
1021 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1022 .src1
= quirk_flipped_r24
? src0
: src1
,
1027 nir_alu_src
*nirmods
[2] = { NULL
};
1029 if (nr_inputs
== 2) {
1030 nirmods
[0] = &instr
->src
[0];
1031 nirmods
[1] = &instr
->src
[1];
1032 } else if (nr_inputs
== 1) {
1033 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1038 /* These were lowered to a move, so apply the corresponding mod */
1040 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1041 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
1043 if (instr
->op
== nir_op_fneg
)
1044 s
->negate
= !s
->negate
;
1046 if (instr
->op
== nir_op_fabs
)
1050 bool is_int
= midgard_is_integer_op(op
);
1052 ins
.mask
= mask_of(nr_components
);
1054 midgard_vector_alu alu
= {
1056 .reg_mode
= reg_mode
,
1057 .dest_override
= dest_override
,
1060 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1061 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1064 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1067 ins
.mask
&= instr
->dest
.write_mask
;
1071 /* Late fixup for emulated instructions */
1073 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1074 /* Presently, our second argument is an inline #0 constant.
1075 * Switch over to an embedded 1.0 constant (that can't fit
1076 * inline, since we're 32-bit, not 16-bit like the inline
1079 ins
.ssa_args
.inline_constant
= false;
1080 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1081 ins
.has_constants
= true;
1083 if (instr
->op
== nir_op_b2f32
) {
1084 ins
.constants
[0] = 1.0f
;
1086 /* Type pun it into place */
1088 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1091 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1092 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1093 /* Lots of instructions need a 0 plonked in */
1094 ins
.ssa_args
.inline_constant
= false;
1095 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1096 ins
.has_constants
= true;
1097 ins
.constants
[0] = 0.0f
;
1098 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1099 } else if (instr
->op
== nir_op_inot
) {
1100 /* ~b = ~(b & b), so duplicate the source */
1101 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
1102 ins
.alu
.src2
= ins
.alu
.src1
;
1105 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1106 /* To avoid duplicating the lookup tables (probably), true LUT
1107 * instructions can only operate as if they were scalars. Lower
1108 * them here by changing the component. */
1110 uint8_t original_swizzle
[4];
1111 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1112 unsigned orig_mask
= ins
.mask
;
1114 for (int i
= 0; i
< nr_components
; ++i
) {
1115 /* Mask the associated component, dropping the
1116 * instruction if needed */
1119 ins
.mask
&= orig_mask
;
1124 for (int j
= 0; j
< 4; ++j
)
1125 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1127 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, false));
1128 emit_mir_instruction(ctx
, ins
);
1131 emit_mir_instruction(ctx
, ins
);
1137 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1138 * optimized) versions of UBO #0 */
1142 compiler_context
*ctx
,
1145 nir_src
*indirect_offset
,
1148 /* TODO: half-floats */
1150 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
1152 /* TODO: Don't split */
1153 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1154 ins
.load_store
.address
= offset
>> 3;
1156 if (indirect_offset
) {
1157 emit_indirect_offset(ctx
, indirect_offset
);
1158 ins
.load_store
.unknown
= 0x8700 | index
; /* xxx: what is this? */
1160 ins
.load_store
.unknown
= 0x1E00 | index
; /* xxx: what is this? */
1163 emit_mir_instruction(ctx
, ins
);
1168 compiler_context
*ctx
,
1169 unsigned dest
, unsigned offset
,
1170 unsigned nr_comp
, unsigned component
,
1171 nir_src
*indirect_offset
, nir_alu_type type
)
1173 /* XXX: Half-floats? */
1174 /* TODO: swizzle, mask */
1176 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1177 ins
.mask
= mask_of(nr_comp
);
1178 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1180 midgard_varying_parameter p
= {
1182 .interpolation
= midgard_interp_default
,
1183 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1187 memcpy(&u
, &p
, sizeof(p
));
1188 ins
.load_store
.varying_parameters
= u
;
1190 if (indirect_offset
) {
1191 /* We need to add in the dynamic index, moved to r27.w */
1192 emit_indirect_offset(ctx
, indirect_offset
);
1193 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1195 /* Just a direct load */
1196 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1199 /* Use the type appropriate load */
1203 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1206 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1208 case nir_type_float
:
1209 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1212 unreachable("Attempted to load unknown type");
1216 emit_mir_instruction(ctx
, ins
);
1220 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
)
1224 /* Figure out which uniform this is */
1225 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1226 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1228 /* Sysvals are prefix uniforms */
1229 unsigned uniform
= ((uintptr_t) val
) - 1;
1231 /* Emit the read itself -- this is never indirect */
1232 emit_ubo_read(ctx
, dest
, uniform
, NULL
, 0);
1236 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1238 unsigned offset
= 0, reg
;
1240 switch (instr
->intrinsic
) {
1241 case nir_intrinsic_discard_if
:
1242 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1246 case nir_intrinsic_discard
: {
1247 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1248 struct midgard_instruction discard
= v_branch(conditional
, false);
1249 discard
.branch
.target_type
= TARGET_DISCARD
;
1250 emit_mir_instruction(ctx
, discard
);
1254 case nir_intrinsic_load_uniform
:
1255 case nir_intrinsic_load_ubo
:
1256 case nir_intrinsic_load_input
: {
1257 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1258 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1260 /* Get the base type of the intrinsic */
1261 /* TODO: Infer type? Does it matter? */
1263 is_ubo
? nir_type_uint
: nir_intrinsic_type(instr
);
1264 t
= nir_alu_type_get_base_type(t
);
1267 offset
= nir_intrinsic_base(instr
);
1270 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1272 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1274 bool direct
= nir_src_is_const(*src_offset
);
1277 offset
+= nir_src_as_uint(*src_offset
);
1279 /* We may need to apply a fractional offset */
1280 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1281 nir_intrinsic_component(instr
) : 0;
1282 reg
= nir_dest_index(ctx
, &instr
->dest
);
1284 if (is_uniform
&& !ctx
->is_blend
) {
1285 emit_ubo_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
, 0);
1286 } else if (is_ubo
) {
1287 nir_src index
= instr
->src
[0];
1289 /* We don't yet support indirect UBOs. For indirect
1290 * block numbers (if that's possible), we don't know
1291 * enough about the hardware yet. For indirect sources,
1292 * we know what we need but we need to add some NIR
1293 * support for lowering correctly with respect to
1296 assert(nir_src_is_const(index
));
1297 assert(nir_src_is_const(*src_offset
));
1299 /* TODO: Alignment */
1300 assert((offset
& 0xF) == 0);
1302 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1303 emit_ubo_read(ctx
, reg
, offset
/ 16, NULL
, uindex
);
1304 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1305 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
, t
);
1306 } else if (ctx
->is_blend
) {
1307 /* For blend shaders, load the input color, which is
1308 * preloaded to r0 */
1310 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1311 emit_mir_instruction(ctx
, move
);
1312 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1313 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1314 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1315 ins
.mask
= mask_of(nr_comp
);
1317 /* Use the type appropriate load */
1321 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1324 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1326 case nir_type_float
:
1327 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1330 unreachable("Attempted to load unknown type");
1334 emit_mir_instruction(ctx
, ins
);
1336 DBG("Unknown load\n");
1343 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1345 case nir_intrinsic_load_raw_output_pan
:
1346 reg
= nir_dest_index(ctx
, &instr
->dest
);
1347 assert(ctx
->is_blend
);
1349 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1350 emit_mir_instruction(ctx
, ins
);
1353 case nir_intrinsic_load_blend_const_color_rgba
: {
1354 assert(ctx
->is_blend
);
1355 reg
= nir_dest_index(ctx
, &instr
->dest
);
1357 /* Blend constants are embedded directly in the shader and
1358 * patched in, so we use some magic routing */
1360 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1361 ins
.has_constants
= true;
1362 ins
.has_blend_constant
= true;
1363 emit_mir_instruction(ctx
, ins
);
1367 case nir_intrinsic_store_output
:
1368 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1370 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1372 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1374 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1375 /* gl_FragColor is not emitted with load/store
1376 * instructions. Instead, it gets plonked into
1377 * r0 at the end of the shader and we do the
1378 * framebuffer writeout dance. TODO: Defer
1381 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1382 emit_mir_instruction(ctx
, move
);
1384 /* Save the index we're writing to for later reference
1385 * in the epilogue */
1387 ctx
->fragment_output
= reg
;
1388 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1389 /* Varyings are written into one of two special
1390 * varying register, r26 or r27. The register itself is
1391 * selected as the register in the st_vary instruction,
1392 * minus the base of 26. E.g. write into r27 and then
1393 * call st_vary(1) */
1395 midgard_instruction ins
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(26));
1396 emit_mir_instruction(ctx
, ins
);
1398 /* We should have been vectorized, though we don't
1399 * currently check that st_vary is emitted only once
1400 * per slot (this is relevant, since there's not a mask
1401 * parameter available on the store [set to 0 by the
1402 * blob]). We do respect the component by adjusting the
1405 unsigned component
= nir_intrinsic_component(instr
);
1407 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(0), offset
);
1408 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1409 st
.load_store
.swizzle
= SWIZZLE_XYZW
<< (2*component
);
1410 emit_mir_instruction(ctx
, st
);
1412 DBG("Unknown store\n");
1418 /* Special case of store_output for lowered blend shaders */
1419 case nir_intrinsic_store_raw_output_pan
:
1420 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1421 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1423 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1424 emit_mir_instruction(ctx
, move
);
1425 ctx
->fragment_output
= reg
;
1429 case nir_intrinsic_load_alpha_ref_float
:
1430 assert(instr
->dest
.is_ssa
);
1432 float ref_value
= ctx
->alpha_ref
;
1434 float *v
= ralloc_array(NULL
, float, 4);
1435 memcpy(v
, &ref_value
, sizeof(float));
1436 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1439 case nir_intrinsic_load_viewport_scale
:
1440 case nir_intrinsic_load_viewport_offset
:
1441 emit_sysval_read(ctx
, &instr
->instr
);
1445 printf ("Unhandled intrinsic\n");
1452 midgard_tex_format(enum glsl_sampler_dim dim
)
1455 case GLSL_SAMPLER_DIM_1D
:
1456 case GLSL_SAMPLER_DIM_BUF
:
1459 case GLSL_SAMPLER_DIM_2D
:
1460 case GLSL_SAMPLER_DIM_EXTERNAL
:
1463 case GLSL_SAMPLER_DIM_3D
:
1466 case GLSL_SAMPLER_DIM_CUBE
:
1467 return MALI_TEX_CUBE
;
1470 DBG("Unknown sampler dim type\n");
1476 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1480 pan_attach_constant_bias(
1481 compiler_context
*ctx
,
1483 midgard_texture_word
*word
)
1485 /* To attach as constant, it has to *be* constant */
1487 if (!nir_src_is_const(lod
))
1490 float f
= nir_src_as_float(lod
);
1492 /* Break into fixed-point */
1494 float lod_frac
= f
- lod_int
;
1496 /* Carry over negative fractions */
1497 if (lod_frac
< 0.0) {
1503 word
->bias
= float_to_ubyte(lod_frac
);
1504 word
->bias_int
= lod_int
;
1509 static enum mali_sampler_type
1510 midgard_sampler_type(nir_alu_type t
) {
1511 switch (nir_alu_type_get_base_type(t
))
1513 case nir_type_float
:
1514 return MALI_SAMPLER_FLOAT
;
1516 return MALI_SAMPLER_SIGNED
;
1518 return MALI_SAMPLER_UNSIGNED
;
1520 unreachable("Unknown sampler type");
1525 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1526 unsigned midgard_texop
)
1529 //assert (!instr->sampler);
1530 //assert (!instr->texture_array_size);
1532 /* Allocate registers via a round robin scheme to alternate between the two registers */
1533 int reg
= ctx
->texture_op_count
& 1;
1534 int in_reg
= reg
, out_reg
= reg
;
1536 int texture_index
= instr
->texture_index
;
1537 int sampler_index
= texture_index
;
1539 /* No helper to build texture words -- we do it all here */
1540 midgard_instruction ins
= {
1541 .type
= TAG_TEXTURE_4
,
1544 .op
= midgard_texop
,
1545 .format
= midgard_tex_format(instr
->sampler_dim
),
1546 .texture_handle
= texture_index
,
1547 .sampler_handle
= sampler_index
,
1549 /* TODO: Regalloc it in */
1550 .swizzle
= SWIZZLE_XYZW
,
1556 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1560 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1561 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1562 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1563 int nr_comp
= nir_src_num_components(instr
->src
[i
].src
);
1564 midgard_vector_alu_src alu_src
= blank_alu_src
;
1566 switch (instr
->src
[i
].src_type
) {
1567 case nir_tex_src_coord
: {
1568 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1569 /* texelFetch is undefined on samplerCube */
1570 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1572 /* For cubemaps, we need to load coords into
1573 * special r27, and then use a special ld/st op
1574 * to select the face and copy the xy into the
1575 * texture register */
1577 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1579 midgard_instruction move
= v_mov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1580 emit_mir_instruction(ctx
, move
);
1582 midgard_instruction st
= m_st_cubemap_coords(reg
, 0);
1583 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1584 st
.mask
= 0x3; /* xy */
1585 st
.load_store
.swizzle
= alu_src
.swizzle
;
1586 emit_mir_instruction(ctx
, st
);
1588 ins
.texture
.in_reg_swizzle
= swizzle_of(2);
1590 ins
.texture
.in_reg_swizzle
= alu_src
.swizzle
= swizzle_of(nr_comp
);
1592 midgard_instruction mov
= v_mov(index
, alu_src
, reg
);
1593 mov
.mask
= mask_of(nr_comp
);
1594 emit_mir_instruction(ctx
, mov
);
1596 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1597 /* Texel fetch opcodes care about the
1598 * values of z and w, so we actually
1599 * need to spill into a second register
1600 * for a texel fetch with register bias
1601 * (for non-2D). TODO: Implement that
1604 assert(instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
);
1606 midgard_instruction zero
= v_mov(index
, alu_src
, reg
);
1607 zero
.ssa_args
.inline_constant
= true;
1608 zero
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1609 zero
.has_constants
= true;
1610 zero
.mask
= ~mov
.mask
;
1611 emit_mir_instruction(ctx
, zero
);
1613 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYZZ
;
1615 /* Non-texel fetch doesn't need that
1616 * nonsense. However we do use the Z
1617 * for array indexing */
1618 bool is_3d
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
;
1619 ins
.texture
.in_reg_swizzle
= is_3d
? SWIZZLE_XYZZ
: SWIZZLE_XYXZ
;
1626 case nir_tex_src_bias
:
1627 case nir_tex_src_lod
: {
1628 /* Try as a constant if we can */
1630 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1631 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1634 /* Otherwise we use a register. To keep RA simple, we
1635 * put the bias/LOD into the w component of the input
1636 * source, which is otherwise in xy */
1638 alu_src
.swizzle
= SWIZZLE_XXXX
;
1640 midgard_instruction mov
= v_mov(index
, alu_src
, reg
);
1641 mov
.mask
= 1 << COMPONENT_W
;
1642 emit_mir_instruction(ctx
, mov
);
1644 ins
.texture
.lod_register
= true;
1646 midgard_tex_register_select sel
= {
1656 memcpy(&packed
, &sel
, sizeof(packed
));
1657 ins
.texture
.bias
= packed
;
1663 unreachable("Unknown texture source type\n");
1667 /* Set registers to read and write from the same place */
1668 ins
.texture
.in_reg_select
= in_reg
;
1669 ins
.texture
.out_reg_select
= out_reg
;
1671 emit_mir_instruction(ctx
, ins
);
1673 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1674 midgard_instruction ins2
= v_mov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1675 emit_mir_instruction(ctx
, ins2
);
1677 /* Used for .cont and .last hinting */
1678 ctx
->texture_op_count
++;
1682 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1684 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1685 * generic tex in some cases (which confuses the hardware) */
1687 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1689 if (is_vertex
&& instr
->op
== nir_texop_tex
)
1690 instr
->op
= nir_texop_txl
;
1692 switch (instr
->op
) {
1695 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1698 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1701 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1704 emit_sysval_read(ctx
, &instr
->instr
);
1707 unreachable("Unhanlded texture op");
1712 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1714 switch (instr
->type
) {
1715 case nir_jump_break
: {
1716 /* Emit a branch out of the loop */
1717 struct midgard_instruction br
= v_branch(false, false);
1718 br
.branch
.target_type
= TARGET_BREAK
;
1719 br
.branch
.target_break
= ctx
->current_loop_depth
;
1720 emit_mir_instruction(ctx
, br
);
1725 DBG("Unknown jump type %d\n", instr
->type
);
1731 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1733 switch (instr
->type
) {
1734 case nir_instr_type_load_const
:
1735 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1738 case nir_instr_type_intrinsic
:
1739 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1742 case nir_instr_type_alu
:
1743 emit_alu(ctx
, nir_instr_as_alu(instr
));
1746 case nir_instr_type_tex
:
1747 emit_tex(ctx
, nir_instr_as_tex(instr
));
1750 case nir_instr_type_jump
:
1751 emit_jump(ctx
, nir_instr_as_jump(instr
));
1754 case nir_instr_type_ssa_undef
:
1759 DBG("Unhandled instruction type\n");
1765 /* ALU instructions can inline or embed constants, which decreases register
1766 * pressure and saves space. */
1768 #define CONDITIONAL_ATTACH(src) { \
1769 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1772 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1773 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1778 inline_alu_constants(compiler_context
*ctx
)
1780 mir_foreach_instr(ctx
, alu
) {
1781 /* Other instructions cannot inline constants */
1782 if (alu
->type
!= TAG_ALU_4
) continue;
1784 /* If there is already a constant here, we can do nothing */
1785 if (alu
->has_constants
) continue;
1787 /* It makes no sense to inline constants on a branch */
1788 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
1790 CONDITIONAL_ATTACH(src0
);
1792 if (!alu
->has_constants
) {
1793 CONDITIONAL_ATTACH(src1
)
1794 } else if (!alu
->inline_constant
) {
1795 /* Corner case: _two_ vec4 constants, for instance with a
1796 * csel. For this case, we can only use a constant
1797 * register for one, we'll have to emit a move for the
1798 * other. Note, if both arguments are constants, then
1799 * necessarily neither argument depends on the value of
1800 * any particular register. As the destination register
1801 * will be wiped, that means we can spill the constant
1802 * to the destination register.
1805 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
1806 unsigned scratch
= alu
->ssa_args
.dest
;
1809 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1810 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
1812 /* Force a break XXX Defer r31 writes */
1813 ins
.unit
= UNIT_VLUT
;
1815 /* Set the source */
1816 alu
->ssa_args
.src1
= scratch
;
1818 /* Inject us -before- the last instruction which set r31 */
1819 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1825 /* Midgard supports two types of constants, embedded constants (128-bit) and
1826 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1827 * constants can be demoted to inline constants, for space savings and
1828 * sometimes a performance boost */
1831 embedded_to_inline_constant(compiler_context
*ctx
)
1833 mir_foreach_instr(ctx
, ins
) {
1834 if (!ins
->has_constants
) continue;
1836 if (ins
->ssa_args
.inline_constant
) continue;
1838 /* Blend constants must not be inlined by definition */
1839 if (ins
->has_blend_constant
) continue;
1841 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
1842 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
1843 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
1845 if (!(is_16
|| is_32
))
1848 /* src1 cannot be an inline constant due to encoding
1849 * restrictions. So, if possible we try to flip the arguments
1852 int op
= ins
->alu
.op
;
1854 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1856 /* These ops require an operational change to flip
1857 * their arguments TODO */
1858 case midgard_alu_op_flt
:
1859 case midgard_alu_op_fle
:
1860 case midgard_alu_op_ilt
:
1861 case midgard_alu_op_ile
:
1862 case midgard_alu_op_fcsel
:
1863 case midgard_alu_op_icsel
:
1864 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
1869 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
1870 /* Flip the SSA numbers */
1871 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
1872 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1874 /* And flip the modifiers */
1878 src_temp
= ins
->alu
.src2
;
1879 ins
->alu
.src2
= ins
->alu
.src1
;
1880 ins
->alu
.src1
= src_temp
;
1884 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1885 /* Extract the source information */
1887 midgard_vector_alu_src
*src
;
1888 int q
= ins
->alu
.src2
;
1889 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1892 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1893 int component
= src
->swizzle
& 3;
1895 /* Scale constant appropriately, if we can legally */
1896 uint16_t scaled_constant
= 0;
1898 if (midgard_is_integer_op(op
) || is_16
) {
1899 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
1900 scaled_constant
= (uint16_t) iconstants
[component
];
1902 /* Constant overflow after resize */
1903 if (scaled_constant
!= iconstants
[component
])
1906 float original
= (float) ins
->constants
[component
];
1907 scaled_constant
= _mesa_float_to_half(original
);
1909 /* Check for loss of precision. If this is
1910 * mediump, we don't care, but for a highp
1911 * shader, we need to pay attention. NIR
1912 * doesn't yet tell us which mode we're in!
1913 * Practically this prevents most constants
1914 * from being inlined, sadly. */
1916 float fp32
= _mesa_half_to_float(scaled_constant
);
1918 if (fp32
!= original
)
1922 /* We don't know how to handle these with a constant */
1924 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
1925 DBG("Bailing inline constant...\n");
1929 /* Make sure that the constant is not itself a
1930 * vector by checking if all accessed values
1931 * (by the swizzle) are the same. */
1933 uint32_t *cons
= (uint32_t *) ins
->constants
;
1934 uint32_t value
= cons
[component
];
1936 bool is_vector
= false;
1937 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
1939 for (int c
= 1; c
< 4; ++c
) {
1940 /* We only care if this component is actually used */
1941 if (!(mask
& (1 << c
)))
1944 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
1946 if (test
!= value
) {
1955 /* Get rid of the embedded constant */
1956 ins
->has_constants
= false;
1957 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
1958 ins
->ssa_args
.inline_constant
= true;
1959 ins
->inline_constant
= scaled_constant
;
1964 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
1965 * texture pipeline */
1968 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
1970 bool progress
= false;
1972 mir_foreach_instr_in_block_safe(block
, ins
) {
1973 if (ins
->type
!= TAG_ALU_4
) continue;
1974 if (ins
->compact_branch
) continue;
1976 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1977 if (mir_is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
1979 mir_remove_instruction(ins
);
1986 /* Dead code elimination for branches at the end of a block - only one branch
1987 * per block is legal semantically */
1990 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
1992 bool branched
= false;
1994 mir_foreach_instr_in_block_safe(block
, ins
) {
1995 if (!midgard_is_branch_unit(ins
->unit
)) continue;
1997 /* We ignore prepacked branches since the fragment epilogue is
1998 * just generally special */
1999 if (ins
->prepacked_branch
) continue;
2001 /* Discards are similarly special and may not correspond to the
2004 if (ins
->branch
.target_type
== TARGET_DISCARD
) continue;
2007 /* We already branched, so this is dead */
2008 mir_remove_instruction(ins
);
2016 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
2019 if (!is_int
&& src
.mod
) return true;
2021 /* Other int mods don't matter in isolation */
2022 if (is_int
&& src
.mod
== midgard_int_shift
) return true;
2024 /* size-conversion */
2025 if (src
.half
) return true;
2028 for (unsigned c
= 0; c
< 4; ++c
) {
2029 if (!(mask
& (1 << c
))) continue;
2030 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
2037 mir_nontrivial_source2_mod(midgard_instruction
*ins
)
2039 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
2041 midgard_vector_alu_src src2
=
2042 vector_alu_from_unsigned(ins
->alu
.src2
);
2044 return mir_nontrivial_mod(src2
, is_int
, ins
->mask
);
2048 mir_nontrivial_outmod(midgard_instruction
*ins
)
2050 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
2051 unsigned mod
= ins
->alu
.outmod
;
2053 /* Type conversion is a sort of outmod */
2054 if (ins
->alu
.dest_override
!= midgard_dest_override_none
)
2058 return mod
!= midgard_outmod_int_wrap
;
2060 return mod
!= midgard_outmod_none
;
2064 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
2066 bool progress
= false;
2068 mir_foreach_instr_in_block_safe(block
, ins
) {
2069 if (ins
->type
!= TAG_ALU_4
) continue;
2070 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
2072 unsigned from
= ins
->ssa_args
.src1
;
2073 unsigned to
= ins
->ssa_args
.dest
;
2075 /* We only work on pure SSA */
2077 if (to
>= SSA_FIXED_MINIMUM
) continue;
2078 if (from
>= SSA_FIXED_MINIMUM
) continue;
2079 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
2080 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
2082 /* Constant propagation is not handled here, either */
2083 if (ins
->ssa_args
.inline_constant
) continue;
2084 if (ins
->has_constants
) continue;
2086 if (mir_nontrivial_source2_mod(ins
)) continue;
2087 if (mir_nontrivial_outmod(ins
)) continue;
2089 /* We're clear -- rewrite */
2090 mir_rewrite_index_src(ctx
, to
, from
);
2091 mir_remove_instruction(ins
);
2098 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2099 * the move can be propagated away entirely */
2102 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2105 if (comp
== midgard_outmod_none
)
2108 if (*outmod
== midgard_outmod_none
) {
2113 /* TODO: Compose rules */
2118 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2120 bool progress
= false;
2122 mir_foreach_instr_in_block_safe(block
, ins
) {
2123 if (ins
->type
!= TAG_ALU_4
) continue;
2124 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2125 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2127 /* TODO: Registers? */
2128 unsigned src
= ins
->ssa_args
.src1
;
2129 if (src
>= ctx
->func
->impl
->ssa_alloc
) continue;
2130 assert(!mir_has_multiple_writes(ctx
, src
));
2132 /* There might be a source modifier, too */
2133 if (mir_nontrivial_source2_mod(ins
)) continue;
2135 /* Backpropagate the modifier */
2136 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2137 if (v
->type
!= TAG_ALU_4
) continue;
2138 if (v
->ssa_args
.dest
!= src
) continue;
2140 /* Can we even take a float outmod? */
2141 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2143 midgard_outmod_float temp
= v
->alu
.outmod
;
2144 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2146 /* Throw in the towel.. */
2147 if (!progress
) break;
2149 /* Otherwise, transfer the modifier */
2150 v
->alu
.outmod
= temp
;
2151 ins
->alu
.outmod
= midgard_outmod_none
;
2161 emit_fragment_epilogue(compiler_context
*ctx
)
2163 /* Special case: writing out constants requires us to include the move
2164 * explicitly now, so shove it into r0 */
2166 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
2168 if (constant_value
) {
2169 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
2170 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
2171 emit_mir_instruction(ctx
, ins
);
2174 /* Perform the actual fragment writeout. We have two writeout/branch
2175 * instructions, forming a loop until writeout is successful as per the
2176 * docs. TODO: gl_FragDepth */
2178 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2179 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2182 static midgard_block
*
2183 emit_block(compiler_context
*ctx
, nir_block
*block
)
2185 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
2186 list_addtail(&this_block
->link
, &ctx
->blocks
);
2188 this_block
->is_scheduled
= false;
2191 ctx
->texture_index
[0] = -1;
2192 ctx
->texture_index
[1] = -1;
2194 /* Add us as a successor to the block we are following */
2195 if (ctx
->current_block
)
2196 midgard_block_add_successor(ctx
->current_block
, this_block
);
2198 /* Set up current block */
2199 list_inithead(&this_block
->instructions
);
2200 ctx
->current_block
= this_block
;
2202 nir_foreach_instr(instr
, block
) {
2203 emit_instr(ctx
, instr
);
2204 ++ctx
->instruction_count
;
2207 inline_alu_constants(ctx
);
2208 embedded_to_inline_constant(ctx
);
2210 /* Append fragment shader epilogue (value writeout) */
2211 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2212 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2213 emit_fragment_epilogue(ctx
);
2217 if (block
== nir_start_block(ctx
->func
->impl
))
2218 ctx
->initial_block
= this_block
;
2220 if (block
== nir_impl_last_block(ctx
->func
->impl
))
2221 ctx
->final_block
= this_block
;
2223 /* Allow the next control flow to access us retroactively, for
2225 ctx
->current_block
= this_block
;
2227 /* Document the fallthrough chain */
2228 ctx
->previous_source_block
= this_block
;
2233 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2236 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2238 /* Conditional branches expect the condition in r31.w; emit a move for
2239 * that in the _previous_ block (which is the current block). */
2240 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2242 /* Speculatively emit the branch, but we can't fill it in until later */
2243 EMIT(branch
, true, true);
2244 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2246 /* Emit the two subblocks */
2247 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2249 /* Emit a jump from the end of the then block to the end of the else */
2250 EMIT(branch
, false, false);
2251 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2253 /* Emit second block, and check if it's empty */
2255 int else_idx
= ctx
->block_count
;
2256 int count_in
= ctx
->instruction_count
;
2257 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2258 int after_else_idx
= ctx
->block_count
;
2260 /* Now that we have the subblocks emitted, fix up the branches */
2265 if (ctx
->instruction_count
== count_in
) {
2266 /* The else block is empty, so don't emit an exit jump */
2267 mir_remove_instruction(then_exit
);
2268 then_branch
->branch
.target_block
= after_else_idx
;
2270 then_branch
->branch
.target_block
= else_idx
;
2271 then_exit
->branch
.target_block
= after_else_idx
;
2276 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2278 /* Remember where we are */
2279 midgard_block
*start_block
= ctx
->current_block
;
2281 /* Allocate a loop number, growing the current inner loop depth */
2282 int loop_idx
= ++ctx
->current_loop_depth
;
2284 /* Get index from before the body so we can loop back later */
2285 int start_idx
= ctx
->block_count
;
2287 /* Emit the body itself */
2288 emit_cf_list(ctx
, &nloop
->body
);
2290 /* Branch back to loop back */
2291 struct midgard_instruction br_back
= v_branch(false, false);
2292 br_back
.branch
.target_block
= start_idx
;
2293 emit_mir_instruction(ctx
, br_back
);
2295 /* Mark down that branch in the graph. Note that we're really branching
2296 * to the block *after* we started in. TODO: Why doesn't the branch
2297 * itself have an off-by-one then...? */
2298 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
2300 /* Find the index of the block about to follow us (note: we don't add
2301 * one; blocks are 0-indexed so we get a fencepost problem) */
2302 int break_block_idx
= ctx
->block_count
;
2304 /* Fix up the break statements we emitted to point to the right place,
2305 * now that we can allocate a block number for them */
2307 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2308 mir_foreach_instr_in_block(block
, ins
) {
2309 if (ins
->type
!= TAG_ALU_4
) continue;
2310 if (!ins
->compact_branch
) continue;
2311 if (ins
->prepacked_branch
) continue;
2313 /* We found a branch -- check the type to see if we need to do anything */
2314 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2316 /* It's a break! Check if it's our break */
2317 if (ins
->branch
.target_break
!= loop_idx
) continue;
2319 /* Okay, cool, we're breaking out of this loop.
2320 * Rewrite from a break to a goto */
2322 ins
->branch
.target_type
= TARGET_GOTO
;
2323 ins
->branch
.target_block
= break_block_idx
;
2327 /* Now that we've finished emitting the loop, free up the depth again
2328 * so we play nice with recursion amid nested loops */
2329 --ctx
->current_loop_depth
;
2331 /* Dump loop stats */
2335 static midgard_block
*
2336 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2338 midgard_block
*start_block
= NULL
;
2340 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2341 switch (node
->type
) {
2342 case nir_cf_node_block
: {
2343 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2346 start_block
= block
;
2351 case nir_cf_node_if
:
2352 emit_if(ctx
, nir_cf_node_as_if(node
));
2355 case nir_cf_node_loop
:
2356 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2359 case nir_cf_node_function
:
2368 /* Due to lookahead, we need to report the first tag executed in the command
2369 * stream and in branch targets. An initial block might be empty, so iterate
2370 * until we find one that 'works' */
2373 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2375 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2377 unsigned first_tag
= 0;
2380 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
2382 if (initial_bundle
) {
2383 first_tag
= initial_bundle
->tag
;
2387 /* Initial block is empty, try the next block */
2388 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
2389 } while(initial_block
!= NULL
);
2396 midgard_compile_shader_nir(struct midgard_screen
*screen
, nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2398 struct util_dynarray
*compiled
= &program
->compiled
;
2400 midgard_debug
= debug_get_option_midgard_debug();
2402 compiler_context ictx
= {
2405 .stage
= nir
->info
.stage
,
2407 .is_blend
= is_blend
,
2408 .blend_constant_offset
= 0,
2410 .alpha_ref
= program
->alpha_ref
2413 compiler_context
*ctx
= &ictx
;
2415 /* Start off with a safe cutoff, allowing usage of all 16 work
2416 * registers. Later, we'll promote uniform reads to uniform registers
2417 * if we determine it is beneficial to do so */
2418 ctx
->uniform_cutoff
= 8;
2420 /* Initialize at a global (not block) level hash tables */
2422 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2423 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2424 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2426 /* Record the varying mapping for the command stream's bookkeeping */
2428 struct exec_list
*varyings
=
2429 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2431 unsigned max_varying
= 0;
2432 nir_foreach_variable(var
, varyings
) {
2433 unsigned loc
= var
->data
.driver_location
;
2434 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2436 for (int c
= 0; c
< sz
; ++c
) {
2437 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2438 max_varying
= MAX2(max_varying
, loc
+ c
);
2442 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2443 * (so we don't accidentally duplicate the epilogue since mesa/st has
2444 * messed with our I/O quite a bit already) */
2446 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2448 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2449 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2450 NIR_PASS_V(nir
, nir_clamp_psiz
, 1.0, 1024.0);
2453 NIR_PASS_V(nir
, nir_lower_var_copies
);
2454 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2455 NIR_PASS_V(nir
, nir_split_var_copies
);
2456 NIR_PASS_V(nir
, nir_lower_var_copies
);
2457 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2458 NIR_PASS_V(nir
, nir_lower_var_copies
);
2459 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2461 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2463 /* Optimisation passes */
2467 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2468 nir_print_shader(nir
, stdout
);
2471 /* Assign sysvals and counts, now that we're sure
2472 * (post-optimisation) */
2474 midgard_nir_assign_sysvals(ctx
, nir
);
2476 program
->uniform_count
= nir
->num_uniforms
;
2477 program
->sysval_count
= ctx
->sysval_count
;
2478 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2480 nir_foreach_function(func
, nir
) {
2484 list_inithead(&ctx
->blocks
);
2485 ctx
->block_count
= 0;
2488 emit_cf_list(ctx
, &func
->impl
->body
);
2489 emit_block(ctx
, func
->impl
->end_block
);
2491 break; /* TODO: Multi-function shaders */
2494 util_dynarray_init(compiled
, NULL
);
2496 /* MIR-level optimizations */
2498 bool progress
= false;
2503 mir_foreach_block(ctx
, block
) {
2504 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2505 progress
|= midgard_opt_copy_prop(ctx
, block
);
2506 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2510 /* Nested control-flow can result in dead branches at the end of the
2511 * block. This messes with our analysis and is just dead code, so cull
2513 mir_foreach_block(ctx
, block
) {
2514 midgard_opt_cull_dead_branch(ctx
, block
);
2518 schedule_program(ctx
);
2520 /* Now that all the bundles are scheduled and we can calculate block
2521 * sizes, emit actual branch instructions rather than placeholders */
2523 int br_block_idx
= 0;
2525 mir_foreach_block(ctx
, block
) {
2526 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2527 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2528 midgard_instruction
*ins
= bundle
->instructions
[c
];
2530 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2532 if (ins
->prepacked_branch
) continue;
2534 /* Parse some basic branch info */
2535 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2536 bool is_conditional
= ins
->branch
.conditional
;
2537 bool is_inverted
= ins
->branch
.invert_conditional
;
2538 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2540 /* Determine the block we're jumping to */
2541 int target_number
= ins
->branch
.target_block
;
2543 /* Report the destination tag */
2544 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2546 /* Count up the number of quadwords we're
2547 * jumping over = number of quadwords until
2548 * (br_block_idx, target_number) */
2550 int quadword_offset
= 0;
2553 /* Jump to the end of the shader. We
2554 * need to include not only the
2555 * following blocks, but also the
2556 * contents of our current block (since
2557 * discard can come in the middle of
2560 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
2562 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
2563 quadword_offset
+= quadword_size(bun
->tag
);
2566 mir_foreach_block_from(ctx
, blk
, b
) {
2567 quadword_offset
+= b
->quadword_count
;
2570 } else if (target_number
> br_block_idx
) {
2573 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2574 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2577 quadword_offset
+= blk
->quadword_count
;
2580 /* Jump backwards */
2582 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2583 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2586 quadword_offset
-= blk
->quadword_count
;
2590 /* Unconditional extended branches (far jumps)
2591 * have issues, so we always use a conditional
2592 * branch, setting the condition to always for
2593 * unconditional. For compact unconditional
2594 * branches, cond isn't used so it doesn't
2595 * matter what we pick. */
2597 midgard_condition cond
=
2598 !is_conditional
? midgard_condition_always
:
2599 is_inverted
? midgard_condition_false
:
2600 midgard_condition_true
;
2602 midgard_jmp_writeout_op op
=
2603 is_discard
? midgard_jmp_writeout_op_discard
:
2604 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2605 midgard_jmp_writeout_op_branch_cond
;
2608 midgard_branch_extended branch
=
2609 midgard_create_branch_extended(
2614 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2615 } else if (is_conditional
|| is_discard
) {
2616 midgard_branch_cond branch
= {
2618 .dest_tag
= dest_tag
,
2619 .offset
= quadword_offset
,
2623 assert(branch
.offset
== quadword_offset
);
2625 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2627 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2629 midgard_branch_uncond branch
= {
2631 .dest_tag
= dest_tag
,
2632 .offset
= quadword_offset
,
2636 assert(branch
.offset
== quadword_offset
);
2638 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2646 /* Emit flat binary from the instruction arrays. Iterate each block in
2647 * sequence. Save instruction boundaries such that lookahead tags can
2648 * be assigned easily */
2650 /* Cache _all_ bundles in source order for lookahead across failed branches */
2652 int bundle_count
= 0;
2653 mir_foreach_block(ctx
, block
) {
2654 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2656 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2658 mir_foreach_block(ctx
, block
) {
2659 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2660 source_order_bundles
[bundle_idx
++] = bundle
;
2664 int current_bundle
= 0;
2666 /* Midgard prefetches instruction types, so during emission we
2667 * need to lookahead. Unless this is the last instruction, in
2668 * which we return 1. Or if this is the second to last and the
2669 * last is an ALU, then it's also 1... */
2671 mir_foreach_block(ctx
, block
) {
2672 mir_foreach_bundle_in_block(block
, bundle
) {
2675 if (current_bundle
+ 1 < bundle_count
) {
2676 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2678 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2685 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2689 /* TODO: Free deeper */
2690 //util_dynarray_fini(&block->instructions);
2693 free(source_order_bundles
);
2695 /* Report the very first tag executed */
2696 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2698 /* Deal with off-by-one related to the fencepost problem */
2699 program
->work_register_count
= ctx
->work_registers
+ 1;
2700 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2702 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2703 program
->tls_size
= ctx
->tls_size
;
2705 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2706 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);
2708 if (midgard_debug
& MIDGARD_DBG_SHADERDB
) {
2709 unsigned nr_bundles
= 0, nr_ins
= 0, nr_quadwords
= 0;
2711 /* Count instructions and bundles */
2713 mir_foreach_instr_global(ctx
, ins
) {
2717 mir_foreach_block(ctx
, block
) {
2718 nr_bundles
+= util_dynarray_num_elements(
2719 &block
->bundles
, midgard_bundle
);
2721 nr_quadwords
+= block
->quadword_count
;
2724 /* Calculate thread count. There are certain cutoffs by
2725 * register count for thread count */
2727 unsigned nr_registers
= program
->work_register_count
;
2729 unsigned nr_threads
=
2730 (nr_registers
<= 4) ? 4 :
2731 (nr_registers
<= 8) ? 2 :
2736 fprintf(stderr
, "shader%d - %s shader: "
2737 "%u inst, %u bundles, %u quadwords, "
2738 "%u registers, %u threads, %u loops, "
2739 "%d:%d spills:fills\n",
2741 gl_shader_stage_name(ctx
->stage
),
2742 nr_ins
, nr_bundles
, nr_quadwords
,
2743 nr_registers
, nr_threads
,
2745 ctx
->spills
, ctx
->fills
);