2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
63 unsigned SHADER_DB_COUNT
= 0;
65 int midgard_debug
= 0;
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 midgard_is_branch_unit(unsigned unit
)
75 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
79 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
85 for (unsigned i
= 0; i
< block
->nr_successors
; ++i
) {
86 if (block
->successors
[i
] == successor
)
90 block
->successors
[block
->nr_successors
++] = successor
;
91 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
94 /* Helpers to generate midgard_instruction's using macro magic, since every
95 * driver seems to do it that way */
97 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
99 #define M_LOAD_STORE(name, store) \
100 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
101 midgard_instruction i = { \
102 .type = TAG_LOAD_STORE_4, \
106 .src = { -1, -1, -1 }, \
109 .op = midgard_op_##name, \
110 .swizzle = SWIZZLE_XYZW, \
116 i.ssa_args.src[0] = ssa; \
118 i.ssa_args.dest = ssa; \
123 #define M_LOAD(name) M_LOAD_STORE(name, false)
124 #define M_STORE(name) M_LOAD_STORE(name, true)
126 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
127 * the corresponding Midgard source */
129 static midgard_vector_alu_src
130 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
131 bool half
, bool sext
)
133 if (!src
) return blank_alu_src
;
135 /* Figure out how many components there are so we can adjust the
136 * swizzle. Specifically we want to broadcast the last channel so
137 * things like ball2/3 work
140 if (broadcast_count
) {
141 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
143 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
144 src
->swizzle
[c
] = last_component
;
148 midgard_vector_alu_src alu_src
= {
152 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
156 alu_src
.mod
= midgard_int_normal
;
158 /* Sign/zero-extend if needed */
162 midgard_int_sign_extend
163 : midgard_int_zero_extend
;
166 /* These should have been lowered away */
167 assert(!(src
->abs
|| src
->negate
));
169 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
175 /* load/store instructions have both 32-bit and 16-bit variants, depending on
176 * whether we are using vectors composed of highp or mediump. At the moment, we
177 * don't support half-floats -- this requires changes in other parts of the
178 * compiler -- therefore the 16-bit versions are commented out. */
180 //M_LOAD(ld_attr_16);
182 //M_LOAD(ld_vary_16);
184 //M_LOAD(ld_uniform_16);
185 M_LOAD(ld_uniform_32
);
186 M_LOAD(ld_color_buffer_8
);
187 //M_STORE(st_vary_16);
189 M_LOAD(st_cubemap_coords
);
191 static midgard_instruction
192 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
194 midgard_branch_cond branch
= {
202 memcpy(&compact
, &branch
, sizeof(branch
));
204 midgard_instruction ins
= {
206 .unit
= ALU_ENAB_BR_COMPACT
,
207 .prepacked_branch
= true,
208 .compact_branch
= true,
209 .br_compact
= compact
,
212 .src
= { -1, -1, -1 },
216 if (op
== midgard_jmp_writeout_op_writeout
)
222 static midgard_instruction
223 v_branch(bool conditional
, bool invert
)
225 midgard_instruction ins
= {
227 .unit
= ALU_ENAB_BRANCH
,
228 .compact_branch
= true,
230 .conditional
= conditional
,
231 .invert_conditional
= invert
235 .src
= { -1, -1, -1 },
242 static midgard_branch_extended
243 midgard_create_branch_extended( midgard_condition cond
,
244 midgard_jmp_writeout_op op
,
246 signed quadword_offset
)
248 /* The condition code is actually a LUT describing a function to
249 * combine multiple condition codes. However, we only support a single
250 * condition code at the moment, so we just duplicate over a bunch of
253 uint16_t duplicated_cond
=
263 midgard_branch_extended branch
= {
265 .dest_tag
= dest_tag
,
266 .offset
= quadword_offset
,
267 .cond
= duplicated_cond
274 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
276 ins
->has_constants
= true;
277 memcpy(&ins
->constants
, constants
, 16);
281 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
283 return glsl_count_attribute_slots(type
, false);
286 /* Lower fdot2 to a vector multiplication followed by channel addition */
288 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
290 if (alu
->op
!= nir_op_fdot2
)
293 b
->cursor
= nir_before_instr(&alu
->instr
);
295 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
296 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
298 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
300 nir_ssa_def
*sum
= nir_fadd(b
,
301 nir_channel(b
, product
, 0),
302 nir_channel(b
, product
, 1));
304 /* Replace the fdot2 with this sum */
305 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
309 midgard_sysval_for_ssbo(nir_intrinsic_instr
*instr
)
311 nir_src index
= instr
->src
[0];
312 assert(nir_src_is_const(index
));
313 uint32_t uindex
= nir_src_as_uint(index
);
315 return PAN_SYSVAL(SSBO
, uindex
);
319 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
321 switch (instr
->intrinsic
) {
322 case nir_intrinsic_load_viewport_scale
:
323 return PAN_SYSVAL_VIEWPORT_SCALE
;
324 case nir_intrinsic_load_viewport_offset
:
325 return PAN_SYSVAL_VIEWPORT_OFFSET
;
326 case nir_intrinsic_load_ssbo
:
327 return midgard_sysval_for_ssbo(instr
);
333 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
336 nir_intrinsic_instr
*intr
;
337 nir_dest
*dst
= NULL
;
341 switch (instr
->type
) {
342 case nir_instr_type_intrinsic
:
343 intr
= nir_instr_as_intrinsic(instr
);
344 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
347 case nir_instr_type_tex
:
348 tex
= nir_instr_as_tex(instr
);
349 if (tex
->op
!= nir_texop_txs
)
352 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
353 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
354 nir_tex_instr_dest_size(tex
) -
355 (tex
->is_array
? 1 : 0),
364 *dest
= nir_dest_index(ctx
, dst
);
370 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
374 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
378 /* We have a sysval load; check if it's already been assigned */
380 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
383 /* It hasn't -- so assign it now! */
385 unsigned id
= ctx
->sysval_count
++;
386 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
387 ctx
->sysvals
[id
] = sysval
;
391 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
393 ctx
->sysval_count
= 0;
395 nir_foreach_function(function
, shader
) {
396 if (!function
->impl
) continue;
398 nir_foreach_block(block
, function
->impl
) {
399 nir_foreach_instr_safe(instr
, block
) {
400 midgard_nir_assign_sysval_body(ctx
, instr
);
407 midgard_nir_lower_fdot2(nir_shader
*shader
)
409 bool progress
= false;
411 nir_foreach_function(function
, shader
) {
412 if (!function
->impl
) continue;
415 nir_builder
*b
= &_b
;
416 nir_builder_init(b
, function
->impl
);
418 nir_foreach_block(block
, function
->impl
) {
419 nir_foreach_instr_safe(instr
, block
) {
420 if (instr
->type
!= nir_instr_type_alu
) continue;
422 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
423 midgard_nir_lower_fdot2_body(b
, alu
);
429 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
436 /* Flushes undefined values to zero */
439 optimise_nir(nir_shader
*nir
)
442 unsigned lower_flrp
=
443 (nir
->options
->lower_flrp16
? 16 : 0) |
444 (nir
->options
->lower_flrp32
? 32 : 0) |
445 (nir
->options
->lower_flrp64
? 64 : 0);
447 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
448 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
449 NIR_PASS(progress
, nir
, nir_lower_idiv
);
451 nir_lower_tex_options lower_tex_1st_pass_options
= {
456 nir_lower_tex_options lower_tex_2nd_pass_options
= {
457 .lower_txs_lod
= true,
460 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_1st_pass_options
);
461 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_2nd_pass_options
);
466 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
467 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
469 NIR_PASS(progress
, nir
, nir_copy_prop
);
470 NIR_PASS(progress
, nir
, nir_opt_dce
);
471 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
472 NIR_PASS(progress
, nir
, nir_opt_cse
);
473 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
474 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
475 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
477 if (lower_flrp
!= 0) {
478 bool lower_flrp_progress
= false;
479 NIR_PASS(lower_flrp_progress
,
483 false /* always_precise */,
484 nir
->options
->lower_ffma
);
485 if (lower_flrp_progress
) {
486 NIR_PASS(progress
, nir
,
487 nir_opt_constant_folding
);
491 /* Nothing should rematerialize any flrps, so we only
492 * need to do this lowering once.
497 NIR_PASS(progress
, nir
, nir_opt_undef
);
498 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
500 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
503 nir_var_function_temp
);
505 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
508 /* Must be run at the end to prevent creation of fsin/fcos ops */
509 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
514 NIR_PASS(progress
, nir
, nir_opt_dce
);
515 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
516 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
517 NIR_PASS(progress
, nir
, nir_copy_prop
);
520 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
522 /* We implement booleans as 32-bit 0/~0 */
523 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
525 /* Now that booleans are lowered, we can run out late opts */
526 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
528 /* Lower mods for float ops only. Integer ops don't support modifiers
529 * (saturate doesn't make sense on integers, neg/abs require dedicated
532 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
533 NIR_PASS(progress
, nir
, nir_copy_prop
);
534 NIR_PASS(progress
, nir
, nir_opt_dce
);
536 /* Take us out of SSA */
537 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
538 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
540 /* We are a vector architecture; write combine where possible */
541 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
542 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
544 NIR_PASS(progress
, nir
, nir_opt_dce
);
547 /* Do not actually emit a load; instead, cache the constant for inlining */
550 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
552 nir_ssa_def def
= instr
->def
;
554 float *v
= rzalloc_array(NULL
, float, 4);
555 nir_const_load_to_arr(v
, instr
, f32
);
557 /* Shifted for SSA, +1 for off-by-one */
558 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, v
);
561 /* Normally constants are embedded implicitly, but for I/O and such we have to
562 * explicitly emit a move with the constant source */
565 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
567 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
569 if (constant_value
) {
570 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, to
);
571 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
572 emit_mir_instruction(ctx
, ins
);
577 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
579 unsigned comp
= src
->swizzle
[0];
581 for (unsigned c
= 1; c
< nr_components
; ++c
) {
582 if (src
->swizzle
[c
] != comp
)
589 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
590 * output of a conditional test) into that register */
593 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
595 int condition
= nir_src_index(ctx
, src
);
597 /* Source to swizzle the desired component into w */
599 const midgard_vector_alu_src alu_src
= {
600 .swizzle
= SWIZZLE(component
, component
, component
, component
),
603 /* There is no boolean move instruction. Instead, we simulate a move by
604 * ANDing the condition with itself to get it into r31.w */
606 midgard_instruction ins
= {
609 /* We need to set the conditional as close as possible */
610 .precede_break
= true,
611 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
612 .mask
= 1 << COMPONENT_W
,
615 .src
= { condition
, condition
, -1 },
616 .dest
= SSA_FIXED_REGISTER(31),
620 .op
= midgard_alu_op_iand
,
621 .outmod
= midgard_outmod_int_wrap
,
622 .reg_mode
= midgard_reg_mode_32
,
623 .dest_override
= midgard_dest_override_none
,
624 .src1
= vector_alu_srco_unsigned(alu_src
),
625 .src2
= vector_alu_srco_unsigned(alu_src
)
629 emit_mir_instruction(ctx
, ins
);
632 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
636 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
638 int condition
= nir_src_index(ctx
, &src
->src
);
640 /* Source to swizzle the desired component into w */
642 const midgard_vector_alu_src alu_src
= {
643 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
646 /* There is no boolean move instruction. Instead, we simulate a move by
647 * ANDing the condition with itself to get it into r31.w */
649 midgard_instruction ins
= {
651 .precede_break
= true,
652 .mask
= mask_of(nr_comp
),
654 .src
= { condition
, condition
, -1 },
655 .dest
= SSA_FIXED_REGISTER(31),
658 .op
= midgard_alu_op_iand
,
659 .outmod
= midgard_outmod_int_wrap
,
660 .reg_mode
= midgard_reg_mode_32
,
661 .dest_override
= midgard_dest_override_none
,
662 .src1
= vector_alu_srco_unsigned(alu_src
),
663 .src2
= vector_alu_srco_unsigned(alu_src
)
667 emit_mir_instruction(ctx
, ins
);
670 #define ALU_CASE(nir, _op) \
672 op = midgard_alu_op_##_op; \
673 assert(src_bitsize == dst_bitsize); \
676 #define ALU_CASE_BCAST(nir, _op, count) \
678 op = midgard_alu_op_##_op; \
679 broadcast_swizzle = count; \
680 assert(src_bitsize == dst_bitsize); \
683 nir_is_fzero_constant(nir_src src
)
685 if (!nir_src_is_const(src
))
688 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
689 if (nir_src_comp_as_float(src
, c
) != 0.0)
696 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
697 * special treatment override this anyway. */
699 static midgard_reg_mode
700 reg_mode_for_nir(nir_alu_instr
*instr
)
702 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
704 switch (src_bitsize
) {
706 return midgard_reg_mode_8
;
708 return midgard_reg_mode_16
;
710 return midgard_reg_mode_32
;
712 return midgard_reg_mode_64
;
714 unreachable("Invalid bit size");
719 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
721 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
722 * is handled elsewhere */
724 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
725 midgard_emit_derivatives(ctx
, instr
);
729 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
731 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
732 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
733 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
735 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
736 * supported. A few do not and are commented for now. Also, there are a
737 * number of NIR ops which Midgard does not support and need to be
738 * lowered, also TODO. This switch block emits the opcode and calling
739 * convention of the Midgard instruction; actual packing is done in
744 /* Number of components valid to check for the instruction (the rest
745 * will be forced to the last), or 0 to use as-is. Relevant as
746 * ball-type instructions have a channel count in NIR but are all vec4
749 unsigned broadcast_swizzle
= 0;
751 /* What register mode should we operate in? */
752 midgard_reg_mode reg_mode
=
753 reg_mode_for_nir(instr
);
755 /* Do we need a destination override? Used for inline
758 midgard_dest_override dest_override
=
759 midgard_dest_override_none
;
761 /* Should we use a smaller respective source and sign-extend? */
763 bool half_1
= false, sext_1
= false;
764 bool half_2
= false, sext_2
= false;
766 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
767 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
770 ALU_CASE(fadd
, fadd
);
771 ALU_CASE(fmul
, fmul
);
772 ALU_CASE(fmin
, fmin
);
773 ALU_CASE(fmax
, fmax
);
774 ALU_CASE(imin
, imin
);
775 ALU_CASE(imax
, imax
);
776 ALU_CASE(umin
, umin
);
777 ALU_CASE(umax
, umax
);
778 ALU_CASE(ffloor
, ffloor
);
779 ALU_CASE(fround_even
, froundeven
);
780 ALU_CASE(ftrunc
, ftrunc
);
781 ALU_CASE(fceil
, fceil
);
782 ALU_CASE(fdot3
, fdot3
);
783 ALU_CASE(fdot4
, fdot4
);
784 ALU_CASE(iadd
, iadd
);
785 ALU_CASE(isub
, isub
);
786 ALU_CASE(imul
, imul
);
788 /* Zero shoved as second-arg */
789 ALU_CASE(iabs
, iabsdiff
);
793 ALU_CASE(feq32
, feq
);
794 ALU_CASE(fne32
, fne
);
795 ALU_CASE(flt32
, flt
);
796 ALU_CASE(ieq32
, ieq
);
797 ALU_CASE(ine32
, ine
);
798 ALU_CASE(ilt32
, ilt
);
799 ALU_CASE(ult32
, ult
);
801 /* We don't have a native b2f32 instruction. Instead, like many
802 * GPUs, we exploit booleans as 0/~0 for false/true, and
803 * correspondingly AND
804 * by 1.0 to do the type conversion. For the moment, prime us
807 * iand [whatever], #0
809 * At the end of emit_alu (as MIR), we'll fix-up the constant
812 ALU_CASE(b2f32
, iand
);
813 ALU_CASE(b2i32
, iand
);
815 /* Likewise, we don't have a dedicated f2b32 instruction, but
816 * we can do a "not equal to 0.0" test. */
818 ALU_CASE(f2b32
, fne
);
819 ALU_CASE(i2b32
, ine
);
821 ALU_CASE(frcp
, frcp
);
822 ALU_CASE(frsq
, frsqrt
);
823 ALU_CASE(fsqrt
, fsqrt
);
824 ALU_CASE(fexp2
, fexp2
);
825 ALU_CASE(flog2
, flog2
);
827 ALU_CASE(f2i32
, f2i_rtz
);
828 ALU_CASE(f2u32
, f2u_rtz
);
829 ALU_CASE(i2f32
, i2f_rtz
);
830 ALU_CASE(u2f32
, u2f_rtz
);
832 ALU_CASE(f2i16
, f2i_rtz
);
833 ALU_CASE(f2u16
, f2u_rtz
);
834 ALU_CASE(i2f16
, i2f_rtz
);
835 ALU_CASE(u2f16
, u2f_rtz
);
837 ALU_CASE(fsin
, fsin
);
838 ALU_CASE(fcos
, fcos
);
840 /* We'll set invert */
841 ALU_CASE(inot
, imov
);
842 ALU_CASE(iand
, iand
);
844 ALU_CASE(ixor
, ixor
);
845 ALU_CASE(ishl
, ishl
);
846 ALU_CASE(ishr
, iasr
);
847 ALU_CASE(ushr
, ilsr
);
849 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
850 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
851 ALU_CASE(b32all_fequal4
, fball_eq
);
853 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
854 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
855 ALU_CASE(b32any_fnequal4
, fbany_neq
);
857 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
858 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
859 ALU_CASE(b32all_iequal4
, iball_eq
);
861 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
862 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
863 ALU_CASE(b32any_inequal4
, ibany_neq
);
865 /* Source mods will be shoved in later */
866 ALU_CASE(fabs
, fmov
);
867 ALU_CASE(fneg
, fmov
);
868 ALU_CASE(fsat
, fmov
);
870 /* For size conversion, we use a move. Ideally though we would squash
871 * these ops together; maybe that has to happen after in NIR as part of
872 * propagation...? An earlier algebraic pass ensured we step down by
873 * only / exactly one size. If stepping down, we use a dest override to
874 * reduce the size; if stepping up, we use a larger-sized move with a
875 * half source and a sign/zero-extension modifier */
880 /* If we end up upscale, we'll need a sign-extend on the
881 * operand (the second argument) */
887 op
= midgard_alu_op_imov
;
889 if (dst_bitsize
== (src_bitsize
* 2)) {
893 /* Use a greater register mode */
895 } else if (src_bitsize
== (dst_bitsize
* 2)) {
896 /* Converting down */
897 dest_override
= midgard_dest_override_lower
;
904 assert(src_bitsize
== 32);
906 op
= midgard_alu_op_fmov
;
907 dest_override
= midgard_dest_override_lower
;
912 assert(src_bitsize
== 16);
914 op
= midgard_alu_op_fmov
;
921 /* For greater-or-equal, we lower to less-or-equal and flip the
929 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
930 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
931 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
932 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
935 /* Swap via temporary */
936 nir_alu_src temp
= instr
->src
[1];
937 instr
->src
[1] = instr
->src
[0];
938 instr
->src
[0] = temp
;
943 case nir_op_b32csel
: {
944 /* Midgard features both fcsel and icsel, depending on
945 * the type of the arguments/output. However, as long
946 * as we're careful we can _always_ use icsel and
947 * _never_ need fcsel, since the latter does additional
948 * floating-point-specific processing whereas the
949 * former just moves bits on the wire. It's not obvious
950 * why these are separate opcodes, save for the ability
951 * to do things like sat/pos/abs/neg for free */
953 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
954 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
956 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
959 /* Emit the condition into r31 */
962 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
964 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
966 /* The condition is the first argument; move the other
967 * arguments up one to be a binary instruction for
970 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
975 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
980 /* Midgard can perform certain modifiers on output of an ALU op */
983 if (midgard_is_integer_out_op(op
)) {
984 outmod
= midgard_outmod_int_wrap
;
986 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
987 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
990 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
992 if (instr
->op
== nir_op_fmax
) {
993 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
994 op
= midgard_alu_op_fmov
;
996 outmod
= midgard_outmod_pos
;
997 instr
->src
[0] = instr
->src
[1];
998 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
999 op
= midgard_alu_op_fmov
;
1001 outmod
= midgard_outmod_pos
;
1005 /* Fetch unit, quirks, etc information */
1006 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1007 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1009 /* src0 will always exist afaik, but src1 will not for 1-argument
1010 * instructions. The latter can only be fetched if the instruction
1011 * needs it, or else we may segfault. */
1013 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1014 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1016 /* Rather than use the instruction generation helpers, we do it
1017 * ourselves here to avoid the mess */
1019 midgard_instruction ins
= {
1023 quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1024 quirk_flipped_r24
? src0
: src1
,
1031 nir_alu_src
*nirmods
[2] = { NULL
};
1033 if (nr_inputs
== 2) {
1034 nirmods
[0] = &instr
->src
[0];
1035 nirmods
[1] = &instr
->src
[1];
1036 } else if (nr_inputs
== 1) {
1037 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1042 /* These were lowered to a move, so apply the corresponding mod */
1044 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1045 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
1047 if (instr
->op
== nir_op_fneg
)
1048 s
->negate
= !s
->negate
;
1050 if (instr
->op
== nir_op_fabs
)
1054 bool is_int
= midgard_is_integer_op(op
);
1056 ins
.mask
= mask_of(nr_components
);
1058 midgard_vector_alu alu
= {
1060 .reg_mode
= reg_mode
,
1061 .dest_override
= dest_override
,
1064 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1065 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1068 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1071 ins
.mask
&= instr
->dest
.write_mask
;
1075 /* Late fixup for emulated instructions */
1077 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1078 /* Presently, our second argument is an inline #0 constant.
1079 * Switch over to an embedded 1.0 constant (that can't fit
1080 * inline, since we're 32-bit, not 16-bit like the inline
1083 ins
.ssa_args
.inline_constant
= false;
1084 ins
.ssa_args
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1085 ins
.has_constants
= true;
1087 if (instr
->op
== nir_op_b2f32
) {
1088 ins
.constants
[0] = 1.0f
;
1090 /* Type pun it into place */
1092 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1095 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1096 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1097 /* Lots of instructions need a 0 plonked in */
1098 ins
.ssa_args
.inline_constant
= false;
1099 ins
.ssa_args
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1100 ins
.has_constants
= true;
1101 ins
.constants
[0] = 0.0f
;
1102 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1103 } else if (instr
->op
== nir_op_inot
) {
1107 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1108 /* To avoid duplicating the lookup tables (probably), true LUT
1109 * instructions can only operate as if they were scalars. Lower
1110 * them here by changing the component. */
1112 uint8_t original_swizzle
[4];
1113 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1114 unsigned orig_mask
= ins
.mask
;
1116 for (int i
= 0; i
< nr_components
; ++i
) {
1117 /* Mask the associated component, dropping the
1118 * instruction if needed */
1121 ins
.mask
&= orig_mask
;
1126 for (int j
= 0; j
< 4; ++j
)
1127 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1129 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, false));
1130 emit_mir_instruction(ctx
, ins
);
1133 emit_mir_instruction(ctx
, ins
);
1139 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1140 * optimized) versions of UBO #0 */
1142 midgard_instruction
*
1144 compiler_context
*ctx
,
1147 nir_src
*indirect_offset
,
1150 /* TODO: half-floats */
1152 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
1154 /* TODO: Don't split */
1155 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1156 ins
.load_store
.address
= offset
>> 3;
1158 if (indirect_offset
) {
1159 ins
.ssa_args
.src
[1] = nir_src_index(ctx
, indirect_offset
);
1160 ins
.load_store
.arg_2
= 0x80;
1162 ins
.load_store
.arg_2
= 0x1E;
1165 ins
.load_store
.arg_1
= index
;
1167 return emit_mir_instruction(ctx
, ins
);
1172 compiler_context
*ctx
,
1173 unsigned dest
, unsigned offset
,
1174 unsigned nr_comp
, unsigned component
,
1175 nir_src
*indirect_offset
, nir_alu_type type
)
1177 /* XXX: Half-floats? */
1178 /* TODO: swizzle, mask */
1180 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1181 ins
.mask
= mask_of(nr_comp
);
1182 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1184 midgard_varying_parameter p
= {
1186 .interpolation
= midgard_interp_default
,
1187 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1191 memcpy(&u
, &p
, sizeof(p
));
1192 ins
.load_store
.varying_parameters
= u
;
1194 if (indirect_offset
)
1195 ins
.ssa_args
.src
[1] = nir_src_index(ctx
, indirect_offset
);
1197 ins
.load_store
.arg_2
= 0x1E;
1199 ins
.load_store
.arg_1
= 0x9E;
1201 /* Use the type appropriate load */
1205 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1208 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1210 case nir_type_float
:
1211 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1214 unreachable("Attempted to load unknown type");
1218 emit_mir_instruction(ctx
, ins
);
1222 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
, signed dest_override
,
1223 unsigned nr_components
)
1227 /* Figure out which uniform this is */
1228 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1229 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1231 if (dest_override
>= 0)
1232 dest
= dest_override
;
1234 /* Sysvals are prefix uniforms */
1235 unsigned uniform
= ((uintptr_t) val
) - 1;
1237 /* Emit the read itself -- this is never indirect */
1238 midgard_instruction
*ins
=
1239 emit_ubo_read(ctx
, dest
, uniform
, NULL
, 0);
1241 ins
->mask
= mask_of(nr_components
);
1245 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1247 unsigned offset
= 0, reg
;
1249 switch (instr
->intrinsic
) {
1250 case nir_intrinsic_discard_if
:
1251 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1255 case nir_intrinsic_discard
: {
1256 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1257 struct midgard_instruction discard
= v_branch(conditional
, false);
1258 discard
.branch
.target_type
= TARGET_DISCARD
;
1259 emit_mir_instruction(ctx
, discard
);
1263 case nir_intrinsic_load_uniform
:
1264 case nir_intrinsic_load_ubo
:
1265 case nir_intrinsic_load_input
: {
1266 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1267 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1269 /* Get the base type of the intrinsic */
1270 /* TODO: Infer type? Does it matter? */
1272 is_ubo
? nir_type_uint
: nir_intrinsic_type(instr
);
1273 t
= nir_alu_type_get_base_type(t
);
1276 offset
= nir_intrinsic_base(instr
);
1279 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1281 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1283 bool direct
= nir_src_is_const(*src_offset
);
1286 offset
+= nir_src_as_uint(*src_offset
);
1288 /* We may need to apply a fractional offset */
1289 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1290 nir_intrinsic_component(instr
) : 0;
1291 reg
= nir_dest_index(ctx
, &instr
->dest
);
1293 if (is_uniform
&& !ctx
->is_blend
) {
1294 emit_ubo_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
, 0);
1295 } else if (is_ubo
) {
1296 nir_src index
= instr
->src
[0];
1298 /* We don't yet support indirect UBOs. For indirect
1299 * block numbers (if that's possible), we don't know
1300 * enough about the hardware yet. For indirect sources,
1301 * we know what we need but we need to add some NIR
1302 * support for lowering correctly with respect to
1305 assert(nir_src_is_const(index
));
1306 assert(nir_src_is_const(*src_offset
));
1308 /* TODO: Alignment */
1309 assert((offset
& 0xF) == 0);
1311 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1312 emit_ubo_read(ctx
, reg
, offset
/ 16, NULL
, uindex
);
1313 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1314 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
, t
);
1315 } else if (ctx
->is_blend
) {
1316 /* For blend shaders, load the input color, which is
1317 * preloaded to r0 */
1319 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), blank_alu_src
, reg
);
1320 emit_mir_instruction(ctx
, move
);
1321 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1322 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1323 ins
.load_store
.arg_1
= 0x1E;
1324 ins
.load_store
.arg_2
= 0x1E;
1325 ins
.mask
= mask_of(nr_comp
);
1327 /* Use the type appropriate load */
1331 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1334 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1336 case nir_type_float
:
1337 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1340 unreachable("Attempted to load unknown type");
1344 emit_mir_instruction(ctx
, ins
);
1346 DBG("Unknown load\n");
1353 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1355 case nir_intrinsic_load_raw_output_pan
:
1356 reg
= nir_dest_index(ctx
, &instr
->dest
);
1357 assert(ctx
->is_blend
);
1359 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1360 emit_mir_instruction(ctx
, ins
);
1363 case nir_intrinsic_load_blend_const_color_rgba
: {
1364 assert(ctx
->is_blend
);
1365 reg
= nir_dest_index(ctx
, &instr
->dest
);
1367 /* Blend constants are embedded directly in the shader and
1368 * patched in, so we use some magic routing */
1370 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1371 ins
.has_constants
= true;
1372 ins
.has_blend_constant
= true;
1373 emit_mir_instruction(ctx
, ins
);
1377 case nir_intrinsic_store_output
:
1378 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1380 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1382 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1384 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1385 /* gl_FragColor is not emitted with load/store
1386 * instructions. Instead, it gets plonked into
1387 * r0 at the end of the shader and we do the
1388 * framebuffer writeout dance. TODO: Defer
1391 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1392 emit_mir_instruction(ctx
, move
);
1394 /* Save the index we're writing to for later reference
1395 * in the epilogue */
1397 ctx
->fragment_output
= reg
;
1398 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1399 /* We should have been vectorized, though we don't
1400 * currently check that st_vary is emitted only once
1401 * per slot (this is relevant, since there's not a mask
1402 * parameter available on the store [set to 0 by the
1403 * blob]). We do respect the component by adjusting the
1404 * swizzle. If this is a constant source, we'll need to
1405 * emit that explicitly. */
1407 emit_explicit_constant(ctx
, reg
, reg
);
1409 unsigned component
= nir_intrinsic_component(instr
);
1411 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1412 st
.load_store
.arg_1
= 0x9E;
1413 st
.load_store
.arg_2
= 0x1E;
1414 st
.load_store
.swizzle
= SWIZZLE_XYZW
<< (2*component
);
1415 emit_mir_instruction(ctx
, st
);
1417 DBG("Unknown store\n");
1423 /* Special case of store_output for lowered blend shaders */
1424 case nir_intrinsic_store_raw_output_pan
:
1425 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1426 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1428 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1429 emit_mir_instruction(ctx
, move
);
1430 ctx
->fragment_output
= reg
;
1434 case nir_intrinsic_load_alpha_ref_float
:
1435 assert(instr
->dest
.is_ssa
);
1437 float ref_value
= ctx
->alpha_ref
;
1439 /* See emit_load_const */
1440 float *v
= ralloc_array(NULL
, float, 4);
1441 memcpy(v
, &ref_value
, sizeof(float));
1442 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (instr
->dest
.ssa
.index
<< 1) + 1, v
);
1445 case nir_intrinsic_load_viewport_scale
:
1446 case nir_intrinsic_load_viewport_offset
:
1447 emit_sysval_read(ctx
, &instr
->instr
, -1, 3);
1451 printf ("Unhandled intrinsic\n");
1458 midgard_tex_format(enum glsl_sampler_dim dim
)
1461 case GLSL_SAMPLER_DIM_1D
:
1462 case GLSL_SAMPLER_DIM_BUF
:
1465 case GLSL_SAMPLER_DIM_2D
:
1466 case GLSL_SAMPLER_DIM_EXTERNAL
:
1469 case GLSL_SAMPLER_DIM_3D
:
1472 case GLSL_SAMPLER_DIM_CUBE
:
1473 return MALI_TEX_CUBE
;
1476 DBG("Unknown sampler dim type\n");
1482 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1486 pan_attach_constant_bias(
1487 compiler_context
*ctx
,
1489 midgard_texture_word
*word
)
1491 /* To attach as constant, it has to *be* constant */
1493 if (!nir_src_is_const(lod
))
1496 float f
= nir_src_as_float(lod
);
1498 /* Break into fixed-point */
1500 float lod_frac
= f
- lod_int
;
1502 /* Carry over negative fractions */
1503 if (lod_frac
< 0.0) {
1509 word
->bias
= float_to_ubyte(lod_frac
);
1510 word
->bias_int
= lod_int
;
1515 static enum mali_sampler_type
1516 midgard_sampler_type(nir_alu_type t
) {
1517 switch (nir_alu_type_get_base_type(t
))
1519 case nir_type_float
:
1520 return MALI_SAMPLER_FLOAT
;
1522 return MALI_SAMPLER_SIGNED
;
1524 return MALI_SAMPLER_UNSIGNED
;
1526 unreachable("Unknown sampler type");
1531 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1532 unsigned midgard_texop
)
1535 //assert (!instr->sampler);
1536 //assert (!instr->texture_array_size);
1538 int texture_index
= instr
->texture_index
;
1539 int sampler_index
= texture_index
;
1541 /* No helper to build texture words -- we do it all here */
1542 midgard_instruction ins
= {
1543 .type
= TAG_TEXTURE_4
,
1546 .dest
= nir_dest_index(ctx
, &instr
->dest
),
1547 .src
= { -1, -1, -1 },
1550 .op
= midgard_texop
,
1551 .format
= midgard_tex_format(instr
->sampler_dim
),
1552 .texture_handle
= texture_index
,
1553 .sampler_handle
= sampler_index
,
1554 .swizzle
= SWIZZLE_XYZW
,
1555 .in_reg_swizzle
= SWIZZLE_XYZW
,
1561 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1565 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1566 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1567 midgard_vector_alu_src alu_src
= blank_alu_src
;
1569 switch (instr
->src
[i
].src_type
) {
1570 case nir_tex_src_coord
: {
1571 emit_explicit_constant(ctx
, index
, index
);
1573 /* Texelfetch coordinates uses all four elements
1574 * (xyz/index) regardless of texture dimensionality,
1575 * which means it's necessary to zero the unused
1576 * components to keep everything happy */
1578 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1579 unsigned old_index
= index
;
1581 index
= make_compiler_temp(ctx
);
1583 /* mov index, old_index */
1584 midgard_instruction mov
= v_mov(old_index
, blank_alu_src
, index
);
1586 emit_mir_instruction(ctx
, mov
);
1588 /* mov index.zw, #0 */
1589 mov
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
),
1590 blank_alu_src
, index
);
1591 mov
.has_constants
= true;
1592 mov
.mask
= (1 << COMPONENT_Z
) | (1 << COMPONENT_W
);
1593 emit_mir_instruction(ctx
, mov
);
1596 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1597 /* texelFetch is undefined on samplerCube */
1598 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1600 /* For cubemaps, we use a special ld/st op to
1601 * select the face and copy the xy into the
1602 * texture register */
1604 unsigned temp
= make_compiler_temp(ctx
);
1605 midgard_instruction st
= m_st_cubemap_coords(temp
, 0);
1606 st
.ssa_args
.src
[0] = index
;
1607 st
.mask
= 0x3; /* xy */
1608 st
.load_store
.arg_1
= 0x20;
1609 st
.load_store
.swizzle
= alu_src
.swizzle
;
1610 emit_mir_instruction(ctx
, st
);
1612 ins
.ssa_args
.src
[0] = temp
;
1614 ins
.ssa_args
.src
[0] = index
;
1617 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1618 /* Array component in w but NIR wants it in z */
1619 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYZZ
;
1625 case nir_tex_src_bias
:
1626 case nir_tex_src_lod
: {
1627 /* Try as a constant if we can */
1629 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1630 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1633 ins
.texture
.lod_register
= true;
1634 ins
.ssa_args
.src
[1] = index
;
1635 emit_explicit_constant(ctx
, index
, index
);
1641 unreachable("Unknown texture source type\n");
1645 emit_mir_instruction(ctx
, ins
);
1647 /* Used for .cont and .last hinting */
1648 ctx
->texture_op_count
++;
1652 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1654 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1655 * generic tex in some cases (which confuses the hardware) */
1657 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1659 if (is_vertex
&& instr
->op
== nir_texop_tex
)
1660 instr
->op
= nir_texop_txl
;
1662 switch (instr
->op
) {
1665 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1668 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1671 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1674 emit_sysval_read(ctx
, &instr
->instr
, -1, 4);
1677 unreachable("Unhanlded texture op");
1682 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1684 switch (instr
->type
) {
1685 case nir_jump_break
: {
1686 /* Emit a branch out of the loop */
1687 struct midgard_instruction br
= v_branch(false, false);
1688 br
.branch
.target_type
= TARGET_BREAK
;
1689 br
.branch
.target_break
= ctx
->current_loop_depth
;
1690 emit_mir_instruction(ctx
, br
);
1695 DBG("Unknown jump type %d\n", instr
->type
);
1701 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1703 switch (instr
->type
) {
1704 case nir_instr_type_load_const
:
1705 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1708 case nir_instr_type_intrinsic
:
1709 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1712 case nir_instr_type_alu
:
1713 emit_alu(ctx
, nir_instr_as_alu(instr
));
1716 case nir_instr_type_tex
:
1717 emit_tex(ctx
, nir_instr_as_tex(instr
));
1720 case nir_instr_type_jump
:
1721 emit_jump(ctx
, nir_instr_as_jump(instr
));
1724 case nir_instr_type_ssa_undef
:
1729 DBG("Unhandled instruction type\n");
1735 /* ALU instructions can inline or embed constants, which decreases register
1736 * pressure and saves space. */
1738 #define CONDITIONAL_ATTACH(src) { \
1739 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1742 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1743 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1748 inline_alu_constants(compiler_context
*ctx
)
1750 mir_foreach_instr(ctx
, alu
) {
1751 /* Other instructions cannot inline constants */
1752 if (alu
->type
!= TAG_ALU_4
) continue;
1754 /* If there is already a constant here, we can do nothing */
1755 if (alu
->has_constants
) continue;
1757 CONDITIONAL_ATTACH(src
[0]);
1759 if (!alu
->has_constants
) {
1760 CONDITIONAL_ATTACH(src
[1])
1761 } else if (!alu
->inline_constant
) {
1762 /* Corner case: _two_ vec4 constants, for instance with a
1763 * csel. For this case, we can only use a constant
1764 * register for one, we'll have to emit a move for the
1765 * other. Note, if both arguments are constants, then
1766 * necessarily neither argument depends on the value of
1767 * any particular register. As the destination register
1768 * will be wiped, that means we can spill the constant
1769 * to the destination register.
1772 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src
[1] + 1);
1773 unsigned scratch
= alu
->ssa_args
.dest
;
1776 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1777 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src
[1] + 1);
1779 /* Force a break XXX Defer r31 writes */
1780 ins
.unit
= UNIT_VLUT
;
1782 /* Set the source */
1783 alu
->ssa_args
.src
[1] = scratch
;
1785 /* Inject us -before- the last instruction which set r31 */
1786 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1792 /* Being a little silly with the names, but returns the op that is the bitwise
1793 * inverse of the op with the argument switched. I.e. (f and g are
1796 * f(a, b) = ~g(b, a)
1798 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
1800 * f(a, b) = ~g(b, a)
1801 * ~f(a, b) = g(b, a)
1802 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
1805 * Thus we define this function in pairs.
1808 static inline midgard_alu_op
1809 mir_contrapositive(midgard_alu_op op
)
1812 case midgard_alu_op_flt
:
1813 return midgard_alu_op_fle
;
1814 case midgard_alu_op_fle
:
1815 return midgard_alu_op_flt
;
1817 case midgard_alu_op_ilt
:
1818 return midgard_alu_op_ile
;
1819 case midgard_alu_op_ile
:
1820 return midgard_alu_op_ilt
;
1823 unreachable("No known contrapositive");
1827 /* Midgard supports two types of constants, embedded constants (128-bit) and
1828 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1829 * constants can be demoted to inline constants, for space savings and
1830 * sometimes a performance boost */
1833 embedded_to_inline_constant(compiler_context
*ctx
)
1835 mir_foreach_instr(ctx
, ins
) {
1836 if (!ins
->has_constants
) continue;
1838 if (ins
->ssa_args
.inline_constant
) continue;
1840 /* Blend constants must not be inlined by definition */
1841 if (ins
->has_blend_constant
) continue;
1843 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
1844 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
1845 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
1847 if (!(is_16
|| is_32
))
1850 /* src1 cannot be an inline constant due to encoding
1851 * restrictions. So, if possible we try to flip the arguments
1854 int op
= ins
->alu
.op
;
1856 if (ins
->ssa_args
.src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1857 bool flip
= alu_opcode_props
[op
].props
& OP_COMMUTES
;
1860 /* Conditionals can be inverted */
1861 case midgard_alu_op_flt
:
1862 case midgard_alu_op_ilt
:
1863 case midgard_alu_op_fle
:
1864 case midgard_alu_op_ile
:
1865 ins
->alu
.op
= mir_contrapositive(ins
->alu
.op
);
1870 case midgard_alu_op_fcsel
:
1871 case midgard_alu_op_icsel
:
1872 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
1878 /* Flip the SSA numbers */
1879 ins
->ssa_args
.src
[0] = ins
->ssa_args
.src
[1];
1880 ins
->ssa_args
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1882 /* And flip the modifiers */
1886 src_temp
= ins
->alu
.src2
;
1887 ins
->alu
.src2
= ins
->alu
.src1
;
1888 ins
->alu
.src1
= src_temp
;
1892 if (ins
->ssa_args
.src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1893 /* Extract the source information */
1895 midgard_vector_alu_src
*src
;
1896 int q
= ins
->alu
.src2
;
1897 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1900 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1901 int component
= src
->swizzle
& 3;
1903 /* Scale constant appropriately, if we can legally */
1904 uint16_t scaled_constant
= 0;
1906 if (midgard_is_integer_op(op
) || is_16
) {
1907 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
1908 scaled_constant
= (uint16_t) iconstants
[component
];
1910 /* Constant overflow after resize */
1911 if (scaled_constant
!= iconstants
[component
])
1914 float original
= (float) ins
->constants
[component
];
1915 scaled_constant
= _mesa_float_to_half(original
);
1917 /* Check for loss of precision. If this is
1918 * mediump, we don't care, but for a highp
1919 * shader, we need to pay attention. NIR
1920 * doesn't yet tell us which mode we're in!
1921 * Practically this prevents most constants
1922 * from being inlined, sadly. */
1924 float fp32
= _mesa_half_to_float(scaled_constant
);
1926 if (fp32
!= original
)
1930 /* We don't know how to handle these with a constant */
1932 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
1933 DBG("Bailing inline constant...\n");
1937 /* Make sure that the constant is not itself a
1938 * vector by checking if all accessed values
1939 * (by the swizzle) are the same. */
1941 uint32_t *cons
= (uint32_t *) ins
->constants
;
1942 uint32_t value
= cons
[component
];
1944 bool is_vector
= false;
1945 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
1947 for (int c
= 1; c
< 4; ++c
) {
1948 /* We only care if this component is actually used */
1949 if (!(mask
& (1 << c
)))
1952 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
1954 if (test
!= value
) {
1963 /* Get rid of the embedded constant */
1964 ins
->has_constants
= false;
1965 ins
->ssa_args
.src
[1] = -1;
1966 ins
->ssa_args
.inline_constant
= true;
1967 ins
->inline_constant
= scaled_constant
;
1972 /* Dead code elimination for branches at the end of a block - only one branch
1973 * per block is legal semantically */
1976 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
1978 bool branched
= false;
1980 mir_foreach_instr_in_block_safe(block
, ins
) {
1981 if (!midgard_is_branch_unit(ins
->unit
)) continue;
1983 /* We ignore prepacked branches since the fragment epilogue is
1984 * just generally special */
1985 if (ins
->prepacked_branch
) continue;
1987 /* Discards are similarly special and may not correspond to the
1990 if (ins
->branch
.target_type
== TARGET_DISCARD
) continue;
1993 /* We already branched, so this is dead */
1994 mir_remove_instruction(ins
);
2001 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2002 * the move can be propagated away entirely */
2005 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2008 if (comp
== midgard_outmod_none
)
2011 if (*outmod
== midgard_outmod_none
) {
2016 /* TODO: Compose rules */
2021 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2023 bool progress
= false;
2025 mir_foreach_instr_in_block_safe(block
, ins
) {
2026 if (ins
->type
!= TAG_ALU_4
) continue;
2027 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2028 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2030 /* TODO: Registers? */
2031 unsigned src
= ins
->ssa_args
.src
[1];
2032 if (src
& IS_REG
) continue;
2033 assert(!mir_has_multiple_writes(ctx
, src
));
2035 /* There might be a source modifier, too */
2036 if (mir_nontrivial_source2_mod(ins
)) continue;
2038 /* Backpropagate the modifier */
2039 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2040 if (v
->type
!= TAG_ALU_4
) continue;
2041 if (v
->ssa_args
.dest
!= src
) continue;
2043 /* Can we even take a float outmod? */
2044 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2046 midgard_outmod_float temp
= v
->alu
.outmod
;
2047 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2049 /* Throw in the towel.. */
2050 if (!progress
) break;
2052 /* Otherwise, transfer the modifier */
2053 v
->alu
.outmod
= temp
;
2054 ins
->alu
.outmod
= midgard_outmod_none
;
2064 emit_fragment_epilogue(compiler_context
*ctx
)
2066 emit_explicit_constant(ctx
, ctx
->fragment_output
, SSA_FIXED_REGISTER(0));
2068 /* Perform the actual fragment writeout. We have two writeout/branch
2069 * instructions, forming a loop until writeout is successful as per the
2070 * docs. TODO: gl_FragDepth */
2072 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2073 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2076 static midgard_block
*
2077 emit_block(compiler_context
*ctx
, nir_block
*block
)
2079 midgard_block
*this_block
= ctx
->after_block
;
2080 ctx
->after_block
= NULL
;
2083 this_block
= calloc(sizeof(midgard_block
), 1);
2085 list_addtail(&this_block
->link
, &ctx
->blocks
);
2087 this_block
->is_scheduled
= false;
2090 ctx
->texture_index
[0] = -1;
2091 ctx
->texture_index
[1] = -1;
2093 /* Set up current block */
2094 list_inithead(&this_block
->instructions
);
2095 ctx
->current_block
= this_block
;
2097 nir_foreach_instr(instr
, block
) {
2098 emit_instr(ctx
, instr
);
2099 ++ctx
->instruction_count
;
2102 inline_alu_constants(ctx
);
2103 embedded_to_inline_constant(ctx
);
2105 /* Append fragment shader epilogue (value writeout) */
2106 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2107 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2108 emit_fragment_epilogue(ctx
);
2112 /* Allow the next control flow to access us retroactively, for
2114 ctx
->current_block
= this_block
;
2119 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2122 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2124 midgard_block
*before_block
= ctx
->current_block
;
2126 /* Conditional branches expect the condition in r31.w; emit a move for
2127 * that in the _previous_ block (which is the current block). */
2128 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2130 /* Speculatively emit the branch, but we can't fill it in until later */
2131 EMIT(branch
, true, true);
2132 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2134 /* Emit the two subblocks. */
2135 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2136 midgard_block
*end_then_block
= ctx
->current_block
;
2138 /* Emit a jump from the end of the then block to the end of the else */
2139 EMIT(branch
, false, false);
2140 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2142 /* Emit second block, and check if it's empty */
2144 int else_idx
= ctx
->block_count
;
2145 int count_in
= ctx
->instruction_count
;
2146 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2147 midgard_block
*end_else_block
= ctx
->current_block
;
2148 int after_else_idx
= ctx
->block_count
;
2150 /* Now that we have the subblocks emitted, fix up the branches */
2155 if (ctx
->instruction_count
== count_in
) {
2156 /* The else block is empty, so don't emit an exit jump */
2157 mir_remove_instruction(then_exit
);
2158 then_branch
->branch
.target_block
= after_else_idx
;
2160 then_branch
->branch
.target_block
= else_idx
;
2161 then_exit
->branch
.target_block
= after_else_idx
;
2164 /* Wire up the successors */
2166 ctx
->after_block
= calloc(sizeof(midgard_block
), 1);
2168 midgard_block_add_successor(before_block
, then_block
);
2169 midgard_block_add_successor(before_block
, else_block
);
2171 midgard_block_add_successor(end_then_block
, ctx
->after_block
);
2172 midgard_block_add_successor(end_else_block
, ctx
->after_block
);
2176 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2178 /* Remember where we are */
2179 midgard_block
*start_block
= ctx
->current_block
;
2181 /* Allocate a loop number, growing the current inner loop depth */
2182 int loop_idx
= ++ctx
->current_loop_depth
;
2184 /* Get index from before the body so we can loop back later */
2185 int start_idx
= ctx
->block_count
;
2187 /* Emit the body itself */
2188 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2190 /* Branch back to loop back */
2191 struct midgard_instruction br_back
= v_branch(false, false);
2192 br_back
.branch
.target_block
= start_idx
;
2193 emit_mir_instruction(ctx
, br_back
);
2195 /* Mark down that branch in the graph. */
2196 midgard_block_add_successor(start_block
, loop_block
);
2197 midgard_block_add_successor(ctx
->current_block
, loop_block
);
2199 /* Find the index of the block about to follow us (note: we don't add
2200 * one; blocks are 0-indexed so we get a fencepost problem) */
2201 int break_block_idx
= ctx
->block_count
;
2203 /* Fix up the break statements we emitted to point to the right place,
2204 * now that we can allocate a block number for them */
2205 ctx
->after_block
= calloc(sizeof(midgard_block
), 1);
2207 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2208 mir_foreach_instr_in_block(block
, ins
) {
2209 if (ins
->type
!= TAG_ALU_4
) continue;
2210 if (!ins
->compact_branch
) continue;
2211 if (ins
->prepacked_branch
) continue;
2213 /* We found a branch -- check the type to see if we need to do anything */
2214 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2216 /* It's a break! Check if it's our break */
2217 if (ins
->branch
.target_break
!= loop_idx
) continue;
2219 /* Okay, cool, we're breaking out of this loop.
2220 * Rewrite from a break to a goto */
2222 ins
->branch
.target_type
= TARGET_GOTO
;
2223 ins
->branch
.target_block
= break_block_idx
;
2225 midgard_block_add_successor(block
, ctx
->after_block
);
2229 /* Now that we've finished emitting the loop, free up the depth again
2230 * so we play nice with recursion amid nested loops */
2231 --ctx
->current_loop_depth
;
2233 /* Dump loop stats */
2237 static midgard_block
*
2238 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2240 midgard_block
*start_block
= NULL
;
2242 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2243 switch (node
->type
) {
2244 case nir_cf_node_block
: {
2245 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2248 start_block
= block
;
2253 case nir_cf_node_if
:
2254 emit_if(ctx
, nir_cf_node_as_if(node
));
2257 case nir_cf_node_loop
:
2258 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2261 case nir_cf_node_function
:
2270 /* Due to lookahead, we need to report the first tag executed in the command
2271 * stream and in branch targets. An initial block might be empty, so iterate
2272 * until we find one that 'works' */
2275 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2277 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2279 unsigned first_tag
= 0;
2281 mir_foreach_block_from(ctx
, initial_block
, v
) {
2282 midgard_bundle
*initial_bundle
=
2283 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2285 if (initial_bundle
) {
2286 first_tag
= initial_bundle
->tag
;
2295 midgard_compile_shader_nir(struct midgard_screen
*screen
, nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2297 struct util_dynarray
*compiled
= &program
->compiled
;
2299 midgard_debug
= debug_get_option_midgard_debug();
2301 compiler_context ictx
= {
2304 .stage
= nir
->info
.stage
,
2307 .is_blend
= is_blend
,
2308 .blend_constant_offset
= 0,
2310 .alpha_ref
= program
->alpha_ref
2313 compiler_context
*ctx
= &ictx
;
2315 /* Start off with a safe cutoff, allowing usage of all 16 work
2316 * registers. Later, we'll promote uniform reads to uniform registers
2317 * if we determine it is beneficial to do so */
2318 ctx
->uniform_cutoff
= 8;
2320 /* Initialize at a global (not block) level hash tables */
2322 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2323 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2324 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2326 /* Record the varying mapping for the command stream's bookkeeping */
2328 struct exec_list
*varyings
=
2329 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2331 unsigned max_varying
= 0;
2332 nir_foreach_variable(var
, varyings
) {
2333 unsigned loc
= var
->data
.driver_location
;
2334 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2336 for (int c
= 0; c
< sz
; ++c
) {
2337 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2338 max_varying
= MAX2(max_varying
, loc
+ c
);
2342 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2343 * (so we don't accidentally duplicate the epilogue since mesa/st has
2344 * messed with our I/O quite a bit already) */
2346 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2348 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2349 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2350 NIR_PASS_V(nir
, nir_clamp_psiz
, 1.0, 1024.0);
2353 NIR_PASS_V(nir
, nir_lower_var_copies
);
2354 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2355 NIR_PASS_V(nir
, nir_split_var_copies
);
2356 NIR_PASS_V(nir
, nir_lower_var_copies
);
2357 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2358 NIR_PASS_V(nir
, nir_lower_var_copies
);
2359 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2361 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2363 /* Optimisation passes */
2367 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2368 nir_print_shader(nir
, stdout
);
2371 /* Assign sysvals and counts, now that we're sure
2372 * (post-optimisation) */
2374 midgard_nir_assign_sysvals(ctx
, nir
);
2376 program
->uniform_count
= nir
->num_uniforms
;
2377 program
->sysval_count
= ctx
->sysval_count
;
2378 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2380 nir_foreach_function(func
, nir
) {
2384 list_inithead(&ctx
->blocks
);
2385 ctx
->block_count
= 0;
2388 emit_cf_list(ctx
, &func
->impl
->body
);
2389 emit_block(ctx
, func
->impl
->end_block
);
2391 break; /* TODO: Multi-function shaders */
2394 util_dynarray_init(compiled
, NULL
);
2396 /* MIR-level optimizations */
2398 bool progress
= false;
2403 mir_foreach_block(ctx
, block
) {
2404 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2405 progress
|= midgard_opt_copy_prop(ctx
, block
);
2406 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2407 progress
|= midgard_opt_combine_projection(ctx
, block
);
2408 progress
|= midgard_opt_varying_projection(ctx
, block
);
2409 progress
|= midgard_opt_not_propagate(ctx
, block
);
2410 progress
|= midgard_opt_fuse_src_invert(ctx
, block
);
2411 progress
|= midgard_opt_fuse_dest_invert(ctx
, block
);
2415 mir_foreach_block(ctx
, block
) {
2416 midgard_lower_invert(ctx
, block
);
2417 midgard_lower_derivatives(ctx
, block
);
2420 /* Nested control-flow can result in dead branches at the end of the
2421 * block. This messes with our analysis and is just dead code, so cull
2423 mir_foreach_block(ctx
, block
) {
2424 midgard_opt_cull_dead_branch(ctx
, block
);
2427 /* Ensure we were lowered */
2428 mir_foreach_instr_global(ctx
, ins
) {
2429 assert(!ins
->invert
);
2433 schedule_program(ctx
);
2435 /* Now that all the bundles are scheduled and we can calculate block
2436 * sizes, emit actual branch instructions rather than placeholders */
2438 int br_block_idx
= 0;
2440 mir_foreach_block(ctx
, block
) {
2441 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2442 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2443 midgard_instruction
*ins
= bundle
->instructions
[c
];
2445 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2447 if (ins
->prepacked_branch
) continue;
2449 /* Parse some basic branch info */
2450 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2451 bool is_conditional
= ins
->branch
.conditional
;
2452 bool is_inverted
= ins
->branch
.invert_conditional
;
2453 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2455 /* Determine the block we're jumping to */
2456 int target_number
= ins
->branch
.target_block
;
2458 /* Report the destination tag */
2459 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2461 /* Count up the number of quadwords we're
2462 * jumping over = number of quadwords until
2463 * (br_block_idx, target_number) */
2465 int quadword_offset
= 0;
2469 } else if (target_number
> br_block_idx
) {
2472 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2473 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2476 quadword_offset
+= blk
->quadword_count
;
2479 /* Jump backwards */
2481 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2482 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2485 quadword_offset
-= blk
->quadword_count
;
2489 /* Unconditional extended branches (far jumps)
2490 * have issues, so we always use a conditional
2491 * branch, setting the condition to always for
2492 * unconditional. For compact unconditional
2493 * branches, cond isn't used so it doesn't
2494 * matter what we pick. */
2496 midgard_condition cond
=
2497 !is_conditional
? midgard_condition_always
:
2498 is_inverted
? midgard_condition_false
:
2499 midgard_condition_true
;
2501 midgard_jmp_writeout_op op
=
2502 is_discard
? midgard_jmp_writeout_op_discard
:
2503 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2504 midgard_jmp_writeout_op_branch_cond
;
2507 midgard_branch_extended branch
=
2508 midgard_create_branch_extended(
2513 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2514 } else if (is_conditional
|| is_discard
) {
2515 midgard_branch_cond branch
= {
2517 .dest_tag
= dest_tag
,
2518 .offset
= quadword_offset
,
2522 assert(branch
.offset
== quadword_offset
);
2524 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2526 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2528 midgard_branch_uncond branch
= {
2530 .dest_tag
= dest_tag
,
2531 .offset
= quadword_offset
,
2535 assert(branch
.offset
== quadword_offset
);
2537 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2545 /* Emit flat binary from the instruction arrays. Iterate each block in
2546 * sequence. Save instruction boundaries such that lookahead tags can
2547 * be assigned easily */
2549 /* Cache _all_ bundles in source order for lookahead across failed branches */
2551 int bundle_count
= 0;
2552 mir_foreach_block(ctx
, block
) {
2553 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2555 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2557 mir_foreach_block(ctx
, block
) {
2558 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2559 source_order_bundles
[bundle_idx
++] = bundle
;
2563 int current_bundle
= 0;
2565 /* Midgard prefetches instruction types, so during emission we
2566 * need to lookahead. Unless this is the last instruction, in
2567 * which we return 1. Or if this is the second to last and the
2568 * last is an ALU, then it's also 1... */
2570 mir_foreach_block(ctx
, block
) {
2571 mir_foreach_bundle_in_block(block
, bundle
) {
2574 if (current_bundle
+ 1 < bundle_count
) {
2575 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2577 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2584 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2588 /* TODO: Free deeper */
2589 //util_dynarray_fini(&block->instructions);
2592 free(source_order_bundles
);
2594 /* Report the very first tag executed */
2595 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2597 /* Deal with off-by-one related to the fencepost problem */
2598 program
->work_register_count
= ctx
->work_registers
+ 1;
2599 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2601 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2602 program
->tls_size
= ctx
->tls_size
;
2604 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2605 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);
2607 if (midgard_debug
& MIDGARD_DBG_SHADERDB
) {
2608 unsigned nr_bundles
= 0, nr_ins
= 0, nr_quadwords
= 0;
2610 /* Count instructions and bundles */
2612 mir_foreach_instr_global(ctx
, ins
) {
2616 mir_foreach_block(ctx
, block
) {
2617 nr_bundles
+= util_dynarray_num_elements(
2618 &block
->bundles
, midgard_bundle
);
2620 nr_quadwords
+= block
->quadword_count
;
2623 /* Calculate thread count. There are certain cutoffs by
2624 * register count for thread count */
2626 unsigned nr_registers
= program
->work_register_count
;
2628 unsigned nr_threads
=
2629 (nr_registers
<= 4) ? 4 :
2630 (nr_registers
<= 8) ? 2 :
2635 fprintf(stderr
, "shader%d - %s shader: "
2636 "%u inst, %u bundles, %u quadwords, "
2637 "%u registers, %u threads, %u loops, "
2638 "%d:%d spills:fills\n",
2640 gl_shader_stage_name(ctx
->stage
),
2641 nr_ins
, nr_bundles
, nr_quadwords
,
2642 nr_registers
, nr_threads
,
2644 ctx
->spills
, ctx
->fills
);