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pan/mdg: Promote imov to fmov on a NIR level
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
132 * the corresponding Midgard source */
133
134 static midgard_vector_alu_src
135 vector_alu_modifiers(bool abs, bool neg, bool is_int,
136 bool half, bool sext)
137 {
138 /* Figure out how many components there are so we can adjust.
139 * Specifically we want to broadcast the last channel so things like
140 * ball2/3 work.
141 */
142
143 midgard_vector_alu_src alu_src = {
144 .rep_low = 0,
145 .rep_high = 0,
146 .half = half
147 };
148
149 if (is_int) {
150 alu_src.mod = midgard_int_normal;
151
152 /* Sign/zero-extend if needed */
153
154 if (half) {
155 alu_src.mod = sext ?
156 midgard_int_sign_extend
157 : midgard_int_zero_extend;
158 }
159
160 /* These should have been lowered away */
161 assert(!(abs || neg));
162 } else {
163 alu_src.mod = (abs << 0) | (neg << 1);
164 }
165
166 return alu_src;
167 }
168
169 M_LOAD(ld_attr_32, nir_type_uint32);
170 M_LOAD(ld_vary_32, nir_type_uint32);
171 M_LOAD(ld_ubo_int4, nir_type_uint32);
172 M_LOAD(ld_int4, nir_type_uint32);
173 M_STORE(st_int4, nir_type_uint32);
174 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
175 M_STORE(st_vary_32, nir_type_uint32);
176 M_LOAD(ld_cubemap_coords, nir_type_uint32);
177 M_LOAD(ld_compute_id, nir_type_uint32);
178
179 static midgard_instruction
180 v_branch(bool conditional, bool invert)
181 {
182 midgard_instruction ins = {
183 .type = TAG_ALU_4,
184 .unit = ALU_ENAB_BRANCH,
185 .compact_branch = true,
186 .branch = {
187 .conditional = conditional,
188 .invert_conditional = invert
189 },
190 .dest = ~0,
191 .src = { ~0, ~0, ~0, ~0 },
192 };
193
194 return ins;
195 }
196
197 static midgard_branch_extended
198 midgard_create_branch_extended( midgard_condition cond,
199 midgard_jmp_writeout_op op,
200 unsigned dest_tag,
201 signed quadword_offset)
202 {
203 /* The condition code is actually a LUT describing a function to
204 * combine multiple condition codes. However, we only support a single
205 * condition code at the moment, so we just duplicate over a bunch of
206 * times. */
207
208 uint16_t duplicated_cond =
209 (cond << 14) |
210 (cond << 12) |
211 (cond << 10) |
212 (cond << 8) |
213 (cond << 6) |
214 (cond << 4) |
215 (cond << 2) |
216 (cond << 0);
217
218 midgard_branch_extended branch = {
219 .op = op,
220 .dest_tag = dest_tag,
221 .offset = quadword_offset,
222 .cond = duplicated_cond
223 };
224
225 return branch;
226 }
227
228 static void
229 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
230 {
231 ins->has_constants = true;
232 memcpy(&ins->constants, constants, 16);
233 }
234
235 static int
236 glsl_type_size(const struct glsl_type *type, bool bindless)
237 {
238 return glsl_count_attribute_slots(type, false);
239 }
240
241 /* Lower fdot2 to a vector multiplication followed by channel addition */
242 static void
243 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
244 {
245 if (alu->op != nir_op_fdot2)
246 return;
247
248 b->cursor = nir_before_instr(&alu->instr);
249
250 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
251 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
252
253 nir_ssa_def *product = nir_fmul(b, src0, src1);
254
255 nir_ssa_def *sum = nir_fadd(b,
256 nir_channel(b, product, 0),
257 nir_channel(b, product, 1));
258
259 /* Replace the fdot2 with this sum */
260 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
261 }
262
263 static bool
264 midgard_nir_lower_fdot2(nir_shader *shader)
265 {
266 bool progress = false;
267
268 nir_foreach_function(function, shader) {
269 if (!function->impl) continue;
270
271 nir_builder _b;
272 nir_builder *b = &_b;
273 nir_builder_init(b, function->impl);
274
275 nir_foreach_block(block, function->impl) {
276 nir_foreach_instr_safe(instr, block) {
277 if (instr->type != nir_instr_type_alu) continue;
278
279 nir_alu_instr *alu = nir_instr_as_alu(instr);
280 midgard_nir_lower_fdot2_body(b, alu);
281
282 progress |= true;
283 }
284 }
285
286 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
287
288 }
289
290 return progress;
291 }
292
293 /* Midgard can't write depth and stencil separately. It has to happen in a
294 * single store operation containing both. Let's add a panfrost specific
295 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
296 * one.
297 */
298 static bool
299 midgard_nir_lower_zs_store(nir_shader *nir)
300 {
301 if (nir->info.stage != MESA_SHADER_FRAGMENT)
302 return false;
303
304 nir_variable *z_var = NULL, *s_var = NULL;
305
306 nir_foreach_variable(var, &nir->outputs) {
307 if (var->data.location == FRAG_RESULT_DEPTH)
308 z_var = var;
309 else if (var->data.location == FRAG_RESULT_STENCIL)
310 s_var = var;
311 }
312
313 if (!z_var && !s_var)
314 return false;
315
316 bool progress = false;
317
318 nir_foreach_function(function, nir) {
319 if (!function->impl) continue;
320
321 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
322
323 nir_foreach_block(block, function->impl) {
324 nir_foreach_instr_safe(instr, block) {
325 if (instr->type != nir_instr_type_intrinsic)
326 continue;
327
328 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
329 if (intr->intrinsic != nir_intrinsic_store_output)
330 continue;
331
332 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
333 assert(!z_store);
334 z_store = intr;
335 last_store = intr;
336 }
337
338 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
339 assert(!s_store);
340 s_store = intr;
341 last_store = intr;
342 }
343 }
344 }
345
346 if (!z_store && !s_store) continue;
347
348 nir_builder b;
349 nir_builder_init(&b, function->impl);
350
351 b.cursor = nir_before_instr(&last_store->instr);
352
353 nir_ssa_def *zs_store_src;
354
355 if (z_store && s_store) {
356 nir_ssa_def *srcs[2] = {
357 nir_ssa_for_src(&b, z_store->src[0], 1),
358 nir_ssa_for_src(&b, s_store->src[0], 1),
359 };
360
361 zs_store_src = nir_vec(&b, srcs, 2);
362 } else {
363 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
364 }
365
366 nir_intrinsic_instr *zs_store;
367
368 zs_store = nir_intrinsic_instr_create(b.shader,
369 nir_intrinsic_store_zs_output_pan);
370 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
371 zs_store->num_components = z_store && s_store ? 2 : 1;
372 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
373
374 /* Replace the Z and S store by a ZS store */
375 nir_builder_instr_insert(&b, &zs_store->instr);
376
377 if (z_store)
378 nir_instr_remove(&z_store->instr);
379
380 if (s_store)
381 nir_instr_remove(&s_store->instr);
382
383 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
384 progress = true;
385 }
386
387 return progress;
388 }
389
390 /* Flushes undefined values to zero */
391
392 static void
393 optimise_nir(nir_shader *nir, unsigned quirks)
394 {
395 bool progress;
396 unsigned lower_flrp =
397 (nir->options->lower_flrp16 ? 16 : 0) |
398 (nir->options->lower_flrp32 ? 32 : 0) |
399 (nir->options->lower_flrp64 ? 64 : 0);
400
401 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
402 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
403
404 nir_lower_tex_options lower_tex_options = {
405 .lower_txs_lod = true,
406 .lower_txp = ~0,
407 .lower_tex_without_implicit_lod =
408 (quirks & MIDGARD_EXPLICIT_LOD),
409
410 /* TODO: we have native gradient.. */
411 .lower_txd = true,
412 };
413
414 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
415
416 /* Must lower fdot2 after tex is lowered */
417 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
418
419 /* T720 is broken. */
420
421 if (quirks & MIDGARD_BROKEN_LOD)
422 NIR_PASS_V(nir, midgard_nir_lod_errata);
423
424 do {
425 progress = false;
426
427 NIR_PASS(progress, nir, nir_lower_var_copies);
428 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
429
430 NIR_PASS(progress, nir, nir_copy_prop);
431 NIR_PASS(progress, nir, nir_opt_remove_phis);
432 NIR_PASS(progress, nir, nir_opt_dce);
433 NIR_PASS(progress, nir, nir_opt_dead_cf);
434 NIR_PASS(progress, nir, nir_opt_cse);
435 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
436 NIR_PASS(progress, nir, nir_opt_algebraic);
437 NIR_PASS(progress, nir, nir_opt_constant_folding);
438
439 if (lower_flrp != 0) {
440 bool lower_flrp_progress = false;
441 NIR_PASS(lower_flrp_progress,
442 nir,
443 nir_lower_flrp,
444 lower_flrp,
445 false /* always_precise */,
446 nir->options->lower_ffma);
447 if (lower_flrp_progress) {
448 NIR_PASS(progress, nir,
449 nir_opt_constant_folding);
450 progress = true;
451 }
452
453 /* Nothing should rematerialize any flrps, so we only
454 * need to do this lowering once.
455 */
456 lower_flrp = 0;
457 }
458
459 NIR_PASS(progress, nir, nir_opt_undef);
460 NIR_PASS(progress, nir, nir_undef_to_zero);
461
462 NIR_PASS(progress, nir, nir_opt_loop_unroll,
463 nir_var_shader_in |
464 nir_var_shader_out |
465 nir_var_function_temp);
466
467 NIR_PASS(progress, nir, nir_opt_vectorize);
468 } while (progress);
469
470 /* Must be run at the end to prevent creation of fsin/fcos ops */
471 NIR_PASS(progress, nir, midgard_nir_scale_trig);
472
473 do {
474 progress = false;
475
476 NIR_PASS(progress, nir, nir_opt_dce);
477 NIR_PASS(progress, nir, nir_opt_algebraic);
478 NIR_PASS(progress, nir, nir_opt_constant_folding);
479 NIR_PASS(progress, nir, nir_copy_prop);
480 } while (progress);
481
482 NIR_PASS(progress, nir, nir_opt_algebraic_late);
483 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
484
485 /* We implement booleans as 32-bit 0/~0 */
486 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
487
488 /* Now that booleans are lowered, we can run out late opts */
489 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
490 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
491
492 NIR_PASS(progress, nir, nir_copy_prop);
493 NIR_PASS(progress, nir, nir_opt_dce);
494
495 /* Take us out of SSA */
496 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
497 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
498
499 /* We are a vector architecture; write combine where possible */
500 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
501 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
502
503 NIR_PASS(progress, nir, nir_opt_dce);
504 }
505
506 /* Do not actually emit a load; instead, cache the constant for inlining */
507
508 static void
509 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
510 {
511 nir_ssa_def def = instr->def;
512
513 midgard_constants *consts = rzalloc(NULL, midgard_constants);
514
515 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
516
517 #define RAW_CONST_COPY(bits) \
518 nir_const_value_to_array(consts->u##bits, instr->value, \
519 instr->def.num_components, u##bits)
520
521 switch (instr->def.bit_size) {
522 case 64:
523 RAW_CONST_COPY(64);
524 break;
525 case 32:
526 RAW_CONST_COPY(32);
527 break;
528 case 16:
529 RAW_CONST_COPY(16);
530 break;
531 case 8:
532 RAW_CONST_COPY(8);
533 break;
534 default:
535 unreachable("Invalid bit_size for load_const instruction\n");
536 }
537
538 /* Shifted for SSA, +1 for off-by-one */
539 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
540 }
541
542 /* Normally constants are embedded implicitly, but for I/O and such we have to
543 * explicitly emit a move with the constant source */
544
545 static void
546 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
547 {
548 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
549
550 if (constant_value) {
551 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
552 attach_constants(ctx, &ins, constant_value, node + 1);
553 emit_mir_instruction(ctx, ins);
554 }
555 }
556
557 static bool
558 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
559 {
560 unsigned comp = src->swizzle[0];
561
562 for (unsigned c = 1; c < nr_components; ++c) {
563 if (src->swizzle[c] != comp)
564 return true;
565 }
566
567 return false;
568 }
569
570 #define ALU_CASE(nir, _op) \
571 case nir_op_##nir: \
572 op = midgard_alu_op_##_op; \
573 assert(src_bitsize == dst_bitsize); \
574 break;
575
576 #define ALU_CASE_BCAST(nir, _op, count) \
577 case nir_op_##nir: \
578 op = midgard_alu_op_##_op; \
579 broadcast_swizzle = count; \
580 assert(src_bitsize == dst_bitsize); \
581 break;
582
583 #define ALU_CHECK_CMP(sext) \
584 if (src_bitsize == 16 && dst_bitsize == 32) { \
585 half_1 = true; \
586 half_2 = true; \
587 sext_1 = sext; \
588 sext_2 = sext; \
589 } else { \
590 assert(src_bitsize == dst_bitsize); \
591 } \
592
593 #define ALU_CASE_CMP(nir, _op, sext) \
594 case nir_op_##nir: \
595 op = midgard_alu_op_##_op; \
596 ALU_CHECK_CMP(sext); \
597 break;
598
599 /* Analyze the sizes of the dest and inputs to determine reg mode. */
600
601 static midgard_reg_mode
602 reg_mode_for_nir(nir_alu_instr *instr)
603 {
604 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
605 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
606 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
607
608 switch (max_bitsize) {
609 case 8:
610 return midgard_reg_mode_8;
611 case 16:
612 return midgard_reg_mode_16;
613 case 32:
614 return midgard_reg_mode_32;
615 case 64:
616 return midgard_reg_mode_64;
617 default:
618 unreachable("Invalid bit size");
619 }
620 }
621
622 /* Compare mir_lower_invert */
623 static bool
624 nir_accepts_inot(nir_op op, unsigned src)
625 {
626 switch (op) {
627 case nir_op_ior:
628 case nir_op_iand:
629 case nir_op_ixor:
630 return true;
631 case nir_op_b32csel:
632 /* Only the condition */
633 return (src == 0);
634 default:
635 return false;
636 }
637 }
638
639 static bool
640 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
641 {
642 if (pan_has_dest_mod(dest, op)) {
643 assert((*dest)->is_ssa);
644 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
645 return true;
646 }
647
648 return false;
649 }
650
651 static void
652 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, bool is_int, unsigned bcast_count)
653 {
654 nir_alu_src src = instr->src[i];
655
656 if (!is_int) {
657 if (pan_has_source_mod(&src, nir_op_fneg))
658 *neg = !(*neg);
659
660 if (pan_has_source_mod(&src, nir_op_fabs))
661 *abs = true;
662 }
663
664 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
665 *not = true;
666
667 unsigned bits = nir_src_bit_size(src.src);
668
669 ins->src[to] = nir_src_index(NULL, &src.src);
670 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
671
672 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
673 ins->swizzle[to][c] = src.swizzle[
674 (!bcast_count || c < bcast_count) ? c :
675 (bcast_count - 1)];
676 }
677 }
678
679 /* Midgard features both fcsel and icsel, depending on whether you want int or
680 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
681 * we should emit an int or float csel depending on what modifiers could be
682 * placed. In the absense of modifiers, this is probably arbitrary. */
683
684 static bool
685 mir_is_bcsel_float(nir_alu_instr *instr)
686 {
687 nir_op intmods[] = {
688 nir_op_i2i8, nir_op_i2i16,
689 nir_op_i2i32, nir_op_i2i64
690 };
691
692 nir_op floatmods[] = {
693 nir_op_fabs, nir_op_fneg,
694 nir_op_f2f16, nir_op_f2f32,
695 nir_op_f2f64
696 };
697
698 nir_op floatdestmods[] = {
699 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
700 nir_op_f2f16, nir_op_f2f32
701 };
702
703 signed score = 0;
704
705 for (unsigned i = 1; i < 3; ++i) {
706 nir_alu_src s = instr->src[i];
707 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
708 if (pan_has_source_mod(&s, intmods[q]))
709 score--;
710 }
711 }
712
713 for (unsigned i = 1; i < 3; ++i) {
714 nir_alu_src s = instr->src[i];
715 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
716 if (pan_has_source_mod(&s, floatmods[q]))
717 score++;
718 }
719 }
720
721 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
722 nir_dest *dest = &instr->dest.dest;
723 if (pan_has_dest_mod(&dest, floatdestmods[q]))
724 score++;
725 }
726
727 return (score > 0);
728 }
729
730 static void
731 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
732 {
733 nir_dest *dest = &instr->dest.dest;
734
735 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
736 return;
737
738 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
739 * is handled elsewhere */
740
741 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
742 midgard_emit_derivatives(ctx, instr);
743 return;
744 }
745
746 bool is_ssa = dest->is_ssa;
747
748 unsigned nr_components = nir_dest_num_components(*dest);
749 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
750 unsigned op = 0;
751
752 /* Number of components valid to check for the instruction (the rest
753 * will be forced to the last), or 0 to use as-is. Relevant as
754 * ball-type instructions have a channel count in NIR but are all vec4
755 * in Midgard */
756
757 unsigned broadcast_swizzle = 0;
758
759 /* What register mode should we operate in? */
760 midgard_reg_mode reg_mode =
761 reg_mode_for_nir(instr);
762
763 /* Do we need a destination override? Used for inline
764 * type conversion */
765
766 midgard_dest_override dest_override =
767 midgard_dest_override_none;
768
769 /* Should we use a smaller respective source and sign-extend? */
770
771 bool half_1 = false, sext_1 = false;
772 bool half_2 = false, sext_2 = false;
773
774 /* Should we swap arguments? */
775 bool flip_src12 = false;
776
777 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
778 unsigned dst_bitsize = nir_dest_bit_size(*dest);
779
780 switch (instr->op) {
781 ALU_CASE(fadd, fadd);
782 ALU_CASE(fmul, fmul);
783 ALU_CASE(fmin, fmin);
784 ALU_CASE(fmax, fmax);
785 ALU_CASE(imin, imin);
786 ALU_CASE(imax, imax);
787 ALU_CASE(umin, umin);
788 ALU_CASE(umax, umax);
789 ALU_CASE(ffloor, ffloor);
790 ALU_CASE(fround_even, froundeven);
791 ALU_CASE(ftrunc, ftrunc);
792 ALU_CASE(fceil, fceil);
793 ALU_CASE(fdot3, fdot3);
794 ALU_CASE(fdot4, fdot4);
795 ALU_CASE(iadd, iadd);
796 ALU_CASE(isub, isub);
797 ALU_CASE(imul, imul);
798
799 /* Zero shoved as second-arg */
800 ALU_CASE(iabs, iabsdiff);
801
802 ALU_CASE(mov, imov);
803
804 ALU_CASE_CMP(feq32, feq, false);
805 ALU_CASE_CMP(fne32, fne, false);
806 ALU_CASE_CMP(flt32, flt, false);
807 ALU_CASE_CMP(ieq32, ieq, true);
808 ALU_CASE_CMP(ine32, ine, true);
809 ALU_CASE_CMP(ilt32, ilt, true);
810 ALU_CASE_CMP(ult32, ult, false);
811
812 /* We don't have a native b2f32 instruction. Instead, like many
813 * GPUs, we exploit booleans as 0/~0 for false/true, and
814 * correspondingly AND
815 * by 1.0 to do the type conversion. For the moment, prime us
816 * to emit:
817 *
818 * iand [whatever], #0
819 *
820 * At the end of emit_alu (as MIR), we'll fix-up the constant
821 */
822
823 ALU_CASE_CMP(b2f32, iand, true);
824 ALU_CASE_CMP(b2i32, iand, true);
825
826 /* Likewise, we don't have a dedicated f2b32 instruction, but
827 * we can do a "not equal to 0.0" test. */
828
829 ALU_CASE_CMP(f2b32, fne, false);
830 ALU_CASE_CMP(i2b32, ine, true);
831
832 ALU_CASE(frcp, frcp);
833 ALU_CASE(frsq, frsqrt);
834 ALU_CASE(fsqrt, fsqrt);
835 ALU_CASE(fexp2, fexp2);
836 ALU_CASE(flog2, flog2);
837
838 ALU_CASE(f2i64, f2i_rtz);
839 ALU_CASE(f2u64, f2u_rtz);
840 ALU_CASE(i2f64, i2f_rtz);
841 ALU_CASE(u2f64, u2f_rtz);
842
843 ALU_CASE(f2i32, f2i_rtz);
844 ALU_CASE(f2u32, f2u_rtz);
845 ALU_CASE(i2f32, i2f_rtz);
846 ALU_CASE(u2f32, u2f_rtz);
847
848 ALU_CASE(f2i16, f2i_rtz);
849 ALU_CASE(f2u16, f2u_rtz);
850 ALU_CASE(i2f16, i2f_rtz);
851 ALU_CASE(u2f16, u2f_rtz);
852
853 ALU_CASE(fsin, fsin);
854 ALU_CASE(fcos, fcos);
855
856 /* We'll get 0 in the second arg, so:
857 * ~a = ~(a | 0) = nor(a, 0) */
858 ALU_CASE(inot, inor);
859 ALU_CASE(iand, iand);
860 ALU_CASE(ior, ior);
861 ALU_CASE(ixor, ixor);
862 ALU_CASE(ishl, ishl);
863 ALU_CASE(ishr, iasr);
864 ALU_CASE(ushr, ilsr);
865
866 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
867 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
868 ALU_CASE(b32all_fequal4, fball_eq);
869
870 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
871 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
872 ALU_CASE(b32any_fnequal4, fbany_neq);
873
874 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
875 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
876 ALU_CASE(b32all_iequal4, iball_eq);
877
878 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
879 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
880 ALU_CASE(b32any_inequal4, ibany_neq);
881
882 /* Source mods will be shoved in later */
883 ALU_CASE(fabs, fmov);
884 ALU_CASE(fneg, fmov);
885 ALU_CASE(fsat, fmov);
886 ALU_CASE(fsat_signed, fmov);
887 ALU_CASE(fclamp_pos, fmov);
888
889 /* For size conversion, we use a move. Ideally though we would squash
890 * these ops together; maybe that has to happen after in NIR as part of
891 * propagation...? An earlier algebraic pass ensured we step down by
892 * only / exactly one size. If stepping down, we use a dest override to
893 * reduce the size; if stepping up, we use a larger-sized move with a
894 * half source and a sign/zero-extension modifier */
895
896 case nir_op_i2i8:
897 case nir_op_i2i16:
898 case nir_op_i2i32:
899 case nir_op_i2i64:
900 /* If we end up upscale, we'll need a sign-extend on the
901 * operand (the second argument) */
902
903 sext_2 = true;
904 /* fallthrough */
905 case nir_op_u2u8:
906 case nir_op_u2u16:
907 case nir_op_u2u32:
908 case nir_op_u2u64:
909 case nir_op_f2f16:
910 case nir_op_f2f32:
911 case nir_op_f2f64: {
912 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
913 instr->op == nir_op_f2f64)
914 op = midgard_alu_op_fmov;
915 else
916 op = midgard_alu_op_imov;
917
918 if (dst_bitsize == (src_bitsize * 2)) {
919 /* Converting up */
920 half_2 = true;
921 } else if (src_bitsize == (dst_bitsize * 2)) {
922 /* Converting down */
923 dest_override = midgard_dest_override_lower;
924 }
925
926 break;
927 }
928
929 /* For greater-or-equal, we lower to less-or-equal and flip the
930 * arguments */
931
932 case nir_op_fge:
933 case nir_op_fge32:
934 case nir_op_ige32:
935 case nir_op_uge32: {
936 op =
937 instr->op == nir_op_fge ? midgard_alu_op_fle :
938 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
939 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
940 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
941 0;
942
943 flip_src12 = true;
944 ALU_CHECK_CMP(false);
945 break;
946 }
947
948 case nir_op_b32csel: {
949 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
950 bool is_float = mir_is_bcsel_float(instr);
951 op = is_float ?
952 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
953 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
954
955 break;
956 }
957
958 default:
959 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
960 assert(0);
961 return;
962 }
963
964 /* Promote imov to fmov if it might help inline a constant */
965 if (op == midgard_alu_op_imov && nir_src_is_const(instr->src[0].src)
966 && nir_src_bit_size(instr->src[0].src) == 32
967 && nir_is_same_comp_swizzle(instr->src[0].swizzle,
968 nir_src_num_components(instr->src[0].src))) {
969 op = midgard_alu_op_fmov;
970 }
971
972 /* Midgard can perform certain modifiers on output of an ALU op */
973
974 unsigned outmod = 0;
975
976 bool abs[4] = { false };
977 bool neg[4] = { false };
978 bool is_int = midgard_is_integer_op(op);
979
980 if (midgard_is_integer_out_op(op)) {
981 outmod = midgard_outmod_int_wrap;
982 } else if (instr->op == nir_op_fsat) {
983 outmod = midgard_outmod_sat;
984 } else if (instr->op == nir_op_fsat_signed) {
985 outmod = midgard_outmod_sat_signed;
986 } else if (instr->op == nir_op_fclamp_pos) {
987 outmod = midgard_outmod_pos;
988 }
989
990 /* Fetch unit, quirks, etc information */
991 unsigned opcode_props = alu_opcode_props[op].props;
992 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
993
994 /* Look for floating point mods. We have the mods fsat, fsat_signed,
995 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
996 *
997 * fsat_signed(fpos(x)) = fsat(x)
998 * fsat_signed(fsat(x)) = fsat(x)
999 * fpos(fsat_signed(x)) = fsat(x)
1000 * fpos(fsat(x)) = fsat(x)
1001 * fsat(fsat_signed(x)) = fsat(x)
1002 * fsat(fpos(x)) = fsat(x)
1003 *
1004 * So by cases any composition of output modifiers is equivalent to
1005 * fsat alone.
1006 */
1007
1008 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
1009 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
1010 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
1011 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
1012 bool prior = (outmod != midgard_outmod_none);
1013 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
1014
1015 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
1016 fpos ? midgard_outmod_pos :
1017 ssat ? midgard_outmod_sat_signed :
1018 outmod;
1019 }
1020
1021 midgard_instruction ins = {
1022 .type = TAG_ALU_4,
1023 .dest = nir_dest_index(dest),
1024 .dest_type = nir_op_infos[instr->op].output_type
1025 | nir_dest_bit_size(*dest),
1026 };
1027
1028 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
1029 ins.src[i] = ~0;
1030
1031 if (quirk_flipped_r24) {
1032 ins.src[0] = ~0;
1033 mir_copy_src(&ins, instr, 0, 1, &abs[1], &neg[1], &ins.src_invert[1], is_int, broadcast_swizzle);
1034 } else {
1035 for (unsigned i = 0; i < nr_inputs; ++i) {
1036 unsigned to = i;
1037
1038 if (instr->op == nir_op_b32csel) {
1039 /* The condition is the first argument; move
1040 * the other arguments up one to be a binary
1041 * instruction for Midgard with the condition
1042 * last */
1043
1044 if (i == 0)
1045 to = 2;
1046 else if (flip_src12)
1047 to = 2 - i;
1048 else
1049 to = i - 1;
1050 } else if (flip_src12) {
1051 to = 1 - to;
1052 }
1053
1054 mir_copy_src(&ins, instr, i, to, &abs[to], &neg[to], &ins.src_invert[to], is_int, broadcast_swizzle);
1055
1056 /* (!c) ? a : b = c ? b : a */
1057 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1058 ins.src_invert[2] = false;
1059 flip_src12 ^= true;
1060 }
1061 }
1062 }
1063
1064 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1065 /* Lowered to move */
1066 if (instr->op == nir_op_fneg)
1067 neg[1] = !neg[1];
1068
1069 if (instr->op == nir_op_fabs)
1070 abs[1] = true;
1071 }
1072
1073 ins.mask = mask_of(nr_components);
1074
1075 midgard_vector_alu alu = {
1076 .op = op,
1077 .reg_mode = reg_mode,
1078 .dest_override = dest_override,
1079 .outmod = outmod,
1080
1081 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[0], neg[0], is_int, half_1, sext_1)),
1082 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[1], neg[1], is_int, half_2, sext_2)),
1083 };
1084
1085 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1086 * components that don't exist. Note modifier => SSA => !reg => no
1087 * writemask, so we don't have to worry about writemasks here.*/
1088
1089 if (!is_ssa)
1090 ins.mask &= instr->dest.write_mask;
1091
1092 ins.alu = alu;
1093
1094 /* Arrange for creation of iandnot/iornot */
1095 if (ins.src_invert[0] && !ins.src_invert[1]) {
1096 mir_flip(&ins);
1097 ins.src_invert[0] = false;
1098 ins.src_invert[1] = true;
1099 }
1100
1101 /* Late fixup for emulated instructions */
1102
1103 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1104 /* Presently, our second argument is an inline #0 constant.
1105 * Switch over to an embedded 1.0 constant (that can't fit
1106 * inline, since we're 32-bit, not 16-bit like the inline
1107 * constants) */
1108
1109 ins.has_inline_constant = false;
1110 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1111 ins.src_types[1] = nir_type_float32;
1112 ins.has_constants = true;
1113
1114 if (instr->op == nir_op_b2f32)
1115 ins.constants.f32[0] = 1.0f;
1116 else
1117 ins.constants.i32[0] = 1;
1118
1119 for (unsigned c = 0; c < 16; ++c)
1120 ins.swizzle[1][c] = 0;
1121 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1122 /* Lots of instructions need a 0 plonked in */
1123 ins.has_inline_constant = false;
1124 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1125 ins.src_types[1] = nir_type_uint32;
1126 ins.has_constants = true;
1127 ins.constants.u32[0] = 0;
1128
1129 for (unsigned c = 0; c < 16; ++c)
1130 ins.swizzle[1][c] = 0;
1131 }
1132
1133 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1134 /* To avoid duplicating the lookup tables (probably), true LUT
1135 * instructions can only operate as if they were scalars. Lower
1136 * them here by changing the component. */
1137
1138 unsigned orig_mask = ins.mask;
1139
1140 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1141 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1142
1143 for (int i = 0; i < nr_components; ++i) {
1144 /* Mask the associated component, dropping the
1145 * instruction if needed */
1146
1147 ins.mask = 1 << i;
1148 ins.mask &= orig_mask;
1149
1150 if (!ins.mask)
1151 continue;
1152
1153 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1154 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1155
1156 emit_mir_instruction(ctx, ins);
1157 }
1158 } else {
1159 emit_mir_instruction(ctx, ins);
1160 }
1161 }
1162
1163 #undef ALU_CASE
1164
1165 static void
1166 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1167 {
1168 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1169 unsigned nir_mask = 0;
1170 unsigned dsize = 0;
1171
1172 if (is_read) {
1173 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1174 dsize = nir_dest_bit_size(intr->dest);
1175 } else {
1176 nir_mask = nir_intrinsic_write_mask(intr);
1177 dsize = 32;
1178 }
1179
1180 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1181 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1182 mir_set_bytemask(ins, bytemask);
1183
1184 if (dsize == 64)
1185 ins->load_64 = true;
1186 }
1187
1188 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1189 * optimized) versions of UBO #0 */
1190
1191 static midgard_instruction *
1192 emit_ubo_read(
1193 compiler_context *ctx,
1194 nir_instr *instr,
1195 unsigned dest,
1196 unsigned offset,
1197 nir_src *indirect_offset,
1198 unsigned indirect_shift,
1199 unsigned index)
1200 {
1201 /* TODO: half-floats */
1202
1203 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1204 ins.constants.u32[0] = offset;
1205
1206 if (instr->type == nir_instr_type_intrinsic)
1207 mir_set_intr_mask(instr, &ins, true);
1208
1209 if (indirect_offset) {
1210 ins.src[2] = nir_src_index(ctx, indirect_offset);
1211 ins.src_types[2] = nir_type_uint32;
1212 ins.load_store.arg_2 = (indirect_shift << 5);
1213 } else {
1214 ins.load_store.arg_2 = 0x1E;
1215 }
1216
1217 ins.load_store.arg_1 = index;
1218
1219 return emit_mir_instruction(ctx, ins);
1220 }
1221
1222 /* Globals are like UBOs if you squint. And shared memory is like globals if
1223 * you squint even harder */
1224
1225 static void
1226 emit_global(
1227 compiler_context *ctx,
1228 nir_instr *instr,
1229 bool is_read,
1230 unsigned srcdest,
1231 nir_src *offset,
1232 bool is_shared)
1233 {
1234 /* TODO: types */
1235
1236 midgard_instruction ins;
1237
1238 if (is_read)
1239 ins = m_ld_int4(srcdest, 0);
1240 else
1241 ins = m_st_int4(srcdest, 0);
1242
1243 mir_set_offset(ctx, &ins, offset, is_shared);
1244 mir_set_intr_mask(instr, &ins, is_read);
1245
1246 emit_mir_instruction(ctx, ins);
1247 }
1248
1249 static void
1250 emit_varying_read(
1251 compiler_context *ctx,
1252 unsigned dest, unsigned offset,
1253 unsigned nr_comp, unsigned component,
1254 nir_src *indirect_offset, nir_alu_type type, bool flat)
1255 {
1256 /* XXX: Half-floats? */
1257 /* TODO: swizzle, mask */
1258
1259 midgard_instruction ins = m_ld_vary_32(dest, offset);
1260 ins.mask = mask_of(nr_comp);
1261
1262 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1263 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1264
1265 midgard_varying_parameter p = {
1266 .is_varying = 1,
1267 .interpolation = midgard_interp_default,
1268 .flat = flat,
1269 };
1270
1271 unsigned u;
1272 memcpy(&u, &p, sizeof(p));
1273 ins.load_store.varying_parameters = u;
1274
1275 if (indirect_offset) {
1276 ins.src[2] = nir_src_index(ctx, indirect_offset);
1277 ins.src_types[2] = nir_type_uint32;
1278 } else
1279 ins.load_store.arg_2 = 0x1E;
1280
1281 ins.load_store.arg_1 = 0x9E;
1282
1283 /* Use the type appropriate load */
1284 switch (type) {
1285 case nir_type_uint:
1286 case nir_type_bool:
1287 ins.load_store.op = midgard_op_ld_vary_32u;
1288 break;
1289 case nir_type_int:
1290 ins.load_store.op = midgard_op_ld_vary_32i;
1291 break;
1292 case nir_type_float:
1293 ins.load_store.op = midgard_op_ld_vary_32;
1294 break;
1295 default:
1296 unreachable("Attempted to load unknown type");
1297 break;
1298 }
1299
1300 emit_mir_instruction(ctx, ins);
1301 }
1302
1303 static void
1304 emit_attr_read(
1305 compiler_context *ctx,
1306 unsigned dest, unsigned offset,
1307 unsigned nr_comp, nir_alu_type t)
1308 {
1309 midgard_instruction ins = m_ld_attr_32(dest, offset);
1310 ins.load_store.arg_1 = 0x1E;
1311 ins.load_store.arg_2 = 0x1E;
1312 ins.mask = mask_of(nr_comp);
1313
1314 /* Use the type appropriate load */
1315 switch (t) {
1316 case nir_type_uint:
1317 case nir_type_bool:
1318 ins.load_store.op = midgard_op_ld_attr_32u;
1319 break;
1320 case nir_type_int:
1321 ins.load_store.op = midgard_op_ld_attr_32i;
1322 break;
1323 case nir_type_float:
1324 ins.load_store.op = midgard_op_ld_attr_32;
1325 break;
1326 default:
1327 unreachable("Attempted to load unknown type");
1328 break;
1329 }
1330
1331 emit_mir_instruction(ctx, ins);
1332 }
1333
1334 static void
1335 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1336 unsigned nr_components, unsigned offset)
1337 {
1338 nir_dest nir_dest;
1339
1340 /* Figure out which uniform this is */
1341 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1342 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1343
1344 unsigned dest = nir_dest_index(&nir_dest);
1345
1346 /* Sysvals are prefix uniforms */
1347 unsigned uniform = ((uintptr_t) val) - 1;
1348
1349 /* Emit the read itself -- this is never indirect */
1350 midgard_instruction *ins =
1351 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1352
1353 ins->mask = mask_of(nr_components);
1354 }
1355
1356 static unsigned
1357 compute_builtin_arg(nir_op op)
1358 {
1359 switch (op) {
1360 case nir_intrinsic_load_work_group_id:
1361 return 0x14;
1362 case nir_intrinsic_load_local_invocation_id:
1363 return 0x10;
1364 default:
1365 unreachable("Invalid compute paramater loaded");
1366 }
1367 }
1368
1369 static void
1370 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1371 {
1372 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1373
1374 midgard_instruction *br = ctx->writeout_branch[rt];
1375
1376 assert(!br);
1377
1378 emit_explicit_constant(ctx, src, src);
1379
1380 struct midgard_instruction ins =
1381 v_branch(false, false);
1382
1383 ins.writeout = true;
1384
1385 /* Add dependencies */
1386 ins.src[0] = src;
1387 ins.src_types[0] = nir_type_uint32;
1388 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1389 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1390
1391 /* Emit the branch */
1392 br = emit_mir_instruction(ctx, ins);
1393 schedule_barrier(ctx);
1394 ctx->writeout_branch[rt] = br;
1395
1396 /* Push our current location = current block count - 1 = where we'll
1397 * jump to. Maybe a bit too clever for my own good */
1398
1399 br->branch.target_block = ctx->block_count - 1;
1400 }
1401
1402 static void
1403 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1404 {
1405 unsigned reg = nir_dest_index(&instr->dest);
1406 midgard_instruction ins = m_ld_compute_id(reg, 0);
1407 ins.mask = mask_of(3);
1408 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1409 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1410 emit_mir_instruction(ctx, ins);
1411 }
1412
1413 static unsigned
1414 vertex_builtin_arg(nir_op op)
1415 {
1416 switch (op) {
1417 case nir_intrinsic_load_vertex_id:
1418 return PAN_VERTEX_ID;
1419 case nir_intrinsic_load_instance_id:
1420 return PAN_INSTANCE_ID;
1421 default:
1422 unreachable("Invalid vertex builtin");
1423 }
1424 }
1425
1426 static void
1427 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1428 {
1429 unsigned reg = nir_dest_index(&instr->dest);
1430 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1431 }
1432
1433 static void
1434 emit_control_barrier(compiler_context *ctx)
1435 {
1436 midgard_instruction ins = {
1437 .type = TAG_TEXTURE_4,
1438 .src = { ~0, ~0, ~0, ~0 },
1439 .texture = {
1440 .op = TEXTURE_OP_BARRIER,
1441
1442 /* TODO: optimize */
1443 .barrier_buffer = 1,
1444 .barrier_shared = 1
1445 }
1446 };
1447
1448 emit_mir_instruction(ctx, ins);
1449 }
1450
1451 static const nir_variable *
1452 search_var(struct exec_list *vars, unsigned driver_loc)
1453 {
1454 nir_foreach_variable(var, vars) {
1455 if (var->data.driver_location == driver_loc)
1456 return var;
1457 }
1458
1459 return NULL;
1460 }
1461
1462 static unsigned
1463 mir_get_branch_cond(nir_src *src, bool *invert)
1464 {
1465 /* Wrap it. No swizzle since it's a scalar */
1466
1467 nir_alu_src alu = {
1468 .src = *src
1469 };
1470
1471 *invert = pan_has_source_mod(&alu, nir_op_inot);
1472 return nir_src_index(NULL, &alu.src);
1473 }
1474
1475 static void
1476 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1477 {
1478 unsigned offset = 0, reg;
1479
1480 switch (instr->intrinsic) {
1481 case nir_intrinsic_discard_if:
1482 case nir_intrinsic_discard: {
1483 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1484 struct midgard_instruction discard = v_branch(conditional, false);
1485 discard.branch.target_type = TARGET_DISCARD;
1486
1487 if (conditional) {
1488 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1489 &discard.branch.invert_conditional);
1490 discard.src_types[0] = nir_type_uint32;
1491 }
1492
1493 emit_mir_instruction(ctx, discard);
1494 schedule_barrier(ctx);
1495
1496 break;
1497 }
1498
1499 case nir_intrinsic_load_uniform:
1500 case nir_intrinsic_load_ubo:
1501 case nir_intrinsic_load_global:
1502 case nir_intrinsic_load_shared:
1503 case nir_intrinsic_load_input:
1504 case nir_intrinsic_load_interpolated_input: {
1505 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1506 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1507 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1508 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1509 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1510 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1511
1512 /* Get the base type of the intrinsic */
1513 /* TODO: Infer type? Does it matter? */
1514 nir_alu_type t =
1515 (is_ubo || is_global || is_shared) ? nir_type_uint :
1516 (is_interp) ? nir_type_float :
1517 nir_intrinsic_type(instr);
1518
1519 t = nir_alu_type_get_base_type(t);
1520
1521 if (!(is_ubo || is_global)) {
1522 offset = nir_intrinsic_base(instr);
1523 }
1524
1525 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1526
1527 nir_src *src_offset = nir_get_io_offset_src(instr);
1528
1529 bool direct = nir_src_is_const(*src_offset);
1530 nir_src *indirect_offset = direct ? NULL : src_offset;
1531
1532 if (direct)
1533 offset += nir_src_as_uint(*src_offset);
1534
1535 /* We may need to apply a fractional offset */
1536 int component = (is_flat || is_interp) ?
1537 nir_intrinsic_component(instr) : 0;
1538 reg = nir_dest_index(&instr->dest);
1539
1540 if (is_uniform && !ctx->is_blend) {
1541 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1542 } else if (is_ubo) {
1543 nir_src index = instr->src[0];
1544
1545 /* TODO: Is indirect block number possible? */
1546 assert(nir_src_is_const(index));
1547
1548 uint32_t uindex = nir_src_as_uint(index) + 1;
1549 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1550 } else if (is_global || is_shared) {
1551 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1552 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1553 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1554 } else if (ctx->is_blend) {
1555 /* For blend shaders, load the input color, which is
1556 * preloaded to r0 */
1557
1558 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1559 emit_mir_instruction(ctx, move);
1560 schedule_barrier(ctx);
1561 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1562 emit_attr_read(ctx, reg, offset, nr_comp, t);
1563 } else {
1564 DBG("Unknown load\n");
1565 assert(0);
1566 }
1567
1568 break;
1569 }
1570
1571 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1572 case nir_intrinsic_load_barycentric_pixel:
1573 case nir_intrinsic_load_barycentric_centroid:
1574 break;
1575
1576 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1577
1578 case nir_intrinsic_load_raw_output_pan:
1579 case nir_intrinsic_load_output_u8_as_fp16_pan:
1580 reg = nir_dest_index(&instr->dest);
1581 assert(ctx->is_blend);
1582
1583 /* T720 and below use different blend opcodes with slightly
1584 * different semantics than T760 and up */
1585
1586 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1587 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1588
1589 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1590 ld.load_store.op = old_blend ?
1591 midgard_op_ld_color_buffer_u8_as_fp16_old :
1592 midgard_op_ld_color_buffer_u8_as_fp16;
1593
1594 if (old_blend) {
1595 ld.load_store.address = 1;
1596 ld.load_store.arg_2 = 0x1E;
1597 }
1598
1599 for (unsigned c = 4; c < 16; ++c)
1600 ld.swizzle[0][c] = 0;
1601
1602 ld.dest_type = nir_type_float16;
1603 }
1604
1605 emit_mir_instruction(ctx, ld);
1606 break;
1607
1608 case nir_intrinsic_load_blend_const_color_rgba: {
1609 assert(ctx->is_blend);
1610 reg = nir_dest_index(&instr->dest);
1611
1612 /* Blend constants are embedded directly in the shader and
1613 * patched in, so we use some magic routing */
1614
1615 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1616 ins.has_constants = true;
1617 ins.has_blend_constant = true;
1618 emit_mir_instruction(ctx, ins);
1619 break;
1620 }
1621
1622 case nir_intrinsic_store_zs_output_pan: {
1623 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1624 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1625 MIDGARD_ZS_RT);
1626
1627 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1628
1629 if (!nir_intrinsic_component(instr))
1630 br->writeout_depth = true;
1631 if (nir_intrinsic_component(instr) ||
1632 instr->num_components)
1633 br->writeout_stencil = true;
1634 assert(br->writeout_depth | br->writeout_stencil);
1635 break;
1636 }
1637
1638 case nir_intrinsic_store_output:
1639 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1640
1641 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1642
1643 reg = nir_src_index(ctx, &instr->src[0]);
1644
1645 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1646 const nir_variable *var;
1647 enum midgard_rt_id rt;
1648
1649 var = search_var(&ctx->nir->outputs,
1650 nir_intrinsic_base(instr));
1651 assert(var);
1652 if (var->data.location == FRAG_RESULT_COLOR)
1653 rt = MIDGARD_COLOR_RT0;
1654 else if (var->data.location >= FRAG_RESULT_DATA0)
1655 rt = MIDGARD_COLOR_RT0 + var->data.location -
1656 FRAG_RESULT_DATA0;
1657 else
1658 assert(0);
1659
1660 emit_fragment_store(ctx, reg, rt);
1661 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1662 /* We should have been vectorized, though we don't
1663 * currently check that st_vary is emitted only once
1664 * per slot (this is relevant, since there's not a mask
1665 * parameter available on the store [set to 0 by the
1666 * blob]). We do respect the component by adjusting the
1667 * swizzle. If this is a constant source, we'll need to
1668 * emit that explicitly. */
1669
1670 emit_explicit_constant(ctx, reg, reg);
1671
1672 unsigned dst_component = nir_intrinsic_component(instr);
1673 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1674
1675 midgard_instruction st = m_st_vary_32(reg, offset);
1676 st.load_store.arg_1 = 0x9E;
1677 st.load_store.arg_2 = 0x1E;
1678
1679 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1680 case nir_type_uint:
1681 case nir_type_bool:
1682 st.load_store.op = midgard_op_st_vary_32u;
1683 break;
1684 case nir_type_int:
1685 st.load_store.op = midgard_op_st_vary_32i;
1686 break;
1687 case nir_type_float:
1688 st.load_store.op = midgard_op_st_vary_32;
1689 break;
1690 default:
1691 unreachable("Attempted to store unknown type");
1692 break;
1693 }
1694
1695 /* nir_intrinsic_component(store_intr) encodes the
1696 * destination component start. Source component offset
1697 * adjustment is taken care of in
1698 * install_registers_instr(), when offset_swizzle() is
1699 * called.
1700 */
1701 unsigned src_component = COMPONENT_X;
1702
1703 assert(nr_comp > 0);
1704 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1705 st.swizzle[0][i] = src_component;
1706 if (i >= dst_component && i < dst_component + nr_comp - 1)
1707 src_component++;
1708 }
1709
1710 emit_mir_instruction(ctx, st);
1711 } else {
1712 DBG("Unknown store\n");
1713 assert(0);
1714 }
1715
1716 break;
1717
1718 /* Special case of store_output for lowered blend shaders */
1719 case nir_intrinsic_store_raw_output_pan:
1720 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1721 reg = nir_src_index(ctx, &instr->src[0]);
1722
1723 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1724 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1725 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1726 * of:
1727 *
1728 * imov r0.xyzw, r0.xxxx
1729 */
1730
1731 unsigned expanded = make_compiler_temp(ctx);
1732
1733 midgard_instruction splatter = v_mov(reg, expanded);
1734
1735 for (unsigned c = 0; c < 16; ++c)
1736 splatter.swizzle[1][c] = 0;
1737
1738 emit_mir_instruction(ctx, splatter);
1739 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1740 } else
1741 emit_fragment_store(ctx, reg, ctx->blend_rt);
1742
1743 break;
1744
1745 case nir_intrinsic_store_global:
1746 case nir_intrinsic_store_shared:
1747 reg = nir_src_index(ctx, &instr->src[0]);
1748 emit_explicit_constant(ctx, reg, reg);
1749
1750 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1751 break;
1752
1753 case nir_intrinsic_load_ssbo_address:
1754 emit_sysval_read(ctx, &instr->instr, 1, 0);
1755 break;
1756
1757 case nir_intrinsic_get_buffer_size:
1758 emit_sysval_read(ctx, &instr->instr, 1, 8);
1759 break;
1760
1761 case nir_intrinsic_load_viewport_scale:
1762 case nir_intrinsic_load_viewport_offset:
1763 case nir_intrinsic_load_num_work_groups:
1764 case nir_intrinsic_load_sampler_lod_parameters_pan:
1765 emit_sysval_read(ctx, &instr->instr, 3, 0);
1766 break;
1767
1768 case nir_intrinsic_load_work_group_id:
1769 case nir_intrinsic_load_local_invocation_id:
1770 emit_compute_builtin(ctx, instr);
1771 break;
1772
1773 case nir_intrinsic_load_vertex_id:
1774 case nir_intrinsic_load_instance_id:
1775 emit_vertex_builtin(ctx, instr);
1776 break;
1777
1778 case nir_intrinsic_memory_barrier_buffer:
1779 case nir_intrinsic_memory_barrier_shared:
1780 break;
1781
1782 case nir_intrinsic_control_barrier:
1783 schedule_barrier(ctx);
1784 emit_control_barrier(ctx);
1785 schedule_barrier(ctx);
1786 break;
1787
1788 default:
1789 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1790 assert(0);
1791 break;
1792 }
1793 }
1794
1795 static unsigned
1796 midgard_tex_format(enum glsl_sampler_dim dim)
1797 {
1798 switch (dim) {
1799 case GLSL_SAMPLER_DIM_1D:
1800 case GLSL_SAMPLER_DIM_BUF:
1801 return MALI_TEX_1D;
1802
1803 case GLSL_SAMPLER_DIM_2D:
1804 case GLSL_SAMPLER_DIM_EXTERNAL:
1805 case GLSL_SAMPLER_DIM_RECT:
1806 return MALI_TEX_2D;
1807
1808 case GLSL_SAMPLER_DIM_3D:
1809 return MALI_TEX_3D;
1810
1811 case GLSL_SAMPLER_DIM_CUBE:
1812 return MALI_TEX_CUBE;
1813
1814 default:
1815 DBG("Unknown sampler dim type\n");
1816 assert(0);
1817 return 0;
1818 }
1819 }
1820
1821 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1822 * was successful */
1823
1824 static bool
1825 pan_attach_constant_bias(
1826 compiler_context *ctx,
1827 nir_src lod,
1828 midgard_texture_word *word)
1829 {
1830 /* To attach as constant, it has to *be* constant */
1831
1832 if (!nir_src_is_const(lod))
1833 return false;
1834
1835 float f = nir_src_as_float(lod);
1836
1837 /* Break into fixed-point */
1838 signed lod_int = f;
1839 float lod_frac = f - lod_int;
1840
1841 /* Carry over negative fractions */
1842 if (lod_frac < 0.0) {
1843 lod_int--;
1844 lod_frac += 1.0;
1845 }
1846
1847 /* Encode */
1848 word->bias = float_to_ubyte(lod_frac);
1849 word->bias_int = lod_int;
1850
1851 return true;
1852 }
1853
1854 static void
1855 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1856 unsigned midgard_texop)
1857 {
1858 /* TODO */
1859 //assert (!instr->sampler);
1860
1861 int texture_index = instr->texture_index;
1862 int sampler_index = texture_index;
1863
1864 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1865 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1866
1867 midgard_instruction ins = {
1868 .type = TAG_TEXTURE_4,
1869 .mask = 0xF,
1870 .dest = nir_dest_index(&instr->dest),
1871 .src = { ~0, ~0, ~0, ~0 },
1872 .dest_type = dest_type,
1873 .swizzle = SWIZZLE_IDENTITY_4,
1874 .texture = {
1875 .op = midgard_texop,
1876 .format = midgard_tex_format(instr->sampler_dim),
1877 .texture_handle = texture_index,
1878 .sampler_handle = sampler_index,
1879 .shadow = instr->is_shadow,
1880 }
1881 };
1882
1883 if (instr->is_shadow && !instr->is_new_style_shadow)
1884 for (int i = 0; i < 4; ++i)
1885 ins.swizzle[0][i] = COMPONENT_X;
1886
1887 /* We may need a temporary for the coordinate */
1888
1889 bool needs_temp_coord =
1890 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1891 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1892 (instr->is_shadow);
1893
1894 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1895
1896 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1897 int index = nir_src_index(ctx, &instr->src[i].src);
1898 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1899 unsigned sz = nir_src_bit_size(instr->src[i].src);
1900 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1901
1902 switch (instr->src[i].src_type) {
1903 case nir_tex_src_coord: {
1904 emit_explicit_constant(ctx, index, index);
1905
1906 unsigned coord_mask = mask_of(instr->coord_components);
1907
1908 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1909
1910 if (flip_zw)
1911 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1912
1913 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1914 /* texelFetch is undefined on samplerCube */
1915 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1916
1917 /* For cubemaps, we use a special ld/st op to
1918 * select the face and copy the xy into the
1919 * texture register */
1920
1921 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1922 ld.src[1] = index;
1923 ld.src_types[1] = T;
1924 ld.mask = 0x3; /* xy */
1925 ld.load_store.arg_1 = 0x20;
1926 ld.swizzle[1][3] = COMPONENT_X;
1927 emit_mir_instruction(ctx, ld);
1928
1929 /* xyzw -> xyxx */
1930 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1931 ins.swizzle[1][3] = COMPONENT_X;
1932 } else if (needs_temp_coord) {
1933 /* mov coord_temp, coords */
1934 midgard_instruction mov = v_mov(index, coords);
1935 mov.mask = coord_mask;
1936
1937 if (flip_zw)
1938 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1939
1940 emit_mir_instruction(ctx, mov);
1941 } else {
1942 coords = index;
1943 }
1944
1945 ins.src[1] = coords;
1946 ins.src_types[1] = T;
1947
1948 /* Texelfetch coordinates uses all four elements
1949 * (xyz/index) regardless of texture dimensionality,
1950 * which means it's necessary to zero the unused
1951 * components to keep everything happy */
1952
1953 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1954 /* mov index.zw, #0, or generalized */
1955 midgard_instruction mov =
1956 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1957 mov.has_constants = true;
1958 mov.mask = coord_mask ^ 0xF;
1959 emit_mir_instruction(ctx, mov);
1960 }
1961
1962 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1963 /* Array component in w but NIR wants it in z,
1964 * but if we have a temp coord we already fixed
1965 * that up */
1966
1967 if (nr_components == 3) {
1968 ins.swizzle[1][2] = COMPONENT_Z;
1969 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1970 } else if (nr_components == 2) {
1971 ins.swizzle[1][2] =
1972 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1973 ins.swizzle[1][3] = COMPONENT_X;
1974 } else
1975 unreachable("Invalid texture 2D components");
1976 }
1977
1978 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1979 /* We zeroed */
1980 ins.swizzle[1][2] = COMPONENT_Z;
1981 ins.swizzle[1][3] = COMPONENT_W;
1982 }
1983
1984 break;
1985 }
1986
1987 case nir_tex_src_bias:
1988 case nir_tex_src_lod: {
1989 /* Try as a constant if we can */
1990
1991 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1992 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1993 break;
1994
1995 ins.texture.lod_register = true;
1996 ins.src[2] = index;
1997 ins.src_types[2] = T;
1998
1999 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2000 ins.swizzle[2][c] = COMPONENT_X;
2001
2002 emit_explicit_constant(ctx, index, index);
2003
2004 break;
2005 };
2006
2007 case nir_tex_src_offset: {
2008 ins.texture.offset_register = true;
2009 ins.src[3] = index;
2010 ins.src_types[3] = T;
2011
2012 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2013 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
2014
2015 emit_explicit_constant(ctx, index, index);
2016 break;
2017 };
2018
2019 case nir_tex_src_comparator: {
2020 unsigned comp = COMPONENT_Z;
2021
2022 /* mov coord_temp.foo, coords */
2023 midgard_instruction mov = v_mov(index, coords);
2024 mov.mask = 1 << comp;
2025
2026 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
2027 mov.swizzle[1][i] = COMPONENT_X;
2028
2029 emit_mir_instruction(ctx, mov);
2030 break;
2031 }
2032
2033 default: {
2034 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
2035 assert(0);
2036 }
2037 }
2038 }
2039
2040 emit_mir_instruction(ctx, ins);
2041 }
2042
2043 static void
2044 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2045 {
2046 switch (instr->op) {
2047 case nir_texop_tex:
2048 case nir_texop_txb:
2049 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2050 break;
2051 case nir_texop_txl:
2052 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2053 break;
2054 case nir_texop_txf:
2055 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2056 break;
2057 case nir_texop_txs:
2058 emit_sysval_read(ctx, &instr->instr, 4, 0);
2059 break;
2060 default: {
2061 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2062 assert(0);
2063 }
2064 }
2065 }
2066
2067 static void
2068 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2069 {
2070 switch (instr->type) {
2071 case nir_jump_break: {
2072 /* Emit a branch out of the loop */
2073 struct midgard_instruction br = v_branch(false, false);
2074 br.branch.target_type = TARGET_BREAK;
2075 br.branch.target_break = ctx->current_loop_depth;
2076 emit_mir_instruction(ctx, br);
2077 break;
2078 }
2079
2080 default:
2081 DBG("Unknown jump type %d\n", instr->type);
2082 break;
2083 }
2084 }
2085
2086 static void
2087 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2088 {
2089 switch (instr->type) {
2090 case nir_instr_type_load_const:
2091 emit_load_const(ctx, nir_instr_as_load_const(instr));
2092 break;
2093
2094 case nir_instr_type_intrinsic:
2095 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2096 break;
2097
2098 case nir_instr_type_alu:
2099 emit_alu(ctx, nir_instr_as_alu(instr));
2100 break;
2101
2102 case nir_instr_type_tex:
2103 emit_tex(ctx, nir_instr_as_tex(instr));
2104 break;
2105
2106 case nir_instr_type_jump:
2107 emit_jump(ctx, nir_instr_as_jump(instr));
2108 break;
2109
2110 case nir_instr_type_ssa_undef:
2111 /* Spurious */
2112 break;
2113
2114 default:
2115 DBG("Unhandled instruction type\n");
2116 break;
2117 }
2118 }
2119
2120
2121 /* ALU instructions can inline or embed constants, which decreases register
2122 * pressure and saves space. */
2123
2124 #define CONDITIONAL_ATTACH(idx) { \
2125 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2126 \
2127 if (entry) { \
2128 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2129 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2130 } \
2131 }
2132
2133 static void
2134 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2135 {
2136 mir_foreach_instr_in_block(block, alu) {
2137 /* Other instructions cannot inline constants */
2138 if (alu->type != TAG_ALU_4) continue;
2139 if (alu->compact_branch) continue;
2140
2141 /* If there is already a constant here, we can do nothing */
2142 if (alu->has_constants) continue;
2143
2144 CONDITIONAL_ATTACH(0);
2145
2146 if (!alu->has_constants) {
2147 CONDITIONAL_ATTACH(1)
2148 } else if (!alu->inline_constant) {
2149 /* Corner case: _two_ vec4 constants, for instance with a
2150 * csel. For this case, we can only use a constant
2151 * register for one, we'll have to emit a move for the
2152 * other. */
2153
2154 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2155 unsigned scratch = make_compiler_temp(ctx);
2156
2157 if (entry) {
2158 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2159 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2160
2161 /* Set the source */
2162 alu->src[1] = scratch;
2163
2164 /* Inject us -before- the last instruction which set r31 */
2165 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2166 }
2167 }
2168 }
2169 }
2170
2171 /* Midgard supports two types of constants, embedded constants (128-bit) and
2172 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2173 * constants can be demoted to inline constants, for space savings and
2174 * sometimes a performance boost */
2175
2176 static void
2177 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2178 {
2179 mir_foreach_instr_in_block(block, ins) {
2180 if (!ins->has_constants) continue;
2181 if (ins->has_inline_constant) continue;
2182
2183 /* Blend constants must not be inlined by definition */
2184 if (ins->has_blend_constant) continue;
2185
2186 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2187 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2188 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2189
2190 if (!(is_16 || is_32))
2191 continue;
2192
2193 /* src1 cannot be an inline constant due to encoding
2194 * restrictions. So, if possible we try to flip the arguments
2195 * in that case */
2196
2197 int op = ins->alu.op;
2198
2199 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2200 alu_opcode_props[op].props & OP_COMMUTES) {
2201 mir_flip(ins);
2202 }
2203
2204 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2205 /* Extract the source information */
2206
2207 midgard_vector_alu_src *src;
2208 int q = ins->alu.src2;
2209 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2210 src = m;
2211
2212 /* Component is from the swizzle. Take a nonzero component */
2213 assert(ins->mask);
2214 unsigned first_comp = ffs(ins->mask) - 1;
2215 unsigned component = ins->swizzle[1][first_comp];
2216
2217 /* Scale constant appropriately, if we can legally */
2218 uint16_t scaled_constant = 0;
2219
2220 if (is_16) {
2221 scaled_constant = ins->constants.u16[component];
2222 } else if (midgard_is_integer_op(op)) {
2223 scaled_constant = ins->constants.u32[component];
2224
2225 /* Constant overflow after resize */
2226 if (scaled_constant != ins->constants.u32[component])
2227 continue;
2228 } else {
2229 float original = ins->constants.f32[component];
2230 scaled_constant = _mesa_float_to_half(original);
2231
2232 /* Check for loss of precision. If this is
2233 * mediump, we don't care, but for a highp
2234 * shader, we need to pay attention. NIR
2235 * doesn't yet tell us which mode we're in!
2236 * Practically this prevents most constants
2237 * from being inlined, sadly. */
2238
2239 float fp32 = _mesa_half_to_float(scaled_constant);
2240
2241 if (fp32 != original)
2242 continue;
2243 }
2244
2245 /* We don't know how to handle these with a constant */
2246
2247 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2248 DBG("Bailing inline constant...\n");
2249 continue;
2250 }
2251
2252 /* Make sure that the constant is not itself a vector
2253 * by checking if all accessed values are the same. */
2254
2255 const midgard_constants *cons = &ins->constants;
2256 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2257
2258 bool is_vector = false;
2259 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2260
2261 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2262 /* We only care if this component is actually used */
2263 if (!(mask & (1 << c)))
2264 continue;
2265
2266 uint32_t test = is_16 ?
2267 cons->u16[ins->swizzle[1][c]] :
2268 cons->u32[ins->swizzle[1][c]];
2269
2270 if (test != value) {
2271 is_vector = true;
2272 break;
2273 }
2274 }
2275
2276 if (is_vector)
2277 continue;
2278
2279 /* Get rid of the embedded constant */
2280 ins->has_constants = false;
2281 ins->src[1] = ~0;
2282 ins->has_inline_constant = true;
2283 ins->inline_constant = scaled_constant;
2284 }
2285 }
2286 }
2287
2288 /* Dead code elimination for branches at the end of a block - only one branch
2289 * per block is legal semantically */
2290
2291 static void
2292 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2293 {
2294 bool branched = false;
2295
2296 mir_foreach_instr_in_block_safe(block, ins) {
2297 if (!midgard_is_branch_unit(ins->unit)) continue;
2298
2299 if (branched)
2300 mir_remove_instruction(ins);
2301
2302 branched = true;
2303 }
2304 }
2305
2306 static unsigned
2307 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2308 {
2309 /* Loop to ourselves */
2310 midgard_instruction *br = ctx->writeout_branch[rt];
2311 struct midgard_instruction ins = v_branch(false, false);
2312 ins.writeout = true;
2313 ins.writeout_depth = br->writeout_depth;
2314 ins.writeout_stencil = br->writeout_stencil;
2315 ins.branch.target_block = ctx->block_count - 1;
2316 ins.constants.u32[0] = br->constants.u32[0];
2317 emit_mir_instruction(ctx, ins);
2318
2319 ctx->current_block->epilogue = true;
2320 schedule_barrier(ctx);
2321 return ins.branch.target_block;
2322 }
2323
2324 static midgard_block *
2325 emit_block(compiler_context *ctx, nir_block *block)
2326 {
2327 midgard_block *this_block = ctx->after_block;
2328 ctx->after_block = NULL;
2329
2330 if (!this_block)
2331 this_block = create_empty_block(ctx);
2332
2333 list_addtail(&this_block->base.link, &ctx->blocks);
2334
2335 this_block->scheduled = false;
2336 ++ctx->block_count;
2337
2338 /* Set up current block */
2339 list_inithead(&this_block->base.instructions);
2340 ctx->current_block = this_block;
2341
2342 nir_foreach_instr(instr, block) {
2343 emit_instr(ctx, instr);
2344 ++ctx->instruction_count;
2345 }
2346
2347 return this_block;
2348 }
2349
2350 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2351
2352 static void
2353 emit_if(struct compiler_context *ctx, nir_if *nif)
2354 {
2355 midgard_block *before_block = ctx->current_block;
2356
2357 /* Speculatively emit the branch, but we can't fill it in until later */
2358 bool inv = false;
2359 EMIT(branch, true, true);
2360 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2361 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2362 then_branch->src_types[0] = nir_type_uint32;
2363 then_branch->branch.invert_conditional = !inv;
2364
2365 /* Emit the two subblocks. */
2366 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2367 midgard_block *end_then_block = ctx->current_block;
2368
2369 /* Emit a jump from the end of the then block to the end of the else */
2370 EMIT(branch, false, false);
2371 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2372
2373 /* Emit second block, and check if it's empty */
2374
2375 int else_idx = ctx->block_count;
2376 int count_in = ctx->instruction_count;
2377 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2378 midgard_block *end_else_block = ctx->current_block;
2379 int after_else_idx = ctx->block_count;
2380
2381 /* Now that we have the subblocks emitted, fix up the branches */
2382
2383 assert(then_block);
2384 assert(else_block);
2385
2386 if (ctx->instruction_count == count_in) {
2387 /* The else block is empty, so don't emit an exit jump */
2388 mir_remove_instruction(then_exit);
2389 then_branch->branch.target_block = after_else_idx;
2390 } else {
2391 then_branch->branch.target_block = else_idx;
2392 then_exit->branch.target_block = after_else_idx;
2393 }
2394
2395 /* Wire up the successors */
2396
2397 ctx->after_block = create_empty_block(ctx);
2398
2399 pan_block_add_successor(&before_block->base, &then_block->base);
2400 pan_block_add_successor(&before_block->base, &else_block->base);
2401
2402 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2403 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2404 }
2405
2406 static void
2407 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2408 {
2409 /* Remember where we are */
2410 midgard_block *start_block = ctx->current_block;
2411
2412 /* Allocate a loop number, growing the current inner loop depth */
2413 int loop_idx = ++ctx->current_loop_depth;
2414
2415 /* Get index from before the body so we can loop back later */
2416 int start_idx = ctx->block_count;
2417
2418 /* Emit the body itself */
2419 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2420
2421 /* Branch back to loop back */
2422 struct midgard_instruction br_back = v_branch(false, false);
2423 br_back.branch.target_block = start_idx;
2424 emit_mir_instruction(ctx, br_back);
2425
2426 /* Mark down that branch in the graph. */
2427 pan_block_add_successor(&start_block->base, &loop_block->base);
2428 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2429
2430 /* Find the index of the block about to follow us (note: we don't add
2431 * one; blocks are 0-indexed so we get a fencepost problem) */
2432 int break_block_idx = ctx->block_count;
2433
2434 /* Fix up the break statements we emitted to point to the right place,
2435 * now that we can allocate a block number for them */
2436 ctx->after_block = create_empty_block(ctx);
2437
2438 mir_foreach_block_from(ctx, start_block, _block) {
2439 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2440 if (ins->type != TAG_ALU_4) continue;
2441 if (!ins->compact_branch) continue;
2442
2443 /* We found a branch -- check the type to see if we need to do anything */
2444 if (ins->branch.target_type != TARGET_BREAK) continue;
2445
2446 /* It's a break! Check if it's our break */
2447 if (ins->branch.target_break != loop_idx) continue;
2448
2449 /* Okay, cool, we're breaking out of this loop.
2450 * Rewrite from a break to a goto */
2451
2452 ins->branch.target_type = TARGET_GOTO;
2453 ins->branch.target_block = break_block_idx;
2454
2455 pan_block_add_successor(_block, &ctx->after_block->base);
2456 }
2457 }
2458
2459 /* Now that we've finished emitting the loop, free up the depth again
2460 * so we play nice with recursion amid nested loops */
2461 --ctx->current_loop_depth;
2462
2463 /* Dump loop stats */
2464 ++ctx->loop_count;
2465 }
2466
2467 static midgard_block *
2468 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2469 {
2470 midgard_block *start_block = NULL;
2471
2472 foreach_list_typed(nir_cf_node, node, node, list) {
2473 switch (node->type) {
2474 case nir_cf_node_block: {
2475 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2476
2477 if (!start_block)
2478 start_block = block;
2479
2480 break;
2481 }
2482
2483 case nir_cf_node_if:
2484 emit_if(ctx, nir_cf_node_as_if(node));
2485 break;
2486
2487 case nir_cf_node_loop:
2488 emit_loop(ctx, nir_cf_node_as_loop(node));
2489 break;
2490
2491 case nir_cf_node_function:
2492 assert(0);
2493 break;
2494 }
2495 }
2496
2497 return start_block;
2498 }
2499
2500 /* Due to lookahead, we need to report the first tag executed in the command
2501 * stream and in branch targets. An initial block might be empty, so iterate
2502 * until we find one that 'works' */
2503
2504 static unsigned
2505 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2506 {
2507 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2508
2509 mir_foreach_block_from(ctx, initial_block, _v) {
2510 midgard_block *v = (midgard_block *) _v;
2511 if (v->quadword_count) {
2512 midgard_bundle *initial_bundle =
2513 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2514
2515 return initial_bundle->tag;
2516 }
2517 }
2518
2519 /* Default to a tag 1 which will break from the shader, in case we jump
2520 * to the exit block (i.e. `return` in a compute shader) */
2521
2522 return 1;
2523 }
2524
2525 /* For each fragment writeout instruction, generate a writeout loop to
2526 * associate with it */
2527
2528 static void
2529 mir_add_writeout_loops(compiler_context *ctx)
2530 {
2531 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2532 midgard_instruction *br = ctx->writeout_branch[rt];
2533 if (!br) continue;
2534
2535 unsigned popped = br->branch.target_block;
2536 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2537 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2538 br->branch.target_type = TARGET_GOTO;
2539
2540 /* If we have more RTs, we'll need to restore back after our
2541 * loop terminates */
2542
2543 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2544 midgard_instruction uncond = v_branch(false, false);
2545 uncond.branch.target_block = popped;
2546 uncond.branch.target_type = TARGET_GOTO;
2547 emit_mir_instruction(ctx, uncond);
2548 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2549 schedule_barrier(ctx);
2550 } else {
2551 /* We're last, so we can terminate here */
2552 br->last_writeout = true;
2553 }
2554 }
2555 }
2556
2557 int
2558 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2559 {
2560 struct util_dynarray *compiled = &program->compiled;
2561
2562 midgard_debug = debug_get_option_midgard_debug();
2563
2564 /* TODO: Bound against what? */
2565 compiler_context *ctx = rzalloc(NULL, compiler_context);
2566
2567 ctx->nir = nir;
2568 ctx->stage = nir->info.stage;
2569 ctx->is_blend = is_blend;
2570 ctx->alpha_ref = program->alpha_ref;
2571 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2572 ctx->quirks = midgard_get_quirks(gpu_id);
2573
2574 /* Start off with a safe cutoff, allowing usage of all 16 work
2575 * registers. Later, we'll promote uniform reads to uniform registers
2576 * if we determine it is beneficial to do so */
2577 ctx->uniform_cutoff = 8;
2578
2579 /* Initialize at a global (not block) level hash tables */
2580
2581 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2582 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2583
2584 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2585 * (so we don't accidentally duplicate the epilogue since mesa/st has
2586 * messed with our I/O quite a bit already) */
2587
2588 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2589
2590 if (ctx->stage == MESA_SHADER_VERTEX) {
2591 NIR_PASS_V(nir, nir_lower_viewport_transform);
2592 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2593 }
2594
2595 NIR_PASS_V(nir, nir_lower_var_copies);
2596 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2597 NIR_PASS_V(nir, nir_split_var_copies);
2598 NIR_PASS_V(nir, nir_lower_var_copies);
2599 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2600 NIR_PASS_V(nir, nir_lower_var_copies);
2601 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2602
2603 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2604 NIR_PASS_V(nir, nir_lower_ssbo);
2605 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2606
2607 /* Optimisation passes */
2608
2609 optimise_nir(nir, ctx->quirks);
2610
2611 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2612 nir_print_shader(nir, stdout);
2613 }
2614
2615 /* Assign sysvals and counts, now that we're sure
2616 * (post-optimisation) */
2617
2618 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2619 program->sysval_count = ctx->sysvals.sysval_count;
2620 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2621
2622 nir_foreach_function(func, nir) {
2623 if (!func->impl)
2624 continue;
2625
2626 list_inithead(&ctx->blocks);
2627 ctx->block_count = 0;
2628 ctx->func = func;
2629 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2630
2631 emit_cf_list(ctx, &func->impl->body);
2632 free(ctx->already_emitted);
2633 break; /* TODO: Multi-function shaders */
2634 }
2635
2636 util_dynarray_init(compiled, NULL);
2637
2638 /* Per-block lowering before opts */
2639
2640 mir_foreach_block(ctx, _block) {
2641 midgard_block *block = (midgard_block *) _block;
2642 inline_alu_constants(ctx, block);
2643 embedded_to_inline_constant(ctx, block);
2644 }
2645 /* MIR-level optimizations */
2646
2647 bool progress = false;
2648
2649 do {
2650 progress = false;
2651 progress |= midgard_opt_dead_code_eliminate(ctx);
2652
2653 mir_foreach_block(ctx, _block) {
2654 midgard_block *block = (midgard_block *) _block;
2655 progress |= midgard_opt_copy_prop(ctx, block);
2656 progress |= midgard_opt_combine_projection(ctx, block);
2657 progress |= midgard_opt_varying_projection(ctx, block);
2658 }
2659 } while (progress);
2660
2661 mir_foreach_block(ctx, _block) {
2662 midgard_block *block = (midgard_block *) _block;
2663 midgard_lower_derivatives(ctx, block);
2664 midgard_cull_dead_branch(ctx, block);
2665 }
2666
2667 if (ctx->stage == MESA_SHADER_FRAGMENT)
2668 mir_add_writeout_loops(ctx);
2669
2670 /* Analyze now that the code is known but before scheduling creates
2671 * pipeline registers which are harder to track */
2672 mir_analyze_helper_terminate(ctx);
2673 mir_analyze_helper_requirements(ctx);
2674
2675 /* Schedule! */
2676 midgard_schedule_program(ctx);
2677 mir_ra(ctx);
2678
2679 /* Now that all the bundles are scheduled and we can calculate block
2680 * sizes, emit actual branch instructions rather than placeholders */
2681
2682 int br_block_idx = 0;
2683
2684 mir_foreach_block(ctx, _block) {
2685 midgard_block *block = (midgard_block *) _block;
2686 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2687 for (int c = 0; c < bundle->instruction_count; ++c) {
2688 midgard_instruction *ins = bundle->instructions[c];
2689
2690 if (!midgard_is_branch_unit(ins->unit)) continue;
2691
2692 /* Parse some basic branch info */
2693 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2694 bool is_conditional = ins->branch.conditional;
2695 bool is_inverted = ins->branch.invert_conditional;
2696 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2697 bool is_writeout = ins->writeout;
2698
2699 /* Determine the block we're jumping to */
2700 int target_number = ins->branch.target_block;
2701
2702 /* Report the destination tag */
2703 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2704
2705 /* Count up the number of quadwords we're
2706 * jumping over = number of quadwords until
2707 * (br_block_idx, target_number) */
2708
2709 int quadword_offset = 0;
2710
2711 if (is_discard) {
2712 /* Ignored */
2713 } else if (target_number > br_block_idx) {
2714 /* Jump forward */
2715
2716 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2717 midgard_block *blk = mir_get_block(ctx, idx);
2718 assert(blk);
2719
2720 quadword_offset += blk->quadword_count;
2721 }
2722 } else {
2723 /* Jump backwards */
2724
2725 for (int idx = br_block_idx; idx >= target_number; --idx) {
2726 midgard_block *blk = mir_get_block(ctx, idx);
2727 assert(blk);
2728
2729 quadword_offset -= blk->quadword_count;
2730 }
2731 }
2732
2733 /* Unconditional extended branches (far jumps)
2734 * have issues, so we always use a conditional
2735 * branch, setting the condition to always for
2736 * unconditional. For compact unconditional
2737 * branches, cond isn't used so it doesn't
2738 * matter what we pick. */
2739
2740 midgard_condition cond =
2741 !is_conditional ? midgard_condition_always :
2742 is_inverted ? midgard_condition_false :
2743 midgard_condition_true;
2744
2745 midgard_jmp_writeout_op op =
2746 is_discard ? midgard_jmp_writeout_op_discard :
2747 is_writeout ? midgard_jmp_writeout_op_writeout :
2748 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2749 midgard_jmp_writeout_op_branch_cond;
2750
2751 if (!is_compact) {
2752 midgard_branch_extended branch =
2753 midgard_create_branch_extended(
2754 cond, op,
2755 dest_tag,
2756 quadword_offset);
2757
2758 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2759 } else if (is_conditional || is_discard) {
2760 midgard_branch_cond branch = {
2761 .op = op,
2762 .dest_tag = dest_tag,
2763 .offset = quadword_offset,
2764 .cond = cond
2765 };
2766
2767 assert(branch.offset == quadword_offset);
2768
2769 memcpy(&ins->br_compact, &branch, sizeof(branch));
2770 } else {
2771 assert(op == midgard_jmp_writeout_op_branch_uncond);
2772
2773 midgard_branch_uncond branch = {
2774 .op = op,
2775 .dest_tag = dest_tag,
2776 .offset = quadword_offset,
2777 .unknown = 1
2778 };
2779
2780 assert(branch.offset == quadword_offset);
2781
2782 memcpy(&ins->br_compact, &branch, sizeof(branch));
2783 }
2784 }
2785 }
2786
2787 ++br_block_idx;
2788 }
2789
2790 /* Emit flat binary from the instruction arrays. Iterate each block in
2791 * sequence. Save instruction boundaries such that lookahead tags can
2792 * be assigned easily */
2793
2794 /* Cache _all_ bundles in source order for lookahead across failed branches */
2795
2796 int bundle_count = 0;
2797 mir_foreach_block(ctx, _block) {
2798 midgard_block *block = (midgard_block *) _block;
2799 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2800 }
2801 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2802 int bundle_idx = 0;
2803 mir_foreach_block(ctx, _block) {
2804 midgard_block *block = (midgard_block *) _block;
2805 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2806 source_order_bundles[bundle_idx++] = bundle;
2807 }
2808 }
2809
2810 int current_bundle = 0;
2811
2812 /* Midgard prefetches instruction types, so during emission we
2813 * need to lookahead. Unless this is the last instruction, in
2814 * which we return 1. */
2815
2816 mir_foreach_block(ctx, _block) {
2817 midgard_block *block = (midgard_block *) _block;
2818 mir_foreach_bundle_in_block(block, bundle) {
2819 int lookahead = 1;
2820
2821 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2822 lookahead = source_order_bundles[current_bundle + 1]->tag;
2823
2824 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2825 ++current_bundle;
2826 }
2827
2828 /* TODO: Free deeper */
2829 //util_dynarray_fini(&block->instructions);
2830 }
2831
2832 free(source_order_bundles);
2833
2834 /* Report the very first tag executed */
2835 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2836
2837 /* Deal with off-by-one related to the fencepost problem */
2838 program->work_register_count = ctx->work_registers + 1;
2839 program->uniform_cutoff = ctx->uniform_cutoff;
2840
2841 program->blend_patch_offset = ctx->blend_constant_offset;
2842 program->tls_size = ctx->tls_size;
2843
2844 if (midgard_debug & MIDGARD_DBG_SHADERS)
2845 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2846
2847 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2848 unsigned nr_bundles = 0, nr_ins = 0;
2849
2850 /* Count instructions and bundles */
2851
2852 mir_foreach_block(ctx, _block) {
2853 midgard_block *block = (midgard_block *) _block;
2854 nr_bundles += util_dynarray_num_elements(
2855 &block->bundles, midgard_bundle);
2856
2857 mir_foreach_bundle_in_block(block, bun)
2858 nr_ins += bun->instruction_count;
2859 }
2860
2861 /* Calculate thread count. There are certain cutoffs by
2862 * register count for thread count */
2863
2864 unsigned nr_registers = program->work_register_count;
2865
2866 unsigned nr_threads =
2867 (nr_registers <= 4) ? 4 :
2868 (nr_registers <= 8) ? 2 :
2869 1;
2870
2871 /* Dump stats */
2872
2873 fprintf(stderr, "shader%d - %s shader: "
2874 "%u inst, %u bundles, %u quadwords, "
2875 "%u registers, %u threads, %u loops, "
2876 "%u:%u spills:fills\n",
2877 SHADER_DB_COUNT++,
2878 gl_shader_stage_name(ctx->stage),
2879 nr_ins, nr_bundles, ctx->quadword_count,
2880 nr_registers, nr_threads,
2881 ctx->loop_count,
2882 ctx->spills, ctx->fills);
2883 }
2884
2885 ralloc_free(ctx);
2886
2887 return 0;
2888 }