2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
51 #include "midgard_quirks.h"
53 #include "disassemble.h"
55 static const struct debug_named_value debug_options
[] = {
56 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
57 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
62 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
64 unsigned SHADER_DB_COUNT
= 0;
66 int midgard_debug
= 0;
68 #define DBG(fmt, ...) \
69 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
70 fprintf(stderr, "%s:%d: "fmt, \
71 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
74 midgard_is_branch_unit(unsigned unit
)
76 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
79 static midgard_block
*
80 create_empty_block(compiler_context
*ctx
)
82 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
84 blk
->predecessors
= _mesa_set_create(blk
,
86 _mesa_key_pointer_equal
);
88 blk
->source_id
= ctx
->block_source_count
++;
94 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
100 for (unsigned i
= 0; i
< block
->nr_successors
; ++i
) {
101 if (block
->successors
[i
] == successor
)
105 block
->successors
[block
->nr_successors
++] = successor
;
106 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
108 /* Note the predecessor in the other direction */
109 _mesa_set_add(successor
->predecessors
, block
);
113 schedule_barrier(compiler_context
*ctx
)
115 midgard_block
*temp
= ctx
->after_block
;
116 ctx
->after_block
= create_empty_block(ctx
);
118 list_addtail(&ctx
->after_block
->link
, &ctx
->blocks
);
119 list_inithead(&ctx
->after_block
->instructions
);
120 midgard_block_add_successor(ctx
->current_block
, ctx
->after_block
);
121 ctx
->current_block
= ctx
->after_block
;
122 ctx
->after_block
= temp
;
125 /* Helpers to generate midgard_instruction's using macro magic, since every
126 * driver seems to do it that way */
128 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
130 #define M_LOAD_STORE(name, store) \
131 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
132 midgard_instruction i = { \
133 .type = TAG_LOAD_STORE_4, \
136 .src = { ~0, ~0, ~0, ~0 }, \
137 .swizzle = SWIZZLE_IDENTITY_4, \
139 .op = midgard_op_##name, \
152 #define M_LOAD(name) M_LOAD_STORE(name, false)
153 #define M_STORE(name) M_LOAD_STORE(name, true)
155 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
156 * the corresponding Midgard source */
158 static midgard_vector_alu_src
159 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
160 bool half
, bool sext
)
162 /* Figure out how many components there are so we can adjust.
163 * Specifically we want to broadcast the last channel so things like
167 if (broadcast_count
&& src
) {
168 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
170 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
171 src
->swizzle
[c
] = last_component
;
175 midgard_vector_alu_src alu_src
= {
182 alu_src
.mod
= midgard_int_normal
;
184 /* Sign/zero-extend if needed */
188 midgard_int_sign_extend
189 : midgard_int_zero_extend
;
192 /* These should have been lowered away */
194 assert(!(src
->abs
|| src
->negate
));
197 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
203 /* load/store instructions have both 32-bit and 16-bit variants, depending on
204 * whether we are using vectors composed of highp or mediump. At the moment, we
205 * don't support half-floats -- this requires changes in other parts of the
206 * compiler -- therefore the 16-bit versions are commented out. */
208 //M_LOAD(ld_attr_16);
210 //M_LOAD(ld_vary_16);
215 M_LOAD(ld_color_buffer_8
);
216 //M_STORE(st_vary_16);
218 M_LOAD(ld_cubemap_coords
);
219 M_LOAD(ld_compute_id
);
221 static midgard_instruction
222 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
224 midgard_branch_cond branch
= {
232 memcpy(&compact
, &branch
, sizeof(branch
));
234 midgard_instruction ins
= {
236 .unit
= ALU_ENAB_BR_COMPACT
,
237 .prepacked_branch
= true,
238 .compact_branch
= true,
239 .br_compact
= compact
,
241 .src
= { ~0, ~0, ~0, ~0 },
244 if (op
== midgard_jmp_writeout_op_writeout
)
250 static midgard_instruction
251 v_branch(bool conditional
, bool invert
)
253 midgard_instruction ins
= {
255 .unit
= ALU_ENAB_BRANCH
,
256 .compact_branch
= true,
258 .conditional
= conditional
,
259 .invert_conditional
= invert
262 .src
= { ~0, ~0, ~0, ~0 },
268 static midgard_branch_extended
269 midgard_create_branch_extended( midgard_condition cond
,
270 midgard_jmp_writeout_op op
,
272 signed quadword_offset
)
274 /* The condition code is actually a LUT describing a function to
275 * combine multiple condition codes. However, we only support a single
276 * condition code at the moment, so we just duplicate over a bunch of
279 uint16_t duplicated_cond
=
289 midgard_branch_extended branch
= {
291 .dest_tag
= dest_tag
,
292 .offset
= quadword_offset
,
293 .cond
= duplicated_cond
300 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
302 ins
->has_constants
= true;
303 memcpy(&ins
->constants
, constants
, 16);
307 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
309 return glsl_count_attribute_slots(type
, false);
312 /* Lower fdot2 to a vector multiplication followed by channel addition */
314 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
316 if (alu
->op
!= nir_op_fdot2
)
319 b
->cursor
= nir_before_instr(&alu
->instr
);
321 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
322 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
324 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
326 nir_ssa_def
*sum
= nir_fadd(b
,
327 nir_channel(b
, product
, 0),
328 nir_channel(b
, product
, 1));
330 /* Replace the fdot2 with this sum */
331 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
335 midgard_sysval_for_ssbo(nir_intrinsic_instr
*instr
)
337 /* This is way too meta */
338 bool is_store
= instr
->intrinsic
== nir_intrinsic_store_ssbo
;
339 unsigned idx_idx
= is_store
? 1 : 0;
341 nir_src index
= instr
->src
[idx_idx
];
342 assert(nir_src_is_const(index
));
343 uint32_t uindex
= nir_src_as_uint(index
);
345 return PAN_SYSVAL(SSBO
, uindex
);
349 midgard_sysval_for_sampler(nir_intrinsic_instr
*instr
)
351 /* TODO: indirect samplers !!! */
352 nir_src index
= instr
->src
[0];
353 assert(nir_src_is_const(index
));
354 uint32_t uindex
= nir_src_as_uint(index
);
356 return PAN_SYSVAL(SAMPLER
, uindex
);
360 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
362 switch (instr
->intrinsic
) {
363 case nir_intrinsic_load_viewport_scale
:
364 return PAN_SYSVAL_VIEWPORT_SCALE
;
365 case nir_intrinsic_load_viewport_offset
:
366 return PAN_SYSVAL_VIEWPORT_OFFSET
;
367 case nir_intrinsic_load_num_work_groups
:
368 return PAN_SYSVAL_NUM_WORK_GROUPS
;
369 case nir_intrinsic_load_ssbo
:
370 case nir_intrinsic_store_ssbo
:
371 return midgard_sysval_for_ssbo(instr
);
372 case nir_intrinsic_load_sampler_lod_parameters_pan
:
373 return midgard_sysval_for_sampler(instr
);
379 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
382 nir_intrinsic_instr
*intr
;
383 nir_dest
*dst
= NULL
;
387 bool is_store
= false;
389 switch (instr
->type
) {
390 case nir_instr_type_intrinsic
:
391 intr
= nir_instr_as_intrinsic(instr
);
392 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
394 is_store
|= intr
->intrinsic
== nir_intrinsic_store_ssbo
;
396 case nir_instr_type_tex
:
397 tex
= nir_instr_as_tex(instr
);
398 if (tex
->op
!= nir_texop_txs
)
401 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
402 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
403 nir_tex_instr_dest_size(tex
) -
404 (tex
->is_array
? 1 : 0),
412 if (dest
&& dst
&& !is_store
)
413 *dest
= nir_dest_index(ctx
, dst
);
419 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
423 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
427 /* We have a sysval load; check if it's already been assigned */
429 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
432 /* It hasn't -- so assign it now! */
434 unsigned id
= ctx
->sysval_count
++;
435 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
436 ctx
->sysvals
[id
] = sysval
;
440 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
442 ctx
->sysval_count
= 0;
444 nir_foreach_function(function
, shader
) {
445 if (!function
->impl
) continue;
447 nir_foreach_block(block
, function
->impl
) {
448 nir_foreach_instr_safe(instr
, block
) {
449 midgard_nir_assign_sysval_body(ctx
, instr
);
456 midgard_nir_lower_fdot2(nir_shader
*shader
)
458 bool progress
= false;
460 nir_foreach_function(function
, shader
) {
461 if (!function
->impl
) continue;
464 nir_builder
*b
= &_b
;
465 nir_builder_init(b
, function
->impl
);
467 nir_foreach_block(block
, function
->impl
) {
468 nir_foreach_instr_safe(instr
, block
) {
469 if (instr
->type
!= nir_instr_type_alu
) continue;
471 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
472 midgard_nir_lower_fdot2_body(b
, alu
);
478 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
485 /* Flushes undefined values to zero */
488 optimise_nir(nir_shader
*nir
, unsigned quirks
)
491 unsigned lower_flrp
=
492 (nir
->options
->lower_flrp16
? 16 : 0) |
493 (nir
->options
->lower_flrp32
? 32 : 0) |
494 (nir
->options
->lower_flrp64
? 64 : 0);
496 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
497 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
499 nir_lower_tex_options lower_tex_options
= {
500 .lower_txs_lod
= true,
502 .lower_tex_without_implicit_lod
=
503 (quirks
& MIDGARD_EXPLICIT_LOD
),
505 /* TODO: we have native gradient.. */
509 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
511 /* Must lower fdot2 after tex is lowered */
512 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
514 /* T720 is broken. */
516 if (quirks
& MIDGARD_BROKEN_LOD
)
517 NIR_PASS_V(nir
, midgard_nir_lod_errata
);
522 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
523 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
525 NIR_PASS(progress
, nir
, nir_copy_prop
);
526 NIR_PASS(progress
, nir
, nir_opt_dce
);
527 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
528 NIR_PASS(progress
, nir
, nir_opt_cse
);
529 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
530 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
531 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
533 if (lower_flrp
!= 0) {
534 bool lower_flrp_progress
= false;
535 NIR_PASS(lower_flrp_progress
,
539 false /* always_precise */,
540 nir
->options
->lower_ffma
);
541 if (lower_flrp_progress
) {
542 NIR_PASS(progress
, nir
,
543 nir_opt_constant_folding
);
547 /* Nothing should rematerialize any flrps, so we only
548 * need to do this lowering once.
553 NIR_PASS(progress
, nir
, nir_opt_undef
);
554 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
556 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
559 nir_var_function_temp
);
561 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
564 /* Must be run at the end to prevent creation of fsin/fcos ops */
565 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
570 NIR_PASS(progress
, nir
, nir_opt_dce
);
571 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
572 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
573 NIR_PASS(progress
, nir
, nir_copy_prop
);
576 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
578 /* We implement booleans as 32-bit 0/~0 */
579 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
581 /* Now that booleans are lowered, we can run out late opts */
582 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
584 /* Lower mods for float ops only. Integer ops don't support modifiers
585 * (saturate doesn't make sense on integers, neg/abs require dedicated
588 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
589 NIR_PASS(progress
, nir
, nir_copy_prop
);
590 NIR_PASS(progress
, nir
, nir_opt_dce
);
592 /* Take us out of SSA */
593 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
594 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
596 /* We are a vector architecture; write combine where possible */
597 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
598 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
600 NIR_PASS(progress
, nir
, nir_opt_dce
);
603 /* Do not actually emit a load; instead, cache the constant for inlining */
606 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
608 nir_ssa_def def
= instr
->def
;
610 float *v
= rzalloc_array(NULL
, float, 4);
611 nir_const_value_to_array(v
, instr
->value
, instr
->def
.num_components
, f32
);
613 /* Shifted for SSA, +1 for off-by-one */
614 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, v
);
617 /* Normally constants are embedded implicitly, but for I/O and such we have to
618 * explicitly emit a move with the constant source */
621 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
623 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
625 if (constant_value
) {
626 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), to
);
627 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
628 emit_mir_instruction(ctx
, ins
);
633 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
635 unsigned comp
= src
->swizzle
[0];
637 for (unsigned c
= 1; c
< nr_components
; ++c
) {
638 if (src
->swizzle
[c
] != comp
)
645 #define ALU_CASE(nir, _op) \
647 op = midgard_alu_op_##_op; \
648 assert(src_bitsize == dst_bitsize); \
651 #define ALU_CASE_BCAST(nir, _op, count) \
653 op = midgard_alu_op_##_op; \
654 broadcast_swizzle = count; \
655 assert(src_bitsize == dst_bitsize); \
658 nir_is_fzero_constant(nir_src src
)
660 if (!nir_src_is_const(src
))
663 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
664 if (nir_src_comp_as_float(src
, c
) != 0.0)
671 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
672 * special treatment override this anyway. */
674 static midgard_reg_mode
675 reg_mode_for_nir(nir_alu_instr
*instr
)
677 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
679 switch (src_bitsize
) {
681 return midgard_reg_mode_8
;
683 return midgard_reg_mode_16
;
685 return midgard_reg_mode_32
;
687 return midgard_reg_mode_64
;
689 unreachable("Invalid bit size");
694 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
696 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
697 * is handled elsewhere */
699 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
700 midgard_emit_derivatives(ctx
, instr
);
704 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
706 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
707 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
708 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
710 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
711 * supported. A few do not and are commented for now. Also, there are a
712 * number of NIR ops which Midgard does not support and need to be
713 * lowered, also TODO. This switch block emits the opcode and calling
714 * convention of the Midgard instruction; actual packing is done in
719 /* Number of components valid to check for the instruction (the rest
720 * will be forced to the last), or 0 to use as-is. Relevant as
721 * ball-type instructions have a channel count in NIR but are all vec4
724 unsigned broadcast_swizzle
= 0;
726 /* What register mode should we operate in? */
727 midgard_reg_mode reg_mode
=
728 reg_mode_for_nir(instr
);
730 /* Do we need a destination override? Used for inline
733 midgard_dest_override dest_override
=
734 midgard_dest_override_none
;
736 /* Should we use a smaller respective source and sign-extend? */
738 bool half_1
= false, sext_1
= false;
739 bool half_2
= false, sext_2
= false;
741 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
742 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
745 ALU_CASE(fadd
, fadd
);
746 ALU_CASE(fmul
, fmul
);
747 ALU_CASE(fmin
, fmin
);
748 ALU_CASE(fmax
, fmax
);
749 ALU_CASE(imin
, imin
);
750 ALU_CASE(imax
, imax
);
751 ALU_CASE(umin
, umin
);
752 ALU_CASE(umax
, umax
);
753 ALU_CASE(ffloor
, ffloor
);
754 ALU_CASE(fround_even
, froundeven
);
755 ALU_CASE(ftrunc
, ftrunc
);
756 ALU_CASE(fceil
, fceil
);
757 ALU_CASE(fdot3
, fdot3
);
758 ALU_CASE(fdot4
, fdot4
);
759 ALU_CASE(iadd
, iadd
);
760 ALU_CASE(isub
, isub
);
761 ALU_CASE(imul
, imul
);
763 /* Zero shoved as second-arg */
764 ALU_CASE(iabs
, iabsdiff
);
768 ALU_CASE(feq32
, feq
);
769 ALU_CASE(fne32
, fne
);
770 ALU_CASE(flt32
, flt
);
771 ALU_CASE(ieq32
, ieq
);
772 ALU_CASE(ine32
, ine
);
773 ALU_CASE(ilt32
, ilt
);
774 ALU_CASE(ult32
, ult
);
776 /* We don't have a native b2f32 instruction. Instead, like many
777 * GPUs, we exploit booleans as 0/~0 for false/true, and
778 * correspondingly AND
779 * by 1.0 to do the type conversion. For the moment, prime us
782 * iand [whatever], #0
784 * At the end of emit_alu (as MIR), we'll fix-up the constant
787 ALU_CASE(b2f32
, iand
);
788 ALU_CASE(b2i32
, iand
);
790 /* Likewise, we don't have a dedicated f2b32 instruction, but
791 * we can do a "not equal to 0.0" test. */
793 ALU_CASE(f2b32
, fne
);
794 ALU_CASE(i2b32
, ine
);
796 ALU_CASE(frcp
, frcp
);
797 ALU_CASE(frsq
, frsqrt
);
798 ALU_CASE(fsqrt
, fsqrt
);
799 ALU_CASE(fexp2
, fexp2
);
800 ALU_CASE(flog2
, flog2
);
802 ALU_CASE(f2i32
, f2i_rtz
);
803 ALU_CASE(f2u32
, f2u_rtz
);
804 ALU_CASE(i2f32
, i2f_rtz
);
805 ALU_CASE(u2f32
, u2f_rtz
);
807 ALU_CASE(f2i16
, f2i_rtz
);
808 ALU_CASE(f2u16
, f2u_rtz
);
809 ALU_CASE(i2f16
, i2f_rtz
);
810 ALU_CASE(u2f16
, u2f_rtz
);
812 ALU_CASE(fsin
, fsin
);
813 ALU_CASE(fcos
, fcos
);
815 /* We'll set invert */
816 ALU_CASE(inot
, imov
);
817 ALU_CASE(iand
, iand
);
819 ALU_CASE(ixor
, ixor
);
820 ALU_CASE(ishl
, ishl
);
821 ALU_CASE(ishr
, iasr
);
822 ALU_CASE(ushr
, ilsr
);
824 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
825 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
826 ALU_CASE(b32all_fequal4
, fball_eq
);
828 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
829 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
830 ALU_CASE(b32any_fnequal4
, fbany_neq
);
832 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
833 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
834 ALU_CASE(b32all_iequal4
, iball_eq
);
836 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
837 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
838 ALU_CASE(b32any_inequal4
, ibany_neq
);
840 /* Source mods will be shoved in later */
841 ALU_CASE(fabs
, fmov
);
842 ALU_CASE(fneg
, fmov
);
843 ALU_CASE(fsat
, fmov
);
845 /* For size conversion, we use a move. Ideally though we would squash
846 * these ops together; maybe that has to happen after in NIR as part of
847 * propagation...? An earlier algebraic pass ensured we step down by
848 * only / exactly one size. If stepping down, we use a dest override to
849 * reduce the size; if stepping up, we use a larger-sized move with a
850 * half source and a sign/zero-extension modifier */
856 /* If we end up upscale, we'll need a sign-extend on the
857 * operand (the second argument) */
865 op
= midgard_alu_op_imov
;
867 if (dst_bitsize
== (src_bitsize
* 2)) {
871 /* Use a greater register mode */
873 } else if (src_bitsize
== (dst_bitsize
* 2)) {
874 /* Converting down */
875 dest_override
= midgard_dest_override_lower
;
882 assert(src_bitsize
== 32);
884 op
= midgard_alu_op_fmov
;
885 dest_override
= midgard_dest_override_lower
;
890 assert(src_bitsize
== 16);
892 op
= midgard_alu_op_fmov
;
899 /* For greater-or-equal, we lower to less-or-equal and flip the
907 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
908 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
909 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
910 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
913 /* Swap via temporary */
914 nir_alu_src temp
= instr
->src
[1];
915 instr
->src
[1] = instr
->src
[0];
916 instr
->src
[0] = temp
;
921 case nir_op_b32csel
: {
922 /* Midgard features both fcsel and icsel, depending on
923 * the type of the arguments/output. However, as long
924 * as we're careful we can _always_ use icsel and
925 * _never_ need fcsel, since the latter does additional
926 * floating-point-specific processing whereas the
927 * former just moves bits on the wire. It's not obvious
928 * why these are separate opcodes, save for the ability
929 * to do things like sat/pos/abs/neg for free */
931 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
932 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
934 /* The condition is the first argument; move the other
935 * arguments up one to be a binary instruction for
936 * Midgard with the condition last */
938 nir_alu_src temp
= instr
->src
[2];
940 instr
->src
[2] = instr
->src
[0];
941 instr
->src
[0] = instr
->src
[1];
942 instr
->src
[1] = temp
;
948 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
953 /* Midgard can perform certain modifiers on output of an ALU op */
956 if (midgard_is_integer_out_op(op
)) {
957 outmod
= midgard_outmod_int_wrap
;
959 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
960 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
963 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
965 if (instr
->op
== nir_op_fmax
) {
966 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
967 op
= midgard_alu_op_fmov
;
969 outmod
= midgard_outmod_pos
;
970 instr
->src
[0] = instr
->src
[1];
971 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
972 op
= midgard_alu_op_fmov
;
974 outmod
= midgard_outmod_pos
;
978 /* Fetch unit, quirks, etc information */
979 unsigned opcode_props
= alu_opcode_props
[op
].props
;
980 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
982 /* src0 will always exist afaik, but src1 will not for 1-argument
983 * instructions. The latter can only be fetched if the instruction
984 * needs it, or else we may segfault. */
986 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
987 unsigned src1
= nr_inputs
>= 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : ~0;
988 unsigned src2
= nr_inputs
== 3 ? nir_alu_src_index(ctx
, &instr
->src
[2]) : ~0;
989 assert(nr_inputs
<= 3);
991 /* Rather than use the instruction generation helpers, we do it
992 * ourselves here to avoid the mess */
994 midgard_instruction ins
= {
997 quirk_flipped_r24
? ~0 : src0
,
998 quirk_flipped_r24
? src0
: src1
,
1005 nir_alu_src
*nirmods
[3] = { NULL
};
1007 if (nr_inputs
>= 2) {
1008 nirmods
[0] = &instr
->src
[0];
1009 nirmods
[1] = &instr
->src
[1];
1010 } else if (nr_inputs
== 1) {
1011 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1017 nirmods
[2] = &instr
->src
[2];
1019 /* These were lowered to a move, so apply the corresponding mod */
1021 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1022 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
1024 if (instr
->op
== nir_op_fneg
)
1025 s
->negate
= !s
->negate
;
1027 if (instr
->op
== nir_op_fabs
)
1031 bool is_int
= midgard_is_integer_op(op
);
1033 ins
.mask
= mask_of(nr_components
);
1035 midgard_vector_alu alu
= {
1037 .reg_mode
= reg_mode
,
1038 .dest_override
= dest_override
,
1041 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1042 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1045 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1048 ins
.mask
&= instr
->dest
.write_mask
;
1050 for (unsigned m
= 0; m
< 3; ++m
) {
1054 for (unsigned c
= 0; c
< NIR_MAX_VEC_COMPONENTS
; ++c
)
1055 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[c
];
1057 /* Replicate. TODO: remove when vec16 lands */
1058 for (unsigned c
= NIR_MAX_VEC_COMPONENTS
; c
< MIR_VEC_COMPONENTS
; ++c
)
1059 ins
.swizzle
[m
][c
] = nirmods
[m
]->swizzle
[NIR_MAX_VEC_COMPONENTS
- 1];
1062 if (nr_inputs
== 3) {
1063 /* Conditions can't have mods */
1064 assert(!nirmods
[2]->abs
);
1065 assert(!nirmods
[2]->negate
);
1070 /* Late fixup for emulated instructions */
1072 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1073 /* Presently, our second argument is an inline #0 constant.
1074 * Switch over to an embedded 1.0 constant (that can't fit
1075 * inline, since we're 32-bit, not 16-bit like the inline
1078 ins
.has_inline_constant
= false;
1079 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1080 ins
.has_constants
= true;
1082 if (instr
->op
== nir_op_b2f32
) {
1084 memcpy(&ins
.constants
, &f
, sizeof(float));
1086 ins
.constants
[0] = 1;
1090 for (unsigned c
= 0; c
< 16; ++c
)
1091 ins
.swizzle
[1][c
] = 0;
1092 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1093 /* Lots of instructions need a 0 plonked in */
1094 ins
.has_inline_constant
= false;
1095 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1096 ins
.has_constants
= true;
1097 ins
.constants
[0] = 0;
1099 for (unsigned c
= 0; c
< 16; ++c
)
1100 ins
.swizzle
[1][c
] = 0;
1101 } else if (instr
->op
== nir_op_inot
) {
1105 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1106 /* To avoid duplicating the lookup tables (probably), true LUT
1107 * instructions can only operate as if they were scalars. Lower
1108 * them here by changing the component. */
1110 unsigned orig_mask
= ins
.mask
;
1112 for (int i
= 0; i
< nr_components
; ++i
) {
1113 /* Mask the associated component, dropping the
1114 * instruction if needed */
1117 ins
.mask
&= orig_mask
;
1122 for (unsigned j
= 0; j
< MIR_VEC_COMPONENTS
; ++j
)
1123 ins
.swizzle
[0][j
] = nirmods
[0]->swizzle
[i
]; /* Pull from the correct component */
1125 emit_mir_instruction(ctx
, ins
);
1128 emit_mir_instruction(ctx
, ins
);
1135 mir_set_intr_mask(nir_instr
*instr
, midgard_instruction
*ins
, bool is_read
)
1137 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1138 unsigned nir_mask
= 0;
1142 nir_mask
= mask_of(nir_intrinsic_dest_components(intr
));
1143 dsize
= nir_dest_bit_size(intr
->dest
);
1145 nir_mask
= nir_intrinsic_write_mask(intr
);
1149 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1150 unsigned bytemask
= mir_to_bytemask(mir_mode_for_destsize(dsize
), nir_mask
);
1151 mir_set_bytemask(ins
, bytemask
);
1154 ins
->load_64
= true;
1157 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1158 * optimized) versions of UBO #0 */
1160 midgard_instruction
*
1162 compiler_context
*ctx
,
1166 nir_src
*indirect_offset
,
1169 /* TODO: half-floats */
1171 midgard_instruction ins
= m_ld_ubo_int4(dest
, 0);
1172 ins
.constants
[0] = offset
;
1174 if (instr
->type
== nir_instr_type_intrinsic
)
1175 mir_set_intr_mask(instr
, &ins
, true);
1177 if (indirect_offset
) {
1178 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1179 ins
.load_store
.arg_2
= 0x80;
1181 ins
.load_store
.arg_2
= 0x1E;
1184 ins
.load_store
.arg_1
= index
;
1186 return emit_mir_instruction(ctx
, ins
);
1189 /* SSBO reads are like UBO reads if you squint */
1193 compiler_context
*ctx
,
1198 nir_src
*indirect_offset
,
1203 midgard_instruction ins
;
1206 ins
= m_ld_int4(srcdest
, offset
);
1208 ins
= m_st_int4(srcdest
, offset
);
1210 /* SSBO reads use a generic memory read interface, so we need the
1211 * address of the SSBO as the first argument. This is a sysval. */
1213 unsigned addr
= make_compiler_temp(ctx
);
1214 emit_sysval_read(ctx
, instr
, addr
, 2);
1216 /* The source array:
1218 * src[0] = store ? value : unused
1222 * We would like arg_1 = the address and
1223 * arg_2 = the offset.
1228 /* TODO: What is this? It looks superficially like a shift << 5, but
1229 * arg_1 doesn't take a shift Should it be E0 or A0? We also need the
1230 * indirect offset. */
1232 if (indirect_offset
) {
1233 ins
.load_store
.arg_1
|= 0xE0;
1234 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1236 ins
.load_store
.arg_2
= 0x7E;
1239 /* TODO: Bounds check */
1241 /* Finally, we emit the direct offset */
1243 ins
.load_store
.varying_parameters
= (offset
& 0x1FF) << 1;
1244 ins
.load_store
.address
= (offset
>> 9);
1245 mir_set_intr_mask(instr
, &ins
, is_read
);
1247 emit_mir_instruction(ctx
, ins
);
1252 compiler_context
*ctx
,
1253 unsigned dest
, unsigned offset
,
1254 unsigned nr_comp
, unsigned component
,
1255 nir_src
*indirect_offset
, nir_alu_type type
)
1257 /* XXX: Half-floats? */
1258 /* TODO: swizzle, mask */
1260 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1261 ins
.mask
= mask_of(nr_comp
);
1263 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
)
1264 ins
.swizzle
[0][i
] = MIN2(i
+ component
, COMPONENT_W
);
1266 midgard_varying_parameter p
= {
1268 .interpolation
= midgard_interp_default
,
1269 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1273 memcpy(&u
, &p
, sizeof(p
));
1274 ins
.load_store
.varying_parameters
= u
;
1276 if (indirect_offset
)
1277 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1279 ins
.load_store
.arg_2
= 0x1E;
1281 ins
.load_store
.arg_1
= 0x9E;
1283 /* Use the type appropriate load */
1287 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1290 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1292 case nir_type_float
:
1293 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1296 unreachable("Attempted to load unknown type");
1300 emit_mir_instruction(ctx
, ins
);
1304 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
, signed dest_override
,
1305 unsigned nr_components
)
1309 /* Figure out which uniform this is */
1310 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1311 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1313 if (dest_override
>= 0)
1314 dest
= dest_override
;
1316 /* Sysvals are prefix uniforms */
1317 unsigned uniform
= ((uintptr_t) val
) - 1;
1319 /* Emit the read itself -- this is never indirect */
1320 midgard_instruction
*ins
=
1321 emit_ubo_read(ctx
, instr
, dest
, uniform
* 16, NULL
, 0);
1323 ins
->mask
= mask_of(nr_components
);
1327 compute_builtin_arg(nir_op op
)
1330 case nir_intrinsic_load_work_group_id
:
1332 case nir_intrinsic_load_local_invocation_id
:
1335 unreachable("Invalid compute paramater loaded");
1339 /* Emit store for a fragment shader, which is encoded via a fancy branch. TODO:
1340 * Handle MRT here */
1342 emit_fragment_epilogue(compiler_context
*ctx
, unsigned rt
);
1345 emit_fragment_store(compiler_context
*ctx
, unsigned src
, unsigned rt
)
1347 emit_explicit_constant(ctx
, src
, src
);
1349 struct midgard_instruction ins
=
1350 v_alu_br_compact_cond(midgard_jmp_writeout_op_writeout
, TAG_ALU_8
, 0, midgard_condition_always
);
1352 /* Add dependencies */
1354 ins
.constants
[0] = rt
* 0x100;
1356 /* Emit the branch */
1357 emit_mir_instruction(ctx
, ins
);
1358 schedule_barrier(ctx
);
1360 emit_fragment_epilogue(ctx
, rt
);
1364 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1366 unsigned reg
= nir_dest_index(ctx
, &instr
->dest
);
1367 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1368 ins
.mask
= mask_of(3);
1369 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1370 emit_mir_instruction(ctx
, ins
);
1373 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1375 unsigned offset
= 0, reg
;
1377 switch (instr
->intrinsic
) {
1378 case nir_intrinsic_discard_if
:
1379 case nir_intrinsic_discard
: {
1380 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1381 struct midgard_instruction discard
= v_branch(conditional
, false);
1382 discard
.branch
.target_type
= TARGET_DISCARD
;
1385 discard
.src
[0] = nir_src_index(ctx
, &instr
->src
[0]);
1387 emit_mir_instruction(ctx
, discard
);
1388 schedule_barrier(ctx
);
1393 case nir_intrinsic_load_uniform
:
1394 case nir_intrinsic_load_ubo
:
1395 case nir_intrinsic_load_ssbo
:
1396 case nir_intrinsic_load_input
: {
1397 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1398 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1399 bool is_ssbo
= instr
->intrinsic
== nir_intrinsic_load_ssbo
;
1401 /* Get the base type of the intrinsic */
1402 /* TODO: Infer type? Does it matter? */
1404 (is_ubo
|| is_ssbo
) ? nir_type_uint
: nir_intrinsic_type(instr
);
1405 t
= nir_alu_type_get_base_type(t
);
1407 if (!(is_ubo
|| is_ssbo
)) {
1408 offset
= nir_intrinsic_base(instr
);
1411 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1413 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1415 bool direct
= nir_src_is_const(*src_offset
);
1416 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1419 offset
+= nir_src_as_uint(*src_offset
);
1421 /* We may need to apply a fractional offset */
1422 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1423 nir_intrinsic_component(instr
) : 0;
1424 reg
= nir_dest_index(ctx
, &instr
->dest
);
1426 if (is_uniform
&& !ctx
->is_blend
) {
1427 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysval_count
+ offset
) * 16, indirect_offset
, 0);
1428 } else if (is_ubo
) {
1429 nir_src index
= instr
->src
[0];
1431 /* We don't yet support indirect UBOs. For indirect
1432 * block numbers (if that's possible), we don't know
1433 * enough about the hardware yet. For indirect sources,
1434 * we know what we need but we need to add some NIR
1435 * support for lowering correctly with respect to
1438 assert(nir_src_is_const(index
));
1439 assert(nir_src_is_const(*src_offset
));
1441 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1442 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, NULL
, uindex
);
1443 } else if (is_ssbo
) {
1444 nir_src index
= instr
->src
[0];
1445 assert(nir_src_is_const(index
));
1446 uint32_t uindex
= nir_src_as_uint(index
);
1448 emit_ssbo_access(ctx
, &instr
->instr
, true, reg
, offset
, indirect_offset
, uindex
);
1449 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1450 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
, t
);
1451 } else if (ctx
->is_blend
) {
1452 /* For blend shaders, load the input color, which is
1453 * preloaded to r0 */
1455 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), reg
);
1456 emit_mir_instruction(ctx
, move
);
1457 schedule_barrier(ctx
);
1458 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1459 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1460 ins
.load_store
.arg_1
= 0x1E;
1461 ins
.load_store
.arg_2
= 0x1E;
1462 ins
.mask
= mask_of(nr_comp
);
1464 /* Use the type appropriate load */
1468 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1471 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1473 case nir_type_float
:
1474 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1477 unreachable("Attempted to load unknown type");
1481 emit_mir_instruction(ctx
, ins
);
1483 DBG("Unknown load\n");
1490 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1492 case nir_intrinsic_load_raw_output_pan
:
1493 case nir_intrinsic_load_output_u8_as_fp16_pan
:
1494 reg
= nir_dest_index(ctx
, &instr
->dest
);
1495 assert(ctx
->is_blend
);
1497 /* T720 and below use different blend opcodes with slightly
1498 * different semantics than T760 and up */
1500 midgard_instruction ld
= m_ld_color_buffer_8(reg
, 0);
1501 bool old_blend
= ctx
->quirks
& MIDGARD_OLD_BLEND
;
1503 if (instr
->intrinsic
== nir_intrinsic_load_output_u8_as_fp16_pan
) {
1504 ld
.load_store
.op
= old_blend
?
1505 midgard_op_ld_color_buffer_u8_as_fp16_old
:
1506 midgard_op_ld_color_buffer_u8_as_fp16
;
1509 ld
.load_store
.address
= 1;
1510 ld
.load_store
.arg_2
= 0x1E;
1513 for (unsigned c
= 2; c
< 16; ++c
)
1514 ld
.swizzle
[0][c
] = 0;
1517 emit_mir_instruction(ctx
, ld
);
1520 case nir_intrinsic_load_blend_const_color_rgba
: {
1521 assert(ctx
->is_blend
);
1522 reg
= nir_dest_index(ctx
, &instr
->dest
);
1524 /* Blend constants are embedded directly in the shader and
1525 * patched in, so we use some magic routing */
1527 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), reg
);
1528 ins
.has_constants
= true;
1529 ins
.has_blend_constant
= true;
1530 emit_mir_instruction(ctx
, ins
);
1534 case nir_intrinsic_store_output
:
1535 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1537 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1539 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1541 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1542 /* Determine number of render targets */
1543 emit_fragment_store(ctx
, reg
, offset
);
1544 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1545 /* We should have been vectorized, though we don't
1546 * currently check that st_vary is emitted only once
1547 * per slot (this is relevant, since there's not a mask
1548 * parameter available on the store [set to 0 by the
1549 * blob]). We do respect the component by adjusting the
1550 * swizzle. If this is a constant source, we'll need to
1551 * emit that explicitly. */
1553 emit_explicit_constant(ctx
, reg
, reg
);
1555 unsigned component
= nir_intrinsic_component(instr
);
1556 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1558 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1559 st
.load_store
.arg_1
= 0x9E;
1560 st
.load_store
.arg_2
= 0x1E;
1562 for (unsigned i
= 0; i
< ARRAY_SIZE(st
.swizzle
[0]); ++i
)
1563 st
.swizzle
[0][i
] = MIN2(i
+ component
, nr_comp
);
1565 emit_mir_instruction(ctx
, st
);
1567 DBG("Unknown store\n");
1573 /* Special case of store_output for lowered blend shaders */
1574 case nir_intrinsic_store_raw_output_pan
:
1575 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1576 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1578 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1579 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1580 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1583 * imov r0.xyzw, r0.xxxx
1586 unsigned expanded
= make_compiler_temp(ctx
);
1588 midgard_instruction splatter
= v_mov(reg
, expanded
);
1590 for (unsigned c
= 0; c
< 16; ++c
)
1591 splatter
.swizzle
[1][c
] = 0;
1593 emit_mir_instruction(ctx
, splatter
);
1594 emit_fragment_store(ctx
, expanded
, ctx
->blend_rt
);
1596 emit_fragment_store(ctx
, reg
, ctx
->blend_rt
);
1600 case nir_intrinsic_store_ssbo
:
1601 assert(nir_src_is_const(instr
->src
[1]));
1603 bool direct_offset
= nir_src_is_const(instr
->src
[2]);
1604 offset
= direct_offset
? nir_src_as_uint(instr
->src
[2]) : 0;
1605 nir_src
*indirect_offset
= direct_offset
? NULL
: &instr
->src
[2];
1606 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1608 uint32_t uindex
= nir_src_as_uint(instr
->src
[1]);
1610 emit_explicit_constant(ctx
, reg
, reg
);
1611 emit_ssbo_access(ctx
, &instr
->instr
, false, reg
, offset
, indirect_offset
, uindex
);
1614 case nir_intrinsic_load_viewport_scale
:
1615 case nir_intrinsic_load_viewport_offset
:
1616 case nir_intrinsic_load_num_work_groups
:
1617 case nir_intrinsic_load_sampler_lod_parameters_pan
:
1618 emit_sysval_read(ctx
, &instr
->instr
, ~0, 3);
1621 case nir_intrinsic_load_work_group_id
:
1622 case nir_intrinsic_load_local_invocation_id
:
1623 emit_compute_builtin(ctx
, instr
);
1627 printf ("Unhandled intrinsic\n");
1634 midgard_tex_format(enum glsl_sampler_dim dim
)
1637 case GLSL_SAMPLER_DIM_1D
:
1638 case GLSL_SAMPLER_DIM_BUF
:
1641 case GLSL_SAMPLER_DIM_2D
:
1642 case GLSL_SAMPLER_DIM_EXTERNAL
:
1643 case GLSL_SAMPLER_DIM_RECT
:
1646 case GLSL_SAMPLER_DIM_3D
:
1649 case GLSL_SAMPLER_DIM_CUBE
:
1650 return MALI_TEX_CUBE
;
1653 DBG("Unknown sampler dim type\n");
1659 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1663 pan_attach_constant_bias(
1664 compiler_context
*ctx
,
1666 midgard_texture_word
*word
)
1668 /* To attach as constant, it has to *be* constant */
1670 if (!nir_src_is_const(lod
))
1673 float f
= nir_src_as_float(lod
);
1675 /* Break into fixed-point */
1677 float lod_frac
= f
- lod_int
;
1679 /* Carry over negative fractions */
1680 if (lod_frac
< 0.0) {
1686 word
->bias
= float_to_ubyte(lod_frac
);
1687 word
->bias_int
= lod_int
;
1692 static enum mali_sampler_type
1693 midgard_sampler_type(nir_alu_type t
) {
1694 switch (nir_alu_type_get_base_type(t
))
1696 case nir_type_float
:
1697 return MALI_SAMPLER_FLOAT
;
1699 return MALI_SAMPLER_SIGNED
;
1701 return MALI_SAMPLER_UNSIGNED
;
1703 unreachable("Unknown sampler type");
1708 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1709 unsigned midgard_texop
)
1712 //assert (!instr->sampler);
1713 //assert (!instr->texture_array_size);
1715 int texture_index
= instr
->texture_index
;
1716 int sampler_index
= texture_index
;
1718 /* No helper to build texture words -- we do it all here */
1719 midgard_instruction ins
= {
1720 .type
= TAG_TEXTURE_4
,
1722 .dest
= nir_dest_index(ctx
, &instr
->dest
),
1723 .src
= { ~0, ~0, ~0, ~0 },
1724 .swizzle
= SWIZZLE_IDENTITY_4
,
1726 .op
= midgard_texop
,
1727 .format
= midgard_tex_format(instr
->sampler_dim
),
1728 .texture_handle
= texture_index
,
1729 .sampler_handle
= sampler_index
,
1735 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1736 .shadow
= instr
->is_shadow
,
1740 /* We may need a temporary for the coordinate */
1742 bool needs_temp_coord
=
1743 (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) ||
1746 unsigned coords
= needs_temp_coord
? make_compiler_temp_reg(ctx
) : 0;
1748 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1749 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1750 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
1752 switch (instr
->src
[i
].src_type
) {
1753 case nir_tex_src_coord
: {
1754 emit_explicit_constant(ctx
, index
, index
);
1756 if (needs_temp_coord
) {
1757 /* mov coord_temp, coords */
1758 midgard_instruction mov
= v_mov(index
, coords
);
1760 emit_mir_instruction(ctx
, mov
);
1765 /* Texelfetch coordinates uses all four elements
1766 * (xyz/index) regardless of texture dimensionality,
1767 * which means it's necessary to zero the unused
1768 * components to keep everything happy */
1770 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1771 /* mov index.zw, #0 */
1772 midgard_instruction mov
=
1773 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), coords
);
1774 mov
.has_constants
= true;
1775 mov
.mask
= (1 << COMPONENT_Z
) | (1 << COMPONENT_W
);
1776 emit_mir_instruction(ctx
, mov
);
1779 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1780 /* texelFetch is undefined on samplerCube */
1781 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1783 /* For cubemaps, we use a special ld/st op to
1784 * select the face and copy the xy into the
1785 * texture register */
1787 unsigned temp
= make_compiler_temp(ctx
);
1788 midgard_instruction ld
= m_ld_cubemap_coords(temp
, 0);
1790 ld
.mask
= 0x3; /* xy */
1791 ld
.load_store
.arg_1
= 0x20;
1792 ld
.swizzle
[1][3] = COMPONENT_X
;
1793 emit_mir_instruction(ctx
, ld
);
1797 ins
.swizzle
[1][2] = COMPONENT_X
;
1798 ins
.swizzle
[1][3] = COMPONENT_X
;
1800 ins
.src
[1] = coords
;
1803 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1804 /* Array component in w but NIR wants it in z */
1805 if (nr_components
== 3) {
1806 ins
.swizzle
[1][2] = COMPONENT_Z
;
1807 ins
.swizzle
[1][3] = COMPONENT_Z
;
1808 } else if (nr_components
== 2) {
1810 instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
1811 ins
.swizzle
[1][3] = COMPONENT_X
;
1813 unreachable("Invalid texture 2D components");
1819 case nir_tex_src_bias
:
1820 case nir_tex_src_lod
: {
1821 /* Try as a constant if we can */
1823 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1824 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1827 ins
.texture
.lod_register
= true;
1830 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
1831 ins
.swizzle
[2][c
] = COMPONENT_X
;
1833 emit_explicit_constant(ctx
, index
, index
);
1838 case nir_tex_src_offset
: {
1839 ins
.texture
.offset_register
= true;
1842 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
1843 ins
.swizzle
[3][c
] = (c
> COMPONENT_Z
) ? 0 : c
;
1845 emit_explicit_constant(ctx
, index
, index
);
1848 case nir_tex_src_comparator
: {
1849 /* TODO: generalize */
1850 unsigned comp
= COMPONENT_Z
;
1852 /* mov coord_temp.foo, coords */
1853 midgard_instruction mov
= v_mov(index
, coords
);
1854 mov
.mask
= 1 << comp
;
1856 for (unsigned i
= 0; i
< MIR_VEC_COMPONENTS
; ++i
)
1857 mov
.swizzle
[1][i
] = COMPONENT_X
;
1859 emit_mir_instruction(ctx
, mov
);
1864 unreachable("Unknown texture source type\n");
1868 emit_mir_instruction(ctx
, ins
);
1870 /* Used for .cont and .last hinting */
1871 ctx
->texture_op_count
++;
1875 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1877 switch (instr
->op
) {
1880 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1883 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1886 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1889 emit_sysval_read(ctx
, &instr
->instr
, ~0, 4);
1892 unreachable("Unhanlded texture op");
1897 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1899 switch (instr
->type
) {
1900 case nir_jump_break
: {
1901 /* Emit a branch out of the loop */
1902 struct midgard_instruction br
= v_branch(false, false);
1903 br
.branch
.target_type
= TARGET_BREAK
;
1904 br
.branch
.target_break
= ctx
->current_loop_depth
;
1905 emit_mir_instruction(ctx
, br
);
1910 DBG("Unknown jump type %d\n", instr
->type
);
1916 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1918 switch (instr
->type
) {
1919 case nir_instr_type_load_const
:
1920 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1923 case nir_instr_type_intrinsic
:
1924 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1927 case nir_instr_type_alu
:
1928 emit_alu(ctx
, nir_instr_as_alu(instr
));
1931 case nir_instr_type_tex
:
1932 emit_tex(ctx
, nir_instr_as_tex(instr
));
1935 case nir_instr_type_jump
:
1936 emit_jump(ctx
, nir_instr_as_jump(instr
));
1939 case nir_instr_type_ssa_undef
:
1944 DBG("Unhandled instruction type\n");
1950 /* ALU instructions can inline or embed constants, which decreases register
1951 * pressure and saves space. */
1953 #define CONDITIONAL_ATTACH(idx) { \
1954 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
1957 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
1958 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1963 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
1965 mir_foreach_instr_in_block(block
, alu
) {
1966 /* Other instructions cannot inline constants */
1967 if (alu
->type
!= TAG_ALU_4
) continue;
1968 if (alu
->compact_branch
) continue;
1970 /* If there is already a constant here, we can do nothing */
1971 if (alu
->has_constants
) continue;
1973 CONDITIONAL_ATTACH(0);
1975 if (!alu
->has_constants
) {
1976 CONDITIONAL_ATTACH(1)
1977 } else if (!alu
->inline_constant
) {
1978 /* Corner case: _two_ vec4 constants, for instance with a
1979 * csel. For this case, we can only use a constant
1980 * register for one, we'll have to emit a move for the
1981 * other. Note, if both arguments are constants, then
1982 * necessarily neither argument depends on the value of
1983 * any particular register. As the destination register
1984 * will be wiped, that means we can spill the constant
1985 * to the destination register.
1988 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
1989 unsigned scratch
= alu
->dest
;
1992 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), scratch
);
1993 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
1995 /* Set the source */
1996 alu
->src
[1] = scratch
;
1998 /* Inject us -before- the last instruction which set r31 */
1999 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
2005 /* Being a little silly with the names, but returns the op that is the bitwise
2006 * inverse of the op with the argument switched. I.e. (f and g are
2009 * f(a, b) = ~g(b, a)
2011 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
2013 * f(a, b) = ~g(b, a)
2014 * ~f(a, b) = g(b, a)
2015 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
2018 * Thus we define this function in pairs.
2021 static inline midgard_alu_op
2022 mir_contrapositive(midgard_alu_op op
)
2025 case midgard_alu_op_flt
:
2026 return midgard_alu_op_fle
;
2027 case midgard_alu_op_fle
:
2028 return midgard_alu_op_flt
;
2030 case midgard_alu_op_ilt
:
2031 return midgard_alu_op_ile
;
2032 case midgard_alu_op_ile
:
2033 return midgard_alu_op_ilt
;
2036 unreachable("No known contrapositive");
2040 /* Midgard supports two types of constants, embedded constants (128-bit) and
2041 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2042 * constants can be demoted to inline constants, for space savings and
2043 * sometimes a performance boost */
2046 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
2048 mir_foreach_instr_in_block(block
, ins
) {
2049 if (!ins
->has_constants
) continue;
2050 if (ins
->has_inline_constant
) continue;
2052 /* Blend constants must not be inlined by definition */
2053 if (ins
->has_blend_constant
) continue;
2055 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2056 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
2057 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
2059 if (!(is_16
|| is_32
))
2062 /* src1 cannot be an inline constant due to encoding
2063 * restrictions. So, if possible we try to flip the arguments
2066 int op
= ins
->alu
.op
;
2068 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2069 bool flip
= alu_opcode_props
[op
].props
& OP_COMMUTES
;
2072 /* Conditionals can be inverted */
2073 case midgard_alu_op_flt
:
2074 case midgard_alu_op_ilt
:
2075 case midgard_alu_op_fle
:
2076 case midgard_alu_op_ile
:
2077 ins
->alu
.op
= mir_contrapositive(ins
->alu
.op
);
2082 case midgard_alu_op_fcsel
:
2083 case midgard_alu_op_icsel
:
2084 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
2093 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2094 /* Extract the source information */
2096 midgard_vector_alu_src
*src
;
2097 int q
= ins
->alu
.src2
;
2098 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2101 /* Component is from the swizzle. Take a nonzero component */
2103 unsigned first_comp
= ffs(ins
->mask
) - 1;
2104 unsigned component
= ins
->swizzle
[1][first_comp
];
2106 /* Scale constant appropriately, if we can legally */
2107 uint16_t scaled_constant
= 0;
2109 if (midgard_is_integer_op(op
) || is_16
) {
2110 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2111 scaled_constant
= (uint16_t) iconstants
[component
];
2113 /* Constant overflow after resize */
2114 if (scaled_constant
!= iconstants
[component
])
2117 float *f
= (float *) ins
->constants
;
2118 float original
= f
[component
];
2119 scaled_constant
= _mesa_float_to_half(original
);
2121 /* Check for loss of precision. If this is
2122 * mediump, we don't care, but for a highp
2123 * shader, we need to pay attention. NIR
2124 * doesn't yet tell us which mode we're in!
2125 * Practically this prevents most constants
2126 * from being inlined, sadly. */
2128 float fp32
= _mesa_half_to_float(scaled_constant
);
2130 if (fp32
!= original
)
2134 /* We don't know how to handle these with a constant */
2136 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
2137 DBG("Bailing inline constant...\n");
2141 /* Make sure that the constant is not itself a vector
2142 * by checking if all accessed values are the same. */
2144 uint32_t *cons
= ins
->constants
;
2145 uint32_t value
= cons
[component
];
2147 bool is_vector
= false;
2148 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2150 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
2151 /* We only care if this component is actually used */
2152 if (!(mask
& (1 << c
)))
2155 uint32_t test
= cons
[ins
->swizzle
[1][c
]];
2157 if (test
!= value
) {
2166 /* Get rid of the embedded constant */
2167 ins
->has_constants
= false;
2169 ins
->has_inline_constant
= true;
2170 ins
->inline_constant
= scaled_constant
;
2175 /* Dead code elimination for branches at the end of a block - only one branch
2176 * per block is legal semantically */
2179 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2181 bool branched
= false;
2183 mir_foreach_instr_in_block_safe(block
, ins
) {
2184 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2187 mir_remove_instruction(ins
);
2193 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2194 * the move can be propagated away entirely */
2197 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2200 if (comp
== midgard_outmod_none
)
2203 if (*outmod
== midgard_outmod_none
) {
2208 /* TODO: Compose rules */
2213 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2215 bool progress
= false;
2217 mir_foreach_instr_in_block_safe(block
, ins
) {
2218 if (ins
->type
!= TAG_ALU_4
) continue;
2219 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2220 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2222 /* TODO: Registers? */
2223 unsigned src
= ins
->src
[1];
2224 if (src
& IS_REG
) continue;
2226 /* There might be a source modifier, too */
2227 if (mir_nontrivial_source2_mod(ins
)) continue;
2229 /* Backpropagate the modifier */
2230 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2231 if (v
->type
!= TAG_ALU_4
) continue;
2232 if (v
->dest
!= src
) continue;
2234 /* Can we even take a float outmod? */
2235 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2237 midgard_outmod_float temp
= v
->alu
.outmod
;
2238 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2240 /* Throw in the towel.. */
2241 if (!progress
) break;
2243 /* Otherwise, transfer the modifier */
2244 v
->alu
.outmod
= temp
;
2245 ins
->alu
.outmod
= midgard_outmod_none
;
2255 emit_fragment_epilogue(compiler_context
*ctx
, unsigned rt
)
2257 /* Include a move to specify the render target */
2260 midgard_instruction rt_move
= v_mov(SSA_FIXED_REGISTER(1),
2261 SSA_FIXED_REGISTER(1));
2262 rt_move
.mask
= 1 << COMPONENT_Z
;
2263 rt_move
.unit
= UNIT_SADD
;
2264 emit_mir_instruction(ctx
, rt_move
);
2267 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_8
, -2, midgard_condition_always
);
2268 ctx
->current_block
->epilogue
= true;
2269 schedule_barrier(ctx
);
2272 static midgard_block
*
2273 emit_block(compiler_context
*ctx
, nir_block
*block
)
2275 midgard_block
*this_block
= ctx
->after_block
;
2276 ctx
->after_block
= NULL
;
2279 this_block
= create_empty_block(ctx
);
2281 list_addtail(&this_block
->link
, &ctx
->blocks
);
2283 this_block
->is_scheduled
= false;
2286 /* Set up current block */
2287 list_inithead(&this_block
->instructions
);
2288 ctx
->current_block
= this_block
;
2290 nir_foreach_instr(instr
, block
) {
2291 emit_instr(ctx
, instr
);
2292 ++ctx
->instruction_count
;
2298 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2301 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2303 midgard_block
*before_block
= ctx
->current_block
;
2305 /* Speculatively emit the branch, but we can't fill it in until later */
2306 EMIT(branch
, true, true);
2307 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2308 then_branch
->src
[0] = nir_src_index(ctx
, &nif
->condition
);
2310 /* Emit the two subblocks. */
2311 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2312 midgard_block
*end_then_block
= ctx
->current_block
;
2314 /* Emit a jump from the end of the then block to the end of the else */
2315 EMIT(branch
, false, false);
2316 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2318 /* Emit second block, and check if it's empty */
2320 int else_idx
= ctx
->block_count
;
2321 int count_in
= ctx
->instruction_count
;
2322 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2323 midgard_block
*end_else_block
= ctx
->current_block
;
2324 int after_else_idx
= ctx
->block_count
;
2326 /* Now that we have the subblocks emitted, fix up the branches */
2331 if (ctx
->instruction_count
== count_in
) {
2332 /* The else block is empty, so don't emit an exit jump */
2333 mir_remove_instruction(then_exit
);
2334 then_branch
->branch
.target_block
= after_else_idx
;
2336 then_branch
->branch
.target_block
= else_idx
;
2337 then_exit
->branch
.target_block
= after_else_idx
;
2340 /* Wire up the successors */
2342 ctx
->after_block
= create_empty_block(ctx
);
2344 midgard_block_add_successor(before_block
, then_block
);
2345 midgard_block_add_successor(before_block
, else_block
);
2347 midgard_block_add_successor(end_then_block
, ctx
->after_block
);
2348 midgard_block_add_successor(end_else_block
, ctx
->after_block
);
2352 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2354 /* Remember where we are */
2355 midgard_block
*start_block
= ctx
->current_block
;
2357 /* Allocate a loop number, growing the current inner loop depth */
2358 int loop_idx
= ++ctx
->current_loop_depth
;
2360 /* Get index from before the body so we can loop back later */
2361 int start_idx
= ctx
->block_count
;
2363 /* Emit the body itself */
2364 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2366 /* Branch back to loop back */
2367 struct midgard_instruction br_back
= v_branch(false, false);
2368 br_back
.branch
.target_block
= start_idx
;
2369 emit_mir_instruction(ctx
, br_back
);
2371 /* Mark down that branch in the graph. */
2372 midgard_block_add_successor(start_block
, loop_block
);
2373 midgard_block_add_successor(ctx
->current_block
, loop_block
);
2375 /* Find the index of the block about to follow us (note: we don't add
2376 * one; blocks are 0-indexed so we get a fencepost problem) */
2377 int break_block_idx
= ctx
->block_count
;
2379 /* Fix up the break statements we emitted to point to the right place,
2380 * now that we can allocate a block number for them */
2381 ctx
->after_block
= create_empty_block(ctx
);
2383 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2384 mir_foreach_instr_in_block(block
, ins
) {
2385 if (ins
->type
!= TAG_ALU_4
) continue;
2386 if (!ins
->compact_branch
) continue;
2387 if (ins
->prepacked_branch
) continue;
2389 /* We found a branch -- check the type to see if we need to do anything */
2390 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2392 /* It's a break! Check if it's our break */
2393 if (ins
->branch
.target_break
!= loop_idx
) continue;
2395 /* Okay, cool, we're breaking out of this loop.
2396 * Rewrite from a break to a goto */
2398 ins
->branch
.target_type
= TARGET_GOTO
;
2399 ins
->branch
.target_block
= break_block_idx
;
2401 midgard_block_add_successor(block
, ctx
->after_block
);
2405 /* Now that we've finished emitting the loop, free up the depth again
2406 * so we play nice with recursion amid nested loops */
2407 --ctx
->current_loop_depth
;
2409 /* Dump loop stats */
2413 static midgard_block
*
2414 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2416 midgard_block
*start_block
= NULL
;
2418 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2419 switch (node
->type
) {
2420 case nir_cf_node_block
: {
2421 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2424 start_block
= block
;
2429 case nir_cf_node_if
:
2430 emit_if(ctx
, nir_cf_node_as_if(node
));
2433 case nir_cf_node_loop
:
2434 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2437 case nir_cf_node_function
:
2446 /* Due to lookahead, we need to report the first tag executed in the command
2447 * stream and in branch targets. An initial block might be empty, so iterate
2448 * until we find one that 'works' */
2451 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2453 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2455 unsigned first_tag
= 0;
2457 mir_foreach_block_from(ctx
, initial_block
, v
) {
2458 if (v
->quadword_count
) {
2459 midgard_bundle
*initial_bundle
=
2460 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2462 first_tag
= initial_bundle
->tag
;
2471 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
, unsigned blend_rt
, unsigned gpu_id
, bool shaderdb
)
2473 struct util_dynarray
*compiled
= &program
->compiled
;
2475 midgard_debug
= debug_get_option_midgard_debug();
2477 /* TODO: Bound against what? */
2478 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2481 ctx
->stage
= nir
->info
.stage
;
2482 ctx
->is_blend
= is_blend
;
2483 ctx
->alpha_ref
= program
->alpha_ref
;
2484 ctx
->blend_rt
= blend_rt
;
2485 ctx
->quirks
= midgard_get_quirks(gpu_id
);
2487 /* Start off with a safe cutoff, allowing usage of all 16 work
2488 * registers. Later, we'll promote uniform reads to uniform registers
2489 * if we determine it is beneficial to do so */
2490 ctx
->uniform_cutoff
= 8;
2492 /* Initialize at a global (not block) level hash tables */
2494 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2495 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2496 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2498 /* Record the varying mapping for the command stream's bookkeeping */
2500 struct exec_list
*varyings
=
2501 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2503 unsigned max_varying
= 0;
2504 nir_foreach_variable(var
, varyings
) {
2505 unsigned loc
= var
->data
.driver_location
;
2506 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2508 for (int c
= 0; c
< sz
; ++c
) {
2509 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2510 max_varying
= MAX2(max_varying
, loc
+ c
);
2514 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2515 * (so we don't accidentally duplicate the epilogue since mesa/st has
2516 * messed with our I/O quite a bit already) */
2518 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2520 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2521 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2522 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2525 NIR_PASS_V(nir
, nir_lower_var_copies
);
2526 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2527 NIR_PASS_V(nir
, nir_split_var_copies
);
2528 NIR_PASS_V(nir
, nir_lower_var_copies
);
2529 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2530 NIR_PASS_V(nir
, nir_lower_var_copies
);
2531 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2533 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2535 /* Optimisation passes */
2537 optimise_nir(nir
, ctx
->quirks
);
2539 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2540 nir_print_shader(nir
, stdout
);
2543 /* Assign sysvals and counts, now that we're sure
2544 * (post-optimisation) */
2546 midgard_nir_assign_sysvals(ctx
, nir
);
2548 program
->uniform_count
= nir
->num_uniforms
;
2549 program
->sysval_count
= ctx
->sysval_count
;
2550 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2552 nir_foreach_function(func
, nir
) {
2556 list_inithead(&ctx
->blocks
);
2557 ctx
->block_count
= 0;
2560 emit_cf_list(ctx
, &func
->impl
->body
);
2561 break; /* TODO: Multi-function shaders */
2564 util_dynarray_init(compiled
, NULL
);
2566 /* Per-block lowering before opts */
2568 mir_foreach_block(ctx
, block
) {
2569 inline_alu_constants(ctx
, block
);
2570 midgard_opt_promote_fmov(ctx
, block
);
2571 embedded_to_inline_constant(ctx
, block
);
2573 /* MIR-level optimizations */
2575 bool progress
= false;
2580 mir_foreach_block(ctx
, block
) {
2581 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2582 progress
|= midgard_opt_copy_prop(ctx
, block
);
2583 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2584 progress
|= midgard_opt_combine_projection(ctx
, block
);
2585 progress
|= midgard_opt_varying_projection(ctx
, block
);
2586 progress
|= midgard_opt_not_propagate(ctx
, block
);
2587 progress
|= midgard_opt_fuse_src_invert(ctx
, block
);
2588 progress
|= midgard_opt_fuse_dest_invert(ctx
, block
);
2589 progress
|= midgard_opt_csel_invert(ctx
, block
);
2590 progress
|= midgard_opt_drop_cmp_invert(ctx
, block
);
2594 mir_foreach_block(ctx
, block
) {
2595 midgard_lower_invert(ctx
, block
);
2596 midgard_lower_derivatives(ctx
, block
);
2599 /* Nested control-flow can result in dead branches at the end of the
2600 * block. This messes with our analysis and is just dead code, so cull
2602 mir_foreach_block(ctx
, block
) {
2603 midgard_opt_cull_dead_branch(ctx
, block
);
2606 /* Ensure we were lowered */
2607 mir_foreach_instr_global(ctx
, ins
) {
2608 assert(!ins
->invert
);
2612 schedule_program(ctx
);
2615 /* Now that all the bundles are scheduled and we can calculate block
2616 * sizes, emit actual branch instructions rather than placeholders */
2618 int br_block_idx
= 0;
2620 mir_foreach_block(ctx
, block
) {
2621 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2622 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2623 midgard_instruction
*ins
= bundle
->instructions
[c
];
2625 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2627 if (ins
->prepacked_branch
) continue;
2629 /* Parse some basic branch info */
2630 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2631 bool is_conditional
= ins
->branch
.conditional
;
2632 bool is_inverted
= ins
->branch
.invert_conditional
;
2633 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2635 /* Determine the block we're jumping to */
2636 int target_number
= ins
->branch
.target_block
;
2638 /* Report the destination tag */
2639 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2641 /* Count up the number of quadwords we're
2642 * jumping over = number of quadwords until
2643 * (br_block_idx, target_number) */
2645 int quadword_offset
= 0;
2649 } else if (target_number
> br_block_idx
) {
2652 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2653 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2656 quadword_offset
+= blk
->quadword_count
;
2659 /* Jump backwards */
2661 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2662 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2665 quadword_offset
-= blk
->quadword_count
;
2669 /* Unconditional extended branches (far jumps)
2670 * have issues, so we always use a conditional
2671 * branch, setting the condition to always for
2672 * unconditional. For compact unconditional
2673 * branches, cond isn't used so it doesn't
2674 * matter what we pick. */
2676 midgard_condition cond
=
2677 !is_conditional
? midgard_condition_always
:
2678 is_inverted
? midgard_condition_false
:
2679 midgard_condition_true
;
2681 midgard_jmp_writeout_op op
=
2682 is_discard
? midgard_jmp_writeout_op_discard
:
2683 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2684 midgard_jmp_writeout_op_branch_cond
;
2687 midgard_branch_extended branch
=
2688 midgard_create_branch_extended(
2693 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2694 } else if (is_conditional
|| is_discard
) {
2695 midgard_branch_cond branch
= {
2697 .dest_tag
= dest_tag
,
2698 .offset
= quadword_offset
,
2702 assert(branch
.offset
== quadword_offset
);
2704 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2706 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2708 midgard_branch_uncond branch
= {
2710 .dest_tag
= dest_tag
,
2711 .offset
= quadword_offset
,
2715 assert(branch
.offset
== quadword_offset
);
2717 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2725 /* Emit flat binary from the instruction arrays. Iterate each block in
2726 * sequence. Save instruction boundaries such that lookahead tags can
2727 * be assigned easily */
2729 /* Cache _all_ bundles in source order for lookahead across failed branches */
2731 int bundle_count
= 0;
2732 mir_foreach_block(ctx
, block
) {
2733 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2735 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2737 mir_foreach_block(ctx
, block
) {
2738 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2739 source_order_bundles
[bundle_idx
++] = bundle
;
2743 int current_bundle
= 0;
2745 /* Midgard prefetches instruction types, so during emission we
2746 * need to lookahead. Unless this is the last instruction, in
2747 * which we return 1. Or if this is the second to last and the
2748 * last is an ALU, then it's also 1... */
2750 mir_foreach_block(ctx
, block
) {
2751 mir_foreach_bundle_in_block(block
, bundle
) {
2754 if (current_bundle
+ 1 < bundle_count
) {
2755 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2757 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2764 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2768 /* TODO: Free deeper */
2769 //util_dynarray_fini(&block->instructions);
2772 free(source_order_bundles
);
2774 /* Report the very first tag executed */
2775 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2777 /* Deal with off-by-one related to the fencepost problem */
2778 program
->work_register_count
= ctx
->work_registers
+ 1;
2779 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2781 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2782 program
->tls_size
= ctx
->tls_size
;
2784 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2785 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
, gpu_id
, ctx
->stage
);
2787 if (midgard_debug
& MIDGARD_DBG_SHADERDB
|| shaderdb
) {
2788 unsigned nr_bundles
= 0, nr_ins
= 0;
2790 /* Count instructions and bundles */
2792 mir_foreach_block(ctx
, block
) {
2793 nr_bundles
+= util_dynarray_num_elements(
2794 &block
->bundles
, midgard_bundle
);
2796 mir_foreach_bundle_in_block(block
, bun
)
2797 nr_ins
+= bun
->instruction_count
;
2800 /* Calculate thread count. There are certain cutoffs by
2801 * register count for thread count */
2803 unsigned nr_registers
= program
->work_register_count
;
2805 unsigned nr_threads
=
2806 (nr_registers
<= 4) ? 4 :
2807 (nr_registers
<= 8) ? 2 :
2812 fprintf(stderr
, "shader%d - %s shader: "
2813 "%u inst, %u bundles, %u quadwords, "
2814 "%u registers, %u threads, %u loops, "
2815 "%u:%u spills:fills\n",
2817 gl_shader_stage_name(ctx
->stage
),
2818 nr_ins
, nr_bundles
, ctx
->quadword_count
,
2819 nr_registers
, nr_threads
,
2821 ctx
->spills
, ctx
->fills
);