2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
63 unsigned SHADER_DB_COUNT
= 0;
65 int midgard_debug
= 0;
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 midgard_is_branch_unit(unsigned unit
)
75 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
78 static midgard_block
*
79 create_empty_block(compiler_context
*ctx
)
81 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
83 blk
->predecessors
= _mesa_set_create(blk
,
85 _mesa_key_pointer_equal
);
87 blk
->source_id
= ctx
->block_source_count
++;
93 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
99 for (unsigned i
= 0; i
< block
->nr_successors
; ++i
) {
100 if (block
->successors
[i
] == successor
)
104 block
->successors
[block
->nr_successors
++] = successor
;
105 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
107 /* Note the predecessor in the other direction */
108 _mesa_set_add(successor
->predecessors
, block
);
112 schedule_barrier(compiler_context
*ctx
)
114 midgard_block
*temp
= ctx
->after_block
;
115 ctx
->after_block
= create_empty_block(ctx
);
117 list_addtail(&ctx
->after_block
->link
, &ctx
->blocks
);
118 list_inithead(&ctx
->after_block
->instructions
);
119 midgard_block_add_successor(ctx
->current_block
, ctx
->after_block
);
120 ctx
->current_block
= ctx
->after_block
;
121 ctx
->after_block
= temp
;
124 /* Helpers to generate midgard_instruction's using macro magic, since every
125 * driver seems to do it that way */
127 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
129 #define M_LOAD_STORE(name, store) \
130 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
131 midgard_instruction i = { \
132 .type = TAG_LOAD_STORE_4, \
135 .src = { ~0, ~0, ~0 }, \
137 .op = midgard_op_##name, \
138 .swizzle = SWIZZLE_XYZW, \
151 #define M_LOAD(name) M_LOAD_STORE(name, false)
152 #define M_STORE(name) M_LOAD_STORE(name, true)
154 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
155 * the corresponding Midgard source */
157 static midgard_vector_alu_src
158 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
159 bool half
, bool sext
)
161 if (!src
) return blank_alu_src
;
163 /* Figure out how many components there are so we can adjust the
164 * swizzle. Specifically we want to broadcast the last channel so
165 * things like ball2/3 work
168 if (broadcast_count
) {
169 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
171 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
172 src
->swizzle
[c
] = last_component
;
176 midgard_vector_alu_src alu_src
= {
180 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
184 alu_src
.mod
= midgard_int_normal
;
186 /* Sign/zero-extend if needed */
190 midgard_int_sign_extend
191 : midgard_int_zero_extend
;
194 /* These should have been lowered away */
195 assert(!(src
->abs
|| src
->negate
));
197 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
203 /* load/store instructions have both 32-bit and 16-bit variants, depending on
204 * whether we are using vectors composed of highp or mediump. At the moment, we
205 * don't support half-floats -- this requires changes in other parts of the
206 * compiler -- therefore the 16-bit versions are commented out. */
208 //M_LOAD(ld_attr_16);
210 //M_LOAD(ld_vary_16);
215 M_LOAD(ld_color_buffer_8
);
216 //M_STORE(st_vary_16);
218 M_LOAD(ld_cubemap_coords
);
219 M_LOAD(ld_compute_id
);
221 static midgard_instruction
222 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
224 midgard_branch_cond branch
= {
232 memcpy(&compact
, &branch
, sizeof(branch
));
234 midgard_instruction ins
= {
236 .unit
= ALU_ENAB_BR_COMPACT
,
237 .prepacked_branch
= true,
238 .compact_branch
= true,
239 .br_compact
= compact
,
241 .src
= { ~0, ~0, ~0 },
244 if (op
== midgard_jmp_writeout_op_writeout
)
250 static midgard_instruction
251 v_branch(bool conditional
, bool invert
)
253 midgard_instruction ins
= {
255 .unit
= ALU_ENAB_BRANCH
,
256 .compact_branch
= true,
258 .conditional
= conditional
,
259 .invert_conditional
= invert
262 .src
= { ~0, ~0, ~0 },
268 static midgard_branch_extended
269 midgard_create_branch_extended( midgard_condition cond
,
270 midgard_jmp_writeout_op op
,
272 signed quadword_offset
)
274 /* The condition code is actually a LUT describing a function to
275 * combine multiple condition codes. However, we only support a single
276 * condition code at the moment, so we just duplicate over a bunch of
279 uint16_t duplicated_cond
=
289 midgard_branch_extended branch
= {
291 .dest_tag
= dest_tag
,
292 .offset
= quadword_offset
,
293 .cond
= duplicated_cond
300 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
302 ins
->has_constants
= true;
303 memcpy(&ins
->constants
, constants
, 16);
307 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
309 return glsl_count_attribute_slots(type
, false);
312 /* Lower fdot2 to a vector multiplication followed by channel addition */
314 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
316 if (alu
->op
!= nir_op_fdot2
)
319 b
->cursor
= nir_before_instr(&alu
->instr
);
321 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
322 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
324 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
326 nir_ssa_def
*sum
= nir_fadd(b
,
327 nir_channel(b
, product
, 0),
328 nir_channel(b
, product
, 1));
330 /* Replace the fdot2 with this sum */
331 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
335 midgard_sysval_for_ssbo(nir_intrinsic_instr
*instr
)
337 /* This is way too meta */
338 bool is_store
= instr
->intrinsic
== nir_intrinsic_store_ssbo
;
339 unsigned idx_idx
= is_store
? 1 : 0;
341 nir_src index
= instr
->src
[idx_idx
];
342 assert(nir_src_is_const(index
));
343 uint32_t uindex
= nir_src_as_uint(index
);
345 return PAN_SYSVAL(SSBO
, uindex
);
349 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
351 switch (instr
->intrinsic
) {
352 case nir_intrinsic_load_viewport_scale
:
353 return PAN_SYSVAL_VIEWPORT_SCALE
;
354 case nir_intrinsic_load_viewport_offset
:
355 return PAN_SYSVAL_VIEWPORT_OFFSET
;
356 case nir_intrinsic_load_num_work_groups
:
357 return PAN_SYSVAL_NUM_WORK_GROUPS
;
358 case nir_intrinsic_load_ssbo
:
359 case nir_intrinsic_store_ssbo
:
360 return midgard_sysval_for_ssbo(instr
);
366 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
369 nir_intrinsic_instr
*intr
;
370 nir_dest
*dst
= NULL
;
374 bool is_store
= false;
376 switch (instr
->type
) {
377 case nir_instr_type_intrinsic
:
378 intr
= nir_instr_as_intrinsic(instr
);
379 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
381 is_store
|= intr
->intrinsic
== nir_intrinsic_store_ssbo
;
383 case nir_instr_type_tex
:
384 tex
= nir_instr_as_tex(instr
);
385 if (tex
->op
!= nir_texop_txs
)
388 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
389 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
390 nir_tex_instr_dest_size(tex
) -
391 (tex
->is_array
? 1 : 0),
399 if (dest
&& dst
&& !is_store
)
400 *dest
= nir_dest_index(ctx
, dst
);
406 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
410 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
414 /* We have a sysval load; check if it's already been assigned */
416 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
419 /* It hasn't -- so assign it now! */
421 unsigned id
= ctx
->sysval_count
++;
422 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
423 ctx
->sysvals
[id
] = sysval
;
427 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
429 ctx
->sysval_count
= 0;
431 nir_foreach_function(function
, shader
) {
432 if (!function
->impl
) continue;
434 nir_foreach_block(block
, function
->impl
) {
435 nir_foreach_instr_safe(instr
, block
) {
436 midgard_nir_assign_sysval_body(ctx
, instr
);
443 midgard_nir_lower_fdot2(nir_shader
*shader
)
445 bool progress
= false;
447 nir_foreach_function(function
, shader
) {
448 if (!function
->impl
) continue;
451 nir_builder
*b
= &_b
;
452 nir_builder_init(b
, function
->impl
);
454 nir_foreach_block(block
, function
->impl
) {
455 nir_foreach_instr_safe(instr
, block
) {
456 if (instr
->type
!= nir_instr_type_alu
) continue;
458 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
459 midgard_nir_lower_fdot2_body(b
, alu
);
465 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
472 /* Flushes undefined values to zero */
475 optimise_nir(nir_shader
*nir
)
478 unsigned lower_flrp
=
479 (nir
->options
->lower_flrp16
? 16 : 0) |
480 (nir
->options
->lower_flrp32
? 32 : 0) |
481 (nir
->options
->lower_flrp64
? 64 : 0);
483 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
484 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
485 NIR_PASS(progress
, nir
, nir_lower_idiv
);
487 nir_lower_tex_options lower_tex_options
= {
488 .lower_txs_lod
= true,
492 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
497 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
498 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
500 NIR_PASS(progress
, nir
, nir_copy_prop
);
501 NIR_PASS(progress
, nir
, nir_opt_dce
);
502 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
503 NIR_PASS(progress
, nir
, nir_opt_cse
);
504 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
505 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
506 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
508 if (lower_flrp
!= 0) {
509 bool lower_flrp_progress
= false;
510 NIR_PASS(lower_flrp_progress
,
514 false /* always_precise */,
515 nir
->options
->lower_ffma
);
516 if (lower_flrp_progress
) {
517 NIR_PASS(progress
, nir
,
518 nir_opt_constant_folding
);
522 /* Nothing should rematerialize any flrps, so we only
523 * need to do this lowering once.
528 NIR_PASS(progress
, nir
, nir_opt_undef
);
529 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
531 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
534 nir_var_function_temp
);
536 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
539 /* Must be run at the end to prevent creation of fsin/fcos ops */
540 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
545 NIR_PASS(progress
, nir
, nir_opt_dce
);
546 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
547 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
548 NIR_PASS(progress
, nir
, nir_copy_prop
);
551 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
553 /* We implement booleans as 32-bit 0/~0 */
554 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
556 /* Now that booleans are lowered, we can run out late opts */
557 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
559 /* Lower mods for float ops only. Integer ops don't support modifiers
560 * (saturate doesn't make sense on integers, neg/abs require dedicated
563 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
564 NIR_PASS(progress
, nir
, nir_copy_prop
);
565 NIR_PASS(progress
, nir
, nir_opt_dce
);
567 /* Take us out of SSA */
568 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
569 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
571 /* We are a vector architecture; write combine where possible */
572 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
573 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
575 NIR_PASS(progress
, nir
, nir_opt_dce
);
578 /* Do not actually emit a load; instead, cache the constant for inlining */
581 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
583 nir_ssa_def def
= instr
->def
;
585 float *v
= rzalloc_array(NULL
, float, 4);
586 nir_const_value_to_array(v
, instr
->value
, instr
->def
.num_components
, f32
);
588 /* Shifted for SSA, +1 for off-by-one */
589 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, v
);
592 /* Normally constants are embedded implicitly, but for I/O and such we have to
593 * explicitly emit a move with the constant source */
596 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
598 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
600 if (constant_value
) {
601 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, to
);
602 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
603 emit_mir_instruction(ctx
, ins
);
608 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
610 unsigned comp
= src
->swizzle
[0];
612 for (unsigned c
= 1; c
< nr_components
; ++c
) {
613 if (src
->swizzle
[c
] != comp
)
620 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
621 * output of a conditional test) into that register */
624 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
626 int condition
= nir_src_index(ctx
, src
);
628 /* Source to swizzle the desired component into w */
630 const midgard_vector_alu_src alu_src
= {
631 .swizzle
= SWIZZLE(component
, component
, component
, component
),
634 /* There is no boolean move instruction. Instead, we simulate a move by
635 * ANDing the condition with itself to get it into r31.w */
637 midgard_instruction ins
= {
640 /* We need to set the conditional as close as possible */
641 .precede_break
= true,
642 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
643 .mask
= 1 << COMPONENT_W
,
644 .src
= { condition
, condition
, ~0 },
645 .dest
= SSA_FIXED_REGISTER(31),
648 .op
= midgard_alu_op_iand
,
649 .outmod
= midgard_outmod_int_wrap
,
650 .reg_mode
= midgard_reg_mode_32
,
651 .dest_override
= midgard_dest_override_none
,
652 .src1
= vector_alu_srco_unsigned(alu_src
),
653 .src2
= vector_alu_srco_unsigned(alu_src
)
657 emit_mir_instruction(ctx
, ins
);
660 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
664 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
666 int condition
= nir_src_index(ctx
, &src
->src
);
668 /* Source to swizzle the desired component into w */
670 const midgard_vector_alu_src alu_src
= {
671 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
674 /* There is no boolean move instruction. Instead, we simulate a move by
675 * ANDing the condition with itself to get it into r31.w */
677 midgard_instruction ins
= {
679 .precede_break
= true,
680 .mask
= mask_of(nr_comp
),
681 .src
= { condition
, condition
, ~0 },
682 .dest
= SSA_FIXED_REGISTER(31),
684 .op
= midgard_alu_op_iand
,
685 .outmod
= midgard_outmod_int_wrap
,
686 .reg_mode
= midgard_reg_mode_32
,
687 .dest_override
= midgard_dest_override_none
,
688 .src1
= vector_alu_srco_unsigned(alu_src
),
689 .src2
= vector_alu_srco_unsigned(alu_src
)
693 emit_mir_instruction(ctx
, ins
);
696 #define ALU_CASE(nir, _op) \
698 op = midgard_alu_op_##_op; \
699 assert(src_bitsize == dst_bitsize); \
702 #define ALU_CASE_BCAST(nir, _op, count) \
704 op = midgard_alu_op_##_op; \
705 broadcast_swizzle = count; \
706 assert(src_bitsize == dst_bitsize); \
709 nir_is_fzero_constant(nir_src src
)
711 if (!nir_src_is_const(src
))
714 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
715 if (nir_src_comp_as_float(src
, c
) != 0.0)
722 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
723 * special treatment override this anyway. */
725 static midgard_reg_mode
726 reg_mode_for_nir(nir_alu_instr
*instr
)
728 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
730 switch (src_bitsize
) {
732 return midgard_reg_mode_8
;
734 return midgard_reg_mode_16
;
736 return midgard_reg_mode_32
;
738 return midgard_reg_mode_64
;
740 unreachable("Invalid bit size");
745 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
747 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
748 * is handled elsewhere */
750 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
751 midgard_emit_derivatives(ctx
, instr
);
755 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
757 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
758 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
759 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
761 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
762 * supported. A few do not and are commented for now. Also, there are a
763 * number of NIR ops which Midgard does not support and need to be
764 * lowered, also TODO. This switch block emits the opcode and calling
765 * convention of the Midgard instruction; actual packing is done in
770 /* Number of components valid to check for the instruction (the rest
771 * will be forced to the last), or 0 to use as-is. Relevant as
772 * ball-type instructions have a channel count in NIR but are all vec4
775 unsigned broadcast_swizzle
= 0;
777 /* What register mode should we operate in? */
778 midgard_reg_mode reg_mode
=
779 reg_mode_for_nir(instr
);
781 /* Do we need a destination override? Used for inline
784 midgard_dest_override dest_override
=
785 midgard_dest_override_none
;
787 /* Should we use a smaller respective source and sign-extend? */
789 bool half_1
= false, sext_1
= false;
790 bool half_2
= false, sext_2
= false;
792 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
793 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
796 ALU_CASE(fadd
, fadd
);
797 ALU_CASE(fmul
, fmul
);
798 ALU_CASE(fmin
, fmin
);
799 ALU_CASE(fmax
, fmax
);
800 ALU_CASE(imin
, imin
);
801 ALU_CASE(imax
, imax
);
802 ALU_CASE(umin
, umin
);
803 ALU_CASE(umax
, umax
);
804 ALU_CASE(ffloor
, ffloor
);
805 ALU_CASE(fround_even
, froundeven
);
806 ALU_CASE(ftrunc
, ftrunc
);
807 ALU_CASE(fceil
, fceil
);
808 ALU_CASE(fdot3
, fdot3
);
809 ALU_CASE(fdot4
, fdot4
);
810 ALU_CASE(iadd
, iadd
);
811 ALU_CASE(isub
, isub
);
812 ALU_CASE(imul
, imul
);
814 /* Zero shoved as second-arg */
815 ALU_CASE(iabs
, iabsdiff
);
819 ALU_CASE(feq32
, feq
);
820 ALU_CASE(fne32
, fne
);
821 ALU_CASE(flt32
, flt
);
822 ALU_CASE(ieq32
, ieq
);
823 ALU_CASE(ine32
, ine
);
824 ALU_CASE(ilt32
, ilt
);
825 ALU_CASE(ult32
, ult
);
827 /* We don't have a native b2f32 instruction. Instead, like many
828 * GPUs, we exploit booleans as 0/~0 for false/true, and
829 * correspondingly AND
830 * by 1.0 to do the type conversion. For the moment, prime us
833 * iand [whatever], #0
835 * At the end of emit_alu (as MIR), we'll fix-up the constant
838 ALU_CASE(b2f32
, iand
);
839 ALU_CASE(b2i32
, iand
);
841 /* Likewise, we don't have a dedicated f2b32 instruction, but
842 * we can do a "not equal to 0.0" test. */
844 ALU_CASE(f2b32
, fne
);
845 ALU_CASE(i2b32
, ine
);
847 ALU_CASE(frcp
, frcp
);
848 ALU_CASE(frsq
, frsqrt
);
849 ALU_CASE(fsqrt
, fsqrt
);
850 ALU_CASE(fexp2
, fexp2
);
851 ALU_CASE(flog2
, flog2
);
853 ALU_CASE(f2i32
, f2i_rtz
);
854 ALU_CASE(f2u32
, f2u_rtz
);
855 ALU_CASE(i2f32
, i2f_rtz
);
856 ALU_CASE(u2f32
, u2f_rtz
);
858 ALU_CASE(f2i16
, f2i_rtz
);
859 ALU_CASE(f2u16
, f2u_rtz
);
860 ALU_CASE(i2f16
, i2f_rtz
);
861 ALU_CASE(u2f16
, u2f_rtz
);
863 ALU_CASE(fsin
, fsin
);
864 ALU_CASE(fcos
, fcos
);
866 /* We'll set invert */
867 ALU_CASE(inot
, imov
);
868 ALU_CASE(iand
, iand
);
870 ALU_CASE(ixor
, ixor
);
871 ALU_CASE(ishl
, ishl
);
872 ALU_CASE(ishr
, iasr
);
873 ALU_CASE(ushr
, ilsr
);
875 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
876 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
877 ALU_CASE(b32all_fequal4
, fball_eq
);
879 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
880 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
881 ALU_CASE(b32any_fnequal4
, fbany_neq
);
883 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
884 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
885 ALU_CASE(b32all_iequal4
, iball_eq
);
887 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
888 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
889 ALU_CASE(b32any_inequal4
, ibany_neq
);
891 /* Source mods will be shoved in later */
892 ALU_CASE(fabs
, fmov
);
893 ALU_CASE(fneg
, fmov
);
894 ALU_CASE(fsat
, fmov
);
896 /* For size conversion, we use a move. Ideally though we would squash
897 * these ops together; maybe that has to happen after in NIR as part of
898 * propagation...? An earlier algebraic pass ensured we step down by
899 * only / exactly one size. If stepping down, we use a dest override to
900 * reduce the size; if stepping up, we use a larger-sized move with a
901 * half source and a sign/zero-extension modifier */
906 /* If we end up upscale, we'll need a sign-extend on the
907 * operand (the second argument) */
914 op
= midgard_alu_op_imov
;
916 if (dst_bitsize
== (src_bitsize
* 2)) {
920 /* Use a greater register mode */
922 } else if (src_bitsize
== (dst_bitsize
* 2)) {
923 /* Converting down */
924 dest_override
= midgard_dest_override_lower
;
931 assert(src_bitsize
== 32);
933 op
= midgard_alu_op_fmov
;
934 dest_override
= midgard_dest_override_lower
;
939 assert(src_bitsize
== 16);
941 op
= midgard_alu_op_fmov
;
948 /* For greater-or-equal, we lower to less-or-equal and flip the
956 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
957 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
958 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
959 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
962 /* Swap via temporary */
963 nir_alu_src temp
= instr
->src
[1];
964 instr
->src
[1] = instr
->src
[0];
965 instr
->src
[0] = temp
;
970 case nir_op_b32csel
: {
971 /* Midgard features both fcsel and icsel, depending on
972 * the type of the arguments/output. However, as long
973 * as we're careful we can _always_ use icsel and
974 * _never_ need fcsel, since the latter does additional
975 * floating-point-specific processing whereas the
976 * former just moves bits on the wire. It's not obvious
977 * why these are separate opcodes, save for the ability
978 * to do things like sat/pos/abs/neg for free */
980 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
981 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
983 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
986 /* Emit the condition into r31 */
989 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
991 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
993 /* The condition is the first argument; move the other
994 * arguments up one to be a binary instruction for
997 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1002 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1007 /* Midgard can perform certain modifiers on output of an ALU op */
1010 if (midgard_is_integer_out_op(op
)) {
1011 outmod
= midgard_outmod_int_wrap
;
1013 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
1014 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
1017 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
1019 if (instr
->op
== nir_op_fmax
) {
1020 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
1021 op
= midgard_alu_op_fmov
;
1023 outmod
= midgard_outmod_pos
;
1024 instr
->src
[0] = instr
->src
[1];
1025 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1026 op
= midgard_alu_op_fmov
;
1028 outmod
= midgard_outmod_pos
;
1032 /* Fetch unit, quirks, etc information */
1033 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1034 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1036 /* src0 will always exist afaik, but src1 will not for 1-argument
1037 * instructions. The latter can only be fetched if the instruction
1038 * needs it, or else we may segfault. */
1040 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1041 unsigned src1
= nr_inputs
>= 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : ~0;
1042 unsigned src2
= nr_inputs
== 3 ? nir_alu_src_index(ctx
, &instr
->src
[2]) : ~0;
1044 /* Rather than use the instruction generation helpers, we do it
1045 * ourselves here to avoid the mess */
1047 midgard_instruction ins
= {
1050 quirk_flipped_r24
? ~0 : src0
,
1051 quirk_flipped_r24
? src0
: src1
,
1057 nir_alu_src
*nirmods
[3] = { NULL
};
1059 if (nr_inputs
>= 2) {
1060 nirmods
[0] = &instr
->src
[0];
1061 nirmods
[1] = &instr
->src
[1];
1062 } else if (nr_inputs
== 1) {
1063 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1069 nirmods
[2] = &instr
->src
[2];
1071 /* These were lowered to a move, so apply the corresponding mod */
1073 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1074 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
1076 if (instr
->op
== nir_op_fneg
)
1077 s
->negate
= !s
->negate
;
1079 if (instr
->op
== nir_op_fabs
)
1083 bool is_int
= midgard_is_integer_op(op
);
1085 ins
.mask
= mask_of(nr_components
);
1087 midgard_vector_alu alu
= {
1089 .reg_mode
= reg_mode
,
1090 .dest_override
= dest_override
,
1093 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1094 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1097 if (nr_inputs
== 3) {
1098 ins
.cond_swizzle
= SWIZZLE_FROM_ARRAY(nirmods
[2]->swizzle
);
1099 assert(!nirmods
[2]->abs
);
1100 assert(!nirmods
[2]->negate
);
1103 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1106 ins
.mask
&= instr
->dest
.write_mask
;
1110 /* Late fixup for emulated instructions */
1112 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1113 /* Presently, our second argument is an inline #0 constant.
1114 * Switch over to an embedded 1.0 constant (that can't fit
1115 * inline, since we're 32-bit, not 16-bit like the inline
1118 ins
.has_inline_constant
= false;
1119 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1120 ins
.has_constants
= true;
1122 if (instr
->op
== nir_op_b2f32
) {
1124 memcpy(&ins
.constants
, &f
, sizeof(float));
1126 ins
.constants
[0] = 1;
1129 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1130 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1131 /* Lots of instructions need a 0 plonked in */
1132 ins
.has_inline_constant
= false;
1133 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1134 ins
.has_constants
= true;
1135 ins
.constants
[0] = 0;
1136 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1137 } else if (instr
->op
== nir_op_inot
) {
1141 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1142 /* To avoid duplicating the lookup tables (probably), true LUT
1143 * instructions can only operate as if they were scalars. Lower
1144 * them here by changing the component. */
1146 uint8_t original_swizzle
[4];
1147 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1148 unsigned orig_mask
= ins
.mask
;
1150 for (int i
= 0; i
< nr_components
; ++i
) {
1151 /* Mask the associated component, dropping the
1152 * instruction if needed */
1155 ins
.mask
&= orig_mask
;
1160 for (int j
= 0; j
< 4; ++j
)
1161 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1163 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, false));
1164 emit_mir_instruction(ctx
, ins
);
1167 emit_mir_instruction(ctx
, ins
);
1174 mir_mask_for_intr(nir_instr
*instr
, bool is_read
)
1176 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1179 return mask_of(nir_intrinsic_dest_components(intr
));
1181 return nir_intrinsic_write_mask(intr
);
1184 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1185 * optimized) versions of UBO #0 */
1187 midgard_instruction
*
1189 compiler_context
*ctx
,
1193 nir_src
*indirect_offset
,
1196 /* TODO: half-floats */
1198 midgard_instruction ins
= m_ld_ubo_int4(dest
, offset
);
1200 assert((offset
& 0xF) == 0);
1203 /* TODO: Don't split */
1204 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1205 ins
.load_store
.address
= offset
>> 3;
1206 ins
.mask
= mir_mask_for_intr(instr
, true);
1208 if (indirect_offset
) {
1209 ins
.src
[1] = nir_src_index(ctx
, indirect_offset
);
1210 ins
.load_store
.arg_2
= 0x80;
1212 ins
.load_store
.arg_2
= 0x1E;
1215 ins
.load_store
.arg_1
= index
;
1217 return emit_mir_instruction(ctx
, ins
);
1220 /* SSBO reads are like UBO reads if you squint */
1224 compiler_context
*ctx
,
1229 nir_src
*indirect_offset
,
1234 midgard_instruction ins
;
1237 ins
= m_ld_int4(srcdest
, offset
);
1239 ins
= m_st_int4(srcdest
, offset
);
1241 /* SSBO reads use a generic memory read interface, so we need the
1242 * address of the SSBO as the first argument. This is a sysval. */
1244 unsigned addr
= make_compiler_temp(ctx
);
1245 emit_sysval_read(ctx
, instr
, addr
, 2);
1247 /* The source array is a bit of a leaky abstraction for SSBOs.
1248 * Nevertheless, for loads:
1254 * Whereas for stores:
1260 * We would like arg_1 = the address and
1261 * arg_2 = the offset.
1264 ins
.src
[is_read
? 0 : 1] = addr
;
1266 /* TODO: What is this? It looks superficially like a shift << 5, but
1267 * arg_1 doesn't take a shift Should it be E0 or A0? We also need the
1268 * indirect offset. */
1270 if (indirect_offset
) {
1271 ins
.load_store
.arg_1
|= 0xE0;
1272 ins
.src
[is_read
? 1 : 2] = nir_src_index(ctx
, indirect_offset
);
1274 ins
.load_store
.arg_2
= 0x7E;
1277 /* TODO: Bounds check */
1279 /* Finally, we emit the direct offset */
1281 ins
.load_store
.varying_parameters
= (offset
& 0x1FF) << 1;
1282 ins
.load_store
.address
= (offset
>> 9);
1283 ins
.mask
= mir_mask_for_intr(instr
, is_read
);
1285 emit_mir_instruction(ctx
, ins
);
1290 compiler_context
*ctx
,
1291 unsigned dest
, unsigned offset
,
1292 unsigned nr_comp
, unsigned component
,
1293 nir_src
*indirect_offset
, nir_alu_type type
)
1295 /* XXX: Half-floats? */
1296 /* TODO: swizzle, mask */
1298 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1299 ins
.mask
= mask_of(nr_comp
);
1300 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1302 midgard_varying_parameter p
= {
1304 .interpolation
= midgard_interp_default
,
1305 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1309 memcpy(&u
, &p
, sizeof(p
));
1310 ins
.load_store
.varying_parameters
= u
;
1312 if (indirect_offset
)
1313 ins
.src
[1] = nir_src_index(ctx
, indirect_offset
);
1315 ins
.load_store
.arg_2
= 0x1E;
1317 ins
.load_store
.arg_1
= 0x9E;
1319 /* Use the type appropriate load */
1323 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1326 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1328 case nir_type_float
:
1329 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1332 unreachable("Attempted to load unknown type");
1336 emit_mir_instruction(ctx
, ins
);
1340 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
, signed dest_override
,
1341 unsigned nr_components
)
1345 /* Figure out which uniform this is */
1346 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1347 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1349 if (dest_override
>= 0)
1350 dest
= dest_override
;
1352 /* Sysvals are prefix uniforms */
1353 unsigned uniform
= ((uintptr_t) val
) - 1;
1355 /* Emit the read itself -- this is never indirect */
1356 midgard_instruction
*ins
=
1357 emit_ubo_read(ctx
, instr
, dest
, uniform
* 16, NULL
, 0);
1359 ins
->mask
= mask_of(nr_components
);
1363 compute_builtin_arg(nir_op op
)
1366 case nir_intrinsic_load_work_group_id
:
1368 case nir_intrinsic_load_local_invocation_id
:
1371 unreachable("Invalid compute paramater loaded");
1375 /* Emit store for a fragment shader, which is encoded via a fancy branch. TODO:
1376 * Handle MRT here */
1379 emit_fragment_store(compiler_context
*ctx
, unsigned src
, unsigned rt
)
1381 emit_explicit_constant(ctx
, src
, src
);
1383 /* If we're doing MRT, we need to specify the render target */
1385 midgard_instruction rt_move
= {
1390 /* We'll write to r1.z */
1391 rt_move
= v_mov(~0, blank_alu_src
, SSA_FIXED_REGISTER(1));
1392 rt_move
.mask
= 1 << COMPONENT_Z
;
1393 rt_move
.unit
= UNIT_SADD
;
1395 /* r1.z = (rt * 0x100) */
1396 rt_move
.has_inline_constant
= true;
1397 rt_move
.inline_constant
= (rt
* 0x100);
1400 ctx
->work_registers
= MAX2(ctx
->work_registers
, 1);
1403 emit_mir_instruction(ctx
, rt_move
);
1406 /* Next, generate the branch. For R render targets in the writeout, the
1407 * i'th render target jumps to pseudo-offset [2(R-1) + i] */
1409 unsigned outputs
= ctx
->is_blend
? 1 : ctx
->nir
->num_outputs
;
1410 unsigned offset
= (2 * (outputs
- 1)) + rt
;
1412 struct midgard_instruction ins
=
1413 v_alu_br_compact_cond(midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, offset
, midgard_condition_always
);
1415 /* Add dependencies */
1417 ins
.src
[1] = rt_move
.dest
;
1419 /* Emit the branch */
1420 emit_mir_instruction(ctx
, ins
);
1424 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1426 unsigned reg
= nir_dest_index(ctx
, &instr
->dest
);
1427 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1428 ins
.mask
= mask_of(3);
1429 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1430 emit_mir_instruction(ctx
, ins
);
1433 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1435 unsigned offset
= 0, reg
;
1437 switch (instr
->intrinsic
) {
1438 case nir_intrinsic_discard_if
:
1439 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1443 case nir_intrinsic_discard
: {
1444 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1445 struct midgard_instruction discard
= v_branch(conditional
, false);
1446 discard
.branch
.target_type
= TARGET_DISCARD
;
1449 discard
.src
[0] = nir_src_index(ctx
, &instr
->src
[0]);
1451 emit_mir_instruction(ctx
, discard
);
1452 schedule_barrier(ctx
);
1457 case nir_intrinsic_load_uniform
:
1458 case nir_intrinsic_load_ubo
:
1459 case nir_intrinsic_load_ssbo
:
1460 case nir_intrinsic_load_input
: {
1461 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1462 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1463 bool is_ssbo
= instr
->intrinsic
== nir_intrinsic_load_ssbo
;
1465 /* Get the base type of the intrinsic */
1466 /* TODO: Infer type? Does it matter? */
1468 (is_ubo
|| is_ssbo
) ? nir_type_uint
: nir_intrinsic_type(instr
);
1469 t
= nir_alu_type_get_base_type(t
);
1471 if (!(is_ubo
|| is_ssbo
)) {
1472 offset
= nir_intrinsic_base(instr
);
1475 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1477 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1479 bool direct
= nir_src_is_const(*src_offset
);
1480 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1483 offset
+= nir_src_as_uint(*src_offset
);
1485 /* We may need to apply a fractional offset */
1486 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1487 nir_intrinsic_component(instr
) : 0;
1488 reg
= nir_dest_index(ctx
, &instr
->dest
);
1490 if (is_uniform
&& !ctx
->is_blend
) {
1491 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysval_count
+ offset
) * 16, indirect_offset
, 0);
1492 } else if (is_ubo
) {
1493 nir_src index
= instr
->src
[0];
1495 /* We don't yet support indirect UBOs. For indirect
1496 * block numbers (if that's possible), we don't know
1497 * enough about the hardware yet. For indirect sources,
1498 * we know what we need but we need to add some NIR
1499 * support for lowering correctly with respect to
1502 assert(nir_src_is_const(index
));
1503 assert(nir_src_is_const(*src_offset
));
1505 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1506 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, NULL
, uindex
);
1507 } else if (is_ssbo
) {
1508 nir_src index
= instr
->src
[0];
1509 assert(nir_src_is_const(index
));
1510 uint32_t uindex
= nir_src_as_uint(index
);
1512 emit_ssbo_access(ctx
, &instr
->instr
, true, reg
, offset
, indirect_offset
, uindex
);
1513 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1514 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
, t
);
1515 } else if (ctx
->is_blend
) {
1516 /* For blend shaders, load the input color, which is
1517 * preloaded to r0 */
1519 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), blank_alu_src
, reg
);
1520 emit_mir_instruction(ctx
, move
);
1521 schedule_barrier(ctx
);
1522 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1523 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1524 ins
.load_store
.arg_1
= 0x1E;
1525 ins
.load_store
.arg_2
= 0x1E;
1526 ins
.mask
= mask_of(nr_comp
);
1528 /* Use the type appropriate load */
1532 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1535 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1537 case nir_type_float
:
1538 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1541 unreachable("Attempted to load unknown type");
1545 emit_mir_instruction(ctx
, ins
);
1547 DBG("Unknown load\n");
1554 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1556 case nir_intrinsic_load_raw_output_pan
:
1557 reg
= nir_dest_index(ctx
, &instr
->dest
);
1558 assert(ctx
->is_blend
);
1560 midgard_instruction ld
= m_ld_color_buffer_8(reg
, 0);
1561 emit_mir_instruction(ctx
, ld
);
1564 case nir_intrinsic_load_blend_const_color_rgba
: {
1565 assert(ctx
->is_blend
);
1566 reg
= nir_dest_index(ctx
, &instr
->dest
);
1568 /* Blend constants are embedded directly in the shader and
1569 * patched in, so we use some magic routing */
1571 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1572 ins
.has_constants
= true;
1573 ins
.has_blend_constant
= true;
1574 emit_mir_instruction(ctx
, ins
);
1578 case nir_intrinsic_store_output
:
1579 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1581 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1583 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1585 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1586 /* Determine number of render targets */
1587 emit_fragment_store(ctx
, reg
, offset
);
1588 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1589 /* We should have been vectorized, though we don't
1590 * currently check that st_vary is emitted only once
1591 * per slot (this is relevant, since there's not a mask
1592 * parameter available on the store [set to 0 by the
1593 * blob]). We do respect the component by adjusting the
1594 * swizzle. If this is a constant source, we'll need to
1595 * emit that explicitly. */
1597 emit_explicit_constant(ctx
, reg
, reg
);
1599 unsigned component
= nir_intrinsic_component(instr
);
1600 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1602 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1603 st
.load_store
.arg_1
= 0x9E;
1604 st
.load_store
.arg_2
= 0x1E;
1605 st
.load_store
.swizzle
= swizzle_of(nr_comp
) << (2*component
);
1606 emit_mir_instruction(ctx
, st
);
1608 DBG("Unknown store\n");
1614 /* Special case of store_output for lowered blend shaders */
1615 case nir_intrinsic_store_raw_output_pan
:
1616 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1617 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1618 emit_fragment_store(ctx
, reg
, 0);
1622 case nir_intrinsic_store_ssbo
:
1623 assert(nir_src_is_const(instr
->src
[1]));
1625 bool direct_offset
= nir_src_is_const(instr
->src
[2]);
1626 offset
= direct_offset
? nir_src_as_uint(instr
->src
[2]) : 0;
1627 nir_src
*indirect_offset
= direct_offset
? NULL
: &instr
->src
[2];
1628 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1630 uint32_t uindex
= nir_src_as_uint(instr
->src
[1]);
1632 emit_explicit_constant(ctx
, reg
, reg
);
1633 emit_ssbo_access(ctx
, &instr
->instr
, false, reg
, offset
, indirect_offset
, uindex
);
1636 case nir_intrinsic_load_alpha_ref_float
:
1637 assert(instr
->dest
.is_ssa
);
1639 float ref_value
= ctx
->alpha_ref
;
1641 /* See emit_load_const */
1642 float *v
= ralloc_array(NULL
, float, 4);
1643 memcpy(v
, &ref_value
, sizeof(float));
1644 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (instr
->dest
.ssa
.index
<< 1) + 1, v
);
1647 case nir_intrinsic_load_viewport_scale
:
1648 case nir_intrinsic_load_viewport_offset
:
1649 case nir_intrinsic_load_num_work_groups
:
1650 emit_sysval_read(ctx
, &instr
->instr
, ~0, 3);
1653 case nir_intrinsic_load_work_group_id
:
1654 case nir_intrinsic_load_local_invocation_id
:
1655 emit_compute_builtin(ctx
, instr
);
1659 printf ("Unhandled intrinsic\n");
1666 midgard_tex_format(enum glsl_sampler_dim dim
)
1669 case GLSL_SAMPLER_DIM_1D
:
1670 case GLSL_SAMPLER_DIM_BUF
:
1673 case GLSL_SAMPLER_DIM_2D
:
1674 case GLSL_SAMPLER_DIM_EXTERNAL
:
1675 case GLSL_SAMPLER_DIM_RECT
:
1678 case GLSL_SAMPLER_DIM_3D
:
1681 case GLSL_SAMPLER_DIM_CUBE
:
1682 return MALI_TEX_CUBE
;
1685 DBG("Unknown sampler dim type\n");
1691 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1695 pan_attach_constant_bias(
1696 compiler_context
*ctx
,
1698 midgard_texture_word
*word
)
1700 /* To attach as constant, it has to *be* constant */
1702 if (!nir_src_is_const(lod
))
1705 float f
= nir_src_as_float(lod
);
1707 /* Break into fixed-point */
1709 float lod_frac
= f
- lod_int
;
1711 /* Carry over negative fractions */
1712 if (lod_frac
< 0.0) {
1718 word
->bias
= float_to_ubyte(lod_frac
);
1719 word
->bias_int
= lod_int
;
1724 static enum mali_sampler_type
1725 midgard_sampler_type(nir_alu_type t
) {
1726 switch (nir_alu_type_get_base_type(t
))
1728 case nir_type_float
:
1729 return MALI_SAMPLER_FLOAT
;
1731 return MALI_SAMPLER_SIGNED
;
1733 return MALI_SAMPLER_UNSIGNED
;
1735 unreachable("Unknown sampler type");
1740 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1741 unsigned midgard_texop
)
1744 //assert (!instr->sampler);
1745 //assert (!instr->texture_array_size);
1747 int texture_index
= instr
->texture_index
;
1748 int sampler_index
= texture_index
;
1750 /* No helper to build texture words -- we do it all here */
1751 midgard_instruction ins
= {
1752 .type
= TAG_TEXTURE_4
,
1754 .dest
= nir_dest_index(ctx
, &instr
->dest
),
1755 .src
= { ~0, ~0, ~0 },
1757 .op
= midgard_texop
,
1758 .format
= midgard_tex_format(instr
->sampler_dim
),
1759 .texture_handle
= texture_index
,
1760 .sampler_handle
= sampler_index
,
1761 .swizzle
= SWIZZLE_XYZW
,
1762 .in_reg_swizzle
= SWIZZLE_XYZW
,
1768 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1772 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1773 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1774 midgard_vector_alu_src alu_src
= blank_alu_src
;
1775 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
1777 switch (instr
->src
[i
].src_type
) {
1778 case nir_tex_src_coord
: {
1779 emit_explicit_constant(ctx
, index
, index
);
1781 /* Texelfetch coordinates uses all four elements
1782 * (xyz/index) regardless of texture dimensionality,
1783 * which means it's necessary to zero the unused
1784 * components to keep everything happy */
1786 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1787 unsigned old_index
= index
;
1789 index
= make_compiler_temp(ctx
);
1791 /* mov index, old_index */
1792 midgard_instruction mov
= v_mov(old_index
, blank_alu_src
, index
);
1794 emit_mir_instruction(ctx
, mov
);
1796 /* mov index.zw, #0 */
1797 mov
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
),
1798 blank_alu_src
, index
);
1799 mov
.has_constants
= true;
1800 mov
.mask
= (1 << COMPONENT_Z
) | (1 << COMPONENT_W
);
1801 emit_mir_instruction(ctx
, mov
);
1804 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1805 /* texelFetch is undefined on samplerCube */
1806 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1808 /* For cubemaps, we use a special ld/st op to
1809 * select the face and copy the xy into the
1810 * texture register */
1812 unsigned temp
= make_compiler_temp(ctx
);
1813 midgard_instruction ld
= m_ld_cubemap_coords(temp
, 0);
1815 ld
.mask
= 0x3; /* xy */
1816 ld
.load_store
.arg_1
= 0x20;
1817 ld
.load_store
.swizzle
= alu_src
.swizzle
;
1818 emit_mir_instruction(ctx
, ld
);
1821 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYXX
;
1826 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1827 /* Array component in w but NIR wants it in z */
1828 if (nr_components
== 3)
1829 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYZZ
;
1830 else if (nr_components
== 2)
1831 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYXX
;
1833 unreachable("Invalid texture 2D components");
1839 case nir_tex_src_bias
:
1840 case nir_tex_src_lod
: {
1841 /* Try as a constant if we can */
1843 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1844 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1847 ins
.texture
.lod_register
= true;
1849 emit_explicit_constant(ctx
, index
, index
);
1855 unreachable("Unknown texture source type\n");
1859 emit_mir_instruction(ctx
, ins
);
1861 /* Used for .cont and .last hinting */
1862 ctx
->texture_op_count
++;
1866 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1868 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1869 * generic tex in some cases (which confuses the hardware) */
1871 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1873 if (is_vertex
&& instr
->op
== nir_texop_tex
)
1874 instr
->op
= nir_texop_txl
;
1876 switch (instr
->op
) {
1879 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1882 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1885 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1888 emit_sysval_read(ctx
, &instr
->instr
, ~0, 4);
1891 unreachable("Unhanlded texture op");
1896 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1898 switch (instr
->type
) {
1899 case nir_jump_break
: {
1900 /* Emit a branch out of the loop */
1901 struct midgard_instruction br
= v_branch(false, false);
1902 br
.branch
.target_type
= TARGET_BREAK
;
1903 br
.branch
.target_break
= ctx
->current_loop_depth
;
1904 emit_mir_instruction(ctx
, br
);
1909 DBG("Unknown jump type %d\n", instr
->type
);
1915 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1917 switch (instr
->type
) {
1918 case nir_instr_type_load_const
:
1919 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1922 case nir_instr_type_intrinsic
:
1923 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1926 case nir_instr_type_alu
:
1927 emit_alu(ctx
, nir_instr_as_alu(instr
));
1930 case nir_instr_type_tex
:
1931 emit_tex(ctx
, nir_instr_as_tex(instr
));
1934 case nir_instr_type_jump
:
1935 emit_jump(ctx
, nir_instr_as_jump(instr
));
1938 case nir_instr_type_ssa_undef
:
1943 DBG("Unhandled instruction type\n");
1949 /* ALU instructions can inline or embed constants, which decreases register
1950 * pressure and saves space. */
1952 #define CONDITIONAL_ATTACH(idx) { \
1953 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
1956 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
1957 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1962 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
1964 mir_foreach_instr_in_block(block
, alu
) {
1965 /* Other instructions cannot inline constants */
1966 if (alu
->type
!= TAG_ALU_4
) continue;
1967 if (alu
->compact_branch
) continue;
1969 /* If there is already a constant here, we can do nothing */
1970 if (alu
->has_constants
) continue;
1972 CONDITIONAL_ATTACH(0);
1974 if (!alu
->has_constants
) {
1975 CONDITIONAL_ATTACH(1)
1976 } else if (!alu
->inline_constant
) {
1977 /* Corner case: _two_ vec4 constants, for instance with a
1978 * csel. For this case, we can only use a constant
1979 * register for one, we'll have to emit a move for the
1980 * other. Note, if both arguments are constants, then
1981 * necessarily neither argument depends on the value of
1982 * any particular register. As the destination register
1983 * will be wiped, that means we can spill the constant
1984 * to the destination register.
1987 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
1988 unsigned scratch
= alu
->dest
;
1991 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1992 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
1994 /* Set the source */
1995 alu
->src
[1] = scratch
;
1997 /* Inject us -before- the last instruction which set r31 */
1998 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
2004 /* Being a little silly with the names, but returns the op that is the bitwise
2005 * inverse of the op with the argument switched. I.e. (f and g are
2008 * f(a, b) = ~g(b, a)
2010 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
2012 * f(a, b) = ~g(b, a)
2013 * ~f(a, b) = g(b, a)
2014 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
2017 * Thus we define this function in pairs.
2020 static inline midgard_alu_op
2021 mir_contrapositive(midgard_alu_op op
)
2024 case midgard_alu_op_flt
:
2025 return midgard_alu_op_fle
;
2026 case midgard_alu_op_fle
:
2027 return midgard_alu_op_flt
;
2029 case midgard_alu_op_ilt
:
2030 return midgard_alu_op_ile
;
2031 case midgard_alu_op_ile
:
2032 return midgard_alu_op_ilt
;
2035 unreachable("No known contrapositive");
2039 /* Midgard supports two types of constants, embedded constants (128-bit) and
2040 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2041 * constants can be demoted to inline constants, for space savings and
2042 * sometimes a performance boost */
2045 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
2047 mir_foreach_instr_in_block(block
, ins
) {
2048 if (!ins
->has_constants
) continue;
2049 if (ins
->has_inline_constant
) continue;
2051 /* Blend constants must not be inlined by definition */
2052 if (ins
->has_blend_constant
) continue;
2054 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2055 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
2056 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
2058 if (!(is_16
|| is_32
))
2061 /* src1 cannot be an inline constant due to encoding
2062 * restrictions. So, if possible we try to flip the arguments
2065 int op
= ins
->alu
.op
;
2067 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2068 bool flip
= alu_opcode_props
[op
].props
& OP_COMMUTES
;
2071 /* Conditionals can be inverted */
2072 case midgard_alu_op_flt
:
2073 case midgard_alu_op_ilt
:
2074 case midgard_alu_op_fle
:
2075 case midgard_alu_op_ile
:
2076 ins
->alu
.op
= mir_contrapositive(ins
->alu
.op
);
2081 case midgard_alu_op_fcsel
:
2082 case midgard_alu_op_icsel
:
2083 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
2089 /* Flip the SSA numbers */
2090 ins
->src
[0] = ins
->src
[1];
2091 ins
->src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2093 /* And flip the modifiers */
2097 src_temp
= ins
->alu
.src2
;
2098 ins
->alu
.src2
= ins
->alu
.src1
;
2099 ins
->alu
.src1
= src_temp
;
2103 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2104 /* Extract the source information */
2106 midgard_vector_alu_src
*src
;
2107 int q
= ins
->alu
.src2
;
2108 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2111 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2112 int component
= src
->swizzle
& 3;
2114 /* Scale constant appropriately, if we can legally */
2115 uint16_t scaled_constant
= 0;
2117 if (midgard_is_integer_op(op
) || is_16
) {
2118 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2119 scaled_constant
= (uint16_t) iconstants
[component
];
2121 /* Constant overflow after resize */
2122 if (scaled_constant
!= iconstants
[component
])
2125 float *f
= (float *) ins
->constants
;
2126 float original
= f
[component
];
2127 scaled_constant
= _mesa_float_to_half(original
);
2129 /* Check for loss of precision. If this is
2130 * mediump, we don't care, but for a highp
2131 * shader, we need to pay attention. NIR
2132 * doesn't yet tell us which mode we're in!
2133 * Practically this prevents most constants
2134 * from being inlined, sadly. */
2136 float fp32
= _mesa_half_to_float(scaled_constant
);
2138 if (fp32
!= original
)
2142 /* We don't know how to handle these with a constant */
2144 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
2145 DBG("Bailing inline constant...\n");
2149 /* Make sure that the constant is not itself a
2150 * vector by checking if all accessed values
2151 * (by the swizzle) are the same. */
2153 uint32_t *cons
= ins
->constants
;
2154 uint32_t value
= cons
[component
];
2156 bool is_vector
= false;
2157 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2159 for (int c
= 1; c
< 4; ++c
) {
2160 /* We only care if this component is actually used */
2161 if (!(mask
& (1 << c
)))
2164 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2166 if (test
!= value
) {
2175 /* Get rid of the embedded constant */
2176 ins
->has_constants
= false;
2178 ins
->has_inline_constant
= true;
2179 ins
->inline_constant
= scaled_constant
;
2184 /* Dead code elimination for branches at the end of a block - only one branch
2185 * per block is legal semantically */
2188 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2190 bool branched
= false;
2192 mir_foreach_instr_in_block_safe(block
, ins
) {
2193 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2196 mir_remove_instruction(ins
);
2202 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2203 * the move can be propagated away entirely */
2206 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2209 if (comp
== midgard_outmod_none
)
2212 if (*outmod
== midgard_outmod_none
) {
2217 /* TODO: Compose rules */
2222 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2224 bool progress
= false;
2226 mir_foreach_instr_in_block_safe(block
, ins
) {
2227 if (ins
->type
!= TAG_ALU_4
) continue;
2228 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2229 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2231 /* TODO: Registers? */
2232 unsigned src
= ins
->src
[1];
2233 if (src
& IS_REG
) continue;
2234 assert(!mir_has_multiple_writes(ctx
, src
));
2236 /* There might be a source modifier, too */
2237 if (mir_nontrivial_source2_mod(ins
)) continue;
2239 /* Backpropagate the modifier */
2240 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2241 if (v
->type
!= TAG_ALU_4
) continue;
2242 if (v
->dest
!= src
) continue;
2244 /* Can we even take a float outmod? */
2245 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2247 midgard_outmod_float temp
= v
->alu
.outmod
;
2248 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2250 /* Throw in the towel.. */
2251 if (!progress
) break;
2253 /* Otherwise, transfer the modifier */
2254 v
->alu
.outmod
= temp
;
2255 ins
->alu
.outmod
= midgard_outmod_none
;
2265 emit_fragment_epilogue(compiler_context
*ctx
)
2267 /* Just emit the last chunk with the branch */
2268 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, ~0, midgard_condition_always
);
2271 static midgard_block
*
2272 emit_block(compiler_context
*ctx
, nir_block
*block
)
2274 midgard_block
*this_block
= ctx
->after_block
;
2275 ctx
->after_block
= NULL
;
2278 this_block
= create_empty_block(ctx
);
2280 list_addtail(&this_block
->link
, &ctx
->blocks
);
2282 this_block
->is_scheduled
= false;
2285 /* Set up current block */
2286 list_inithead(&this_block
->instructions
);
2287 ctx
->current_block
= this_block
;
2289 nir_foreach_instr(instr
, block
) {
2290 emit_instr(ctx
, instr
);
2291 ++ctx
->instruction_count
;
2297 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2300 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2302 midgard_block
*before_block
= ctx
->current_block
;
2304 /* Conditional branches expect the condition in r31.w; emit a move for
2305 * that in the _previous_ block (which is the current block). */
2306 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2308 /* Speculatively emit the branch, but we can't fill it in until later */
2309 EMIT(branch
, true, true);
2310 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2311 then_branch
->src
[0] = nir_src_index(ctx
, &nif
->condition
);
2313 /* Emit the two subblocks. */
2314 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2315 midgard_block
*end_then_block
= ctx
->current_block
;
2317 /* Emit a jump from the end of the then block to the end of the else */
2318 EMIT(branch
, false, false);
2319 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2321 /* Emit second block, and check if it's empty */
2323 int else_idx
= ctx
->block_count
;
2324 int count_in
= ctx
->instruction_count
;
2325 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2326 midgard_block
*end_else_block
= ctx
->current_block
;
2327 int after_else_idx
= ctx
->block_count
;
2329 /* Now that we have the subblocks emitted, fix up the branches */
2334 if (ctx
->instruction_count
== count_in
) {
2335 /* The else block is empty, so don't emit an exit jump */
2336 mir_remove_instruction(then_exit
);
2337 then_branch
->branch
.target_block
= after_else_idx
;
2339 then_branch
->branch
.target_block
= else_idx
;
2340 then_exit
->branch
.target_block
= after_else_idx
;
2343 /* Wire up the successors */
2345 ctx
->after_block
= create_empty_block(ctx
);
2347 midgard_block_add_successor(before_block
, then_block
);
2348 midgard_block_add_successor(before_block
, else_block
);
2350 midgard_block_add_successor(end_then_block
, ctx
->after_block
);
2351 midgard_block_add_successor(end_else_block
, ctx
->after_block
);
2355 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2357 /* Remember where we are */
2358 midgard_block
*start_block
= ctx
->current_block
;
2360 /* Allocate a loop number, growing the current inner loop depth */
2361 int loop_idx
= ++ctx
->current_loop_depth
;
2363 /* Get index from before the body so we can loop back later */
2364 int start_idx
= ctx
->block_count
;
2366 /* Emit the body itself */
2367 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2369 /* Branch back to loop back */
2370 struct midgard_instruction br_back
= v_branch(false, false);
2371 br_back
.branch
.target_block
= start_idx
;
2372 emit_mir_instruction(ctx
, br_back
);
2374 /* Mark down that branch in the graph. */
2375 midgard_block_add_successor(start_block
, loop_block
);
2376 midgard_block_add_successor(ctx
->current_block
, loop_block
);
2378 /* Find the index of the block about to follow us (note: we don't add
2379 * one; blocks are 0-indexed so we get a fencepost problem) */
2380 int break_block_idx
= ctx
->block_count
;
2382 /* Fix up the break statements we emitted to point to the right place,
2383 * now that we can allocate a block number for them */
2384 ctx
->after_block
= create_empty_block(ctx
);
2386 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2387 mir_foreach_instr_in_block(block
, ins
) {
2388 if (ins
->type
!= TAG_ALU_4
) continue;
2389 if (!ins
->compact_branch
) continue;
2390 if (ins
->prepacked_branch
) continue;
2392 /* We found a branch -- check the type to see if we need to do anything */
2393 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2395 /* It's a break! Check if it's our break */
2396 if (ins
->branch
.target_break
!= loop_idx
) continue;
2398 /* Okay, cool, we're breaking out of this loop.
2399 * Rewrite from a break to a goto */
2401 ins
->branch
.target_type
= TARGET_GOTO
;
2402 ins
->branch
.target_block
= break_block_idx
;
2404 midgard_block_add_successor(block
, ctx
->after_block
);
2408 /* Now that we've finished emitting the loop, free up the depth again
2409 * so we play nice with recursion amid nested loops */
2410 --ctx
->current_loop_depth
;
2412 /* Dump loop stats */
2416 static midgard_block
*
2417 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2419 midgard_block
*start_block
= NULL
;
2421 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2422 switch (node
->type
) {
2423 case nir_cf_node_block
: {
2424 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2427 start_block
= block
;
2432 case nir_cf_node_if
:
2433 emit_if(ctx
, nir_cf_node_as_if(node
));
2436 case nir_cf_node_loop
:
2437 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2440 case nir_cf_node_function
:
2449 /* Due to lookahead, we need to report the first tag executed in the command
2450 * stream and in branch targets. An initial block might be empty, so iterate
2451 * until we find one that 'works' */
2454 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2456 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2458 unsigned first_tag
= 0;
2460 mir_foreach_block_from(ctx
, initial_block
, v
) {
2461 midgard_bundle
*initial_bundle
=
2462 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2464 if (initial_bundle
) {
2465 first_tag
= initial_bundle
->tag
;
2474 midgard_compile_shader_nir(struct midgard_screen
*screen
, nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2476 struct util_dynarray
*compiled
= &program
->compiled
;
2478 midgard_debug
= debug_get_option_midgard_debug();
2480 /* TODO: Bound against what? */
2481 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2484 ctx
->screen
= screen
;
2485 ctx
->stage
= nir
->info
.stage
;
2486 ctx
->is_blend
= is_blend
;
2487 ctx
->alpha_ref
= program
->alpha_ref
;
2489 /* Start off with a safe cutoff, allowing usage of all 16 work
2490 * registers. Later, we'll promote uniform reads to uniform registers
2491 * if we determine it is beneficial to do so */
2492 ctx
->uniform_cutoff
= 8;
2494 /* Initialize at a global (not block) level hash tables */
2496 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2497 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2498 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2500 /* Record the varying mapping for the command stream's bookkeeping */
2502 struct exec_list
*varyings
=
2503 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2505 unsigned max_varying
= 0;
2506 nir_foreach_variable(var
, varyings
) {
2507 unsigned loc
= var
->data
.driver_location
;
2508 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2510 for (int c
= 0; c
< sz
; ++c
) {
2511 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2512 max_varying
= MAX2(max_varying
, loc
+ c
);
2516 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2517 * (so we don't accidentally duplicate the epilogue since mesa/st has
2518 * messed with our I/O quite a bit already) */
2520 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2522 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2523 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2524 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2527 NIR_PASS_V(nir
, nir_lower_var_copies
);
2528 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2529 NIR_PASS_V(nir
, nir_split_var_copies
);
2530 NIR_PASS_V(nir
, nir_lower_var_copies
);
2531 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2532 NIR_PASS_V(nir
, nir_lower_var_copies
);
2533 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2535 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2537 /* Optimisation passes */
2541 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2542 nir_print_shader(nir
, stdout
);
2545 /* Assign sysvals and counts, now that we're sure
2546 * (post-optimisation) */
2548 midgard_nir_assign_sysvals(ctx
, nir
);
2550 program
->uniform_count
= nir
->num_uniforms
;
2551 program
->sysval_count
= ctx
->sysval_count
;
2552 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2554 nir_foreach_function(func
, nir
) {
2558 list_inithead(&ctx
->blocks
);
2559 ctx
->block_count
= 0;
2562 emit_cf_list(ctx
, &func
->impl
->body
);
2564 /* Emit empty exit block with successor */
2566 struct midgard_block
*semi_end
= ctx
->current_block
;
2568 struct midgard_block
*end
=
2569 emit_block(ctx
, func
->impl
->end_block
);
2571 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2572 emit_fragment_epilogue(ctx
);
2574 midgard_block_add_successor(semi_end
, end
);
2576 break; /* TODO: Multi-function shaders */
2579 util_dynarray_init(compiled
, NULL
);
2581 /* Per-block lowering before opts */
2583 mir_foreach_block(ctx
, block
) {
2584 inline_alu_constants(ctx
, block
);
2585 midgard_opt_promote_fmov(ctx
, block
);
2586 embedded_to_inline_constant(ctx
, block
);
2588 /* MIR-level optimizations */
2590 bool progress
= false;
2595 mir_foreach_block(ctx
, block
) {
2596 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2597 progress
|= midgard_opt_copy_prop(ctx
, block
);
2598 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2599 progress
|= midgard_opt_combine_projection(ctx
, block
);
2600 progress
|= midgard_opt_varying_projection(ctx
, block
);
2601 progress
|= midgard_opt_not_propagate(ctx
, block
);
2602 progress
|= midgard_opt_fuse_src_invert(ctx
, block
);
2603 progress
|= midgard_opt_fuse_dest_invert(ctx
, block
);
2607 mir_foreach_block(ctx
, block
) {
2608 midgard_lower_invert(ctx
, block
);
2609 midgard_lower_derivatives(ctx
, block
);
2612 /* Nested control-flow can result in dead branches at the end of the
2613 * block. This messes with our analysis and is just dead code, so cull
2615 mir_foreach_block(ctx
, block
) {
2616 midgard_opt_cull_dead_branch(ctx
, block
);
2619 /* Ensure we were lowered */
2620 mir_foreach_instr_global(ctx
, ins
) {
2621 assert(!ins
->invert
);
2625 schedule_program(ctx
);
2627 /* Now that all the bundles are scheduled and we can calculate block
2628 * sizes, emit actual branch instructions rather than placeholders */
2630 int br_block_idx
= 0;
2632 mir_foreach_block(ctx
, block
) {
2633 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2634 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2635 midgard_instruction
*ins
= bundle
->instructions
[c
];
2637 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2639 if (ins
->prepacked_branch
) continue;
2641 /* Parse some basic branch info */
2642 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2643 bool is_conditional
= ins
->branch
.conditional
;
2644 bool is_inverted
= ins
->branch
.invert_conditional
;
2645 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2647 /* Determine the block we're jumping to */
2648 int target_number
= ins
->branch
.target_block
;
2650 /* Report the destination tag */
2651 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2653 /* Count up the number of quadwords we're
2654 * jumping over = number of quadwords until
2655 * (br_block_idx, target_number) */
2657 int quadword_offset
= 0;
2661 } else if (target_number
> br_block_idx
) {
2664 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2665 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2668 quadword_offset
+= blk
->quadword_count
;
2671 /* Jump backwards */
2673 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2674 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2677 quadword_offset
-= blk
->quadword_count
;
2681 /* Unconditional extended branches (far jumps)
2682 * have issues, so we always use a conditional
2683 * branch, setting the condition to always for
2684 * unconditional. For compact unconditional
2685 * branches, cond isn't used so it doesn't
2686 * matter what we pick. */
2688 midgard_condition cond
=
2689 !is_conditional
? midgard_condition_always
:
2690 is_inverted
? midgard_condition_false
:
2691 midgard_condition_true
;
2693 midgard_jmp_writeout_op op
=
2694 is_discard
? midgard_jmp_writeout_op_discard
:
2695 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2696 midgard_jmp_writeout_op_branch_cond
;
2699 midgard_branch_extended branch
=
2700 midgard_create_branch_extended(
2705 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2706 } else if (is_conditional
|| is_discard
) {
2707 midgard_branch_cond branch
= {
2709 .dest_tag
= dest_tag
,
2710 .offset
= quadword_offset
,
2714 assert(branch
.offset
== quadword_offset
);
2716 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2718 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2720 midgard_branch_uncond branch
= {
2722 .dest_tag
= dest_tag
,
2723 .offset
= quadword_offset
,
2727 assert(branch
.offset
== quadword_offset
);
2729 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2737 /* Emit flat binary from the instruction arrays. Iterate each block in
2738 * sequence. Save instruction boundaries such that lookahead tags can
2739 * be assigned easily */
2741 /* Cache _all_ bundles in source order for lookahead across failed branches */
2743 int bundle_count
= 0;
2744 mir_foreach_block(ctx
, block
) {
2745 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2747 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2749 mir_foreach_block(ctx
, block
) {
2750 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2751 source_order_bundles
[bundle_idx
++] = bundle
;
2755 int current_bundle
= 0;
2757 /* Midgard prefetches instruction types, so during emission we
2758 * need to lookahead. Unless this is the last instruction, in
2759 * which we return 1. Or if this is the second to last and the
2760 * last is an ALU, then it's also 1... */
2762 mir_foreach_block(ctx
, block
) {
2763 mir_foreach_bundle_in_block(block
, bundle
) {
2766 if (current_bundle
+ 1 < bundle_count
) {
2767 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2769 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2776 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2780 /* TODO: Free deeper */
2781 //util_dynarray_fini(&block->instructions);
2784 free(source_order_bundles
);
2786 /* Report the very first tag executed */
2787 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2789 /* Deal with off-by-one related to the fencepost problem */
2790 program
->work_register_count
= ctx
->work_registers
+ 1;
2791 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2793 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2794 program
->tls_size
= ctx
->tls_size
;
2796 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2797 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);
2799 if (midgard_debug
& MIDGARD_DBG_SHADERDB
) {
2800 unsigned nr_bundles
= 0, nr_ins
= 0;
2802 /* Count instructions and bundles */
2804 mir_foreach_block(ctx
, block
) {
2805 nr_bundles
+= util_dynarray_num_elements(
2806 &block
->bundles
, midgard_bundle
);
2808 mir_foreach_bundle_in_block(block
, bun
)
2809 nr_ins
+= bun
->instruction_count
;
2812 /* Calculate thread count. There are certain cutoffs by
2813 * register count for thread count */
2815 unsigned nr_registers
= program
->work_register_count
;
2817 unsigned nr_threads
=
2818 (nr_registers
<= 4) ? 4 :
2819 (nr_registers
<= 8) ? 2 :
2824 fprintf(stderr
, "shader%d - %s shader: "
2825 "%u inst, %u bundles, %u quadwords, "
2826 "%u registers, %u threads, %u loops, "
2827 "%u:%u spills:fills\n",
2829 gl_shader_stage_name(ctx
->stage
),
2830 nr_ins
, nr_bundles
, ctx
->quadword_count
,
2831 nr_registers
, nr_threads
,
2833 ctx
->spills
, ctx
->fills
);