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pan/midgard: Implement derivatives
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
44
45 #include "midgard.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
49 #include "helpers.h"
50 #include "compiler.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71
72 static bool
73 midgard_is_branch_unit(unsigned unit)
74 {
75 return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
76 }
77
78 static void
79 midgard_block_add_successor(midgard_block *block, midgard_block *successor)
80 {
81 block->successors[block->nr_successors++] = successor;
82 assert(block->nr_successors <= ARRAY_SIZE(block->successors));
83 }
84
85 /* Helpers to generate midgard_instruction's using macro magic, since every
86 * driver seems to do it that way */
87
88 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
89
90 #define M_LOAD_STORE(name, rname, uname) \
91 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
92 midgard_instruction i = { \
93 .type = TAG_LOAD_STORE_4, \
94 .mask = 0xF, \
95 .ssa_args = { \
96 .rname = ssa, \
97 .uname = -1, \
98 .src1 = -1 \
99 }, \
100 .load_store = { \
101 .op = midgard_op_##name, \
102 .swizzle = SWIZZLE_XYZW, \
103 .address = address \
104 } \
105 }; \
106 \
107 return i; \
108 }
109
110 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
111 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
112
113 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
114 * the corresponding Midgard source */
115
116 static midgard_vector_alu_src
117 vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
118 bool half, bool sext)
119 {
120 if (!src) return blank_alu_src;
121
122 /* Figure out how many components there are so we can adjust the
123 * swizzle. Specifically we want to broadcast the last channel so
124 * things like ball2/3 work
125 */
126
127 if (broadcast_count) {
128 uint8_t last_component = src->swizzle[broadcast_count - 1];
129
130 for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) {
131 src->swizzle[c] = last_component;
132 }
133 }
134
135 midgard_vector_alu_src alu_src = {
136 .rep_low = 0,
137 .rep_high = 0,
138 .half = half,
139 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle)
140 };
141
142 if (is_int) {
143 alu_src.mod = midgard_int_normal;
144
145 /* Sign/zero-extend if needed */
146
147 if (half) {
148 alu_src.mod = sext ?
149 midgard_int_sign_extend
150 : midgard_int_zero_extend;
151 }
152
153 /* These should have been lowered away */
154 assert(!(src->abs || src->negate));
155 } else {
156 alu_src.mod = (src->abs << 0) | (src->negate << 1);
157 }
158
159 return alu_src;
160 }
161
162 /* load/store instructions have both 32-bit and 16-bit variants, depending on
163 * whether we are using vectors composed of highp or mediump. At the moment, we
164 * don't support half-floats -- this requires changes in other parts of the
165 * compiler -- therefore the 16-bit versions are commented out. */
166
167 //M_LOAD(ld_attr_16);
168 M_LOAD(ld_attr_32);
169 //M_LOAD(ld_vary_16);
170 M_LOAD(ld_vary_32);
171 //M_LOAD(ld_uniform_16);
172 M_LOAD(ld_uniform_32);
173 M_LOAD(ld_color_buffer_8);
174 //M_STORE(st_vary_16);
175 M_STORE(st_vary_32);
176 M_LOAD(st_cubemap_coords);
177
178 static midgard_instruction
179 v_alu_br_compact_cond(midgard_jmp_writeout_op op, unsigned tag, signed offset, unsigned cond)
180 {
181 midgard_branch_cond branch = {
182 .op = op,
183 .dest_tag = tag,
184 .offset = offset,
185 .cond = cond
186 };
187
188 uint16_t compact;
189 memcpy(&compact, &branch, sizeof(branch));
190
191 midgard_instruction ins = {
192 .type = TAG_ALU_4,
193 .unit = ALU_ENAB_BR_COMPACT,
194 .prepacked_branch = true,
195 .compact_branch = true,
196 .br_compact = compact
197 };
198
199 if (op == midgard_jmp_writeout_op_writeout)
200 ins.writeout = true;
201
202 return ins;
203 }
204
205 static midgard_instruction
206 v_branch(bool conditional, bool invert)
207 {
208 midgard_instruction ins = {
209 .type = TAG_ALU_4,
210 .unit = ALU_ENAB_BRANCH,
211 .compact_branch = true,
212 .branch = {
213 .conditional = conditional,
214 .invert_conditional = invert
215 }
216 };
217
218 return ins;
219 }
220
221 static midgard_branch_extended
222 midgard_create_branch_extended( midgard_condition cond,
223 midgard_jmp_writeout_op op,
224 unsigned dest_tag,
225 signed quadword_offset)
226 {
227 /* For unclear reasons, the condition code is repeated 8 times */
228 uint16_t duplicated_cond =
229 (cond << 14) |
230 (cond << 12) |
231 (cond << 10) |
232 (cond << 8) |
233 (cond << 6) |
234 (cond << 4) |
235 (cond << 2) |
236 (cond << 0);
237
238 midgard_branch_extended branch = {
239 .op = op,
240 .dest_tag = dest_tag,
241 .offset = quadword_offset,
242 .cond = duplicated_cond
243 };
244
245 return branch;
246 }
247
248 static void
249 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
250 {
251 ins->has_constants = true;
252 memcpy(&ins->constants, constants, 16);
253 }
254
255 static int
256 glsl_type_size(const struct glsl_type *type, bool bindless)
257 {
258 return glsl_count_attribute_slots(type, false);
259 }
260
261 /* Lower fdot2 to a vector multiplication followed by channel addition */
262 static void
263 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
264 {
265 if (alu->op != nir_op_fdot2)
266 return;
267
268 b->cursor = nir_before_instr(&alu->instr);
269
270 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
271 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
272
273 nir_ssa_def *product = nir_fmul(b, src0, src1);
274
275 nir_ssa_def *sum = nir_fadd(b,
276 nir_channel(b, product, 0),
277 nir_channel(b, product, 1));
278
279 /* Replace the fdot2 with this sum */
280 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
281 }
282
283 static int
284 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
285 {
286 switch (instr->intrinsic) {
287 case nir_intrinsic_load_viewport_scale:
288 return PAN_SYSVAL_VIEWPORT_SCALE;
289 case nir_intrinsic_load_viewport_offset:
290 return PAN_SYSVAL_VIEWPORT_OFFSET;
291 default:
292 return -1;
293 }
294 }
295
296 static int sysval_for_instr(compiler_context *ctx, nir_instr *instr,
297 unsigned *dest)
298 {
299 nir_intrinsic_instr *intr;
300 nir_dest *dst = NULL;
301 nir_tex_instr *tex;
302 int sysval = -1;
303
304 switch (instr->type) {
305 case nir_instr_type_intrinsic:
306 intr = nir_instr_as_intrinsic(instr);
307 sysval = midgard_nir_sysval_for_intrinsic(intr);
308 dst = &intr->dest;
309 break;
310 case nir_instr_type_tex:
311 tex = nir_instr_as_tex(instr);
312 if (tex->op != nir_texop_txs)
313 break;
314
315 sysval = PAN_SYSVAL(TEXTURE_SIZE,
316 PAN_TXS_SYSVAL_ID(tex->texture_index,
317 nir_tex_instr_dest_size(tex) -
318 (tex->is_array ? 1 : 0),
319 tex->is_array));
320 dst = &tex->dest;
321 break;
322 default:
323 break;
324 }
325
326 if (dest && dst)
327 *dest = nir_dest_index(ctx, dst);
328
329 return sysval;
330 }
331
332 static void
333 midgard_nir_assign_sysval_body(compiler_context *ctx, nir_instr *instr)
334 {
335 int sysval;
336
337 sysval = sysval_for_instr(ctx, instr, NULL);
338 if (sysval < 0)
339 return;
340
341 /* We have a sysval load; check if it's already been assigned */
342
343 if (_mesa_hash_table_u64_search(ctx->sysval_to_id, sysval))
344 return;
345
346 /* It hasn't -- so assign it now! */
347
348 unsigned id = ctx->sysval_count++;
349 _mesa_hash_table_u64_insert(ctx->sysval_to_id, sysval, (void *) ((uintptr_t) id + 1));
350 ctx->sysvals[id] = sysval;
351 }
352
353 static void
354 midgard_nir_assign_sysvals(compiler_context *ctx, nir_shader *shader)
355 {
356 ctx->sysval_count = 0;
357
358 nir_foreach_function(function, shader) {
359 if (!function->impl) continue;
360
361 nir_foreach_block(block, function->impl) {
362 nir_foreach_instr_safe(instr, block) {
363 midgard_nir_assign_sysval_body(ctx, instr);
364 }
365 }
366 }
367 }
368
369 static bool
370 midgard_nir_lower_fdot2(nir_shader *shader)
371 {
372 bool progress = false;
373
374 nir_foreach_function(function, shader) {
375 if (!function->impl) continue;
376
377 nir_builder _b;
378 nir_builder *b = &_b;
379 nir_builder_init(b, function->impl);
380
381 nir_foreach_block(block, function->impl) {
382 nir_foreach_instr_safe(instr, block) {
383 if (instr->type != nir_instr_type_alu) continue;
384
385 nir_alu_instr *alu = nir_instr_as_alu(instr);
386 midgard_nir_lower_fdot2_body(b, alu);
387
388 progress |= true;
389 }
390 }
391
392 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
393
394 }
395
396 return progress;
397 }
398
399 /* Flushes undefined values to zero */
400
401 static void
402 optimise_nir(nir_shader *nir)
403 {
404 bool progress;
405 unsigned lower_flrp =
406 (nir->options->lower_flrp16 ? 16 : 0) |
407 (nir->options->lower_flrp32 ? 32 : 0) |
408 (nir->options->lower_flrp64 ? 64 : 0);
409
410 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
411 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
412 NIR_PASS(progress, nir, nir_lower_idiv);
413
414 nir_lower_tex_options lower_tex_1st_pass_options = {
415 .lower_rect = true,
416 .lower_txp = ~0
417 };
418
419 nir_lower_tex_options lower_tex_2nd_pass_options = {
420 .lower_txs_lod = true,
421 };
422
423 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_1st_pass_options);
424 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_2nd_pass_options);
425
426 do {
427 progress = false;
428
429 NIR_PASS(progress, nir, nir_lower_var_copies);
430 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
431
432 NIR_PASS(progress, nir, nir_copy_prop);
433 NIR_PASS(progress, nir, nir_opt_dce);
434 NIR_PASS(progress, nir, nir_opt_dead_cf);
435 NIR_PASS(progress, nir, nir_opt_cse);
436 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
437 NIR_PASS(progress, nir, nir_opt_algebraic);
438 NIR_PASS(progress, nir, nir_opt_constant_folding);
439
440 if (lower_flrp != 0) {
441 bool lower_flrp_progress = false;
442 NIR_PASS(lower_flrp_progress,
443 nir,
444 nir_lower_flrp,
445 lower_flrp,
446 false /* always_precise */,
447 nir->options->lower_ffma);
448 if (lower_flrp_progress) {
449 NIR_PASS(progress, nir,
450 nir_opt_constant_folding);
451 progress = true;
452 }
453
454 /* Nothing should rematerialize any flrps, so we only
455 * need to do this lowering once.
456 */
457 lower_flrp = 0;
458 }
459
460 NIR_PASS(progress, nir, nir_opt_undef);
461 NIR_PASS(progress, nir, nir_undef_to_zero);
462
463 NIR_PASS(progress, nir, nir_opt_loop_unroll,
464 nir_var_shader_in |
465 nir_var_shader_out |
466 nir_var_function_temp);
467
468 NIR_PASS(progress, nir, nir_opt_vectorize);
469 } while (progress);
470
471 /* Must be run at the end to prevent creation of fsin/fcos ops */
472 NIR_PASS(progress, nir, midgard_nir_scale_trig);
473
474 do {
475 progress = false;
476
477 NIR_PASS(progress, nir, nir_opt_dce);
478 NIR_PASS(progress, nir, nir_opt_algebraic);
479 NIR_PASS(progress, nir, nir_opt_constant_folding);
480 NIR_PASS(progress, nir, nir_copy_prop);
481 } while (progress);
482
483 NIR_PASS(progress, nir, nir_opt_algebraic_late);
484
485 /* We implement booleans as 32-bit 0/~0 */
486 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
487
488 /* Now that booleans are lowered, we can run out late opts */
489 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
490
491 /* Lower mods for float ops only. Integer ops don't support modifiers
492 * (saturate doesn't make sense on integers, neg/abs require dedicated
493 * instructions) */
494
495 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
496 NIR_PASS(progress, nir, nir_copy_prop);
497 NIR_PASS(progress, nir, nir_opt_dce);
498
499 /* Take us out of SSA */
500 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
501 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
502
503 /* We are a vector architecture; write combine where possible */
504 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
505 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
506
507 NIR_PASS(progress, nir, nir_opt_dce);
508 }
509
510 /* Do not actually emit a load; instead, cache the constant for inlining */
511
512 static void
513 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
514 {
515 nir_ssa_def def = instr->def;
516
517 float *v = rzalloc_array(NULL, float, 4);
518 nir_const_load_to_arr(v, instr, f32);
519
520 /* Shifted for SSA, +1 for off-by-one */
521 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, v);
522 }
523
524 /* Normally constants are embedded implicitly, but for I/O and such we have to
525 * explicitly emit a move with the constant source */
526
527 static void
528 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
529 {
530 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
531
532 if (constant_value) {
533 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, to);
534 attach_constants(ctx, &ins, constant_value, node + 1);
535 emit_mir_instruction(ctx, ins);
536 }
537 }
538
539 static bool
540 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
541 {
542 unsigned comp = src->swizzle[0];
543
544 for (unsigned c = 1; c < nr_components; ++c) {
545 if (src->swizzle[c] != comp)
546 return true;
547 }
548
549 return false;
550 }
551
552 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
553 * output of a conditional test) into that register */
554
555 static void
556 emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned component)
557 {
558 int condition = nir_src_index(ctx, src);
559
560 /* Source to swizzle the desired component into w */
561
562 const midgard_vector_alu_src alu_src = {
563 .swizzle = SWIZZLE(component, component, component, component),
564 };
565
566 /* There is no boolean move instruction. Instead, we simulate a move by
567 * ANDing the condition with itself to get it into r31.w */
568
569 midgard_instruction ins = {
570 .type = TAG_ALU_4,
571
572 /* We need to set the conditional as close as possible */
573 .precede_break = true,
574 .unit = for_branch ? UNIT_SMUL : UNIT_SADD,
575 .mask = 1 << COMPONENT_W,
576
577 .ssa_args = {
578 .src0 = condition,
579 .src1 = condition,
580 .dest = SSA_FIXED_REGISTER(31),
581 },
582
583 .alu = {
584 .op = midgard_alu_op_iand,
585 .outmod = midgard_outmod_int_wrap,
586 .reg_mode = midgard_reg_mode_32,
587 .dest_override = midgard_dest_override_none,
588 .src1 = vector_alu_srco_unsigned(alu_src),
589 .src2 = vector_alu_srco_unsigned(alu_src)
590 },
591 };
592
593 emit_mir_instruction(ctx, ins);
594 }
595
596 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
597 * r31 instead */
598
599 static void
600 emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp)
601 {
602 int condition = nir_src_index(ctx, &src->src);
603
604 /* Source to swizzle the desired component into w */
605
606 const midgard_vector_alu_src alu_src = {
607 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle),
608 };
609
610 /* There is no boolean move instruction. Instead, we simulate a move by
611 * ANDing the condition with itself to get it into r31.w */
612
613 midgard_instruction ins = {
614 .type = TAG_ALU_4,
615 .precede_break = true,
616 .mask = mask_of(nr_comp),
617 .ssa_args = {
618 .src0 = condition,
619 .src1 = condition,
620 .dest = SSA_FIXED_REGISTER(31),
621 },
622 .alu = {
623 .op = midgard_alu_op_iand,
624 .outmod = midgard_outmod_int_wrap,
625 .reg_mode = midgard_reg_mode_32,
626 .dest_override = midgard_dest_override_none,
627 .src1 = vector_alu_srco_unsigned(alu_src),
628 .src2 = vector_alu_srco_unsigned(alu_src)
629 },
630 };
631
632 emit_mir_instruction(ctx, ins);
633 }
634
635
636
637 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
638 * pinning to eliminate this move in all known cases */
639
640 static void
641 emit_indirect_offset(compiler_context *ctx, nir_src *src)
642 {
643 int offset = nir_src_index(ctx, src);
644
645 midgard_instruction ins = {
646 .type = TAG_ALU_4,
647 .mask = 1 << COMPONENT_W,
648 .ssa_args = {
649 .src0 = SSA_UNUSED_1,
650 .src1 = offset,
651 .dest = SSA_FIXED_REGISTER(REGISTER_OFFSET),
652 },
653 .alu = {
654 .op = midgard_alu_op_imov,
655 .outmod = midgard_outmod_int_wrap,
656 .reg_mode = midgard_reg_mode_32,
657 .dest_override = midgard_dest_override_none,
658 .src1 = vector_alu_srco_unsigned(zero_alu_src),
659 .src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx)
660 },
661 };
662
663 emit_mir_instruction(ctx, ins);
664 }
665
666 #define ALU_CASE(nir, _op) \
667 case nir_op_##nir: \
668 op = midgard_alu_op_##_op; \
669 assert(src_bitsize == dst_bitsize); \
670 break;
671
672 #define ALU_CASE_BCAST(nir, _op, count) \
673 case nir_op_##nir: \
674 op = midgard_alu_op_##_op; \
675 broadcast_swizzle = count; \
676 assert(src_bitsize == dst_bitsize); \
677 break;
678 static bool
679 nir_is_fzero_constant(nir_src src)
680 {
681 if (!nir_src_is_const(src))
682 return false;
683
684 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
685 if (nir_src_comp_as_float(src, c) != 0.0)
686 return false;
687 }
688
689 return true;
690 }
691
692 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
693 * special treatment override this anyway. */
694
695 static midgard_reg_mode
696 reg_mode_for_nir(nir_alu_instr *instr)
697 {
698 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
699
700 switch (src_bitsize) {
701 case 8:
702 return midgard_reg_mode_8;
703 case 16:
704 return midgard_reg_mode_16;
705 case 32:
706 return midgard_reg_mode_32;
707 case 64:
708 return midgard_reg_mode_64;
709 default:
710 unreachable("Invalid bit size");
711 }
712 }
713
714 static void
715 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
716 {
717 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
718 * is handled elsewhere */
719
720 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
721 midgard_emit_derivatives(ctx, instr);
722 return;
723 }
724
725 bool is_ssa = instr->dest.dest.is_ssa;
726
727 unsigned dest = nir_dest_index(ctx, &instr->dest.dest);
728 unsigned nr_components = nir_dest_num_components(instr->dest.dest);
729 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
730
731 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
732 * supported. A few do not and are commented for now. Also, there are a
733 * number of NIR ops which Midgard does not support and need to be
734 * lowered, also TODO. This switch block emits the opcode and calling
735 * convention of the Midgard instruction; actual packing is done in
736 * emit_alu below */
737
738 unsigned op;
739
740 /* Number of components valid to check for the instruction (the rest
741 * will be forced to the last), or 0 to use as-is. Relevant as
742 * ball-type instructions have a channel count in NIR but are all vec4
743 * in Midgard */
744
745 unsigned broadcast_swizzle = 0;
746
747 /* What register mode should we operate in? */
748 midgard_reg_mode reg_mode =
749 reg_mode_for_nir(instr);
750
751 /* Do we need a destination override? Used for inline
752 * type conversion */
753
754 midgard_dest_override dest_override =
755 midgard_dest_override_none;
756
757 /* Should we use a smaller respective source and sign-extend? */
758
759 bool half_1 = false, sext_1 = false;
760 bool half_2 = false, sext_2 = false;
761
762 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
763 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
764
765 switch (instr->op) {
766 ALU_CASE(fadd, fadd);
767 ALU_CASE(fmul, fmul);
768 ALU_CASE(fmin, fmin);
769 ALU_CASE(fmax, fmax);
770 ALU_CASE(imin, imin);
771 ALU_CASE(imax, imax);
772 ALU_CASE(umin, umin);
773 ALU_CASE(umax, umax);
774 ALU_CASE(ffloor, ffloor);
775 ALU_CASE(fround_even, froundeven);
776 ALU_CASE(ftrunc, ftrunc);
777 ALU_CASE(fceil, fceil);
778 ALU_CASE(fdot3, fdot3);
779 ALU_CASE(fdot4, fdot4);
780 ALU_CASE(iadd, iadd);
781 ALU_CASE(isub, isub);
782 ALU_CASE(imul, imul);
783
784 /* Zero shoved as second-arg */
785 ALU_CASE(iabs, iabsdiff);
786
787 ALU_CASE(mov, imov);
788
789 ALU_CASE(feq32, feq);
790 ALU_CASE(fne32, fne);
791 ALU_CASE(flt32, flt);
792 ALU_CASE(ieq32, ieq);
793 ALU_CASE(ine32, ine);
794 ALU_CASE(ilt32, ilt);
795 ALU_CASE(ult32, ult);
796
797 /* We don't have a native b2f32 instruction. Instead, like many
798 * GPUs, we exploit booleans as 0/~0 for false/true, and
799 * correspondingly AND
800 * by 1.0 to do the type conversion. For the moment, prime us
801 * to emit:
802 *
803 * iand [whatever], #0
804 *
805 * At the end of emit_alu (as MIR), we'll fix-up the constant
806 */
807
808 ALU_CASE(b2f32, iand);
809 ALU_CASE(b2i32, iand);
810
811 /* Likewise, we don't have a dedicated f2b32 instruction, but
812 * we can do a "not equal to 0.0" test. */
813
814 ALU_CASE(f2b32, fne);
815 ALU_CASE(i2b32, ine);
816
817 ALU_CASE(frcp, frcp);
818 ALU_CASE(frsq, frsqrt);
819 ALU_CASE(fsqrt, fsqrt);
820 ALU_CASE(fexp2, fexp2);
821 ALU_CASE(flog2, flog2);
822
823 ALU_CASE(f2i32, f2i_rtz);
824 ALU_CASE(f2u32, f2u_rtz);
825 ALU_CASE(i2f32, i2f_rtz);
826 ALU_CASE(u2f32, u2f_rtz);
827
828 ALU_CASE(f2i16, f2i_rtz);
829 ALU_CASE(f2u16, f2u_rtz);
830 ALU_CASE(i2f16, i2f_rtz);
831 ALU_CASE(u2f16, u2f_rtz);
832
833 ALU_CASE(fsin, fsin);
834 ALU_CASE(fcos, fcos);
835
836 /* We'll set invert */
837 ALU_CASE(inot, imov);
838 ALU_CASE(iand, iand);
839 ALU_CASE(ior, ior);
840 ALU_CASE(ixor, ixor);
841 ALU_CASE(ishl, ishl);
842 ALU_CASE(ishr, iasr);
843 ALU_CASE(ushr, ilsr);
844
845 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
846 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
847 ALU_CASE(b32all_fequal4, fball_eq);
848
849 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
850 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
851 ALU_CASE(b32any_fnequal4, fbany_neq);
852
853 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
854 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
855 ALU_CASE(b32all_iequal4, iball_eq);
856
857 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
858 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
859 ALU_CASE(b32any_inequal4, ibany_neq);
860
861 /* Source mods will be shoved in later */
862 ALU_CASE(fabs, fmov);
863 ALU_CASE(fneg, fmov);
864 ALU_CASE(fsat, fmov);
865
866 /* For size conversion, we use a move. Ideally though we would squash
867 * these ops together; maybe that has to happen after in NIR as part of
868 * propagation...? An earlier algebraic pass ensured we step down by
869 * only / exactly one size. If stepping down, we use a dest override to
870 * reduce the size; if stepping up, we use a larger-sized move with a
871 * half source and a sign/zero-extension modifier */
872
873 case nir_op_i2i8:
874 case nir_op_i2i16:
875 case nir_op_i2i32:
876 /* If we end up upscale, we'll need a sign-extend on the
877 * operand (the second argument) */
878
879 sext_2 = true;
880 case nir_op_u2u8:
881 case nir_op_u2u16:
882 case nir_op_u2u32: {
883 op = midgard_alu_op_imov;
884
885 if (dst_bitsize == (src_bitsize * 2)) {
886 /* Converting up */
887 half_2 = true;
888
889 /* Use a greater register mode */
890 reg_mode++;
891 } else if (src_bitsize == (dst_bitsize * 2)) {
892 /* Converting down */
893 dest_override = midgard_dest_override_lower;
894 }
895
896 break;
897 }
898
899 case nir_op_f2f16: {
900 assert(src_bitsize == 32);
901
902 op = midgard_alu_op_fmov;
903 dest_override = midgard_dest_override_lower;
904 break;
905 }
906
907 case nir_op_f2f32: {
908 assert(src_bitsize == 16);
909
910 op = midgard_alu_op_fmov;
911 half_2 = true;
912 reg_mode++;
913 break;
914 }
915
916
917 /* For greater-or-equal, we lower to less-or-equal and flip the
918 * arguments */
919
920 case nir_op_fge:
921 case nir_op_fge32:
922 case nir_op_ige32:
923 case nir_op_uge32: {
924 op =
925 instr->op == nir_op_fge ? midgard_alu_op_fle :
926 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
927 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
928 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
929 0;
930
931 /* Swap via temporary */
932 nir_alu_src temp = instr->src[1];
933 instr->src[1] = instr->src[0];
934 instr->src[0] = temp;
935
936 break;
937 }
938
939 case nir_op_b32csel: {
940 /* Midgard features both fcsel and icsel, depending on
941 * the type of the arguments/output. However, as long
942 * as we're careful we can _always_ use icsel and
943 * _never_ need fcsel, since the latter does additional
944 * floating-point-specific processing whereas the
945 * former just moves bits on the wire. It's not obvious
946 * why these are separate opcodes, save for the ability
947 * to do things like sat/pos/abs/neg for free */
948
949 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
950 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
951
952 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
953 nr_inputs = 2;
954
955 /* Emit the condition into r31 */
956
957 if (mixed)
958 emit_condition_mixed(ctx, &instr->src[0], nr_components);
959 else
960 emit_condition(ctx, &instr->src[0].src, false, instr->src[0].swizzle[0]);
961
962 /* The condition is the first argument; move the other
963 * arguments up one to be a binary instruction for
964 * Midgard */
965
966 memmove(instr->src, instr->src + 1, 2 * sizeof(nir_alu_src));
967 break;
968 }
969
970 default:
971 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
972 assert(0);
973 return;
974 }
975
976 /* Midgard can perform certain modifiers on output of an ALU op */
977 unsigned outmod;
978
979 if (midgard_is_integer_out_op(op)) {
980 outmod = midgard_outmod_int_wrap;
981 } else {
982 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
983 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
984 }
985
986 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
987
988 if (instr->op == nir_op_fmax) {
989 if (nir_is_fzero_constant(instr->src[0].src)) {
990 op = midgard_alu_op_fmov;
991 nr_inputs = 1;
992 outmod = midgard_outmod_pos;
993 instr->src[0] = instr->src[1];
994 } else if (nir_is_fzero_constant(instr->src[1].src)) {
995 op = midgard_alu_op_fmov;
996 nr_inputs = 1;
997 outmod = midgard_outmod_pos;
998 }
999 }
1000
1001 /* Fetch unit, quirks, etc information */
1002 unsigned opcode_props = alu_opcode_props[op].props;
1003 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
1004
1005 /* src0 will always exist afaik, but src1 will not for 1-argument
1006 * instructions. The latter can only be fetched if the instruction
1007 * needs it, or else we may segfault. */
1008
1009 unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
1010 unsigned src1 = nr_inputs == 2 ? nir_alu_src_index(ctx, &instr->src[1]) : SSA_UNUSED_0;
1011
1012 /* Rather than use the instruction generation helpers, we do it
1013 * ourselves here to avoid the mess */
1014
1015 midgard_instruction ins = {
1016 .type = TAG_ALU_4,
1017 .ssa_args = {
1018 .src0 = quirk_flipped_r24 ? SSA_UNUSED_1 : src0,
1019 .src1 = quirk_flipped_r24 ? src0 : src1,
1020 .dest = dest,
1021 }
1022 };
1023
1024 nir_alu_src *nirmods[2] = { NULL };
1025
1026 if (nr_inputs == 2) {
1027 nirmods[0] = &instr->src[0];
1028 nirmods[1] = &instr->src[1];
1029 } else if (nr_inputs == 1) {
1030 nirmods[quirk_flipped_r24] = &instr->src[0];
1031 } else {
1032 assert(0);
1033 }
1034
1035 /* These were lowered to a move, so apply the corresponding mod */
1036
1037 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1038 nir_alu_src *s = nirmods[quirk_flipped_r24];
1039
1040 if (instr->op == nir_op_fneg)
1041 s->negate = !s->negate;
1042
1043 if (instr->op == nir_op_fabs)
1044 s->abs = !s->abs;
1045 }
1046
1047 bool is_int = midgard_is_integer_op(op);
1048
1049 ins.mask = mask_of(nr_components);
1050
1051 midgard_vector_alu alu = {
1052 .op = op,
1053 .reg_mode = reg_mode,
1054 .dest_override = dest_override,
1055 .outmod = outmod,
1056
1057 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)),
1058 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)),
1059 };
1060
1061 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1062
1063 if (!is_ssa)
1064 ins.mask &= instr->dest.write_mask;
1065
1066 ins.alu = alu;
1067
1068 /* Late fixup for emulated instructions */
1069
1070 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1071 /* Presently, our second argument is an inline #0 constant.
1072 * Switch over to an embedded 1.0 constant (that can't fit
1073 * inline, since we're 32-bit, not 16-bit like the inline
1074 * constants) */
1075
1076 ins.ssa_args.inline_constant = false;
1077 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1078 ins.has_constants = true;
1079
1080 if (instr->op == nir_op_b2f32) {
1081 ins.constants[0] = 1.0f;
1082 } else {
1083 /* Type pun it into place */
1084 uint32_t one = 0x1;
1085 memcpy(&ins.constants[0], &one, sizeof(uint32_t));
1086 }
1087
1088 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
1089 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1090 /* Lots of instructions need a 0 plonked in */
1091 ins.ssa_args.inline_constant = false;
1092 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1093 ins.has_constants = true;
1094 ins.constants[0] = 0.0f;
1095 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
1096 } else if (instr->op == nir_op_inot) {
1097 ins.invert = true;
1098 }
1099
1100 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1101 /* To avoid duplicating the lookup tables (probably), true LUT
1102 * instructions can only operate as if they were scalars. Lower
1103 * them here by changing the component. */
1104
1105 uint8_t original_swizzle[4];
1106 memcpy(original_swizzle, nirmods[0]->swizzle, sizeof(nirmods[0]->swizzle));
1107 unsigned orig_mask = ins.mask;
1108
1109 for (int i = 0; i < nr_components; ++i) {
1110 /* Mask the associated component, dropping the
1111 * instruction if needed */
1112
1113 ins.mask = 1 << i;
1114 ins.mask &= orig_mask;
1115
1116 if (!ins.mask)
1117 continue;
1118
1119 for (int j = 0; j < 4; ++j)
1120 nirmods[0]->swizzle[j] = original_swizzle[i]; /* Pull from the correct component */
1121
1122 ins.alu.src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, false));
1123 emit_mir_instruction(ctx, ins);
1124 }
1125 } else {
1126 emit_mir_instruction(ctx, ins);
1127 }
1128 }
1129
1130 #undef ALU_CASE
1131
1132 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1133 * optimized) versions of UBO #0 */
1134
1135 void
1136 emit_ubo_read(
1137 compiler_context *ctx,
1138 unsigned dest,
1139 unsigned offset,
1140 nir_src *indirect_offset,
1141 unsigned index)
1142 {
1143 /* TODO: half-floats */
1144
1145 midgard_instruction ins = m_ld_uniform_32(dest, offset);
1146
1147 /* TODO: Don't split */
1148 ins.load_store.varying_parameters = (offset & 7) << 7;
1149 ins.load_store.address = offset >> 3;
1150
1151 if (indirect_offset) {
1152 emit_indirect_offset(ctx, indirect_offset);
1153 ins.load_store.unknown = 0x8700 | index; /* xxx: what is this? */
1154 } else {
1155 ins.load_store.unknown = 0x1E00 | index; /* xxx: what is this? */
1156 }
1157
1158 emit_mir_instruction(ctx, ins);
1159 }
1160
1161 static void
1162 emit_varying_read(
1163 compiler_context *ctx,
1164 unsigned dest, unsigned offset,
1165 unsigned nr_comp, unsigned component,
1166 nir_src *indirect_offset, nir_alu_type type)
1167 {
1168 /* XXX: Half-floats? */
1169 /* TODO: swizzle, mask */
1170
1171 midgard_instruction ins = m_ld_vary_32(dest, offset);
1172 ins.mask = mask_of(nr_comp);
1173 ins.load_store.swizzle = SWIZZLE_XYZW >> (2 * component);
1174
1175 midgard_varying_parameter p = {
1176 .is_varying = 1,
1177 .interpolation = midgard_interp_default,
1178 .flat = /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1179 };
1180
1181 unsigned u;
1182 memcpy(&u, &p, sizeof(p));
1183 ins.load_store.varying_parameters = u;
1184
1185 if (indirect_offset) {
1186 /* We need to add in the dynamic index, moved to r27.w */
1187 emit_indirect_offset(ctx, indirect_offset);
1188 ins.load_store.unknown = 0x79e; /* xxx: what is this? */
1189 } else {
1190 /* Just a direct load */
1191 ins.load_store.unknown = 0x1e9e; /* xxx: what is this? */
1192 }
1193
1194 /* Use the type appropriate load */
1195 switch (type) {
1196 case nir_type_uint:
1197 case nir_type_bool:
1198 ins.load_store.op = midgard_op_ld_vary_32u;
1199 break;
1200 case nir_type_int:
1201 ins.load_store.op = midgard_op_ld_vary_32i;
1202 break;
1203 case nir_type_float:
1204 ins.load_store.op = midgard_op_ld_vary_32;
1205 break;
1206 default:
1207 unreachable("Attempted to load unknown type");
1208 break;
1209 }
1210
1211 emit_mir_instruction(ctx, ins);
1212 }
1213
1214 static void
1215 emit_sysval_read(compiler_context *ctx, nir_instr *instr)
1216 {
1217 unsigned dest = 0;
1218
1219 /* Figure out which uniform this is */
1220 int sysval = sysval_for_instr(ctx, instr, &dest);
1221 void *val = _mesa_hash_table_u64_search(ctx->sysval_to_id, sysval);
1222
1223 /* Sysvals are prefix uniforms */
1224 unsigned uniform = ((uintptr_t) val) - 1;
1225
1226 /* Emit the read itself -- this is never indirect */
1227 emit_ubo_read(ctx, dest, uniform, NULL, 0);
1228 }
1229
1230 static void
1231 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1232 {
1233 unsigned offset = 0, reg;
1234
1235 switch (instr->intrinsic) {
1236 case nir_intrinsic_discard_if:
1237 emit_condition(ctx, &instr->src[0], true, COMPONENT_X);
1238
1239 /* fallthrough */
1240
1241 case nir_intrinsic_discard: {
1242 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1243 struct midgard_instruction discard = v_branch(conditional, false);
1244 discard.branch.target_type = TARGET_DISCARD;
1245 emit_mir_instruction(ctx, discard);
1246 break;
1247 }
1248
1249 case nir_intrinsic_load_uniform:
1250 case nir_intrinsic_load_ubo:
1251 case nir_intrinsic_load_input: {
1252 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1253 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1254
1255 /* Get the base type of the intrinsic */
1256 /* TODO: Infer type? Does it matter? */
1257 nir_alu_type t =
1258 is_ubo ? nir_type_uint : nir_intrinsic_type(instr);
1259 t = nir_alu_type_get_base_type(t);
1260
1261 if (!is_ubo) {
1262 offset = nir_intrinsic_base(instr);
1263 }
1264
1265 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1266
1267 nir_src *src_offset = nir_get_io_offset_src(instr);
1268
1269 bool direct = nir_src_is_const(*src_offset);
1270
1271 if (direct)
1272 offset += nir_src_as_uint(*src_offset);
1273
1274 /* We may need to apply a fractional offset */
1275 int component = instr->intrinsic == nir_intrinsic_load_input ?
1276 nir_intrinsic_component(instr) : 0;
1277 reg = nir_dest_index(ctx, &instr->dest);
1278
1279 if (is_uniform && !ctx->is_blend) {
1280 emit_ubo_read(ctx, reg, ctx->sysval_count + offset, !direct ? &instr->src[0] : NULL, 0);
1281 } else if (is_ubo) {
1282 nir_src index = instr->src[0];
1283
1284 /* We don't yet support indirect UBOs. For indirect
1285 * block numbers (if that's possible), we don't know
1286 * enough about the hardware yet. For indirect sources,
1287 * we know what we need but we need to add some NIR
1288 * support for lowering correctly with respect to
1289 * 128-bit reads */
1290
1291 assert(nir_src_is_const(index));
1292 assert(nir_src_is_const(*src_offset));
1293
1294 /* TODO: Alignment */
1295 assert((offset & 0xF) == 0);
1296
1297 uint32_t uindex = nir_src_as_uint(index) + 1;
1298 emit_ubo_read(ctx, reg, offset / 16, NULL, uindex);
1299 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1300 emit_varying_read(ctx, reg, offset, nr_comp, component, !direct ? &instr->src[0] : NULL, t);
1301 } else if (ctx->is_blend) {
1302 /* For blend shaders, load the input color, which is
1303 * preloaded to r0 */
1304
1305 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), blank_alu_src, reg);
1306 emit_mir_instruction(ctx, move);
1307 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1308 midgard_instruction ins = m_ld_attr_32(reg, offset);
1309 ins.load_store.unknown = 0x1E1E; /* XXX: What is this? */
1310 ins.mask = mask_of(nr_comp);
1311
1312 /* Use the type appropriate load */
1313 switch (t) {
1314 case nir_type_uint:
1315 case nir_type_bool:
1316 ins.load_store.op = midgard_op_ld_attr_32u;
1317 break;
1318 case nir_type_int:
1319 ins.load_store.op = midgard_op_ld_attr_32i;
1320 break;
1321 case nir_type_float:
1322 ins.load_store.op = midgard_op_ld_attr_32;
1323 break;
1324 default:
1325 unreachable("Attempted to load unknown type");
1326 break;
1327 }
1328
1329 emit_mir_instruction(ctx, ins);
1330 } else {
1331 DBG("Unknown load\n");
1332 assert(0);
1333 }
1334
1335 break;
1336 }
1337
1338 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1339
1340 case nir_intrinsic_load_raw_output_pan:
1341 reg = nir_dest_index(ctx, &instr->dest);
1342 assert(ctx->is_blend);
1343
1344 midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
1345 emit_mir_instruction(ctx, ins);
1346 break;
1347
1348 case nir_intrinsic_load_blend_const_color_rgba: {
1349 assert(ctx->is_blend);
1350 reg = nir_dest_index(ctx, &instr->dest);
1351
1352 /* Blend constants are embedded directly in the shader and
1353 * patched in, so we use some magic routing */
1354
1355 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, reg);
1356 ins.has_constants = true;
1357 ins.has_blend_constant = true;
1358 emit_mir_instruction(ctx, ins);
1359 break;
1360 }
1361
1362 case nir_intrinsic_store_output:
1363 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1364
1365 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1366
1367 reg = nir_src_index(ctx, &instr->src[0]);
1368
1369 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1370 /* gl_FragColor is not emitted with load/store
1371 * instructions. Instead, it gets plonked into
1372 * r0 at the end of the shader and we do the
1373 * framebuffer writeout dance. TODO: Defer
1374 * writes */
1375
1376 midgard_instruction move = v_mov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1377 emit_mir_instruction(ctx, move);
1378
1379 /* Save the index we're writing to for later reference
1380 * in the epilogue */
1381
1382 ctx->fragment_output = reg;
1383 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1384 /* We should have been vectorized, though we don't
1385 * currently check that st_vary is emitted only once
1386 * per slot (this is relevant, since there's not a mask
1387 * parameter available on the store [set to 0 by the
1388 * blob]). We do respect the component by adjusting the
1389 * swizzle. If this is a constant source, we'll need to
1390 * emit that explicitly. */
1391
1392 emit_explicit_constant(ctx, reg, reg);
1393
1394 unsigned component = nir_intrinsic_component(instr);
1395
1396 midgard_instruction st = m_st_vary_32(reg, offset);
1397 st.load_store.unknown = 0x1E9E; /* XXX: What is this? */
1398 st.load_store.swizzle = SWIZZLE_XYZW << (2*component);
1399 emit_mir_instruction(ctx, st);
1400 } else {
1401 DBG("Unknown store\n");
1402 assert(0);
1403 }
1404
1405 break;
1406
1407 /* Special case of store_output for lowered blend shaders */
1408 case nir_intrinsic_store_raw_output_pan:
1409 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1410 reg = nir_src_index(ctx, &instr->src[0]);
1411
1412 midgard_instruction move = v_mov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1413 emit_mir_instruction(ctx, move);
1414 ctx->fragment_output = reg;
1415
1416 break;
1417
1418 case nir_intrinsic_load_alpha_ref_float:
1419 assert(instr->dest.is_ssa);
1420
1421 float ref_value = ctx->alpha_ref;
1422
1423 /* See emit_load_const */
1424 float *v = ralloc_array(NULL, float, 4);
1425 memcpy(v, &ref_value, sizeof(float));
1426 _mesa_hash_table_u64_insert(ctx->ssa_constants, (instr->dest.ssa.index << 1) + 1, v);
1427 break;
1428
1429 case nir_intrinsic_load_viewport_scale:
1430 case nir_intrinsic_load_viewport_offset:
1431 emit_sysval_read(ctx, &instr->instr);
1432 break;
1433
1434 default:
1435 printf ("Unhandled intrinsic\n");
1436 assert(0);
1437 break;
1438 }
1439 }
1440
1441 static unsigned
1442 midgard_tex_format(enum glsl_sampler_dim dim)
1443 {
1444 switch (dim) {
1445 case GLSL_SAMPLER_DIM_1D:
1446 case GLSL_SAMPLER_DIM_BUF:
1447 return MALI_TEX_1D;
1448
1449 case GLSL_SAMPLER_DIM_2D:
1450 case GLSL_SAMPLER_DIM_EXTERNAL:
1451 return MALI_TEX_2D;
1452
1453 case GLSL_SAMPLER_DIM_3D:
1454 return MALI_TEX_3D;
1455
1456 case GLSL_SAMPLER_DIM_CUBE:
1457 return MALI_TEX_CUBE;
1458
1459 default:
1460 DBG("Unknown sampler dim type\n");
1461 assert(0);
1462 return 0;
1463 }
1464 }
1465
1466 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1467 * was successful */
1468
1469 static bool
1470 pan_attach_constant_bias(
1471 compiler_context *ctx,
1472 nir_src lod,
1473 midgard_texture_word *word)
1474 {
1475 /* To attach as constant, it has to *be* constant */
1476
1477 if (!nir_src_is_const(lod))
1478 return false;
1479
1480 float f = nir_src_as_float(lod);
1481
1482 /* Break into fixed-point */
1483 signed lod_int = f;
1484 float lod_frac = f - lod_int;
1485
1486 /* Carry over negative fractions */
1487 if (lod_frac < 0.0) {
1488 lod_int--;
1489 lod_frac += 1.0;
1490 }
1491
1492 /* Encode */
1493 word->bias = float_to_ubyte(lod_frac);
1494 word->bias_int = lod_int;
1495
1496 return true;
1497 }
1498
1499 static enum mali_sampler_type
1500 midgard_sampler_type(nir_alu_type t) {
1501 switch (nir_alu_type_get_base_type(t))
1502 {
1503 case nir_type_float:
1504 return MALI_SAMPLER_FLOAT;
1505 case nir_type_int:
1506 return MALI_SAMPLER_SIGNED;
1507 case nir_type_uint:
1508 return MALI_SAMPLER_UNSIGNED;
1509 default:
1510 unreachable("Unknown sampler type");
1511 }
1512 }
1513
1514 static void
1515 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1516 unsigned midgard_texop)
1517 {
1518 /* TODO */
1519 //assert (!instr->sampler);
1520 //assert (!instr->texture_array_size);
1521
1522 int texture_index = instr->texture_index;
1523 int sampler_index = texture_index;
1524
1525 /* No helper to build texture words -- we do it all here */
1526 midgard_instruction ins = {
1527 .type = TAG_TEXTURE_4,
1528 .mask = 0xF,
1529 .ssa_args = {
1530 .dest = nir_dest_index(ctx, &instr->dest),
1531 .src0 = -1,
1532 .src1 = -1,
1533 },
1534 .texture = {
1535 .op = midgard_texop,
1536 .format = midgard_tex_format(instr->sampler_dim),
1537 .texture_handle = texture_index,
1538 .sampler_handle = sampler_index,
1539 .swizzle = SWIZZLE_XYZW,
1540 .in_reg_swizzle = SWIZZLE_XYZW,
1541
1542 /* TODO: half */
1543 .in_reg_full = 1,
1544 .out_full = 1,
1545
1546 .sampler_type = midgard_sampler_type(instr->dest_type),
1547 }
1548 };
1549
1550 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1551 int index = nir_src_index(ctx, &instr->src[i].src);
1552 midgard_vector_alu_src alu_src = blank_alu_src;
1553
1554 switch (instr->src[i].src_type) {
1555 case nir_tex_src_coord: {
1556 emit_explicit_constant(ctx, index, index);
1557
1558 /* Texelfetch coordinates uses all four elements
1559 * (xyz/index) regardless of texture dimensionality,
1560 * which means it's necessary to zero the unused
1561 * components to keep everything happy */
1562
1563 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1564 unsigned old_index = index;
1565
1566 index = make_compiler_temp(ctx);
1567
1568 /* mov index, old_index */
1569 midgard_instruction mov = v_mov(old_index, blank_alu_src, index);
1570 mov.mask = 0x3;
1571 emit_mir_instruction(ctx, mov);
1572
1573 /* mov index.zw, #0 */
1574 mov = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT),
1575 blank_alu_src, index);
1576 mov.has_constants = true;
1577 mov.mask = (1 << COMPONENT_Z) | (1 << COMPONENT_W);
1578 emit_mir_instruction(ctx, mov);
1579 }
1580
1581 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1582 /* texelFetch is undefined on samplerCube */
1583 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1584
1585 /* For cubemaps, we use a special ld/st op to
1586 * select the face and copy the xy into the
1587 * texture register */
1588
1589 unsigned temp = make_compiler_temp(ctx);
1590
1591 midgard_instruction st = m_st_cubemap_coords(temp, 0);
1592 st.ssa_args.src0 = index;
1593 st.load_store.unknown = 0x24; /* XXX: What is this? */
1594 st.mask = 0x3; /* xy */
1595 st.load_store.swizzle = alu_src.swizzle;
1596 emit_mir_instruction(ctx, st);
1597
1598 ins.ssa_args.src0 = temp;
1599 } else {
1600 ins.ssa_args.src0 = index;
1601 }
1602
1603 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1604 /* Array component in w but NIR wants it in z */
1605 ins.texture.in_reg_swizzle = SWIZZLE_XYZZ;
1606 }
1607
1608 break;
1609 }
1610
1611 case nir_tex_src_bias:
1612 case nir_tex_src_lod: {
1613 /* Try as a constant if we can */
1614
1615 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1616 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1617 break;
1618
1619 ins.texture.lod_register = true;
1620 ins.ssa_args.src1 = index;
1621 emit_explicit_constant(ctx, index, index);
1622
1623 break;
1624 };
1625
1626 default:
1627 unreachable("Unknown texture source type\n");
1628 }
1629 }
1630
1631 emit_mir_instruction(ctx, ins);
1632
1633 /* Used for .cont and .last hinting */
1634 ctx->texture_op_count++;
1635 }
1636
1637 static void
1638 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1639 {
1640 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1641 * generic tex in some cases (which confuses the hardware) */
1642
1643 bool is_vertex = ctx->stage == MESA_SHADER_VERTEX;
1644
1645 if (is_vertex && instr->op == nir_texop_tex)
1646 instr->op = nir_texop_txl;
1647
1648 switch (instr->op) {
1649 case nir_texop_tex:
1650 case nir_texop_txb:
1651 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1652 break;
1653 case nir_texop_txl:
1654 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1655 break;
1656 case nir_texop_txf:
1657 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1658 break;
1659 case nir_texop_txs:
1660 emit_sysval_read(ctx, &instr->instr);
1661 break;
1662 default:
1663 unreachable("Unhanlded texture op");
1664 }
1665 }
1666
1667 static void
1668 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1669 {
1670 switch (instr->type) {
1671 case nir_jump_break: {
1672 /* Emit a branch out of the loop */
1673 struct midgard_instruction br = v_branch(false, false);
1674 br.branch.target_type = TARGET_BREAK;
1675 br.branch.target_break = ctx->current_loop_depth;
1676 emit_mir_instruction(ctx, br);
1677 break;
1678 }
1679
1680 default:
1681 DBG("Unknown jump type %d\n", instr->type);
1682 break;
1683 }
1684 }
1685
1686 static void
1687 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1688 {
1689 switch (instr->type) {
1690 case nir_instr_type_load_const:
1691 emit_load_const(ctx, nir_instr_as_load_const(instr));
1692 break;
1693
1694 case nir_instr_type_intrinsic:
1695 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1696 break;
1697
1698 case nir_instr_type_alu:
1699 emit_alu(ctx, nir_instr_as_alu(instr));
1700 break;
1701
1702 case nir_instr_type_tex:
1703 emit_tex(ctx, nir_instr_as_tex(instr));
1704 break;
1705
1706 case nir_instr_type_jump:
1707 emit_jump(ctx, nir_instr_as_jump(instr));
1708 break;
1709
1710 case nir_instr_type_ssa_undef:
1711 /* Spurious */
1712 break;
1713
1714 default:
1715 DBG("Unhandled instruction type\n");
1716 break;
1717 }
1718 }
1719
1720
1721 /* ALU instructions can inline or embed constants, which decreases register
1722 * pressure and saves space. */
1723
1724 #define CONDITIONAL_ATTACH(src) { \
1725 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1726 \
1727 if (entry) { \
1728 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1729 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1730 } \
1731 }
1732
1733 static void
1734 inline_alu_constants(compiler_context *ctx)
1735 {
1736 mir_foreach_instr(ctx, alu) {
1737 /* Other instructions cannot inline constants */
1738 if (alu->type != TAG_ALU_4) continue;
1739
1740 /* If there is already a constant here, we can do nothing */
1741 if (alu->has_constants) continue;
1742
1743 /* It makes no sense to inline constants on a branch */
1744 if (alu->compact_branch || alu->prepacked_branch) continue;
1745
1746 CONDITIONAL_ATTACH(src0);
1747
1748 if (!alu->has_constants) {
1749 CONDITIONAL_ATTACH(src1)
1750 } else if (!alu->inline_constant) {
1751 /* Corner case: _two_ vec4 constants, for instance with a
1752 * csel. For this case, we can only use a constant
1753 * register for one, we'll have to emit a move for the
1754 * other. Note, if both arguments are constants, then
1755 * necessarily neither argument depends on the value of
1756 * any particular register. As the destination register
1757 * will be wiped, that means we can spill the constant
1758 * to the destination register.
1759 */
1760
1761 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src1 + 1);
1762 unsigned scratch = alu->ssa_args.dest;
1763
1764 if (entry) {
1765 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, scratch);
1766 attach_constants(ctx, &ins, entry, alu->ssa_args.src1 + 1);
1767
1768 /* Force a break XXX Defer r31 writes */
1769 ins.unit = UNIT_VLUT;
1770
1771 /* Set the source */
1772 alu->ssa_args.src1 = scratch;
1773
1774 /* Inject us -before- the last instruction which set r31 */
1775 mir_insert_instruction_before(mir_prev_op(alu), ins);
1776 }
1777 }
1778 }
1779 }
1780
1781 /* Midgard supports two types of constants, embedded constants (128-bit) and
1782 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1783 * constants can be demoted to inline constants, for space savings and
1784 * sometimes a performance boost */
1785
1786 static void
1787 embedded_to_inline_constant(compiler_context *ctx)
1788 {
1789 mir_foreach_instr(ctx, ins) {
1790 if (!ins->has_constants) continue;
1791
1792 if (ins->ssa_args.inline_constant) continue;
1793
1794 /* Blend constants must not be inlined by definition */
1795 if (ins->has_blend_constant) continue;
1796
1797 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
1798 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
1799 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
1800
1801 if (!(is_16 || is_32))
1802 continue;
1803
1804 /* src1 cannot be an inline constant due to encoding
1805 * restrictions. So, if possible we try to flip the arguments
1806 * in that case */
1807
1808 int op = ins->alu.op;
1809
1810 if (ins->ssa_args.src0 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1811 switch (op) {
1812 /* These ops require an operational change to flip
1813 * their arguments TODO */
1814 case midgard_alu_op_flt:
1815 case midgard_alu_op_fle:
1816 case midgard_alu_op_ilt:
1817 case midgard_alu_op_ile:
1818 case midgard_alu_op_fcsel:
1819 case midgard_alu_op_icsel:
1820 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
1821 default:
1822 break;
1823 }
1824
1825 if (alu_opcode_props[op].props & OP_COMMUTES) {
1826 /* Flip the SSA numbers */
1827 ins->ssa_args.src0 = ins->ssa_args.src1;
1828 ins->ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1829
1830 /* And flip the modifiers */
1831
1832 unsigned src_temp;
1833
1834 src_temp = ins->alu.src2;
1835 ins->alu.src2 = ins->alu.src1;
1836 ins->alu.src1 = src_temp;
1837 }
1838 }
1839
1840 if (ins->ssa_args.src1 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1841 /* Extract the source information */
1842
1843 midgard_vector_alu_src *src;
1844 int q = ins->alu.src2;
1845 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
1846 src = m;
1847
1848 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1849 int component = src->swizzle & 3;
1850
1851 /* Scale constant appropriately, if we can legally */
1852 uint16_t scaled_constant = 0;
1853
1854 if (midgard_is_integer_op(op) || is_16) {
1855 unsigned int *iconstants = (unsigned int *) ins->constants;
1856 scaled_constant = (uint16_t) iconstants[component];
1857
1858 /* Constant overflow after resize */
1859 if (scaled_constant != iconstants[component])
1860 continue;
1861 } else {
1862 float original = (float) ins->constants[component];
1863 scaled_constant = _mesa_float_to_half(original);
1864
1865 /* Check for loss of precision. If this is
1866 * mediump, we don't care, but for a highp
1867 * shader, we need to pay attention. NIR
1868 * doesn't yet tell us which mode we're in!
1869 * Practically this prevents most constants
1870 * from being inlined, sadly. */
1871
1872 float fp32 = _mesa_half_to_float(scaled_constant);
1873
1874 if (fp32 != original)
1875 continue;
1876 }
1877
1878 /* We don't know how to handle these with a constant */
1879
1880 bool is_int = midgard_is_integer_op(ins->alu.op);
1881 if (mir_nontrivial_raw_mod(*src, is_int) || src->half || src->rep_low || src->rep_high) {
1882 DBG("Bailing inline constant...\n");
1883 continue;
1884 }
1885
1886 /* Make sure that the constant is not itself a
1887 * vector by checking if all accessed values
1888 * (by the swizzle) are the same. */
1889
1890 uint32_t *cons = (uint32_t *) ins->constants;
1891 uint32_t value = cons[component];
1892
1893 bool is_vector = false;
1894 unsigned mask = effective_writemask(&ins->alu, ins->mask);
1895
1896 for (int c = 1; c < 4; ++c) {
1897 /* We only care if this component is actually used */
1898 if (!(mask & (1 << c)))
1899 continue;
1900
1901 uint32_t test = cons[(src->swizzle >> (2 * c)) & 3];
1902
1903 if (test != value) {
1904 is_vector = true;
1905 break;
1906 }
1907 }
1908
1909 if (is_vector)
1910 continue;
1911
1912 /* Get rid of the embedded constant */
1913 ins->has_constants = false;
1914 ins->ssa_args.src1 = SSA_UNUSED_0;
1915 ins->ssa_args.inline_constant = true;
1916 ins->inline_constant = scaled_constant;
1917 }
1918 }
1919 }
1920
1921 /* Dead code elimination for branches at the end of a block - only one branch
1922 * per block is legal semantically */
1923
1924 static void
1925 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
1926 {
1927 bool branched = false;
1928
1929 mir_foreach_instr_in_block_safe(block, ins) {
1930 if (!midgard_is_branch_unit(ins->unit)) continue;
1931
1932 /* We ignore prepacked branches since the fragment epilogue is
1933 * just generally special */
1934 if (ins->prepacked_branch) continue;
1935
1936 /* Discards are similarly special and may not correspond to the
1937 * end of a block */
1938
1939 if (ins->branch.target_type == TARGET_DISCARD) continue;
1940
1941 if (branched) {
1942 /* We already branched, so this is dead */
1943 mir_remove_instruction(ins);
1944 }
1945
1946 branched = true;
1947 }
1948 }
1949
1950 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
1951 * the move can be propagated away entirely */
1952
1953 static bool
1954 mir_compose_float_outmod(midgard_outmod_float *outmod, midgard_outmod_float comp)
1955 {
1956 /* Nothing to do */
1957 if (comp == midgard_outmod_none)
1958 return true;
1959
1960 if (*outmod == midgard_outmod_none) {
1961 *outmod = comp;
1962 return true;
1963 }
1964
1965 /* TODO: Compose rules */
1966 return false;
1967 }
1968
1969 static bool
1970 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
1971 {
1972 bool progress = false;
1973
1974 mir_foreach_instr_in_block_safe(block, ins) {
1975 if (ins->type != TAG_ALU_4) continue;
1976 if (ins->alu.op != midgard_alu_op_fmov) continue;
1977 if (ins->alu.outmod != midgard_outmod_pos) continue;
1978
1979 /* TODO: Registers? */
1980 unsigned src = ins->ssa_args.src1;
1981 if (src & IS_REG) continue;
1982 assert(!mir_has_multiple_writes(ctx, src));
1983
1984 /* There might be a source modifier, too */
1985 if (mir_nontrivial_source2_mod(ins)) continue;
1986
1987 /* Backpropagate the modifier */
1988 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
1989 if (v->type != TAG_ALU_4) continue;
1990 if (v->ssa_args.dest != src) continue;
1991
1992 /* Can we even take a float outmod? */
1993 if (midgard_is_integer_out_op(v->alu.op)) continue;
1994
1995 midgard_outmod_float temp = v->alu.outmod;
1996 progress |= mir_compose_float_outmod(&temp, ins->alu.outmod);
1997
1998 /* Throw in the towel.. */
1999 if (!progress) break;
2000
2001 /* Otherwise, transfer the modifier */
2002 v->alu.outmod = temp;
2003 ins->alu.outmod = midgard_outmod_none;
2004
2005 break;
2006 }
2007 }
2008
2009 return progress;
2010 }
2011
2012 static void
2013 emit_fragment_epilogue(compiler_context *ctx)
2014 {
2015 emit_explicit_constant(ctx, ctx->fragment_output, SSA_FIXED_REGISTER(0));
2016
2017 /* Perform the actual fragment writeout. We have two writeout/branch
2018 * instructions, forming a loop until writeout is successful as per the
2019 * docs. TODO: gl_FragDepth */
2020
2021 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2022 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2023 }
2024
2025 static midgard_block *
2026 emit_block(compiler_context *ctx, nir_block *block)
2027 {
2028 midgard_block *this_block = calloc(sizeof(midgard_block), 1);
2029 list_addtail(&this_block->link, &ctx->blocks);
2030
2031 this_block->is_scheduled = false;
2032 ++ctx->block_count;
2033
2034 ctx->texture_index[0] = -1;
2035 ctx->texture_index[1] = -1;
2036
2037 /* Add us as a successor to the block we are following */
2038 if (ctx->current_block)
2039 midgard_block_add_successor(ctx->current_block, this_block);
2040
2041 /* Set up current block */
2042 list_inithead(&this_block->instructions);
2043 ctx->current_block = this_block;
2044
2045 nir_foreach_instr(instr, block) {
2046 emit_instr(ctx, instr);
2047 ++ctx->instruction_count;
2048 }
2049
2050 inline_alu_constants(ctx);
2051 embedded_to_inline_constant(ctx);
2052
2053 /* Append fragment shader epilogue (value writeout) */
2054 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2055 if (block == nir_impl_last_block(ctx->func->impl)) {
2056 emit_fragment_epilogue(ctx);
2057 }
2058 }
2059
2060 if (block == nir_start_block(ctx->func->impl))
2061 ctx->initial_block = this_block;
2062
2063 if (block == nir_impl_last_block(ctx->func->impl))
2064 ctx->final_block = this_block;
2065
2066 /* Allow the next control flow to access us retroactively, for
2067 * branching etc */
2068 ctx->current_block = this_block;
2069
2070 /* Document the fallthrough chain */
2071 ctx->previous_source_block = this_block;
2072
2073 return this_block;
2074 }
2075
2076 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2077
2078 static void
2079 emit_if(struct compiler_context *ctx, nir_if *nif)
2080 {
2081 /* Conditional branches expect the condition in r31.w; emit a move for
2082 * that in the _previous_ block (which is the current block). */
2083 emit_condition(ctx, &nif->condition, true, COMPONENT_X);
2084
2085 /* Speculatively emit the branch, but we can't fill it in until later */
2086 EMIT(branch, true, true);
2087 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2088
2089 /* Emit the two subblocks */
2090 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2091
2092 /* Emit a jump from the end of the then block to the end of the else */
2093 EMIT(branch, false, false);
2094 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2095
2096 /* Emit second block, and check if it's empty */
2097
2098 int else_idx = ctx->block_count;
2099 int count_in = ctx->instruction_count;
2100 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2101 int after_else_idx = ctx->block_count;
2102
2103 /* Now that we have the subblocks emitted, fix up the branches */
2104
2105 assert(then_block);
2106 assert(else_block);
2107
2108 if (ctx->instruction_count == count_in) {
2109 /* The else block is empty, so don't emit an exit jump */
2110 mir_remove_instruction(then_exit);
2111 then_branch->branch.target_block = after_else_idx;
2112 } else {
2113 then_branch->branch.target_block = else_idx;
2114 then_exit->branch.target_block = after_else_idx;
2115 }
2116 }
2117
2118 static void
2119 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2120 {
2121 /* Remember where we are */
2122 midgard_block *start_block = ctx->current_block;
2123
2124 /* Allocate a loop number, growing the current inner loop depth */
2125 int loop_idx = ++ctx->current_loop_depth;
2126
2127 /* Get index from before the body so we can loop back later */
2128 int start_idx = ctx->block_count;
2129
2130 /* Emit the body itself */
2131 emit_cf_list(ctx, &nloop->body);
2132
2133 /* Branch back to loop back */
2134 struct midgard_instruction br_back = v_branch(false, false);
2135 br_back.branch.target_block = start_idx;
2136 emit_mir_instruction(ctx, br_back);
2137
2138 /* Mark down that branch in the graph. Note that we're really branching
2139 * to the block *after* we started in. TODO: Why doesn't the branch
2140 * itself have an off-by-one then...? */
2141 midgard_block_add_successor(ctx->current_block, start_block->successors[0]);
2142
2143 /* Find the index of the block about to follow us (note: we don't add
2144 * one; blocks are 0-indexed so we get a fencepost problem) */
2145 int break_block_idx = ctx->block_count;
2146
2147 /* Fix up the break statements we emitted to point to the right place,
2148 * now that we can allocate a block number for them */
2149
2150 list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
2151 mir_foreach_instr_in_block(block, ins) {
2152 if (ins->type != TAG_ALU_4) continue;
2153 if (!ins->compact_branch) continue;
2154 if (ins->prepacked_branch) continue;
2155
2156 /* We found a branch -- check the type to see if we need to do anything */
2157 if (ins->branch.target_type != TARGET_BREAK) continue;
2158
2159 /* It's a break! Check if it's our break */
2160 if (ins->branch.target_break != loop_idx) continue;
2161
2162 /* Okay, cool, we're breaking out of this loop.
2163 * Rewrite from a break to a goto */
2164
2165 ins->branch.target_type = TARGET_GOTO;
2166 ins->branch.target_block = break_block_idx;
2167 }
2168 }
2169
2170 /* Now that we've finished emitting the loop, free up the depth again
2171 * so we play nice with recursion amid nested loops */
2172 --ctx->current_loop_depth;
2173
2174 /* Dump loop stats */
2175 ++ctx->loop_count;
2176 }
2177
2178 static midgard_block *
2179 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2180 {
2181 midgard_block *start_block = NULL;
2182
2183 foreach_list_typed(nir_cf_node, node, node, list) {
2184 switch (node->type) {
2185 case nir_cf_node_block: {
2186 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2187
2188 if (!start_block)
2189 start_block = block;
2190
2191 break;
2192 }
2193
2194 case nir_cf_node_if:
2195 emit_if(ctx, nir_cf_node_as_if(node));
2196 break;
2197
2198 case nir_cf_node_loop:
2199 emit_loop(ctx, nir_cf_node_as_loop(node));
2200 break;
2201
2202 case nir_cf_node_function:
2203 assert(0);
2204 break;
2205 }
2206 }
2207
2208 return start_block;
2209 }
2210
2211 /* Due to lookahead, we need to report the first tag executed in the command
2212 * stream and in branch targets. An initial block might be empty, so iterate
2213 * until we find one that 'works' */
2214
2215 static unsigned
2216 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2217 {
2218 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2219
2220 unsigned first_tag = 0;
2221
2222 do {
2223 midgard_bundle *initial_bundle = util_dynarray_element(&initial_block->bundles, midgard_bundle, 0);
2224
2225 if (initial_bundle) {
2226 first_tag = initial_bundle->tag;
2227 break;
2228 }
2229
2230 /* Initial block is empty, try the next block */
2231 initial_block = list_first_entry(&(initial_block->link), midgard_block, link);
2232 } while(initial_block != NULL);
2233
2234 assert(first_tag);
2235 return first_tag;
2236 }
2237
2238 int
2239 midgard_compile_shader_nir(struct midgard_screen *screen, nir_shader *nir, midgard_program *program, bool is_blend)
2240 {
2241 struct util_dynarray *compiled = &program->compiled;
2242
2243 midgard_debug = debug_get_option_midgard_debug();
2244
2245 compiler_context ictx = {
2246 .nir = nir,
2247 .screen = screen,
2248 .stage = nir->info.stage,
2249 .temp_alloc = 0,
2250
2251 .is_blend = is_blend,
2252 .blend_constant_offset = 0,
2253
2254 .alpha_ref = program->alpha_ref
2255 };
2256
2257 compiler_context *ctx = &ictx;
2258
2259 /* Start off with a safe cutoff, allowing usage of all 16 work
2260 * registers. Later, we'll promote uniform reads to uniform registers
2261 * if we determine it is beneficial to do so */
2262 ctx->uniform_cutoff = 8;
2263
2264 /* Initialize at a global (not block) level hash tables */
2265
2266 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2267 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2268 ctx->sysval_to_id = _mesa_hash_table_u64_create(NULL);
2269
2270 /* Record the varying mapping for the command stream's bookkeeping */
2271
2272 struct exec_list *varyings =
2273 ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs;
2274
2275 unsigned max_varying = 0;
2276 nir_foreach_variable(var, varyings) {
2277 unsigned loc = var->data.driver_location;
2278 unsigned sz = glsl_type_size(var->type, FALSE);
2279
2280 for (int c = 0; c < sz; ++c) {
2281 program->varyings[loc + c] = var->data.location + c;
2282 max_varying = MAX2(max_varying, loc + c);
2283 }
2284 }
2285
2286 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2287 * (so we don't accidentally duplicate the epilogue since mesa/st has
2288 * messed with our I/O quite a bit already) */
2289
2290 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2291
2292 if (ctx->stage == MESA_SHADER_VERTEX) {
2293 NIR_PASS_V(nir, nir_lower_viewport_transform);
2294 NIR_PASS_V(nir, nir_clamp_psiz, 1.0, 1024.0);
2295 }
2296
2297 NIR_PASS_V(nir, nir_lower_var_copies);
2298 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2299 NIR_PASS_V(nir, nir_split_var_copies);
2300 NIR_PASS_V(nir, nir_lower_var_copies);
2301 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2302 NIR_PASS_V(nir, nir_lower_var_copies);
2303 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2304
2305 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2306
2307 /* Optimisation passes */
2308
2309 optimise_nir(nir);
2310
2311 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2312 nir_print_shader(nir, stdout);
2313 }
2314
2315 /* Assign sysvals and counts, now that we're sure
2316 * (post-optimisation) */
2317
2318 midgard_nir_assign_sysvals(ctx, nir);
2319
2320 program->uniform_count = nir->num_uniforms;
2321 program->sysval_count = ctx->sysval_count;
2322 memcpy(program->sysvals, ctx->sysvals, sizeof(ctx->sysvals[0]) * ctx->sysval_count);
2323
2324 nir_foreach_function(func, nir) {
2325 if (!func->impl)
2326 continue;
2327
2328 list_inithead(&ctx->blocks);
2329 ctx->block_count = 0;
2330 ctx->func = func;
2331
2332 emit_cf_list(ctx, &func->impl->body);
2333 emit_block(ctx, func->impl->end_block);
2334
2335 break; /* TODO: Multi-function shaders */
2336 }
2337
2338 util_dynarray_init(compiled, NULL);
2339
2340 /* MIR-level optimizations */
2341
2342 bool progress = false;
2343
2344 do {
2345 progress = false;
2346
2347 mir_foreach_block(ctx, block) {
2348 progress |= midgard_opt_pos_propagate(ctx, block);
2349 progress |= midgard_opt_copy_prop(ctx, block);
2350 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2351 progress |= midgard_opt_combine_projection(ctx, block);
2352 progress |= midgard_opt_varying_projection(ctx, block);
2353 }
2354 } while (progress);
2355
2356 mir_foreach_block(ctx, block) {
2357 midgard_lower_invert(ctx, block);
2358 midgard_lower_derivatives(ctx, block);
2359 }
2360
2361 /* Nested control-flow can result in dead branches at the end of the
2362 * block. This messes with our analysis and is just dead code, so cull
2363 * them */
2364 mir_foreach_block(ctx, block) {
2365 midgard_opt_cull_dead_branch(ctx, block);
2366 }
2367
2368 /* Ensure we were lowered */
2369 mir_foreach_instr_global(ctx, ins) {
2370 assert(!ins->invert);
2371 }
2372
2373 /* Schedule! */
2374 schedule_program(ctx);
2375
2376 /* Now that all the bundles are scheduled and we can calculate block
2377 * sizes, emit actual branch instructions rather than placeholders */
2378
2379 int br_block_idx = 0;
2380
2381 mir_foreach_block(ctx, block) {
2382 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2383 for (int c = 0; c < bundle->instruction_count; ++c) {
2384 midgard_instruction *ins = bundle->instructions[c];
2385
2386 if (!midgard_is_branch_unit(ins->unit)) continue;
2387
2388 if (ins->prepacked_branch) continue;
2389
2390 /* Parse some basic branch info */
2391 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2392 bool is_conditional = ins->branch.conditional;
2393 bool is_inverted = ins->branch.invert_conditional;
2394 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2395
2396 /* Determine the block we're jumping to */
2397 int target_number = ins->branch.target_block;
2398
2399 /* Report the destination tag */
2400 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2401
2402 /* Count up the number of quadwords we're
2403 * jumping over = number of quadwords until
2404 * (br_block_idx, target_number) */
2405
2406 int quadword_offset = 0;
2407
2408 if (is_discard) {
2409 /* Jump to the end of the shader. We
2410 * need to include not only the
2411 * following blocks, but also the
2412 * contents of our current block (since
2413 * discard can come in the middle of
2414 * the block) */
2415
2416 midgard_block *blk = mir_get_block(ctx, br_block_idx + 1);
2417
2418 for (midgard_bundle *bun = bundle + 1; bun < (midgard_bundle *)((char*) block->bundles.data + block->bundles.size); ++bun) {
2419 quadword_offset += quadword_size(bun->tag);
2420 }
2421
2422 mir_foreach_block_from(ctx, blk, b) {
2423 quadword_offset += b->quadword_count;
2424 }
2425
2426 } else if (target_number > br_block_idx) {
2427 /* Jump forward */
2428
2429 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2430 midgard_block *blk = mir_get_block(ctx, idx);
2431 assert(blk);
2432
2433 quadword_offset += blk->quadword_count;
2434 }
2435 } else {
2436 /* Jump backwards */
2437
2438 for (int idx = br_block_idx; idx >= target_number; --idx) {
2439 midgard_block *blk = mir_get_block(ctx, idx);
2440 assert(blk);
2441
2442 quadword_offset -= blk->quadword_count;
2443 }
2444 }
2445
2446 /* Unconditional extended branches (far jumps)
2447 * have issues, so we always use a conditional
2448 * branch, setting the condition to always for
2449 * unconditional. For compact unconditional
2450 * branches, cond isn't used so it doesn't
2451 * matter what we pick. */
2452
2453 midgard_condition cond =
2454 !is_conditional ? midgard_condition_always :
2455 is_inverted ? midgard_condition_false :
2456 midgard_condition_true;
2457
2458 midgard_jmp_writeout_op op =
2459 is_discard ? midgard_jmp_writeout_op_discard :
2460 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2461 midgard_jmp_writeout_op_branch_cond;
2462
2463 if (!is_compact) {
2464 midgard_branch_extended branch =
2465 midgard_create_branch_extended(
2466 cond, op,
2467 dest_tag,
2468 quadword_offset);
2469
2470 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2471 } else if (is_conditional || is_discard) {
2472 midgard_branch_cond branch = {
2473 .op = op,
2474 .dest_tag = dest_tag,
2475 .offset = quadword_offset,
2476 .cond = cond
2477 };
2478
2479 assert(branch.offset == quadword_offset);
2480
2481 memcpy(&ins->br_compact, &branch, sizeof(branch));
2482 } else {
2483 assert(op == midgard_jmp_writeout_op_branch_uncond);
2484
2485 midgard_branch_uncond branch = {
2486 .op = op,
2487 .dest_tag = dest_tag,
2488 .offset = quadword_offset,
2489 .unknown = 1
2490 };
2491
2492 assert(branch.offset == quadword_offset);
2493
2494 memcpy(&ins->br_compact, &branch, sizeof(branch));
2495 }
2496 }
2497 }
2498
2499 ++br_block_idx;
2500 }
2501
2502 /* Emit flat binary from the instruction arrays. Iterate each block in
2503 * sequence. Save instruction boundaries such that lookahead tags can
2504 * be assigned easily */
2505
2506 /* Cache _all_ bundles in source order for lookahead across failed branches */
2507
2508 int bundle_count = 0;
2509 mir_foreach_block(ctx, block) {
2510 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2511 }
2512 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2513 int bundle_idx = 0;
2514 mir_foreach_block(ctx, block) {
2515 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2516 source_order_bundles[bundle_idx++] = bundle;
2517 }
2518 }
2519
2520 int current_bundle = 0;
2521
2522 /* Midgard prefetches instruction types, so during emission we
2523 * need to lookahead. Unless this is the last instruction, in
2524 * which we return 1. Or if this is the second to last and the
2525 * last is an ALU, then it's also 1... */
2526
2527 mir_foreach_block(ctx, block) {
2528 mir_foreach_bundle_in_block(block, bundle) {
2529 int lookahead = 1;
2530
2531 if (current_bundle + 1 < bundle_count) {
2532 uint8_t next = source_order_bundles[current_bundle + 1]->tag;
2533
2534 if (!(current_bundle + 2 < bundle_count) && IS_ALU(next)) {
2535 lookahead = 1;
2536 } else {
2537 lookahead = next;
2538 }
2539 }
2540
2541 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2542 ++current_bundle;
2543 }
2544
2545 /* TODO: Free deeper */
2546 //util_dynarray_fini(&block->instructions);
2547 }
2548
2549 free(source_order_bundles);
2550
2551 /* Report the very first tag executed */
2552 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2553
2554 /* Deal with off-by-one related to the fencepost problem */
2555 program->work_register_count = ctx->work_registers + 1;
2556 program->uniform_cutoff = ctx->uniform_cutoff;
2557
2558 program->blend_patch_offset = ctx->blend_constant_offset;
2559 program->tls_size = ctx->tls_size;
2560
2561 if (midgard_debug & MIDGARD_DBG_SHADERS)
2562 disassemble_midgard(program->compiled.data, program->compiled.size);
2563
2564 if (midgard_debug & MIDGARD_DBG_SHADERDB) {
2565 unsigned nr_bundles = 0, nr_ins = 0, nr_quadwords = 0;
2566
2567 /* Count instructions and bundles */
2568
2569 mir_foreach_instr_global(ctx, ins) {
2570 nr_ins++;
2571 }
2572
2573 mir_foreach_block(ctx, block) {
2574 nr_bundles += util_dynarray_num_elements(
2575 &block->bundles, midgard_bundle);
2576
2577 nr_quadwords += block->quadword_count;
2578 }
2579
2580 /* Calculate thread count. There are certain cutoffs by
2581 * register count for thread count */
2582
2583 unsigned nr_registers = program->work_register_count;
2584
2585 unsigned nr_threads =
2586 (nr_registers <= 4) ? 4 :
2587 (nr_registers <= 8) ? 2 :
2588 1;
2589
2590 /* Dump stats */
2591
2592 fprintf(stderr, "shader%d - %s shader: "
2593 "%u inst, %u bundles, %u quadwords, "
2594 "%u registers, %u threads, %u loops, "
2595 "%d:%d spills:fills\n",
2596 SHADER_DB_COUNT++,
2597 gl_shader_stage_name(ctx->stage),
2598 nr_ins, nr_bundles, nr_quadwords,
2599 nr_registers, nr_threads,
2600 ctx->loop_count,
2601 ctx->spills, ctx->fills);
2602 }
2603
2604
2605 return 0;
2606 }