projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
pan/mdg: Remove mir_*size routines
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 i.dest_type = T; \
121 } else { \
122 i.dest = ssa; \
123 i.dest_type = T; \
124 } \
125 return i; \
126 }
127
128 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
129 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130
131 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
132 * the corresponding Midgard source */
133
134 static midgard_vector_alu_src
135 vector_alu_modifiers(bool abs, bool neg, bool is_int,
136 bool half, bool sext)
137 {
138 /* Figure out how many components there are so we can adjust.
139 * Specifically we want to broadcast the last channel so things like
140 * ball2/3 work.
141 */
142
143 midgard_vector_alu_src alu_src = {
144 .rep_low = 0,
145 .rep_high = 0,
146 .half = half
147 };
148
149 if (is_int) {
150 alu_src.mod = midgard_int_normal;
151
152 /* Sign/zero-extend if needed */
153
154 if (half) {
155 alu_src.mod = sext ?
156 midgard_int_sign_extend
157 : midgard_int_zero_extend;
158 }
159
160 /* These should have been lowered away */
161 assert(!(abs || neg));
162 } else {
163 alu_src.mod = (abs << 0) | (neg << 1);
164 }
165
166 return alu_src;
167 }
168
169 M_LOAD(ld_attr_32, nir_type_uint32);
170 M_LOAD(ld_vary_32, nir_type_uint32);
171 M_LOAD(ld_ubo_int4, nir_type_uint32);
172 M_LOAD(ld_int4, nir_type_uint32);
173 M_STORE(st_int4, nir_type_uint32);
174 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
175 M_STORE(st_vary_32, nir_type_uint32);
176 M_LOAD(ld_cubemap_coords, nir_type_uint32);
177 M_LOAD(ld_compute_id, nir_type_uint32);
178
179 static midgard_instruction
180 v_branch(bool conditional, bool invert)
181 {
182 midgard_instruction ins = {
183 .type = TAG_ALU_4,
184 .unit = ALU_ENAB_BRANCH,
185 .compact_branch = true,
186 .branch = {
187 .conditional = conditional,
188 .invert_conditional = invert
189 },
190 .dest = ~0,
191 .src = { ~0, ~0, ~0, ~0 },
192 };
193
194 return ins;
195 }
196
197 static midgard_branch_extended
198 midgard_create_branch_extended( midgard_condition cond,
199 midgard_jmp_writeout_op op,
200 unsigned dest_tag,
201 signed quadword_offset)
202 {
203 /* The condition code is actually a LUT describing a function to
204 * combine multiple condition codes. However, we only support a single
205 * condition code at the moment, so we just duplicate over a bunch of
206 * times. */
207
208 uint16_t duplicated_cond =
209 (cond << 14) |
210 (cond << 12) |
211 (cond << 10) |
212 (cond << 8) |
213 (cond << 6) |
214 (cond << 4) |
215 (cond << 2) |
216 (cond << 0);
217
218 midgard_branch_extended branch = {
219 .op = op,
220 .dest_tag = dest_tag,
221 .offset = quadword_offset,
222 .cond = duplicated_cond
223 };
224
225 return branch;
226 }
227
228 static void
229 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
230 {
231 ins->has_constants = true;
232 memcpy(&ins->constants, constants, 16);
233 }
234
235 static int
236 glsl_type_size(const struct glsl_type *type, bool bindless)
237 {
238 return glsl_count_attribute_slots(type, false);
239 }
240
241 /* Lower fdot2 to a vector multiplication followed by channel addition */
242 static void
243 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
244 {
245 if (alu->op != nir_op_fdot2)
246 return;
247
248 b->cursor = nir_before_instr(&alu->instr);
249
250 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
251 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
252
253 nir_ssa_def *product = nir_fmul(b, src0, src1);
254
255 nir_ssa_def *sum = nir_fadd(b,
256 nir_channel(b, product, 0),
257 nir_channel(b, product, 1));
258
259 /* Replace the fdot2 with this sum */
260 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
261 }
262
263 static bool
264 midgard_nir_lower_fdot2(nir_shader *shader)
265 {
266 bool progress = false;
267
268 nir_foreach_function(function, shader) {
269 if (!function->impl) continue;
270
271 nir_builder _b;
272 nir_builder *b = &_b;
273 nir_builder_init(b, function->impl);
274
275 nir_foreach_block(block, function->impl) {
276 nir_foreach_instr_safe(instr, block) {
277 if (instr->type != nir_instr_type_alu) continue;
278
279 nir_alu_instr *alu = nir_instr_as_alu(instr);
280 midgard_nir_lower_fdot2_body(b, alu);
281
282 progress |= true;
283 }
284 }
285
286 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
287
288 }
289
290 return progress;
291 }
292
293 /* Midgard can't write depth and stencil separately. It has to happen in a
294 * single store operation containing both. Let's add a panfrost specific
295 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
296 * one.
297 */
298 static bool
299 midgard_nir_lower_zs_store(nir_shader *nir)
300 {
301 if (nir->info.stage != MESA_SHADER_FRAGMENT)
302 return false;
303
304 nir_variable *z_var = NULL, *s_var = NULL;
305
306 nir_foreach_variable(var, &nir->outputs) {
307 if (var->data.location == FRAG_RESULT_DEPTH)
308 z_var = var;
309 else if (var->data.location == FRAG_RESULT_STENCIL)
310 s_var = var;
311 }
312
313 if (!z_var && !s_var)
314 return false;
315
316 bool progress = false;
317
318 nir_foreach_function(function, nir) {
319 if (!function->impl) continue;
320
321 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
322
323 nir_foreach_block(block, function->impl) {
324 nir_foreach_instr_safe(instr, block) {
325 if (instr->type != nir_instr_type_intrinsic)
326 continue;
327
328 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
329 if (intr->intrinsic != nir_intrinsic_store_output)
330 continue;
331
332 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
333 assert(!z_store);
334 z_store = intr;
335 last_store = intr;
336 }
337
338 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
339 assert(!s_store);
340 s_store = intr;
341 last_store = intr;
342 }
343 }
344 }
345
346 if (!z_store && !s_store) continue;
347
348 nir_builder b;
349 nir_builder_init(&b, function->impl);
350
351 b.cursor = nir_before_instr(&last_store->instr);
352
353 nir_ssa_def *zs_store_src;
354
355 if (z_store && s_store) {
356 nir_ssa_def *srcs[2] = {
357 nir_ssa_for_src(&b, z_store->src[0], 1),
358 nir_ssa_for_src(&b, s_store->src[0], 1),
359 };
360
361 zs_store_src = nir_vec(&b, srcs, 2);
362 } else {
363 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
364 }
365
366 nir_intrinsic_instr *zs_store;
367
368 zs_store = nir_intrinsic_instr_create(b.shader,
369 nir_intrinsic_store_zs_output_pan);
370 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
371 zs_store->num_components = z_store && s_store ? 2 : 1;
372 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
373
374 /* Replace the Z and S store by a ZS store */
375 nir_builder_instr_insert(&b, &zs_store->instr);
376
377 if (z_store)
378 nir_instr_remove(&z_store->instr);
379
380 if (s_store)
381 nir_instr_remove(&s_store->instr);
382
383 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
384 progress = true;
385 }
386
387 return progress;
388 }
389
390 /* Flushes undefined values to zero */
391
392 static void
393 optimise_nir(nir_shader *nir, unsigned quirks)
394 {
395 bool progress;
396 unsigned lower_flrp =
397 (nir->options->lower_flrp16 ? 16 : 0) |
398 (nir->options->lower_flrp32 ? 32 : 0) |
399 (nir->options->lower_flrp64 ? 64 : 0);
400
401 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
402 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
403
404 nir_lower_tex_options lower_tex_options = {
405 .lower_txs_lod = true,
406 .lower_txp = ~0,
407 .lower_tex_without_implicit_lod =
408 (quirks & MIDGARD_EXPLICIT_LOD),
409
410 /* TODO: we have native gradient.. */
411 .lower_txd = true,
412 };
413
414 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
415
416 /* Must lower fdot2 after tex is lowered */
417 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
418
419 /* T720 is broken. */
420
421 if (quirks & MIDGARD_BROKEN_LOD)
422 NIR_PASS_V(nir, midgard_nir_lod_errata);
423
424 do {
425 progress = false;
426
427 NIR_PASS(progress, nir, nir_lower_var_copies);
428 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
429
430 NIR_PASS(progress, nir, nir_copy_prop);
431 NIR_PASS(progress, nir, nir_opt_remove_phis);
432 NIR_PASS(progress, nir, nir_opt_dce);
433 NIR_PASS(progress, nir, nir_opt_dead_cf);
434 NIR_PASS(progress, nir, nir_opt_cse);
435 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
436 NIR_PASS(progress, nir, nir_opt_algebraic);
437 NIR_PASS(progress, nir, nir_opt_constant_folding);
438
439 if (lower_flrp != 0) {
440 bool lower_flrp_progress = false;
441 NIR_PASS(lower_flrp_progress,
442 nir,
443 nir_lower_flrp,
444 lower_flrp,
445 false /* always_precise */,
446 nir->options->lower_ffma);
447 if (lower_flrp_progress) {
448 NIR_PASS(progress, nir,
449 nir_opt_constant_folding);
450 progress = true;
451 }
452
453 /* Nothing should rematerialize any flrps, so we only
454 * need to do this lowering once.
455 */
456 lower_flrp = 0;
457 }
458
459 NIR_PASS(progress, nir, nir_opt_undef);
460 NIR_PASS(progress, nir, nir_undef_to_zero);
461
462 NIR_PASS(progress, nir, nir_opt_loop_unroll,
463 nir_var_shader_in |
464 nir_var_shader_out |
465 nir_var_function_temp);
466
467 NIR_PASS(progress, nir, nir_opt_vectorize);
468 } while (progress);
469
470 /* Must be run at the end to prevent creation of fsin/fcos ops */
471 NIR_PASS(progress, nir, midgard_nir_scale_trig);
472
473 do {
474 progress = false;
475
476 NIR_PASS(progress, nir, nir_opt_dce);
477 NIR_PASS(progress, nir, nir_opt_algebraic);
478 NIR_PASS(progress, nir, nir_opt_constant_folding);
479 NIR_PASS(progress, nir, nir_copy_prop);
480 } while (progress);
481
482 NIR_PASS(progress, nir, nir_opt_algebraic_late);
483 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
484
485 /* We implement booleans as 32-bit 0/~0 */
486 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
487
488 /* Now that booleans are lowered, we can run out late opts */
489 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
490 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
491
492 NIR_PASS(progress, nir, nir_copy_prop);
493 NIR_PASS(progress, nir, nir_opt_dce);
494
495 /* Take us out of SSA */
496 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
497 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
498
499 /* We are a vector architecture; write combine where possible */
500 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
501 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
502
503 NIR_PASS(progress, nir, nir_opt_dce);
504 }
505
506 /* Do not actually emit a load; instead, cache the constant for inlining */
507
508 static void
509 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
510 {
511 nir_ssa_def def = instr->def;
512
513 midgard_constants *consts = rzalloc(NULL, midgard_constants);
514
515 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
516
517 #define RAW_CONST_COPY(bits) \
518 nir_const_value_to_array(consts->u##bits, instr->value, \
519 instr->def.num_components, u##bits)
520
521 switch (instr->def.bit_size) {
522 case 64:
523 RAW_CONST_COPY(64);
524 break;
525 case 32:
526 RAW_CONST_COPY(32);
527 break;
528 case 16:
529 RAW_CONST_COPY(16);
530 break;
531 case 8:
532 RAW_CONST_COPY(8);
533 break;
534 default:
535 unreachable("Invalid bit_size for load_const instruction\n");
536 }
537
538 /* Shifted for SSA, +1 for off-by-one */
539 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
540 }
541
542 /* Normally constants are embedded implicitly, but for I/O and such we have to
543 * explicitly emit a move with the constant source */
544
545 static void
546 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
547 {
548 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
549
550 if (constant_value) {
551 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
552 attach_constants(ctx, &ins, constant_value, node + 1);
553 emit_mir_instruction(ctx, ins);
554 }
555 }
556
557 static bool
558 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
559 {
560 unsigned comp = src->swizzle[0];
561
562 for (unsigned c = 1; c < nr_components; ++c) {
563 if (src->swizzle[c] != comp)
564 return true;
565 }
566
567 return false;
568 }
569
570 #define ALU_CASE(nir, _op) \
571 case nir_op_##nir: \
572 op = midgard_alu_op_##_op; \
573 assert(src_bitsize == dst_bitsize); \
574 break;
575
576 #define ALU_CASE_BCAST(nir, _op, count) \
577 case nir_op_##nir: \
578 op = midgard_alu_op_##_op; \
579 broadcast_swizzle = count; \
580 assert(src_bitsize == dst_bitsize); \
581 break;
582
583 #define ALU_CHECK_CMP(sext) \
584 if (src_bitsize == 16 && dst_bitsize == 32) { \
585 half_1 = true; \
586 half_2 = true; \
587 sext_1 = sext; \
588 sext_2 = sext; \
589 } else { \
590 assert(src_bitsize == dst_bitsize); \
591 } \
592
593 #define ALU_CASE_CMP(nir, _op, sext) \
594 case nir_op_##nir: \
595 op = midgard_alu_op_##_op; \
596 ALU_CHECK_CMP(sext); \
597 break;
598
599 /* Analyze the sizes of the dest and inputs to determine reg mode. */
600
601 static midgard_reg_mode
602 reg_mode_for_nir(nir_alu_instr *instr)
603 {
604 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
605 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
606 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
607
608 switch (max_bitsize) {
609 case 8:
610 return midgard_reg_mode_8;
611 case 16:
612 return midgard_reg_mode_16;
613 case 32:
614 return midgard_reg_mode_32;
615 case 64:
616 return midgard_reg_mode_64;
617 default:
618 unreachable("Invalid bit size");
619 }
620 }
621
622 /* Compare mir_lower_invert */
623 static bool
624 nir_accepts_inot(nir_op op, unsigned src)
625 {
626 switch (op) {
627 case nir_op_ior:
628 case nir_op_iand:
629 case nir_op_ixor:
630 return true;
631 case nir_op_b32csel:
632 /* Only the condition */
633 return (src == 0);
634 default:
635 return false;
636 }
637 }
638
639 static bool
640 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
641 {
642 if (pan_has_dest_mod(dest, op)) {
643 assert((*dest)->is_ssa);
644 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
645 return true;
646 }
647
648 return false;
649 }
650
651 static void
652 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, bool is_int, unsigned bcast_count)
653 {
654 nir_alu_src src = instr->src[i];
655
656 if (!is_int) {
657 if (pan_has_source_mod(&src, nir_op_fneg))
658 *neg = !(*neg);
659
660 if (pan_has_source_mod(&src, nir_op_fabs))
661 *abs = true;
662 }
663
664 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
665 *not = true;
666
667 unsigned bits = nir_src_bit_size(src.src);
668
669 ins->src[to] = nir_src_index(NULL, &src.src);
670 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
671
672 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
673 ins->swizzle[to][c] = src.swizzle[
674 (!bcast_count || c < bcast_count) ? c :
675 (bcast_count - 1)];
676 }
677 }
678
679 /* Midgard features both fcsel and icsel, depending on whether you want int or
680 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
681 * we should emit an int or float csel depending on what modifiers could be
682 * placed. In the absense of modifiers, this is probably arbitrary. */
683
684 static bool
685 mir_is_bcsel_float(nir_alu_instr *instr)
686 {
687 nir_op intmods[] = {
688 nir_op_i2i8, nir_op_i2i16,
689 nir_op_i2i32, nir_op_i2i64
690 };
691
692 nir_op floatmods[] = {
693 nir_op_fabs, nir_op_fneg,
694 nir_op_f2f16, nir_op_f2f32,
695 nir_op_f2f64
696 };
697
698 nir_op floatdestmods[] = {
699 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
700 nir_op_f2f16, nir_op_f2f32
701 };
702
703 signed score = 0;
704
705 for (unsigned i = 1; i < 3; ++i) {
706 nir_alu_src s = instr->src[i];
707 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
708 if (pan_has_source_mod(&s, intmods[q]))
709 score--;
710 }
711 }
712
713 for (unsigned i = 1; i < 3; ++i) {
714 nir_alu_src s = instr->src[i];
715 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
716 if (pan_has_source_mod(&s, floatmods[q]))
717 score++;
718 }
719 }
720
721 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
722 nir_dest *dest = &instr->dest.dest;
723 if (pan_has_dest_mod(&dest, floatdestmods[q]))
724 score++;
725 }
726
727 return (score > 0);
728 }
729
730 static void
731 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
732 {
733 nir_dest *dest = &instr->dest.dest;
734
735 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
736 return;
737
738 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
739 * is handled elsewhere */
740
741 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
742 midgard_emit_derivatives(ctx, instr);
743 return;
744 }
745
746 bool is_ssa = dest->is_ssa;
747
748 unsigned nr_components = nir_dest_num_components(*dest);
749 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
750 unsigned op = 0;
751
752 /* Number of components valid to check for the instruction (the rest
753 * will be forced to the last), or 0 to use as-is. Relevant as
754 * ball-type instructions have a channel count in NIR but are all vec4
755 * in Midgard */
756
757 unsigned broadcast_swizzle = 0;
758
759 /* What register mode should we operate in? */
760 midgard_reg_mode reg_mode =
761 reg_mode_for_nir(instr);
762
763 /* Do we need a destination override? Used for inline
764 * type conversion */
765
766 midgard_dest_override dest_override =
767 midgard_dest_override_none;
768
769 /* Should we use a smaller respective source and sign-extend? */
770
771 bool half_1 = false, sext_1 = false;
772 bool half_2 = false, sext_2 = false;
773
774 /* Should we swap arguments? */
775 bool flip_src12 = false;
776
777 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
778 unsigned dst_bitsize = nir_dest_bit_size(*dest);
779
780 switch (instr->op) {
781 ALU_CASE(fadd, fadd);
782 ALU_CASE(fmul, fmul);
783 ALU_CASE(fmin, fmin);
784 ALU_CASE(fmax, fmax);
785 ALU_CASE(imin, imin);
786 ALU_CASE(imax, imax);
787 ALU_CASE(umin, umin);
788 ALU_CASE(umax, umax);
789 ALU_CASE(ffloor, ffloor);
790 ALU_CASE(fround_even, froundeven);
791 ALU_CASE(ftrunc, ftrunc);
792 ALU_CASE(fceil, fceil);
793 ALU_CASE(fdot3, fdot3);
794 ALU_CASE(fdot4, fdot4);
795 ALU_CASE(iadd, iadd);
796 ALU_CASE(isub, isub);
797 ALU_CASE(imul, imul);
798
799 /* Zero shoved as second-arg */
800 ALU_CASE(iabs, iabsdiff);
801
802 ALU_CASE(mov, imov);
803
804 ALU_CASE_CMP(feq32, feq, false);
805 ALU_CASE_CMP(fne32, fne, false);
806 ALU_CASE_CMP(flt32, flt, false);
807 ALU_CASE_CMP(ieq32, ieq, true);
808 ALU_CASE_CMP(ine32, ine, true);
809 ALU_CASE_CMP(ilt32, ilt, true);
810 ALU_CASE_CMP(ult32, ult, false);
811
812 /* We don't have a native b2f32 instruction. Instead, like many
813 * GPUs, we exploit booleans as 0/~0 for false/true, and
814 * correspondingly AND
815 * by 1.0 to do the type conversion. For the moment, prime us
816 * to emit:
817 *
818 * iand [whatever], #0
819 *
820 * At the end of emit_alu (as MIR), we'll fix-up the constant
821 */
822
823 ALU_CASE_CMP(b2f32, iand, true);
824 ALU_CASE_CMP(b2i32, iand, true);
825
826 /* Likewise, we don't have a dedicated f2b32 instruction, but
827 * we can do a "not equal to 0.0" test. */
828
829 ALU_CASE_CMP(f2b32, fne, false);
830 ALU_CASE_CMP(i2b32, ine, true);
831
832 ALU_CASE(frcp, frcp);
833 ALU_CASE(frsq, frsqrt);
834 ALU_CASE(fsqrt, fsqrt);
835 ALU_CASE(fexp2, fexp2);
836 ALU_CASE(flog2, flog2);
837
838 ALU_CASE(f2i64, f2i_rtz);
839 ALU_CASE(f2u64, f2u_rtz);
840 ALU_CASE(i2f64, i2f_rtz);
841 ALU_CASE(u2f64, u2f_rtz);
842
843 ALU_CASE(f2i32, f2i_rtz);
844 ALU_CASE(f2u32, f2u_rtz);
845 ALU_CASE(i2f32, i2f_rtz);
846 ALU_CASE(u2f32, u2f_rtz);
847
848 ALU_CASE(f2i16, f2i_rtz);
849 ALU_CASE(f2u16, f2u_rtz);
850 ALU_CASE(i2f16, i2f_rtz);
851 ALU_CASE(u2f16, u2f_rtz);
852
853 ALU_CASE(fsin, fsin);
854 ALU_CASE(fcos, fcos);
855
856 /* We'll get 0 in the second arg, so:
857 * ~a = ~(a | 0) = nor(a, 0) */
858 ALU_CASE(inot, inor);
859 ALU_CASE(iand, iand);
860 ALU_CASE(ior, ior);
861 ALU_CASE(ixor, ixor);
862 ALU_CASE(ishl, ishl);
863 ALU_CASE(ishr, iasr);
864 ALU_CASE(ushr, ilsr);
865
866 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
867 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
868 ALU_CASE(b32all_fequal4, fball_eq);
869
870 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
871 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
872 ALU_CASE(b32any_fnequal4, fbany_neq);
873
874 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
875 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
876 ALU_CASE(b32all_iequal4, iball_eq);
877
878 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
879 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
880 ALU_CASE(b32any_inequal4, ibany_neq);
881
882 /* Source mods will be shoved in later */
883 ALU_CASE(fabs, fmov);
884 ALU_CASE(fneg, fmov);
885 ALU_CASE(fsat, fmov);
886 ALU_CASE(fsat_signed, fmov);
887 ALU_CASE(fclamp_pos, fmov);
888
889 /* For size conversion, we use a move. Ideally though we would squash
890 * these ops together; maybe that has to happen after in NIR as part of
891 * propagation...? An earlier algebraic pass ensured we step down by
892 * only / exactly one size. If stepping down, we use a dest override to
893 * reduce the size; if stepping up, we use a larger-sized move with a
894 * half source and a sign/zero-extension modifier */
895
896 case nir_op_i2i8:
897 case nir_op_i2i16:
898 case nir_op_i2i32:
899 case nir_op_i2i64:
900 /* If we end up upscale, we'll need a sign-extend on the
901 * operand (the second argument) */
902
903 sext_2 = true;
904 /* fallthrough */
905 case nir_op_u2u8:
906 case nir_op_u2u16:
907 case nir_op_u2u32:
908 case nir_op_u2u64:
909 case nir_op_f2f16:
910 case nir_op_f2f32:
911 case nir_op_f2f64: {
912 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
913 instr->op == nir_op_f2f64)
914 op = midgard_alu_op_fmov;
915 else
916 op = midgard_alu_op_imov;
917
918 if (dst_bitsize == (src_bitsize * 2)) {
919 /* Converting up */
920 half_2 = true;
921 } else if (src_bitsize == (dst_bitsize * 2)) {
922 /* Converting down */
923 dest_override = midgard_dest_override_lower;
924 }
925
926 break;
927 }
928
929 /* For greater-or-equal, we lower to less-or-equal and flip the
930 * arguments */
931
932 case nir_op_fge:
933 case nir_op_fge32:
934 case nir_op_ige32:
935 case nir_op_uge32: {
936 op =
937 instr->op == nir_op_fge ? midgard_alu_op_fle :
938 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
939 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
940 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
941 0;
942
943 flip_src12 = true;
944 ALU_CHECK_CMP(false);
945 break;
946 }
947
948 case nir_op_b32csel: {
949 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
950 bool is_float = mir_is_bcsel_float(instr);
951 op = is_float ?
952 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
953 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
954
955 break;
956 }
957
958 default:
959 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
960 assert(0);
961 return;
962 }
963
964 /* Midgard can perform certain modifiers on output of an ALU op */
965
966 unsigned outmod = 0;
967
968 bool abs[4] = { false };
969 bool neg[4] = { false };
970 bool is_int = midgard_is_integer_op(op);
971
972 if (midgard_is_integer_out_op(op)) {
973 outmod = midgard_outmod_int_wrap;
974 } else if (instr->op == nir_op_fsat) {
975 outmod = midgard_outmod_sat;
976 } else if (instr->op == nir_op_fsat_signed) {
977 outmod = midgard_outmod_sat_signed;
978 } else if (instr->op == nir_op_fclamp_pos) {
979 outmod = midgard_outmod_pos;
980 }
981
982 /* Fetch unit, quirks, etc information */
983 unsigned opcode_props = alu_opcode_props[op].props;
984 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
985
986 /* Look for floating point mods. We have the mods fsat, fsat_signed,
987 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
988 *
989 * fsat_signed(fpos(x)) = fsat(x)
990 * fsat_signed(fsat(x)) = fsat(x)
991 * fpos(fsat_signed(x)) = fsat(x)
992 * fpos(fsat(x)) = fsat(x)
993 * fsat(fsat_signed(x)) = fsat(x)
994 * fsat(fpos(x)) = fsat(x)
995 *
996 * So by cases any composition of output modifiers is equivalent to
997 * fsat alone.
998 */
999
1000 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
1001 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
1002 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
1003 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
1004 bool prior = (outmod != midgard_outmod_none);
1005 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
1006
1007 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
1008 fpos ? midgard_outmod_pos :
1009 ssat ? midgard_outmod_sat_signed :
1010 outmod;
1011 }
1012
1013 midgard_instruction ins = {
1014 .type = TAG_ALU_4,
1015 .dest = nir_dest_index(dest),
1016 .dest_type = nir_op_infos[instr->op].output_type
1017 | nir_dest_bit_size(*dest),
1018 };
1019
1020 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
1021 ins.src[i] = ~0;
1022
1023 if (quirk_flipped_r24) {
1024 ins.src[0] = ~0;
1025 mir_copy_src(&ins, instr, 0, 1, &abs[1], &neg[1], &ins.src_invert[1], is_int, broadcast_swizzle);
1026 } else {
1027 for (unsigned i = 0; i < nr_inputs; ++i) {
1028 unsigned to = i;
1029
1030 if (instr->op == nir_op_b32csel) {
1031 /* The condition is the first argument; move
1032 * the other arguments up one to be a binary
1033 * instruction for Midgard with the condition
1034 * last */
1035
1036 if (i == 0)
1037 to = 2;
1038 else if (flip_src12)
1039 to = 2 - i;
1040 else
1041 to = i - 1;
1042 } else if (flip_src12) {
1043 to = 1 - to;
1044 }
1045
1046 mir_copy_src(&ins, instr, i, to, &abs[to], &neg[to], &ins.src_invert[to], is_int, broadcast_swizzle);
1047
1048 /* (!c) ? a : b = c ? b : a */
1049 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1050 ins.src_invert[2] = false;
1051 flip_src12 ^= true;
1052 }
1053 }
1054 }
1055
1056 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1057 /* Lowered to move */
1058 if (instr->op == nir_op_fneg)
1059 neg[1] = !neg[1];
1060
1061 if (instr->op == nir_op_fabs)
1062 abs[1] = true;
1063 }
1064
1065 ins.mask = mask_of(nr_components);
1066
1067 midgard_vector_alu alu = {
1068 .op = op,
1069 .reg_mode = reg_mode,
1070 .dest_override = dest_override,
1071 .outmod = outmod,
1072
1073 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[0], neg[0], is_int, half_1, sext_1)),
1074 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[1], neg[1], is_int, half_2, sext_2)),
1075 };
1076
1077 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1078 * components that don't exist. Note modifier => SSA => !reg => no
1079 * writemask, so we don't have to worry about writemasks here.*/
1080
1081 if (!is_ssa)
1082 ins.mask &= instr->dest.write_mask;
1083
1084 ins.alu = alu;
1085
1086 /* Arrange for creation of iandnot/iornot */
1087 if (ins.src_invert[0] && !ins.src_invert[1]) {
1088 mir_flip(&ins);
1089 ins.src_invert[0] = false;
1090 ins.src_invert[1] = true;
1091 }
1092
1093 /* Late fixup for emulated instructions */
1094
1095 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1096 /* Presently, our second argument is an inline #0 constant.
1097 * Switch over to an embedded 1.0 constant (that can't fit
1098 * inline, since we're 32-bit, not 16-bit like the inline
1099 * constants) */
1100
1101 ins.has_inline_constant = false;
1102 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1103 ins.src_types[1] = nir_type_float32;
1104 ins.has_constants = true;
1105
1106 if (instr->op == nir_op_b2f32)
1107 ins.constants.f32[0] = 1.0f;
1108 else
1109 ins.constants.i32[0] = 1;
1110
1111 for (unsigned c = 0; c < 16; ++c)
1112 ins.swizzle[1][c] = 0;
1113 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1114 /* Lots of instructions need a 0 plonked in */
1115 ins.has_inline_constant = false;
1116 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1117 ins.src_types[1] = nir_type_uint32;
1118 ins.has_constants = true;
1119 ins.constants.u32[0] = 0;
1120
1121 for (unsigned c = 0; c < 16; ++c)
1122 ins.swizzle[1][c] = 0;
1123 }
1124
1125 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1126 /* To avoid duplicating the lookup tables (probably), true LUT
1127 * instructions can only operate as if they were scalars. Lower
1128 * them here by changing the component. */
1129
1130 unsigned orig_mask = ins.mask;
1131
1132 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1133 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1134
1135 for (int i = 0; i < nr_components; ++i) {
1136 /* Mask the associated component, dropping the
1137 * instruction if needed */
1138
1139 ins.mask = 1 << i;
1140 ins.mask &= orig_mask;
1141
1142 if (!ins.mask)
1143 continue;
1144
1145 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1146 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1147
1148 emit_mir_instruction(ctx, ins);
1149 }
1150 } else {
1151 emit_mir_instruction(ctx, ins);
1152 }
1153 }
1154
1155 #undef ALU_CASE
1156
1157 static void
1158 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1159 {
1160 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1161 unsigned nir_mask = 0;
1162 unsigned dsize = 0;
1163
1164 if (is_read) {
1165 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1166 dsize = nir_dest_bit_size(intr->dest);
1167 } else {
1168 nir_mask = nir_intrinsic_write_mask(intr);
1169 dsize = 32;
1170 }
1171
1172 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1173 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1174 mir_set_bytemask(ins, bytemask);
1175
1176 if (dsize == 64)
1177 ins->load_64 = true;
1178 }
1179
1180 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1181 * optimized) versions of UBO #0 */
1182
1183 static midgard_instruction *
1184 emit_ubo_read(
1185 compiler_context *ctx,
1186 nir_instr *instr,
1187 unsigned dest,
1188 unsigned offset,
1189 nir_src *indirect_offset,
1190 unsigned indirect_shift,
1191 unsigned index)
1192 {
1193 /* TODO: half-floats */
1194
1195 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1196 ins.constants.u32[0] = offset;
1197
1198 if (instr->type == nir_instr_type_intrinsic)
1199 mir_set_intr_mask(instr, &ins, true);
1200
1201 if (indirect_offset) {
1202 ins.src[2] = nir_src_index(ctx, indirect_offset);
1203 ins.src_types[2] = nir_type_uint32;
1204 ins.load_store.arg_2 = (indirect_shift << 5);
1205 } else {
1206 ins.load_store.arg_2 = 0x1E;
1207 }
1208
1209 ins.load_store.arg_1 = index;
1210
1211 return emit_mir_instruction(ctx, ins);
1212 }
1213
1214 /* Globals are like UBOs if you squint. And shared memory is like globals if
1215 * you squint even harder */
1216
1217 static void
1218 emit_global(
1219 compiler_context *ctx,
1220 nir_instr *instr,
1221 bool is_read,
1222 unsigned srcdest,
1223 nir_src *offset,
1224 bool is_shared)
1225 {
1226 /* TODO: types */
1227
1228 midgard_instruction ins;
1229
1230 if (is_read)
1231 ins = m_ld_int4(srcdest, 0);
1232 else
1233 ins = m_st_int4(srcdest, 0);
1234
1235 mir_set_offset(ctx, &ins, offset, is_shared);
1236 mir_set_intr_mask(instr, &ins, is_read);
1237
1238 emit_mir_instruction(ctx, ins);
1239 }
1240
1241 static void
1242 emit_varying_read(
1243 compiler_context *ctx,
1244 unsigned dest, unsigned offset,
1245 unsigned nr_comp, unsigned component,
1246 nir_src *indirect_offset, nir_alu_type type, bool flat)
1247 {
1248 /* XXX: Half-floats? */
1249 /* TODO: swizzle, mask */
1250
1251 midgard_instruction ins = m_ld_vary_32(dest, offset);
1252 ins.mask = mask_of(nr_comp);
1253
1254 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1255 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1256
1257 midgard_varying_parameter p = {
1258 .is_varying = 1,
1259 .interpolation = midgard_interp_default,
1260 .flat = flat,
1261 };
1262
1263 unsigned u;
1264 memcpy(&u, &p, sizeof(p));
1265 ins.load_store.varying_parameters = u;
1266
1267 if (indirect_offset) {
1268 ins.src[2] = nir_src_index(ctx, indirect_offset);
1269 ins.src_types[2] = nir_type_uint32;
1270 } else
1271 ins.load_store.arg_2 = 0x1E;
1272
1273 ins.load_store.arg_1 = 0x9E;
1274
1275 /* Use the type appropriate load */
1276 switch (type) {
1277 case nir_type_uint:
1278 case nir_type_bool:
1279 ins.load_store.op = midgard_op_ld_vary_32u;
1280 break;
1281 case nir_type_int:
1282 ins.load_store.op = midgard_op_ld_vary_32i;
1283 break;
1284 case nir_type_float:
1285 ins.load_store.op = midgard_op_ld_vary_32;
1286 break;
1287 default:
1288 unreachable("Attempted to load unknown type");
1289 break;
1290 }
1291
1292 emit_mir_instruction(ctx, ins);
1293 }
1294
1295 static void
1296 emit_attr_read(
1297 compiler_context *ctx,
1298 unsigned dest, unsigned offset,
1299 unsigned nr_comp, nir_alu_type t)
1300 {
1301 midgard_instruction ins = m_ld_attr_32(dest, offset);
1302 ins.load_store.arg_1 = 0x1E;
1303 ins.load_store.arg_2 = 0x1E;
1304 ins.mask = mask_of(nr_comp);
1305
1306 /* Use the type appropriate load */
1307 switch (t) {
1308 case nir_type_uint:
1309 case nir_type_bool:
1310 ins.load_store.op = midgard_op_ld_attr_32u;
1311 break;
1312 case nir_type_int:
1313 ins.load_store.op = midgard_op_ld_attr_32i;
1314 break;
1315 case nir_type_float:
1316 ins.load_store.op = midgard_op_ld_attr_32;
1317 break;
1318 default:
1319 unreachable("Attempted to load unknown type");
1320 break;
1321 }
1322
1323 emit_mir_instruction(ctx, ins);
1324 }
1325
1326 static void
1327 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1328 unsigned nr_components, unsigned offset)
1329 {
1330 nir_dest nir_dest;
1331
1332 /* Figure out which uniform this is */
1333 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1334 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1335
1336 unsigned dest = nir_dest_index(&nir_dest);
1337
1338 /* Sysvals are prefix uniforms */
1339 unsigned uniform = ((uintptr_t) val) - 1;
1340
1341 /* Emit the read itself -- this is never indirect */
1342 midgard_instruction *ins =
1343 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1344
1345 ins->mask = mask_of(nr_components);
1346 }
1347
1348 static unsigned
1349 compute_builtin_arg(nir_op op)
1350 {
1351 switch (op) {
1352 case nir_intrinsic_load_work_group_id:
1353 return 0x14;
1354 case nir_intrinsic_load_local_invocation_id:
1355 return 0x10;
1356 default:
1357 unreachable("Invalid compute paramater loaded");
1358 }
1359 }
1360
1361 static void
1362 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1363 {
1364 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1365
1366 midgard_instruction *br = ctx->writeout_branch[rt];
1367
1368 assert(!br);
1369
1370 emit_explicit_constant(ctx, src, src);
1371
1372 struct midgard_instruction ins =
1373 v_branch(false, false);
1374
1375 ins.writeout = true;
1376
1377 /* Add dependencies */
1378 ins.src[0] = src;
1379 ins.src_types[0] = nir_type_uint32;
1380 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1381 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1382
1383 /* Emit the branch */
1384 br = emit_mir_instruction(ctx, ins);
1385 schedule_barrier(ctx);
1386 ctx->writeout_branch[rt] = br;
1387
1388 /* Push our current location = current block count - 1 = where we'll
1389 * jump to. Maybe a bit too clever for my own good */
1390
1391 br->branch.target_block = ctx->block_count - 1;
1392 }
1393
1394 static void
1395 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1396 {
1397 unsigned reg = nir_dest_index(&instr->dest);
1398 midgard_instruction ins = m_ld_compute_id(reg, 0);
1399 ins.mask = mask_of(3);
1400 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1401 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1402 emit_mir_instruction(ctx, ins);
1403 }
1404
1405 static unsigned
1406 vertex_builtin_arg(nir_op op)
1407 {
1408 switch (op) {
1409 case nir_intrinsic_load_vertex_id:
1410 return PAN_VERTEX_ID;
1411 case nir_intrinsic_load_instance_id:
1412 return PAN_INSTANCE_ID;
1413 default:
1414 unreachable("Invalid vertex builtin");
1415 }
1416 }
1417
1418 static void
1419 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1420 {
1421 unsigned reg = nir_dest_index(&instr->dest);
1422 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1423 }
1424
1425 static void
1426 emit_control_barrier(compiler_context *ctx)
1427 {
1428 midgard_instruction ins = {
1429 .type = TAG_TEXTURE_4,
1430 .src = { ~0, ~0, ~0, ~0 },
1431 .texture = {
1432 .op = TEXTURE_OP_BARRIER,
1433
1434 /* TODO: optimize */
1435 .barrier_buffer = 1,
1436 .barrier_shared = 1
1437 }
1438 };
1439
1440 emit_mir_instruction(ctx, ins);
1441 }
1442
1443 static const nir_variable *
1444 search_var(struct exec_list *vars, unsigned driver_loc)
1445 {
1446 nir_foreach_variable(var, vars) {
1447 if (var->data.driver_location == driver_loc)
1448 return var;
1449 }
1450
1451 return NULL;
1452 }
1453
1454 static unsigned
1455 mir_get_branch_cond(nir_src *src, bool *invert)
1456 {
1457 /* Wrap it. No swizzle since it's a scalar */
1458
1459 nir_alu_src alu = {
1460 .src = *src
1461 };
1462
1463 *invert = pan_has_source_mod(&alu, nir_op_inot);
1464 return nir_src_index(NULL, &alu.src);
1465 }
1466
1467 static void
1468 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1469 {
1470 unsigned offset = 0, reg;
1471
1472 switch (instr->intrinsic) {
1473 case nir_intrinsic_discard_if:
1474 case nir_intrinsic_discard: {
1475 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1476 struct midgard_instruction discard = v_branch(conditional, false);
1477 discard.branch.target_type = TARGET_DISCARD;
1478
1479 if (conditional) {
1480 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1481 &discard.branch.invert_conditional);
1482 discard.src_types[0] = nir_type_uint32;
1483 }
1484
1485 emit_mir_instruction(ctx, discard);
1486 schedule_barrier(ctx);
1487
1488 break;
1489 }
1490
1491 case nir_intrinsic_load_uniform:
1492 case nir_intrinsic_load_ubo:
1493 case nir_intrinsic_load_global:
1494 case nir_intrinsic_load_shared:
1495 case nir_intrinsic_load_input:
1496 case nir_intrinsic_load_interpolated_input: {
1497 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1498 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1499 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1500 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1501 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1502 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1503
1504 /* Get the base type of the intrinsic */
1505 /* TODO: Infer type? Does it matter? */
1506 nir_alu_type t =
1507 (is_ubo || is_global || is_shared) ? nir_type_uint :
1508 (is_interp) ? nir_type_float :
1509 nir_intrinsic_type(instr);
1510
1511 t = nir_alu_type_get_base_type(t);
1512
1513 if (!(is_ubo || is_global)) {
1514 offset = nir_intrinsic_base(instr);
1515 }
1516
1517 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1518
1519 nir_src *src_offset = nir_get_io_offset_src(instr);
1520
1521 bool direct = nir_src_is_const(*src_offset);
1522 nir_src *indirect_offset = direct ? NULL : src_offset;
1523
1524 if (direct)
1525 offset += nir_src_as_uint(*src_offset);
1526
1527 /* We may need to apply a fractional offset */
1528 int component = (is_flat || is_interp) ?
1529 nir_intrinsic_component(instr) : 0;
1530 reg = nir_dest_index(&instr->dest);
1531
1532 if (is_uniform && !ctx->is_blend) {
1533 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1534 } else if (is_ubo) {
1535 nir_src index = instr->src[0];
1536
1537 /* TODO: Is indirect block number possible? */
1538 assert(nir_src_is_const(index));
1539
1540 uint32_t uindex = nir_src_as_uint(index) + 1;
1541 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1542 } else if (is_global || is_shared) {
1543 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1544 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1545 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1546 } else if (ctx->is_blend) {
1547 /* For blend shaders, load the input color, which is
1548 * preloaded to r0 */
1549
1550 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1551 emit_mir_instruction(ctx, move);
1552 schedule_barrier(ctx);
1553 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1554 emit_attr_read(ctx, reg, offset, nr_comp, t);
1555 } else {
1556 DBG("Unknown load\n");
1557 assert(0);
1558 }
1559
1560 break;
1561 }
1562
1563 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1564 case nir_intrinsic_load_barycentric_pixel:
1565 case nir_intrinsic_load_barycentric_centroid:
1566 break;
1567
1568 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1569
1570 case nir_intrinsic_load_raw_output_pan:
1571 case nir_intrinsic_load_output_u8_as_fp16_pan:
1572 reg = nir_dest_index(&instr->dest);
1573 assert(ctx->is_blend);
1574
1575 /* T720 and below use different blend opcodes with slightly
1576 * different semantics than T760 and up */
1577
1578 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1579 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1580
1581 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1582 ld.load_store.op = old_blend ?
1583 midgard_op_ld_color_buffer_u8_as_fp16_old :
1584 midgard_op_ld_color_buffer_u8_as_fp16;
1585
1586 if (old_blend) {
1587 ld.load_store.address = 1;
1588 ld.load_store.arg_2 = 0x1E;
1589 }
1590
1591 for (unsigned c = 2; c < 16; ++c)
1592 ld.swizzle[0][c] = 0;
1593 }
1594
1595 emit_mir_instruction(ctx, ld);
1596 break;
1597
1598 case nir_intrinsic_load_blend_const_color_rgba: {
1599 assert(ctx->is_blend);
1600 reg = nir_dest_index(&instr->dest);
1601
1602 /* Blend constants are embedded directly in the shader and
1603 * patched in, so we use some magic routing */
1604
1605 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1606 ins.has_constants = true;
1607 ins.has_blend_constant = true;
1608 emit_mir_instruction(ctx, ins);
1609 break;
1610 }
1611
1612 case nir_intrinsic_store_zs_output_pan: {
1613 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1614 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1615 MIDGARD_ZS_RT);
1616
1617 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1618
1619 if (!nir_intrinsic_component(instr))
1620 br->writeout_depth = true;
1621 if (nir_intrinsic_component(instr) ||
1622 instr->num_components)
1623 br->writeout_stencil = true;
1624 assert(br->writeout_depth | br->writeout_stencil);
1625 break;
1626 }
1627
1628 case nir_intrinsic_store_output:
1629 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1630
1631 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1632
1633 reg = nir_src_index(ctx, &instr->src[0]);
1634
1635 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1636 const nir_variable *var;
1637 enum midgard_rt_id rt;
1638
1639 var = search_var(&ctx->nir->outputs,
1640 nir_intrinsic_base(instr));
1641 assert(var);
1642 if (var->data.location == FRAG_RESULT_COLOR)
1643 rt = MIDGARD_COLOR_RT0;
1644 else if (var->data.location >= FRAG_RESULT_DATA0)
1645 rt = MIDGARD_COLOR_RT0 + var->data.location -
1646 FRAG_RESULT_DATA0;
1647 else
1648 assert(0);
1649
1650 emit_fragment_store(ctx, reg, rt);
1651 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1652 /* We should have been vectorized, though we don't
1653 * currently check that st_vary is emitted only once
1654 * per slot (this is relevant, since there's not a mask
1655 * parameter available on the store [set to 0 by the
1656 * blob]). We do respect the component by adjusting the
1657 * swizzle. If this is a constant source, we'll need to
1658 * emit that explicitly. */
1659
1660 emit_explicit_constant(ctx, reg, reg);
1661
1662 unsigned dst_component = nir_intrinsic_component(instr);
1663 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1664
1665 midgard_instruction st = m_st_vary_32(reg, offset);
1666 st.load_store.arg_1 = 0x9E;
1667 st.load_store.arg_2 = 0x1E;
1668
1669 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1670 case nir_type_uint:
1671 case nir_type_bool:
1672 st.load_store.op = midgard_op_st_vary_32u;
1673 break;
1674 case nir_type_int:
1675 st.load_store.op = midgard_op_st_vary_32i;
1676 break;
1677 case nir_type_float:
1678 st.load_store.op = midgard_op_st_vary_32;
1679 break;
1680 default:
1681 unreachable("Attempted to store unknown type");
1682 break;
1683 }
1684
1685 /* nir_intrinsic_component(store_intr) encodes the
1686 * destination component start. Source component offset
1687 * adjustment is taken care of in
1688 * install_registers_instr(), when offset_swizzle() is
1689 * called.
1690 */
1691 unsigned src_component = COMPONENT_X;
1692
1693 assert(nr_comp > 0);
1694 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1695 st.swizzle[0][i] = src_component;
1696 if (i >= dst_component && i < dst_component + nr_comp - 1)
1697 src_component++;
1698 }
1699
1700 emit_mir_instruction(ctx, st);
1701 } else {
1702 DBG("Unknown store\n");
1703 assert(0);
1704 }
1705
1706 break;
1707
1708 /* Special case of store_output for lowered blend shaders */
1709 case nir_intrinsic_store_raw_output_pan:
1710 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1711 reg = nir_src_index(ctx, &instr->src[0]);
1712
1713 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1714 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1715 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1716 * of:
1717 *
1718 * imov r0.xyzw, r0.xxxx
1719 */
1720
1721 unsigned expanded = make_compiler_temp(ctx);
1722
1723 midgard_instruction splatter = v_mov(reg, expanded);
1724
1725 for (unsigned c = 0; c < 16; ++c)
1726 splatter.swizzle[1][c] = 0;
1727
1728 emit_mir_instruction(ctx, splatter);
1729 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1730 } else
1731 emit_fragment_store(ctx, reg, ctx->blend_rt);
1732
1733 break;
1734
1735 case nir_intrinsic_store_global:
1736 case nir_intrinsic_store_shared:
1737 reg = nir_src_index(ctx, &instr->src[0]);
1738 emit_explicit_constant(ctx, reg, reg);
1739
1740 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1741 break;
1742
1743 case nir_intrinsic_load_ssbo_address:
1744 emit_sysval_read(ctx, &instr->instr, 1, 0);
1745 break;
1746
1747 case nir_intrinsic_get_buffer_size:
1748 emit_sysval_read(ctx, &instr->instr, 1, 8);
1749 break;
1750
1751 case nir_intrinsic_load_viewport_scale:
1752 case nir_intrinsic_load_viewport_offset:
1753 case nir_intrinsic_load_num_work_groups:
1754 case nir_intrinsic_load_sampler_lod_parameters_pan:
1755 emit_sysval_read(ctx, &instr->instr, 3, 0);
1756 break;
1757
1758 case nir_intrinsic_load_work_group_id:
1759 case nir_intrinsic_load_local_invocation_id:
1760 emit_compute_builtin(ctx, instr);
1761 break;
1762
1763 case nir_intrinsic_load_vertex_id:
1764 case nir_intrinsic_load_instance_id:
1765 emit_vertex_builtin(ctx, instr);
1766 break;
1767
1768 case nir_intrinsic_memory_barrier_buffer:
1769 case nir_intrinsic_memory_barrier_shared:
1770 break;
1771
1772 case nir_intrinsic_control_barrier:
1773 schedule_barrier(ctx);
1774 emit_control_barrier(ctx);
1775 schedule_barrier(ctx);
1776 break;
1777
1778 default:
1779 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1780 assert(0);
1781 break;
1782 }
1783 }
1784
1785 static unsigned
1786 midgard_tex_format(enum glsl_sampler_dim dim)
1787 {
1788 switch (dim) {
1789 case GLSL_SAMPLER_DIM_1D:
1790 case GLSL_SAMPLER_DIM_BUF:
1791 return MALI_TEX_1D;
1792
1793 case GLSL_SAMPLER_DIM_2D:
1794 case GLSL_SAMPLER_DIM_EXTERNAL:
1795 case GLSL_SAMPLER_DIM_RECT:
1796 return MALI_TEX_2D;
1797
1798 case GLSL_SAMPLER_DIM_3D:
1799 return MALI_TEX_3D;
1800
1801 case GLSL_SAMPLER_DIM_CUBE:
1802 return MALI_TEX_CUBE;
1803
1804 default:
1805 DBG("Unknown sampler dim type\n");
1806 assert(0);
1807 return 0;
1808 }
1809 }
1810
1811 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1812 * was successful */
1813
1814 static bool
1815 pan_attach_constant_bias(
1816 compiler_context *ctx,
1817 nir_src lod,
1818 midgard_texture_word *word)
1819 {
1820 /* To attach as constant, it has to *be* constant */
1821
1822 if (!nir_src_is_const(lod))
1823 return false;
1824
1825 float f = nir_src_as_float(lod);
1826
1827 /* Break into fixed-point */
1828 signed lod_int = f;
1829 float lod_frac = f - lod_int;
1830
1831 /* Carry over negative fractions */
1832 if (lod_frac < 0.0) {
1833 lod_int--;
1834 lod_frac += 1.0;
1835 }
1836
1837 /* Encode */
1838 word->bias = float_to_ubyte(lod_frac);
1839 word->bias_int = lod_int;
1840
1841 return true;
1842 }
1843
1844 static void
1845 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1846 unsigned midgard_texop)
1847 {
1848 /* TODO */
1849 //assert (!instr->sampler);
1850
1851 int texture_index = instr->texture_index;
1852 int sampler_index = texture_index;
1853
1854 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1855 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1856
1857 midgard_instruction ins = {
1858 .type = TAG_TEXTURE_4,
1859 .mask = 0xF,
1860 .dest = nir_dest_index(&instr->dest),
1861 .src = { ~0, ~0, ~0, ~0 },
1862 .dest_type = dest_type,
1863 .swizzle = SWIZZLE_IDENTITY_4,
1864 .texture = {
1865 .op = midgard_texop,
1866 .format = midgard_tex_format(instr->sampler_dim),
1867 .texture_handle = texture_index,
1868 .sampler_handle = sampler_index,
1869 .shadow = instr->is_shadow,
1870 }
1871 };
1872
1873 if (instr->is_shadow && !instr->is_new_style_shadow)
1874 for (int i = 0; i < 4; ++i)
1875 ins.swizzle[0][i] = COMPONENT_X;
1876
1877 /* We may need a temporary for the coordinate */
1878
1879 bool needs_temp_coord =
1880 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1881 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1882 (instr->is_shadow);
1883
1884 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1885
1886 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1887 int index = nir_src_index(ctx, &instr->src[i].src);
1888 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1889 unsigned sz = nir_src_bit_size(instr->src[i].src);
1890 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1891
1892 switch (instr->src[i].src_type) {
1893 case nir_tex_src_coord: {
1894 emit_explicit_constant(ctx, index, index);
1895
1896 unsigned coord_mask = mask_of(instr->coord_components);
1897
1898 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1899
1900 if (flip_zw)
1901 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1902
1903 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1904 /* texelFetch is undefined on samplerCube */
1905 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1906
1907 /* For cubemaps, we use a special ld/st op to
1908 * select the face and copy the xy into the
1909 * texture register */
1910
1911 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1912 ld.src[1] = index;
1913 ld.src_types[1] = T;
1914 ld.mask = 0x3; /* xy */
1915 ld.load_store.arg_1 = 0x20;
1916 ld.swizzle[1][3] = COMPONENT_X;
1917 emit_mir_instruction(ctx, ld);
1918
1919 /* xyzw -> xyxx */
1920 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1921 ins.swizzle[1][3] = COMPONENT_X;
1922 } else if (needs_temp_coord) {
1923 /* mov coord_temp, coords */
1924 midgard_instruction mov = v_mov(index, coords);
1925 mov.mask = coord_mask;
1926
1927 if (flip_zw)
1928 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1929
1930 emit_mir_instruction(ctx, mov);
1931 } else {
1932 coords = index;
1933 }
1934
1935 ins.src[1] = coords;
1936 ins.src_types[1] = T;
1937
1938 /* Texelfetch coordinates uses all four elements
1939 * (xyz/index) regardless of texture dimensionality,
1940 * which means it's necessary to zero the unused
1941 * components to keep everything happy */
1942
1943 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1944 /* mov index.zw, #0, or generalized */
1945 midgard_instruction mov =
1946 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1947 mov.has_constants = true;
1948 mov.mask = coord_mask ^ 0xF;
1949 emit_mir_instruction(ctx, mov);
1950 }
1951
1952 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1953 /* Array component in w but NIR wants it in z,
1954 * but if we have a temp coord we already fixed
1955 * that up */
1956
1957 if (nr_components == 3) {
1958 ins.swizzle[1][2] = COMPONENT_Z;
1959 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1960 } else if (nr_components == 2) {
1961 ins.swizzle[1][2] =
1962 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1963 ins.swizzle[1][3] = COMPONENT_X;
1964 } else
1965 unreachable("Invalid texture 2D components");
1966 }
1967
1968 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1969 /* We zeroed */
1970 ins.swizzle[1][2] = COMPONENT_Z;
1971 ins.swizzle[1][3] = COMPONENT_W;
1972 }
1973
1974 break;
1975 }
1976
1977 case nir_tex_src_bias:
1978 case nir_tex_src_lod: {
1979 /* Try as a constant if we can */
1980
1981 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1982 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1983 break;
1984
1985 ins.texture.lod_register = true;
1986 ins.src[2] = index;
1987 ins.src_types[2] = T;
1988
1989 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1990 ins.swizzle[2][c] = COMPONENT_X;
1991
1992 emit_explicit_constant(ctx, index, index);
1993
1994 break;
1995 };
1996
1997 case nir_tex_src_offset: {
1998 ins.texture.offset_register = true;
1999 ins.src[3] = index;
2000 ins.src_types[3] = T;
2001
2002 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2003 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
2004
2005 emit_explicit_constant(ctx, index, index);
2006 break;
2007 };
2008
2009 case nir_tex_src_comparator: {
2010 unsigned comp = COMPONENT_Z;
2011
2012 /* mov coord_temp.foo, coords */
2013 midgard_instruction mov = v_mov(index, coords);
2014 mov.mask = 1 << comp;
2015
2016 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
2017 mov.swizzle[1][i] = COMPONENT_X;
2018
2019 emit_mir_instruction(ctx, mov);
2020 break;
2021 }
2022
2023 default: {
2024 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
2025 assert(0);
2026 }
2027 }
2028 }
2029
2030 emit_mir_instruction(ctx, ins);
2031 }
2032
2033 static void
2034 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2035 {
2036 switch (instr->op) {
2037 case nir_texop_tex:
2038 case nir_texop_txb:
2039 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2040 break;
2041 case nir_texop_txl:
2042 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2043 break;
2044 case nir_texop_txf:
2045 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2046 break;
2047 case nir_texop_txs:
2048 emit_sysval_read(ctx, &instr->instr, 4, 0);
2049 break;
2050 default: {
2051 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2052 assert(0);
2053 }
2054 }
2055 }
2056
2057 static void
2058 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2059 {
2060 switch (instr->type) {
2061 case nir_jump_break: {
2062 /* Emit a branch out of the loop */
2063 struct midgard_instruction br = v_branch(false, false);
2064 br.branch.target_type = TARGET_BREAK;
2065 br.branch.target_break = ctx->current_loop_depth;
2066 emit_mir_instruction(ctx, br);
2067 break;
2068 }
2069
2070 default:
2071 DBG("Unknown jump type %d\n", instr->type);
2072 break;
2073 }
2074 }
2075
2076 static void
2077 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2078 {
2079 switch (instr->type) {
2080 case nir_instr_type_load_const:
2081 emit_load_const(ctx, nir_instr_as_load_const(instr));
2082 break;
2083
2084 case nir_instr_type_intrinsic:
2085 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2086 break;
2087
2088 case nir_instr_type_alu:
2089 emit_alu(ctx, nir_instr_as_alu(instr));
2090 break;
2091
2092 case nir_instr_type_tex:
2093 emit_tex(ctx, nir_instr_as_tex(instr));
2094 break;
2095
2096 case nir_instr_type_jump:
2097 emit_jump(ctx, nir_instr_as_jump(instr));
2098 break;
2099
2100 case nir_instr_type_ssa_undef:
2101 /* Spurious */
2102 break;
2103
2104 default:
2105 DBG("Unhandled instruction type\n");
2106 break;
2107 }
2108 }
2109
2110
2111 /* ALU instructions can inline or embed constants, which decreases register
2112 * pressure and saves space. */
2113
2114 #define CONDITIONAL_ATTACH(idx) { \
2115 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2116 \
2117 if (entry) { \
2118 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2119 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2120 } \
2121 }
2122
2123 static void
2124 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2125 {
2126 mir_foreach_instr_in_block(block, alu) {
2127 /* Other instructions cannot inline constants */
2128 if (alu->type != TAG_ALU_4) continue;
2129 if (alu->compact_branch) continue;
2130
2131 /* If there is already a constant here, we can do nothing */
2132 if (alu->has_constants) continue;
2133
2134 CONDITIONAL_ATTACH(0);
2135
2136 if (!alu->has_constants) {
2137 CONDITIONAL_ATTACH(1)
2138 } else if (!alu->inline_constant) {
2139 /* Corner case: _two_ vec4 constants, for instance with a
2140 * csel. For this case, we can only use a constant
2141 * register for one, we'll have to emit a move for the
2142 * other. */
2143
2144 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2145 unsigned scratch = make_compiler_temp(ctx);
2146
2147 if (entry) {
2148 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2149 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2150
2151 /* Set the source */
2152 alu->src[1] = scratch;
2153
2154 /* Inject us -before- the last instruction which set r31 */
2155 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2156 }
2157 }
2158 }
2159 }
2160
2161 /* Midgard supports two types of constants, embedded constants (128-bit) and
2162 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2163 * constants can be demoted to inline constants, for space savings and
2164 * sometimes a performance boost */
2165
2166 static void
2167 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2168 {
2169 mir_foreach_instr_in_block(block, ins) {
2170 if (!ins->has_constants) continue;
2171 if (ins->has_inline_constant) continue;
2172
2173 /* Blend constants must not be inlined by definition */
2174 if (ins->has_blend_constant) continue;
2175
2176 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2177 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2178 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2179
2180 if (!(is_16 || is_32))
2181 continue;
2182
2183 /* src1 cannot be an inline constant due to encoding
2184 * restrictions. So, if possible we try to flip the arguments
2185 * in that case */
2186
2187 int op = ins->alu.op;
2188
2189 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2190 alu_opcode_props[op].props & OP_COMMUTES) {
2191 mir_flip(ins);
2192 }
2193
2194 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2195 /* Extract the source information */
2196
2197 midgard_vector_alu_src *src;
2198 int q = ins->alu.src2;
2199 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2200 src = m;
2201
2202 /* Component is from the swizzle. Take a nonzero component */
2203 assert(ins->mask);
2204 unsigned first_comp = ffs(ins->mask) - 1;
2205 unsigned component = ins->swizzle[1][first_comp];
2206
2207 /* Scale constant appropriately, if we can legally */
2208 uint16_t scaled_constant = 0;
2209
2210 if (is_16) {
2211 scaled_constant = ins->constants.u16[component];
2212 } else if (midgard_is_integer_op(op)) {
2213 scaled_constant = ins->constants.u32[component];
2214
2215 /* Constant overflow after resize */
2216 if (scaled_constant != ins->constants.u32[component])
2217 continue;
2218 } else {
2219 float original = ins->constants.f32[component];
2220 scaled_constant = _mesa_float_to_half(original);
2221
2222 /* Check for loss of precision. If this is
2223 * mediump, we don't care, but for a highp
2224 * shader, we need to pay attention. NIR
2225 * doesn't yet tell us which mode we're in!
2226 * Practically this prevents most constants
2227 * from being inlined, sadly. */
2228
2229 float fp32 = _mesa_half_to_float(scaled_constant);
2230
2231 if (fp32 != original)
2232 continue;
2233 }
2234
2235 /* We don't know how to handle these with a constant */
2236
2237 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2238 DBG("Bailing inline constant...\n");
2239 continue;
2240 }
2241
2242 /* Make sure that the constant is not itself a vector
2243 * by checking if all accessed values are the same. */
2244
2245 const midgard_constants *cons = &ins->constants;
2246 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2247
2248 bool is_vector = false;
2249 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2250
2251 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2252 /* We only care if this component is actually used */
2253 if (!(mask & (1 << c)))
2254 continue;
2255
2256 uint32_t test = is_16 ?
2257 cons->u16[ins->swizzle[1][c]] :
2258 cons->u32[ins->swizzle[1][c]];
2259
2260 if (test != value) {
2261 is_vector = true;
2262 break;
2263 }
2264 }
2265
2266 if (is_vector)
2267 continue;
2268
2269 /* Get rid of the embedded constant */
2270 ins->has_constants = false;
2271 ins->src[1] = ~0;
2272 ins->has_inline_constant = true;
2273 ins->inline_constant = scaled_constant;
2274 }
2275 }
2276 }
2277
2278 /* Dead code elimination for branches at the end of a block - only one branch
2279 * per block is legal semantically */
2280
2281 static void
2282 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2283 {
2284 bool branched = false;
2285
2286 mir_foreach_instr_in_block_safe(block, ins) {
2287 if (!midgard_is_branch_unit(ins->unit)) continue;
2288
2289 if (branched)
2290 mir_remove_instruction(ins);
2291
2292 branched = true;
2293 }
2294 }
2295
2296 static unsigned
2297 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2298 {
2299 /* Loop to ourselves */
2300 midgard_instruction *br = ctx->writeout_branch[rt];
2301 struct midgard_instruction ins = v_branch(false, false);
2302 ins.writeout = true;
2303 ins.writeout_depth = br->writeout_depth;
2304 ins.writeout_stencil = br->writeout_stencil;
2305 ins.branch.target_block = ctx->block_count - 1;
2306 ins.constants.u32[0] = br->constants.u32[0];
2307 emit_mir_instruction(ctx, ins);
2308
2309 ctx->current_block->epilogue = true;
2310 schedule_barrier(ctx);
2311 return ins.branch.target_block;
2312 }
2313
2314 static midgard_block *
2315 emit_block(compiler_context *ctx, nir_block *block)
2316 {
2317 midgard_block *this_block = ctx->after_block;
2318 ctx->after_block = NULL;
2319
2320 if (!this_block)
2321 this_block = create_empty_block(ctx);
2322
2323 list_addtail(&this_block->base.link, &ctx->blocks);
2324
2325 this_block->scheduled = false;
2326 ++ctx->block_count;
2327
2328 /* Set up current block */
2329 list_inithead(&this_block->base.instructions);
2330 ctx->current_block = this_block;
2331
2332 nir_foreach_instr(instr, block) {
2333 emit_instr(ctx, instr);
2334 ++ctx->instruction_count;
2335 }
2336
2337 return this_block;
2338 }
2339
2340 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2341
2342 static void
2343 emit_if(struct compiler_context *ctx, nir_if *nif)
2344 {
2345 midgard_block *before_block = ctx->current_block;
2346
2347 /* Speculatively emit the branch, but we can't fill it in until later */
2348 bool inv = false;
2349 EMIT(branch, true, true);
2350 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2351 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2352 then_branch->src_types[0] = nir_type_uint32;
2353 then_branch->branch.invert_conditional = !inv;
2354
2355 /* Emit the two subblocks. */
2356 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2357 midgard_block *end_then_block = ctx->current_block;
2358
2359 /* Emit a jump from the end of the then block to the end of the else */
2360 EMIT(branch, false, false);
2361 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2362
2363 /* Emit second block, and check if it's empty */
2364
2365 int else_idx = ctx->block_count;
2366 int count_in = ctx->instruction_count;
2367 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2368 midgard_block *end_else_block = ctx->current_block;
2369 int after_else_idx = ctx->block_count;
2370
2371 /* Now that we have the subblocks emitted, fix up the branches */
2372
2373 assert(then_block);
2374 assert(else_block);
2375
2376 if (ctx->instruction_count == count_in) {
2377 /* The else block is empty, so don't emit an exit jump */
2378 mir_remove_instruction(then_exit);
2379 then_branch->branch.target_block = after_else_idx;
2380 } else {
2381 then_branch->branch.target_block = else_idx;
2382 then_exit->branch.target_block = after_else_idx;
2383 }
2384
2385 /* Wire up the successors */
2386
2387 ctx->after_block = create_empty_block(ctx);
2388
2389 pan_block_add_successor(&before_block->base, &then_block->base);
2390 pan_block_add_successor(&before_block->base, &else_block->base);
2391
2392 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2393 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2394 }
2395
2396 static void
2397 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2398 {
2399 /* Remember where we are */
2400 midgard_block *start_block = ctx->current_block;
2401
2402 /* Allocate a loop number, growing the current inner loop depth */
2403 int loop_idx = ++ctx->current_loop_depth;
2404
2405 /* Get index from before the body so we can loop back later */
2406 int start_idx = ctx->block_count;
2407
2408 /* Emit the body itself */
2409 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2410
2411 /* Branch back to loop back */
2412 struct midgard_instruction br_back = v_branch(false, false);
2413 br_back.branch.target_block = start_idx;
2414 emit_mir_instruction(ctx, br_back);
2415
2416 /* Mark down that branch in the graph. */
2417 pan_block_add_successor(&start_block->base, &loop_block->base);
2418 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2419
2420 /* Find the index of the block about to follow us (note: we don't add
2421 * one; blocks are 0-indexed so we get a fencepost problem) */
2422 int break_block_idx = ctx->block_count;
2423
2424 /* Fix up the break statements we emitted to point to the right place,
2425 * now that we can allocate a block number for them */
2426 ctx->after_block = create_empty_block(ctx);
2427
2428 mir_foreach_block_from(ctx, start_block, _block) {
2429 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2430 if (ins->type != TAG_ALU_4) continue;
2431 if (!ins->compact_branch) continue;
2432
2433 /* We found a branch -- check the type to see if we need to do anything */
2434 if (ins->branch.target_type != TARGET_BREAK) continue;
2435
2436 /* It's a break! Check if it's our break */
2437 if (ins->branch.target_break != loop_idx) continue;
2438
2439 /* Okay, cool, we're breaking out of this loop.
2440 * Rewrite from a break to a goto */
2441
2442 ins->branch.target_type = TARGET_GOTO;
2443 ins->branch.target_block = break_block_idx;
2444
2445 pan_block_add_successor(_block, &ctx->after_block->base);
2446 }
2447 }
2448
2449 /* Now that we've finished emitting the loop, free up the depth again
2450 * so we play nice with recursion amid nested loops */
2451 --ctx->current_loop_depth;
2452
2453 /* Dump loop stats */
2454 ++ctx->loop_count;
2455 }
2456
2457 static midgard_block *
2458 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2459 {
2460 midgard_block *start_block = NULL;
2461
2462 foreach_list_typed(nir_cf_node, node, node, list) {
2463 switch (node->type) {
2464 case nir_cf_node_block: {
2465 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2466
2467 if (!start_block)
2468 start_block = block;
2469
2470 break;
2471 }
2472
2473 case nir_cf_node_if:
2474 emit_if(ctx, nir_cf_node_as_if(node));
2475 break;
2476
2477 case nir_cf_node_loop:
2478 emit_loop(ctx, nir_cf_node_as_loop(node));
2479 break;
2480
2481 case nir_cf_node_function:
2482 assert(0);
2483 break;
2484 }
2485 }
2486
2487 return start_block;
2488 }
2489
2490 /* Due to lookahead, we need to report the first tag executed in the command
2491 * stream and in branch targets. An initial block might be empty, so iterate
2492 * until we find one that 'works' */
2493
2494 static unsigned
2495 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2496 {
2497 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2498
2499 mir_foreach_block_from(ctx, initial_block, _v) {
2500 midgard_block *v = (midgard_block *) _v;
2501 if (v->quadword_count) {
2502 midgard_bundle *initial_bundle =
2503 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2504
2505 return initial_bundle->tag;
2506 }
2507 }
2508
2509 /* Default to a tag 1 which will break from the shader, in case we jump
2510 * to the exit block (i.e. `return` in a compute shader) */
2511
2512 return 1;
2513 }
2514
2515 /* For each fragment writeout instruction, generate a writeout loop to
2516 * associate with it */
2517
2518 static void
2519 mir_add_writeout_loops(compiler_context *ctx)
2520 {
2521 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2522 midgard_instruction *br = ctx->writeout_branch[rt];
2523 if (!br) continue;
2524
2525 unsigned popped = br->branch.target_block;
2526 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2527 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2528 br->branch.target_type = TARGET_GOTO;
2529
2530 /* If we have more RTs, we'll need to restore back after our
2531 * loop terminates */
2532
2533 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2534 midgard_instruction uncond = v_branch(false, false);
2535 uncond.branch.target_block = popped;
2536 uncond.branch.target_type = TARGET_GOTO;
2537 emit_mir_instruction(ctx, uncond);
2538 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2539 schedule_barrier(ctx);
2540 } else {
2541 /* We're last, so we can terminate here */
2542 br->last_writeout = true;
2543 }
2544 }
2545 }
2546
2547 int
2548 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2549 {
2550 struct util_dynarray *compiled = &program->compiled;
2551
2552 midgard_debug = debug_get_option_midgard_debug();
2553
2554 /* TODO: Bound against what? */
2555 compiler_context *ctx = rzalloc(NULL, compiler_context);
2556
2557 ctx->nir = nir;
2558 ctx->stage = nir->info.stage;
2559 ctx->is_blend = is_blend;
2560 ctx->alpha_ref = program->alpha_ref;
2561 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2562 ctx->quirks = midgard_get_quirks(gpu_id);
2563
2564 /* Start off with a safe cutoff, allowing usage of all 16 work
2565 * registers. Later, we'll promote uniform reads to uniform registers
2566 * if we determine it is beneficial to do so */
2567 ctx->uniform_cutoff = 8;
2568
2569 /* Initialize at a global (not block) level hash tables */
2570
2571 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2572 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2573
2574 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2575 * (so we don't accidentally duplicate the epilogue since mesa/st has
2576 * messed with our I/O quite a bit already) */
2577
2578 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2579
2580 if (ctx->stage == MESA_SHADER_VERTEX) {
2581 NIR_PASS_V(nir, nir_lower_viewport_transform);
2582 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2583 }
2584
2585 NIR_PASS_V(nir, nir_lower_var_copies);
2586 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2587 NIR_PASS_V(nir, nir_split_var_copies);
2588 NIR_PASS_V(nir, nir_lower_var_copies);
2589 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2590 NIR_PASS_V(nir, nir_lower_var_copies);
2591 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2592
2593 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2594 NIR_PASS_V(nir, nir_lower_ssbo);
2595 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2596
2597 /* Optimisation passes */
2598
2599 optimise_nir(nir, ctx->quirks);
2600
2601 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2602 nir_print_shader(nir, stdout);
2603 }
2604
2605 /* Assign sysvals and counts, now that we're sure
2606 * (post-optimisation) */
2607
2608 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2609 program->sysval_count = ctx->sysvals.sysval_count;
2610 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2611
2612 nir_foreach_function(func, nir) {
2613 if (!func->impl)
2614 continue;
2615
2616 list_inithead(&ctx->blocks);
2617 ctx->block_count = 0;
2618 ctx->func = func;
2619 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2620
2621 emit_cf_list(ctx, &func->impl->body);
2622 free(ctx->already_emitted);
2623 break; /* TODO: Multi-function shaders */
2624 }
2625
2626 util_dynarray_init(compiled, NULL);
2627
2628 /* Per-block lowering before opts */
2629
2630 mir_foreach_block(ctx, _block) {
2631 midgard_block *block = (midgard_block *) _block;
2632 inline_alu_constants(ctx, block);
2633 midgard_opt_promote_fmov(ctx, block);
2634 embedded_to_inline_constant(ctx, block);
2635 }
2636 /* MIR-level optimizations */
2637
2638 bool progress = false;
2639
2640 do {
2641 progress = false;
2642 progress |= midgard_opt_dead_code_eliminate(ctx);
2643
2644 mir_foreach_block(ctx, _block) {
2645 midgard_block *block = (midgard_block *) _block;
2646 progress |= midgard_opt_copy_prop(ctx, block);
2647 progress |= midgard_opt_combine_projection(ctx, block);
2648 progress |= midgard_opt_varying_projection(ctx, block);
2649 }
2650 } while (progress);
2651
2652 mir_foreach_block(ctx, _block) {
2653 midgard_block *block = (midgard_block *) _block;
2654 midgard_lower_derivatives(ctx, block);
2655 midgard_cull_dead_branch(ctx, block);
2656 }
2657
2658 if (ctx->stage == MESA_SHADER_FRAGMENT)
2659 mir_add_writeout_loops(ctx);
2660
2661 /* Analyze now that the code is known but before scheduling creates
2662 * pipeline registers which are harder to track */
2663 mir_analyze_helper_terminate(ctx);
2664 mir_analyze_helper_requirements(ctx);
2665
2666 /* Schedule! */
2667 midgard_schedule_program(ctx);
2668 mir_ra(ctx);
2669
2670 /* Now that all the bundles are scheduled and we can calculate block
2671 * sizes, emit actual branch instructions rather than placeholders */
2672
2673 int br_block_idx = 0;
2674
2675 mir_foreach_block(ctx, _block) {
2676 midgard_block *block = (midgard_block *) _block;
2677 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2678 for (int c = 0; c < bundle->instruction_count; ++c) {
2679 midgard_instruction *ins = bundle->instructions[c];
2680
2681 if (!midgard_is_branch_unit(ins->unit)) continue;
2682
2683 /* Parse some basic branch info */
2684 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2685 bool is_conditional = ins->branch.conditional;
2686 bool is_inverted = ins->branch.invert_conditional;
2687 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2688 bool is_writeout = ins->writeout;
2689
2690 /* Determine the block we're jumping to */
2691 int target_number = ins->branch.target_block;
2692
2693 /* Report the destination tag */
2694 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2695
2696 /* Count up the number of quadwords we're
2697 * jumping over = number of quadwords until
2698 * (br_block_idx, target_number) */
2699
2700 int quadword_offset = 0;
2701
2702 if (is_discard) {
2703 /* Ignored */
2704 } else if (target_number > br_block_idx) {
2705 /* Jump forward */
2706
2707 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2708 midgard_block *blk = mir_get_block(ctx, idx);
2709 assert(blk);
2710
2711 quadword_offset += blk->quadword_count;
2712 }
2713 } else {
2714 /* Jump backwards */
2715
2716 for (int idx = br_block_idx; idx >= target_number; --idx) {
2717 midgard_block *blk = mir_get_block(ctx, idx);
2718 assert(blk);
2719
2720 quadword_offset -= blk->quadword_count;
2721 }
2722 }
2723
2724 /* Unconditional extended branches (far jumps)
2725 * have issues, so we always use a conditional
2726 * branch, setting the condition to always for
2727 * unconditional. For compact unconditional
2728 * branches, cond isn't used so it doesn't
2729 * matter what we pick. */
2730
2731 midgard_condition cond =
2732 !is_conditional ? midgard_condition_always :
2733 is_inverted ? midgard_condition_false :
2734 midgard_condition_true;
2735
2736 midgard_jmp_writeout_op op =
2737 is_discard ? midgard_jmp_writeout_op_discard :
2738 is_writeout ? midgard_jmp_writeout_op_writeout :
2739 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2740 midgard_jmp_writeout_op_branch_cond;
2741
2742 if (!is_compact) {
2743 midgard_branch_extended branch =
2744 midgard_create_branch_extended(
2745 cond, op,
2746 dest_tag,
2747 quadword_offset);
2748
2749 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2750 } else if (is_conditional || is_discard) {
2751 midgard_branch_cond branch = {
2752 .op = op,
2753 .dest_tag = dest_tag,
2754 .offset = quadword_offset,
2755 .cond = cond
2756 };
2757
2758 assert(branch.offset == quadword_offset);
2759
2760 memcpy(&ins->br_compact, &branch, sizeof(branch));
2761 } else {
2762 assert(op == midgard_jmp_writeout_op_branch_uncond);
2763
2764 midgard_branch_uncond branch = {
2765 .op = op,
2766 .dest_tag = dest_tag,
2767 .offset = quadword_offset,
2768 .unknown = 1
2769 };
2770
2771 assert(branch.offset == quadword_offset);
2772
2773 memcpy(&ins->br_compact, &branch, sizeof(branch));
2774 }
2775 }
2776 }
2777
2778 ++br_block_idx;
2779 }
2780
2781 /* Emit flat binary from the instruction arrays. Iterate each block in
2782 * sequence. Save instruction boundaries such that lookahead tags can
2783 * be assigned easily */
2784
2785 /* Cache _all_ bundles in source order for lookahead across failed branches */
2786
2787 int bundle_count = 0;
2788 mir_foreach_block(ctx, _block) {
2789 midgard_block *block = (midgard_block *) _block;
2790 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2791 }
2792 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2793 int bundle_idx = 0;
2794 mir_foreach_block(ctx, _block) {
2795 midgard_block *block = (midgard_block *) _block;
2796 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2797 source_order_bundles[bundle_idx++] = bundle;
2798 }
2799 }
2800
2801 int current_bundle = 0;
2802
2803 /* Midgard prefetches instruction types, so during emission we
2804 * need to lookahead. Unless this is the last instruction, in
2805 * which we return 1. */
2806
2807 mir_foreach_block(ctx, _block) {
2808 midgard_block *block = (midgard_block *) _block;
2809 mir_foreach_bundle_in_block(block, bundle) {
2810 int lookahead = 1;
2811
2812 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2813 lookahead = source_order_bundles[current_bundle + 1]->tag;
2814
2815 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2816 ++current_bundle;
2817 }
2818
2819 /* TODO: Free deeper */
2820 //util_dynarray_fini(&block->instructions);
2821 }
2822
2823 free(source_order_bundles);
2824
2825 /* Report the very first tag executed */
2826 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2827
2828 /* Deal with off-by-one related to the fencepost problem */
2829 program->work_register_count = ctx->work_registers + 1;
2830 program->uniform_cutoff = ctx->uniform_cutoff;
2831
2832 program->blend_patch_offset = ctx->blend_constant_offset;
2833 program->tls_size = ctx->tls_size;
2834
2835 if (midgard_debug & MIDGARD_DBG_SHADERS)
2836 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2837
2838 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2839 unsigned nr_bundles = 0, nr_ins = 0;
2840
2841 /* Count instructions and bundles */
2842
2843 mir_foreach_block(ctx, _block) {
2844 midgard_block *block = (midgard_block *) _block;
2845 nr_bundles += util_dynarray_num_elements(
2846 &block->bundles, midgard_bundle);
2847
2848 mir_foreach_bundle_in_block(block, bun)
2849 nr_ins += bun->instruction_count;
2850 }
2851
2852 /* Calculate thread count. There are certain cutoffs by
2853 * register count for thread count */
2854
2855 unsigned nr_registers = program->work_register_count;
2856
2857 unsigned nr_threads =
2858 (nr_registers <= 4) ? 4 :
2859 (nr_registers <= 8) ? 2 :
2860 1;
2861
2862 /* Dump stats */
2863
2864 fprintf(stderr, "shader%d - %s shader: "
2865 "%u inst, %u bundles, %u quadwords, "
2866 "%u registers, %u threads, %u loops, "
2867 "%u:%u spills:fills\n",
2868 SHADER_DB_COUNT++,
2869 gl_shader_stage_name(ctx->stage),
2870 nr_ins, nr_bundles, ctx->quadword_count,
2871 nr_registers, nr_threads,
2872 ctx->loop_count,
2873 ctx->spills, ctx->fills);
2874 }
2875
2876 ralloc_free(ctx);
2877
2878 return 0;
2879 }