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pan/mdg: Apply abs/neg modifiers
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 } else { \
121 i.dest = ssa; \
122 i.dest_type = T; \
123 } \
124 return i; \
125 }
126
127 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
128 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
129
130 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
131 * the corresponding Midgard source */
132
133 static midgard_vector_alu_src
134 vector_alu_modifiers(bool abs, bool neg, bool is_int,
135 bool half, bool sext)
136 {
137 /* Figure out how many components there are so we can adjust.
138 * Specifically we want to broadcast the last channel so things like
139 * ball2/3 work.
140 */
141
142 midgard_vector_alu_src alu_src = {
143 .rep_low = 0,
144 .rep_high = 0,
145 .half = half
146 };
147
148 if (is_int) {
149 alu_src.mod = midgard_int_normal;
150
151 /* Sign/zero-extend if needed */
152
153 if (half) {
154 alu_src.mod = sext ?
155 midgard_int_sign_extend
156 : midgard_int_zero_extend;
157 }
158
159 /* These should have been lowered away */
160 assert(!(abs || neg));
161 } else {
162 alu_src.mod = (abs << 0) | (neg << 1);
163 }
164
165 return alu_src;
166 }
167
168 M_LOAD(ld_attr_32, nir_type_uint32);
169 M_LOAD(ld_vary_32, nir_type_uint32);
170 M_LOAD(ld_ubo_int4, nir_type_uint32);
171 M_LOAD(ld_int4, nir_type_uint32);
172 M_STORE(st_int4, nir_type_uint32);
173 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
174 M_STORE(st_vary_32, nir_type_uint32);
175 M_LOAD(ld_cubemap_coords, nir_type_uint32);
176 M_LOAD(ld_compute_id, nir_type_uint32);
177
178 static midgard_instruction
179 v_branch(bool conditional, bool invert)
180 {
181 midgard_instruction ins = {
182 .type = TAG_ALU_4,
183 .unit = ALU_ENAB_BRANCH,
184 .compact_branch = true,
185 .branch = {
186 .conditional = conditional,
187 .invert_conditional = invert
188 },
189 .dest = ~0,
190 .src = { ~0, ~0, ~0, ~0 },
191 };
192
193 return ins;
194 }
195
196 static midgard_branch_extended
197 midgard_create_branch_extended( midgard_condition cond,
198 midgard_jmp_writeout_op op,
199 unsigned dest_tag,
200 signed quadword_offset)
201 {
202 /* The condition code is actually a LUT describing a function to
203 * combine multiple condition codes. However, we only support a single
204 * condition code at the moment, so we just duplicate over a bunch of
205 * times. */
206
207 uint16_t duplicated_cond =
208 (cond << 14) |
209 (cond << 12) |
210 (cond << 10) |
211 (cond << 8) |
212 (cond << 6) |
213 (cond << 4) |
214 (cond << 2) |
215 (cond << 0);
216
217 midgard_branch_extended branch = {
218 .op = op,
219 .dest_tag = dest_tag,
220 .offset = quadword_offset,
221 .cond = duplicated_cond
222 };
223
224 return branch;
225 }
226
227 static void
228 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
229 {
230 ins->has_constants = true;
231 memcpy(&ins->constants, constants, 16);
232 }
233
234 static int
235 glsl_type_size(const struct glsl_type *type, bool bindless)
236 {
237 return glsl_count_attribute_slots(type, false);
238 }
239
240 /* Lower fdot2 to a vector multiplication followed by channel addition */
241 static void
242 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
243 {
244 if (alu->op != nir_op_fdot2)
245 return;
246
247 b->cursor = nir_before_instr(&alu->instr);
248
249 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
250 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
251
252 nir_ssa_def *product = nir_fmul(b, src0, src1);
253
254 nir_ssa_def *sum = nir_fadd(b,
255 nir_channel(b, product, 0),
256 nir_channel(b, product, 1));
257
258 /* Replace the fdot2 with this sum */
259 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
260 }
261
262 static bool
263 midgard_nir_lower_fdot2(nir_shader *shader)
264 {
265 bool progress = false;
266
267 nir_foreach_function(function, shader) {
268 if (!function->impl) continue;
269
270 nir_builder _b;
271 nir_builder *b = &_b;
272 nir_builder_init(b, function->impl);
273
274 nir_foreach_block(block, function->impl) {
275 nir_foreach_instr_safe(instr, block) {
276 if (instr->type != nir_instr_type_alu) continue;
277
278 nir_alu_instr *alu = nir_instr_as_alu(instr);
279 midgard_nir_lower_fdot2_body(b, alu);
280
281 progress |= true;
282 }
283 }
284
285 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
286
287 }
288
289 return progress;
290 }
291
292 /* Midgard can't write depth and stencil separately. It has to happen in a
293 * single store operation containing both. Let's add a panfrost specific
294 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
295 * one.
296 */
297 static bool
298 midgard_nir_lower_zs_store(nir_shader *nir)
299 {
300 if (nir->info.stage != MESA_SHADER_FRAGMENT)
301 return false;
302
303 nir_variable *z_var = NULL, *s_var = NULL;
304
305 nir_foreach_variable(var, &nir->outputs) {
306 if (var->data.location == FRAG_RESULT_DEPTH)
307 z_var = var;
308 else if (var->data.location == FRAG_RESULT_STENCIL)
309 s_var = var;
310 }
311
312 if (!z_var && !s_var)
313 return false;
314
315 bool progress = false;
316
317 nir_foreach_function(function, nir) {
318 if (!function->impl) continue;
319
320 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
321
322 nir_foreach_block(block, function->impl) {
323 nir_foreach_instr_safe(instr, block) {
324 if (instr->type != nir_instr_type_intrinsic)
325 continue;
326
327 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
328 if (intr->intrinsic != nir_intrinsic_store_output)
329 continue;
330
331 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
332 assert(!z_store);
333 z_store = intr;
334 last_store = intr;
335 }
336
337 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
338 assert(!s_store);
339 s_store = intr;
340 last_store = intr;
341 }
342 }
343 }
344
345 if (!z_store && !s_store) continue;
346
347 nir_builder b;
348 nir_builder_init(&b, function->impl);
349
350 b.cursor = nir_before_instr(&last_store->instr);
351
352 nir_ssa_def *zs_store_src;
353
354 if (z_store && s_store) {
355 nir_ssa_def *srcs[2] = {
356 nir_ssa_for_src(&b, z_store->src[0], 1),
357 nir_ssa_for_src(&b, s_store->src[0], 1),
358 };
359
360 zs_store_src = nir_vec(&b, srcs, 2);
361 } else {
362 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
363 }
364
365 nir_intrinsic_instr *zs_store;
366
367 zs_store = nir_intrinsic_instr_create(b.shader,
368 nir_intrinsic_store_zs_output_pan);
369 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
370 zs_store->num_components = z_store && s_store ? 2 : 1;
371 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
372
373 /* Replace the Z and S store by a ZS store */
374 nir_builder_instr_insert(&b, &zs_store->instr);
375
376 if (z_store)
377 nir_instr_remove(&z_store->instr);
378
379 if (s_store)
380 nir_instr_remove(&s_store->instr);
381
382 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
383 progress = true;
384 }
385
386 return progress;
387 }
388
389 /* Flushes undefined values to zero */
390
391 static void
392 optimise_nir(nir_shader *nir, unsigned quirks)
393 {
394 bool progress;
395 unsigned lower_flrp =
396 (nir->options->lower_flrp16 ? 16 : 0) |
397 (nir->options->lower_flrp32 ? 32 : 0) |
398 (nir->options->lower_flrp64 ? 64 : 0);
399
400 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
401 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
402
403 nir_lower_tex_options lower_tex_options = {
404 .lower_txs_lod = true,
405 .lower_txp = ~0,
406 .lower_tex_without_implicit_lod =
407 (quirks & MIDGARD_EXPLICIT_LOD),
408
409 /* TODO: we have native gradient.. */
410 .lower_txd = true,
411 };
412
413 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
414
415 /* Must lower fdot2 after tex is lowered */
416 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
417
418 /* T720 is broken. */
419
420 if (quirks & MIDGARD_BROKEN_LOD)
421 NIR_PASS_V(nir, midgard_nir_lod_errata);
422
423 do {
424 progress = false;
425
426 NIR_PASS(progress, nir, nir_lower_var_copies);
427 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
428
429 NIR_PASS(progress, nir, nir_copy_prop);
430 NIR_PASS(progress, nir, nir_opt_remove_phis);
431 NIR_PASS(progress, nir, nir_opt_dce);
432 NIR_PASS(progress, nir, nir_opt_dead_cf);
433 NIR_PASS(progress, nir, nir_opt_cse);
434 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
435 NIR_PASS(progress, nir, nir_opt_algebraic);
436 NIR_PASS(progress, nir, nir_opt_constant_folding);
437
438 if (lower_flrp != 0) {
439 bool lower_flrp_progress = false;
440 NIR_PASS(lower_flrp_progress,
441 nir,
442 nir_lower_flrp,
443 lower_flrp,
444 false /* always_precise */,
445 nir->options->lower_ffma);
446 if (lower_flrp_progress) {
447 NIR_PASS(progress, nir,
448 nir_opt_constant_folding);
449 progress = true;
450 }
451
452 /* Nothing should rematerialize any flrps, so we only
453 * need to do this lowering once.
454 */
455 lower_flrp = 0;
456 }
457
458 NIR_PASS(progress, nir, nir_opt_undef);
459 NIR_PASS(progress, nir, nir_undef_to_zero);
460
461 NIR_PASS(progress, nir, nir_opt_loop_unroll,
462 nir_var_shader_in |
463 nir_var_shader_out |
464 nir_var_function_temp);
465
466 NIR_PASS(progress, nir, nir_opt_vectorize);
467 } while (progress);
468
469 /* Must be run at the end to prevent creation of fsin/fcos ops */
470 NIR_PASS(progress, nir, midgard_nir_scale_trig);
471
472 do {
473 progress = false;
474
475 NIR_PASS(progress, nir, nir_opt_dce);
476 NIR_PASS(progress, nir, nir_opt_algebraic);
477 NIR_PASS(progress, nir, nir_opt_constant_folding);
478 NIR_PASS(progress, nir, nir_copy_prop);
479 } while (progress);
480
481 NIR_PASS(progress, nir, nir_opt_algebraic_late);
482 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
483
484 /* We implement booleans as 32-bit 0/~0 */
485 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
486
487 /* Now that booleans are lowered, we can run out late opts */
488 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
489
490 NIR_PASS(progress, nir, nir_copy_prop);
491 NIR_PASS(progress, nir, nir_opt_dce);
492
493 /* Take us out of SSA */
494 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
495 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
496
497 /* We are a vector architecture; write combine where possible */
498 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
499 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
500
501 NIR_PASS(progress, nir, nir_opt_dce);
502 }
503
504 /* Do not actually emit a load; instead, cache the constant for inlining */
505
506 static void
507 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
508 {
509 nir_ssa_def def = instr->def;
510
511 midgard_constants *consts = rzalloc(NULL, midgard_constants);
512
513 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
514
515 #define RAW_CONST_COPY(bits) \
516 nir_const_value_to_array(consts->u##bits, instr->value, \
517 instr->def.num_components, u##bits)
518
519 switch (instr->def.bit_size) {
520 case 64:
521 RAW_CONST_COPY(64);
522 break;
523 case 32:
524 RAW_CONST_COPY(32);
525 break;
526 case 16:
527 RAW_CONST_COPY(16);
528 break;
529 case 8:
530 RAW_CONST_COPY(8);
531 break;
532 default:
533 unreachable("Invalid bit_size for load_const instruction\n");
534 }
535
536 /* Shifted for SSA, +1 for off-by-one */
537 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
538 }
539
540 /* Normally constants are embedded implicitly, but for I/O and such we have to
541 * explicitly emit a move with the constant source */
542
543 static void
544 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
545 {
546 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
547
548 if (constant_value) {
549 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
550 attach_constants(ctx, &ins, constant_value, node + 1);
551 emit_mir_instruction(ctx, ins);
552 }
553 }
554
555 static bool
556 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
557 {
558 unsigned comp = src->swizzle[0];
559
560 for (unsigned c = 1; c < nr_components; ++c) {
561 if (src->swizzle[c] != comp)
562 return true;
563 }
564
565 return false;
566 }
567
568 #define ALU_CASE(nir, _op) \
569 case nir_op_##nir: \
570 op = midgard_alu_op_##_op; \
571 assert(src_bitsize == dst_bitsize); \
572 break;
573
574 #define ALU_CASE_BCAST(nir, _op, count) \
575 case nir_op_##nir: \
576 op = midgard_alu_op_##_op; \
577 broadcast_swizzle = count; \
578 assert(src_bitsize == dst_bitsize); \
579 break;
580 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
581 * special treatment override this anyway. */
582
583 static midgard_reg_mode
584 reg_mode_for_nir(nir_alu_instr *instr)
585 {
586 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
587
588 switch (src_bitsize) {
589 case 8:
590 return midgard_reg_mode_8;
591 case 16:
592 return midgard_reg_mode_16;
593 case 32:
594 return midgard_reg_mode_32;
595 case 64:
596 return midgard_reg_mode_64;
597 default:
598 unreachable("Invalid bit size");
599 }
600 }
601
602 static void
603 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool is_int, unsigned bcast_count)
604 {
605 nir_alu_src src = instr->src[i];
606
607 if (!is_int) {
608 if (pan_has_source_mod(&src, nir_op_fneg))
609 *neg = !(*neg);
610
611 if (pan_has_source_mod(&src, nir_op_fabs))
612 *abs = true;
613 }
614
615 unsigned bits = nir_src_bit_size(src.src);
616
617 ins->src[to] = nir_src_index(NULL, &src.src);
618 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
619
620 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
621 ins->swizzle[to][c] = src.swizzle[
622 (!bcast_count || c < bcast_count) ? c :
623 (bcast_count - 1)];
624 }
625 }
626
627 static void
628 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
629 {
630 nir_dest *dest = &instr->dest.dest;
631
632 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
633 return;
634
635 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
636 * is handled elsewhere */
637
638 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
639 midgard_emit_derivatives(ctx, instr);
640 return;
641 }
642
643 bool is_ssa = dest->is_ssa;
644
645 unsigned nr_components = nir_dest_num_components(*dest);
646 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
647 unsigned op = 0;
648
649 /* Number of components valid to check for the instruction (the rest
650 * will be forced to the last), or 0 to use as-is. Relevant as
651 * ball-type instructions have a channel count in NIR but are all vec4
652 * in Midgard */
653
654 unsigned broadcast_swizzle = 0;
655
656 /* What register mode should we operate in? */
657 midgard_reg_mode reg_mode =
658 reg_mode_for_nir(instr);
659
660 /* Do we need a destination override? Used for inline
661 * type conversion */
662
663 midgard_dest_override dest_override =
664 midgard_dest_override_none;
665
666 /* Should we use a smaller respective source and sign-extend? */
667
668 bool half_1 = false, sext_1 = false;
669 bool half_2 = false, sext_2 = false;
670
671 /* Should we swap arguments? */
672 bool flip_src12 = false;
673
674 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
675 unsigned dst_bitsize = nir_dest_bit_size(*dest);
676
677 switch (instr->op) {
678 ALU_CASE(fadd, fadd);
679 ALU_CASE(fmul, fmul);
680 ALU_CASE(fmin, fmin);
681 ALU_CASE(fmax, fmax);
682 ALU_CASE(imin, imin);
683 ALU_CASE(imax, imax);
684 ALU_CASE(umin, umin);
685 ALU_CASE(umax, umax);
686 ALU_CASE(ffloor, ffloor);
687 ALU_CASE(fround_even, froundeven);
688 ALU_CASE(ftrunc, ftrunc);
689 ALU_CASE(fceil, fceil);
690 ALU_CASE(fdot3, fdot3);
691 ALU_CASE(fdot4, fdot4);
692 ALU_CASE(iadd, iadd);
693 ALU_CASE(isub, isub);
694 ALU_CASE(imul, imul);
695
696 /* Zero shoved as second-arg */
697 ALU_CASE(iabs, iabsdiff);
698
699 ALU_CASE(mov, imov);
700
701 ALU_CASE(feq32, feq);
702 ALU_CASE(fne32, fne);
703 ALU_CASE(flt32, flt);
704 ALU_CASE(ieq32, ieq);
705 ALU_CASE(ine32, ine);
706 ALU_CASE(ilt32, ilt);
707 ALU_CASE(ult32, ult);
708
709 /* We don't have a native b2f32 instruction. Instead, like many
710 * GPUs, we exploit booleans as 0/~0 for false/true, and
711 * correspondingly AND
712 * by 1.0 to do the type conversion. For the moment, prime us
713 * to emit:
714 *
715 * iand [whatever], #0
716 *
717 * At the end of emit_alu (as MIR), we'll fix-up the constant
718 */
719
720 ALU_CASE(b2f32, iand);
721 ALU_CASE(b2i32, iand);
722
723 /* Likewise, we don't have a dedicated f2b32 instruction, but
724 * we can do a "not equal to 0.0" test. */
725
726 ALU_CASE(f2b32, fne);
727 ALU_CASE(i2b32, ine);
728
729 ALU_CASE(frcp, frcp);
730 ALU_CASE(frsq, frsqrt);
731 ALU_CASE(fsqrt, fsqrt);
732 ALU_CASE(fexp2, fexp2);
733 ALU_CASE(flog2, flog2);
734
735 ALU_CASE(f2i64, f2i_rtz);
736 ALU_CASE(f2u64, f2u_rtz);
737 ALU_CASE(i2f64, i2f_rtz);
738 ALU_CASE(u2f64, u2f_rtz);
739
740 ALU_CASE(f2i32, f2i_rtz);
741 ALU_CASE(f2u32, f2u_rtz);
742 ALU_CASE(i2f32, i2f_rtz);
743 ALU_CASE(u2f32, u2f_rtz);
744
745 ALU_CASE(f2i16, f2i_rtz);
746 ALU_CASE(f2u16, f2u_rtz);
747 ALU_CASE(i2f16, i2f_rtz);
748 ALU_CASE(u2f16, u2f_rtz);
749
750 ALU_CASE(fsin, fsin);
751 ALU_CASE(fcos, fcos);
752
753 /* We'll set invert */
754 ALU_CASE(inot, imov);
755 ALU_CASE(iand, iand);
756 ALU_CASE(ior, ior);
757 ALU_CASE(ixor, ixor);
758 ALU_CASE(ishl, ishl);
759 ALU_CASE(ishr, iasr);
760 ALU_CASE(ushr, ilsr);
761
762 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
763 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
764 ALU_CASE(b32all_fequal4, fball_eq);
765
766 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
767 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
768 ALU_CASE(b32any_fnequal4, fbany_neq);
769
770 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
771 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
772 ALU_CASE(b32all_iequal4, iball_eq);
773
774 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
775 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
776 ALU_CASE(b32any_inequal4, ibany_neq);
777
778 /* Source mods will be shoved in later */
779 ALU_CASE(fabs, fmov);
780 ALU_CASE(fneg, fmov);
781 ALU_CASE(fsat, fmov);
782 ALU_CASE(fsat_signed, fmov);
783 ALU_CASE(fclamp_pos, fmov);
784
785 /* For size conversion, we use a move. Ideally though we would squash
786 * these ops together; maybe that has to happen after in NIR as part of
787 * propagation...? An earlier algebraic pass ensured we step down by
788 * only / exactly one size. If stepping down, we use a dest override to
789 * reduce the size; if stepping up, we use a larger-sized move with a
790 * half source and a sign/zero-extension modifier */
791
792 case nir_op_i2i8:
793 case nir_op_i2i16:
794 case nir_op_i2i32:
795 case nir_op_i2i64:
796 /* If we end up upscale, we'll need a sign-extend on the
797 * operand (the second argument) */
798
799 sext_2 = true;
800 /* fallthrough */
801 case nir_op_u2u8:
802 case nir_op_u2u16:
803 case nir_op_u2u32:
804 case nir_op_u2u64:
805 case nir_op_f2f16:
806 case nir_op_f2f32:
807 case nir_op_f2f64: {
808 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
809 instr->op == nir_op_f2f64)
810 op = midgard_alu_op_fmov;
811 else
812 op = midgard_alu_op_imov;
813
814 if (dst_bitsize == (src_bitsize * 2)) {
815 /* Converting up */
816 half_2 = true;
817
818 /* Use a greater register mode */
819 reg_mode++;
820 } else if (src_bitsize == (dst_bitsize * 2)) {
821 /* Converting down */
822 dest_override = midgard_dest_override_lower;
823 }
824
825 break;
826 }
827
828 /* For greater-or-equal, we lower to less-or-equal and flip the
829 * arguments */
830
831 case nir_op_fge:
832 case nir_op_fge32:
833 case nir_op_ige32:
834 case nir_op_uge32: {
835 op =
836 instr->op == nir_op_fge ? midgard_alu_op_fle :
837 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
838 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
839 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
840 0;
841
842 flip_src12 = true;
843 break;
844 }
845
846 case nir_op_b32csel: {
847 /* Midgard features both fcsel and icsel, depending on
848 * the type of the arguments/output. However, as long
849 * as we're careful we can _always_ use icsel and
850 * _never_ need fcsel, since the latter does additional
851 * floating-point-specific processing whereas the
852 * former just moves bits on the wire. It's not obvious
853 * why these are separate opcodes, save for the ability
854 * to do things like sat/pos/abs/neg for free */
855
856 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
857 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
858
859 break;
860 }
861
862 default:
863 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
864 assert(0);
865 return;
866 }
867
868 /* Midgard can perform certain modifiers on output of an ALU op */
869
870 unsigned outmod = 0;
871
872 bool abs[4] = { false };
873 bool neg[4] = { false };
874 bool is_int = midgard_is_integer_op(op);
875
876 if (midgard_is_integer_out_op(op)) {
877 outmod = midgard_outmod_int_wrap;
878 } else if (instr->op == nir_op_fsat) {
879 outmod = midgard_outmod_sat;
880 } else if (instr->op == nir_op_fsat_signed) {
881 outmod = midgard_outmod_sat_signed;
882 } else if (instr->op == nir_op_fclamp_pos) {
883 outmod = midgard_outmod_pos;
884 }
885
886 /* Fetch unit, quirks, etc information */
887 unsigned opcode_props = alu_opcode_props[op].props;
888 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
889
890 midgard_instruction ins = {
891 .type = TAG_ALU_4,
892 .dest = nir_dest_index(dest),
893 .dest_type = nir_op_infos[instr->op].output_type
894 | nir_dest_bit_size(*dest),
895 };
896
897 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
898 ins.src[i] = ~0;
899
900 if (quirk_flipped_r24) {
901 ins.src[0] = ~0;
902 mir_copy_src(&ins, instr, 0, 1, &abs[1], &neg[1], is_int, broadcast_swizzle);
903 } else {
904 for (unsigned i = 0; i < nr_inputs; ++i) {
905 unsigned to = i;
906
907 if (instr->op == nir_op_b32csel) {
908 /* The condition is the first argument; move
909 * the other arguments up one to be a binary
910 * instruction for Midgard with the condition
911 * last */
912
913 if (i == 0)
914 to = 2;
915 else
916 to = i - 1;
917 } else if (flip_src12) {
918 to = 1 - to;
919 }
920
921 mir_copy_src(&ins, instr, i, to, &abs[to], &neg[to], is_int, broadcast_swizzle);
922 }
923 }
924
925 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
926 /* Lowered to move */
927 if (instr->op == nir_op_fneg)
928 neg[1] = !neg[1];
929
930 if (instr->op == nir_op_fabs)
931 abs[1] = true;
932 }
933
934 ins.mask = mask_of(nr_components);
935
936 midgard_vector_alu alu = {
937 .op = op,
938 .reg_mode = reg_mode,
939 .dest_override = dest_override,
940 .outmod = outmod,
941
942 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[0], neg[0], is_int, half_1, sext_1)),
943 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[1], neg[1], is_int, half_2, sext_2)),
944 };
945
946 /* Apply writemask if non-SSA, keeping in mind that we can't write to
947 * components that don't exist. Note modifier => SSA => !reg => no
948 * writemask, so we don't have to worry about writemasks here.*/
949
950 if (!is_ssa)
951 ins.mask &= instr->dest.write_mask;
952
953 ins.alu = alu;
954
955 /* Late fixup for emulated instructions */
956
957 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
958 /* Presently, our second argument is an inline #0 constant.
959 * Switch over to an embedded 1.0 constant (that can't fit
960 * inline, since we're 32-bit, not 16-bit like the inline
961 * constants) */
962
963 ins.has_inline_constant = false;
964 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
965 ins.src_types[1] = nir_type_float32;
966 ins.has_constants = true;
967
968 if (instr->op == nir_op_b2f32)
969 ins.constants.f32[0] = 1.0f;
970 else
971 ins.constants.i32[0] = 1;
972
973 for (unsigned c = 0; c < 16; ++c)
974 ins.swizzle[1][c] = 0;
975 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
976 /* Lots of instructions need a 0 plonked in */
977 ins.has_inline_constant = false;
978 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
979 ins.src_types[1] = nir_type_uint32;
980 ins.has_constants = true;
981 ins.constants.u32[0] = 0;
982
983 for (unsigned c = 0; c < 16; ++c)
984 ins.swizzle[1][c] = 0;
985 } else if (instr->op == nir_op_inot) {
986 ins.invert = true;
987 }
988
989 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
990 /* To avoid duplicating the lookup tables (probably), true LUT
991 * instructions can only operate as if they were scalars. Lower
992 * them here by changing the component. */
993
994 unsigned orig_mask = ins.mask;
995
996 unsigned swizzle_back[MIR_VEC_COMPONENTS];
997 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
998
999 for (int i = 0; i < nr_components; ++i) {
1000 /* Mask the associated component, dropping the
1001 * instruction if needed */
1002
1003 ins.mask = 1 << i;
1004 ins.mask &= orig_mask;
1005
1006 if (!ins.mask)
1007 continue;
1008
1009 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1010 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1011
1012 emit_mir_instruction(ctx, ins);
1013 }
1014 } else {
1015 emit_mir_instruction(ctx, ins);
1016 }
1017 }
1018
1019 #undef ALU_CASE
1020
1021 static void
1022 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1023 {
1024 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1025 unsigned nir_mask = 0;
1026 unsigned dsize = 0;
1027
1028 if (is_read) {
1029 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1030 dsize = nir_dest_bit_size(intr->dest);
1031 } else {
1032 nir_mask = nir_intrinsic_write_mask(intr);
1033 dsize = 32;
1034 }
1035
1036 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1037 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1038 mir_set_bytemask(ins, bytemask);
1039
1040 if (dsize == 64)
1041 ins->load_64 = true;
1042 }
1043
1044 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1045 * optimized) versions of UBO #0 */
1046
1047 static midgard_instruction *
1048 emit_ubo_read(
1049 compiler_context *ctx,
1050 nir_instr *instr,
1051 unsigned dest,
1052 unsigned offset,
1053 nir_src *indirect_offset,
1054 unsigned indirect_shift,
1055 unsigned index)
1056 {
1057 /* TODO: half-floats */
1058
1059 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1060 ins.constants.u32[0] = offset;
1061
1062 if (instr->type == nir_instr_type_intrinsic)
1063 mir_set_intr_mask(instr, &ins, true);
1064
1065 if (indirect_offset) {
1066 ins.src[2] = nir_src_index(ctx, indirect_offset);
1067 ins.src_types[2] = nir_type_uint32;
1068 ins.load_store.arg_2 = (indirect_shift << 5);
1069 } else {
1070 ins.load_store.arg_2 = 0x1E;
1071 }
1072
1073 ins.load_store.arg_1 = index;
1074
1075 return emit_mir_instruction(ctx, ins);
1076 }
1077
1078 /* Globals are like UBOs if you squint. And shared memory is like globals if
1079 * you squint even harder */
1080
1081 static void
1082 emit_global(
1083 compiler_context *ctx,
1084 nir_instr *instr,
1085 bool is_read,
1086 unsigned srcdest,
1087 nir_src *offset,
1088 bool is_shared)
1089 {
1090 /* TODO: types */
1091
1092 midgard_instruction ins;
1093
1094 if (is_read)
1095 ins = m_ld_int4(srcdest, 0);
1096 else
1097 ins = m_st_int4(srcdest, 0);
1098
1099 mir_set_offset(ctx, &ins, offset, is_shared);
1100 mir_set_intr_mask(instr, &ins, is_read);
1101
1102 emit_mir_instruction(ctx, ins);
1103 }
1104
1105 static void
1106 emit_varying_read(
1107 compiler_context *ctx,
1108 unsigned dest, unsigned offset,
1109 unsigned nr_comp, unsigned component,
1110 nir_src *indirect_offset, nir_alu_type type, bool flat)
1111 {
1112 /* XXX: Half-floats? */
1113 /* TODO: swizzle, mask */
1114
1115 midgard_instruction ins = m_ld_vary_32(dest, offset);
1116 ins.mask = mask_of(nr_comp);
1117
1118 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1119 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1120
1121 midgard_varying_parameter p = {
1122 .is_varying = 1,
1123 .interpolation = midgard_interp_default,
1124 .flat = flat,
1125 };
1126
1127 unsigned u;
1128 memcpy(&u, &p, sizeof(p));
1129 ins.load_store.varying_parameters = u;
1130
1131 if (indirect_offset) {
1132 ins.src[2] = nir_src_index(ctx, indirect_offset);
1133 ins.src_types[2] = nir_type_uint32;
1134 } else
1135 ins.load_store.arg_2 = 0x1E;
1136
1137 ins.load_store.arg_1 = 0x9E;
1138
1139 /* Use the type appropriate load */
1140 switch (type) {
1141 case nir_type_uint:
1142 case nir_type_bool:
1143 ins.load_store.op = midgard_op_ld_vary_32u;
1144 break;
1145 case nir_type_int:
1146 ins.load_store.op = midgard_op_ld_vary_32i;
1147 break;
1148 case nir_type_float:
1149 ins.load_store.op = midgard_op_ld_vary_32;
1150 break;
1151 default:
1152 unreachable("Attempted to load unknown type");
1153 break;
1154 }
1155
1156 emit_mir_instruction(ctx, ins);
1157 }
1158
1159 static void
1160 emit_attr_read(
1161 compiler_context *ctx,
1162 unsigned dest, unsigned offset,
1163 unsigned nr_comp, nir_alu_type t)
1164 {
1165 midgard_instruction ins = m_ld_attr_32(dest, offset);
1166 ins.load_store.arg_1 = 0x1E;
1167 ins.load_store.arg_2 = 0x1E;
1168 ins.mask = mask_of(nr_comp);
1169
1170 /* Use the type appropriate load */
1171 switch (t) {
1172 case nir_type_uint:
1173 case nir_type_bool:
1174 ins.load_store.op = midgard_op_ld_attr_32u;
1175 break;
1176 case nir_type_int:
1177 ins.load_store.op = midgard_op_ld_attr_32i;
1178 break;
1179 case nir_type_float:
1180 ins.load_store.op = midgard_op_ld_attr_32;
1181 break;
1182 default:
1183 unreachable("Attempted to load unknown type");
1184 break;
1185 }
1186
1187 emit_mir_instruction(ctx, ins);
1188 }
1189
1190 static void
1191 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1192 unsigned nr_components, unsigned offset)
1193 {
1194 nir_dest nir_dest;
1195
1196 /* Figure out which uniform this is */
1197 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1198 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1199
1200 unsigned dest = nir_dest_index(&nir_dest);
1201
1202 /* Sysvals are prefix uniforms */
1203 unsigned uniform = ((uintptr_t) val) - 1;
1204
1205 /* Emit the read itself -- this is never indirect */
1206 midgard_instruction *ins =
1207 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1208
1209 ins->mask = mask_of(nr_components);
1210 }
1211
1212 static unsigned
1213 compute_builtin_arg(nir_op op)
1214 {
1215 switch (op) {
1216 case nir_intrinsic_load_work_group_id:
1217 return 0x14;
1218 case nir_intrinsic_load_local_invocation_id:
1219 return 0x10;
1220 default:
1221 unreachable("Invalid compute paramater loaded");
1222 }
1223 }
1224
1225 static void
1226 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1227 {
1228 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1229
1230 midgard_instruction *br = ctx->writeout_branch[rt];
1231
1232 assert(!br);
1233
1234 emit_explicit_constant(ctx, src, src);
1235
1236 struct midgard_instruction ins =
1237 v_branch(false, false);
1238
1239 ins.writeout = true;
1240
1241 /* Add dependencies */
1242 ins.src[0] = src;
1243 ins.src_types[0] = nir_type_uint32;
1244 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1245 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1246
1247 /* Emit the branch */
1248 br = emit_mir_instruction(ctx, ins);
1249 schedule_barrier(ctx);
1250 ctx->writeout_branch[rt] = br;
1251
1252 /* Push our current location = current block count - 1 = where we'll
1253 * jump to. Maybe a bit too clever for my own good */
1254
1255 br->branch.target_block = ctx->block_count - 1;
1256 }
1257
1258 static void
1259 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1260 {
1261 unsigned reg = nir_dest_index(&instr->dest);
1262 midgard_instruction ins = m_ld_compute_id(reg, 0);
1263 ins.mask = mask_of(3);
1264 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1265 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1266 emit_mir_instruction(ctx, ins);
1267 }
1268
1269 static unsigned
1270 vertex_builtin_arg(nir_op op)
1271 {
1272 switch (op) {
1273 case nir_intrinsic_load_vertex_id:
1274 return PAN_VERTEX_ID;
1275 case nir_intrinsic_load_instance_id:
1276 return PAN_INSTANCE_ID;
1277 default:
1278 unreachable("Invalid vertex builtin");
1279 }
1280 }
1281
1282 static void
1283 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1284 {
1285 unsigned reg = nir_dest_index(&instr->dest);
1286 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1287 }
1288
1289 static void
1290 emit_control_barrier(compiler_context *ctx)
1291 {
1292 midgard_instruction ins = {
1293 .type = TAG_TEXTURE_4,
1294 .src = { ~0, ~0, ~0, ~0 },
1295 .texture = {
1296 .op = TEXTURE_OP_BARRIER,
1297
1298 /* TODO: optimize */
1299 .barrier_buffer = 1,
1300 .barrier_shared = 1
1301 }
1302 };
1303
1304 emit_mir_instruction(ctx, ins);
1305 }
1306
1307 static const nir_variable *
1308 search_var(struct exec_list *vars, unsigned driver_loc)
1309 {
1310 nir_foreach_variable(var, vars) {
1311 if (var->data.driver_location == driver_loc)
1312 return var;
1313 }
1314
1315 return NULL;
1316 }
1317
1318 static void
1319 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1320 {
1321 unsigned offset = 0, reg;
1322
1323 switch (instr->intrinsic) {
1324 case nir_intrinsic_discard_if:
1325 case nir_intrinsic_discard: {
1326 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1327 struct midgard_instruction discard = v_branch(conditional, false);
1328 discard.branch.target_type = TARGET_DISCARD;
1329
1330 if (conditional) {
1331 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1332 discard.src_types[0] = nir_type_uint32;
1333 }
1334
1335 emit_mir_instruction(ctx, discard);
1336 schedule_barrier(ctx);
1337
1338 break;
1339 }
1340
1341 case nir_intrinsic_load_uniform:
1342 case nir_intrinsic_load_ubo:
1343 case nir_intrinsic_load_global:
1344 case nir_intrinsic_load_shared:
1345 case nir_intrinsic_load_input:
1346 case nir_intrinsic_load_interpolated_input: {
1347 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1348 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1349 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1350 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1351 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1352 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1353
1354 /* Get the base type of the intrinsic */
1355 /* TODO: Infer type? Does it matter? */
1356 nir_alu_type t =
1357 (is_ubo || is_global || is_shared) ? nir_type_uint :
1358 (is_interp) ? nir_type_float :
1359 nir_intrinsic_type(instr);
1360
1361 t = nir_alu_type_get_base_type(t);
1362
1363 if (!(is_ubo || is_global)) {
1364 offset = nir_intrinsic_base(instr);
1365 }
1366
1367 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1368
1369 nir_src *src_offset = nir_get_io_offset_src(instr);
1370
1371 bool direct = nir_src_is_const(*src_offset);
1372 nir_src *indirect_offset = direct ? NULL : src_offset;
1373
1374 if (direct)
1375 offset += nir_src_as_uint(*src_offset);
1376
1377 /* We may need to apply a fractional offset */
1378 int component = (is_flat || is_interp) ?
1379 nir_intrinsic_component(instr) : 0;
1380 reg = nir_dest_index(&instr->dest);
1381
1382 if (is_uniform && !ctx->is_blend) {
1383 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1384 } else if (is_ubo) {
1385 nir_src index = instr->src[0];
1386
1387 /* TODO: Is indirect block number possible? */
1388 assert(nir_src_is_const(index));
1389
1390 uint32_t uindex = nir_src_as_uint(index) + 1;
1391 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1392 } else if (is_global || is_shared) {
1393 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1394 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1395 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1396 } else if (ctx->is_blend) {
1397 /* For blend shaders, load the input color, which is
1398 * preloaded to r0 */
1399
1400 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1401 emit_mir_instruction(ctx, move);
1402 schedule_barrier(ctx);
1403 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1404 emit_attr_read(ctx, reg, offset, nr_comp, t);
1405 } else {
1406 DBG("Unknown load\n");
1407 assert(0);
1408 }
1409
1410 break;
1411 }
1412
1413 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1414 case nir_intrinsic_load_barycentric_pixel:
1415 case nir_intrinsic_load_barycentric_centroid:
1416 break;
1417
1418 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1419
1420 case nir_intrinsic_load_raw_output_pan:
1421 case nir_intrinsic_load_output_u8_as_fp16_pan:
1422 reg = nir_dest_index(&instr->dest);
1423 assert(ctx->is_blend);
1424
1425 /* T720 and below use different blend opcodes with slightly
1426 * different semantics than T760 and up */
1427
1428 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1429 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1430
1431 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1432 ld.load_store.op = old_blend ?
1433 midgard_op_ld_color_buffer_u8_as_fp16_old :
1434 midgard_op_ld_color_buffer_u8_as_fp16;
1435
1436 if (old_blend) {
1437 ld.load_store.address = 1;
1438 ld.load_store.arg_2 = 0x1E;
1439 }
1440
1441 for (unsigned c = 2; c < 16; ++c)
1442 ld.swizzle[0][c] = 0;
1443 }
1444
1445 emit_mir_instruction(ctx, ld);
1446 break;
1447
1448 case nir_intrinsic_load_blend_const_color_rgba: {
1449 assert(ctx->is_blend);
1450 reg = nir_dest_index(&instr->dest);
1451
1452 /* Blend constants are embedded directly in the shader and
1453 * patched in, so we use some magic routing */
1454
1455 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1456 ins.has_constants = true;
1457 ins.has_blend_constant = true;
1458 emit_mir_instruction(ctx, ins);
1459 break;
1460 }
1461
1462 case nir_intrinsic_store_zs_output_pan: {
1463 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1464 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1465 MIDGARD_ZS_RT);
1466
1467 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1468
1469 if (!nir_intrinsic_component(instr))
1470 br->writeout_depth = true;
1471 if (nir_intrinsic_component(instr) ||
1472 instr->num_components)
1473 br->writeout_stencil = true;
1474 assert(br->writeout_depth | br->writeout_stencil);
1475 break;
1476 }
1477
1478 case nir_intrinsic_store_output:
1479 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1480
1481 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1482
1483 reg = nir_src_index(ctx, &instr->src[0]);
1484
1485 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1486 const nir_variable *var;
1487 enum midgard_rt_id rt;
1488
1489 var = search_var(&ctx->nir->outputs,
1490 nir_intrinsic_base(instr));
1491 assert(var);
1492 if (var->data.location == FRAG_RESULT_COLOR)
1493 rt = MIDGARD_COLOR_RT0;
1494 else if (var->data.location >= FRAG_RESULT_DATA0)
1495 rt = MIDGARD_COLOR_RT0 + var->data.location -
1496 FRAG_RESULT_DATA0;
1497 else
1498 assert(0);
1499
1500 emit_fragment_store(ctx, reg, rt);
1501 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1502 /* We should have been vectorized, though we don't
1503 * currently check that st_vary is emitted only once
1504 * per slot (this is relevant, since there's not a mask
1505 * parameter available on the store [set to 0 by the
1506 * blob]). We do respect the component by adjusting the
1507 * swizzle. If this is a constant source, we'll need to
1508 * emit that explicitly. */
1509
1510 emit_explicit_constant(ctx, reg, reg);
1511
1512 unsigned dst_component = nir_intrinsic_component(instr);
1513 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1514
1515 midgard_instruction st = m_st_vary_32(reg, offset);
1516 st.load_store.arg_1 = 0x9E;
1517 st.load_store.arg_2 = 0x1E;
1518
1519 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1520 case nir_type_uint:
1521 case nir_type_bool:
1522 st.load_store.op = midgard_op_st_vary_32u;
1523 break;
1524 case nir_type_int:
1525 st.load_store.op = midgard_op_st_vary_32i;
1526 break;
1527 case nir_type_float:
1528 st.load_store.op = midgard_op_st_vary_32;
1529 break;
1530 default:
1531 unreachable("Attempted to store unknown type");
1532 break;
1533 }
1534
1535 /* nir_intrinsic_component(store_intr) encodes the
1536 * destination component start. Source component offset
1537 * adjustment is taken care of in
1538 * install_registers_instr(), when offset_swizzle() is
1539 * called.
1540 */
1541 unsigned src_component = COMPONENT_X;
1542
1543 assert(nr_comp > 0);
1544 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1545 st.swizzle[0][i] = src_component;
1546 if (i >= dst_component && i < dst_component + nr_comp - 1)
1547 src_component++;
1548 }
1549
1550 emit_mir_instruction(ctx, st);
1551 } else {
1552 DBG("Unknown store\n");
1553 assert(0);
1554 }
1555
1556 break;
1557
1558 /* Special case of store_output for lowered blend shaders */
1559 case nir_intrinsic_store_raw_output_pan:
1560 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1561 reg = nir_src_index(ctx, &instr->src[0]);
1562
1563 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1564 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1565 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1566 * of:
1567 *
1568 * imov r0.xyzw, r0.xxxx
1569 */
1570
1571 unsigned expanded = make_compiler_temp(ctx);
1572
1573 midgard_instruction splatter = v_mov(reg, expanded);
1574
1575 for (unsigned c = 0; c < 16; ++c)
1576 splatter.swizzle[1][c] = 0;
1577
1578 emit_mir_instruction(ctx, splatter);
1579 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1580 } else
1581 emit_fragment_store(ctx, reg, ctx->blend_rt);
1582
1583 break;
1584
1585 case nir_intrinsic_store_global:
1586 case nir_intrinsic_store_shared:
1587 reg = nir_src_index(ctx, &instr->src[0]);
1588 emit_explicit_constant(ctx, reg, reg);
1589
1590 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1591 break;
1592
1593 case nir_intrinsic_load_ssbo_address:
1594 emit_sysval_read(ctx, &instr->instr, 1, 0);
1595 break;
1596
1597 case nir_intrinsic_get_buffer_size:
1598 emit_sysval_read(ctx, &instr->instr, 1, 8);
1599 break;
1600
1601 case nir_intrinsic_load_viewport_scale:
1602 case nir_intrinsic_load_viewport_offset:
1603 case nir_intrinsic_load_num_work_groups:
1604 case nir_intrinsic_load_sampler_lod_parameters_pan:
1605 emit_sysval_read(ctx, &instr->instr, 3, 0);
1606 break;
1607
1608 case nir_intrinsic_load_work_group_id:
1609 case nir_intrinsic_load_local_invocation_id:
1610 emit_compute_builtin(ctx, instr);
1611 break;
1612
1613 case nir_intrinsic_load_vertex_id:
1614 case nir_intrinsic_load_instance_id:
1615 emit_vertex_builtin(ctx, instr);
1616 break;
1617
1618 case nir_intrinsic_memory_barrier_buffer:
1619 case nir_intrinsic_memory_barrier_shared:
1620 break;
1621
1622 case nir_intrinsic_control_barrier:
1623 schedule_barrier(ctx);
1624 emit_control_barrier(ctx);
1625 schedule_barrier(ctx);
1626 break;
1627
1628 default:
1629 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1630 assert(0);
1631 break;
1632 }
1633 }
1634
1635 static unsigned
1636 midgard_tex_format(enum glsl_sampler_dim dim)
1637 {
1638 switch (dim) {
1639 case GLSL_SAMPLER_DIM_1D:
1640 case GLSL_SAMPLER_DIM_BUF:
1641 return MALI_TEX_1D;
1642
1643 case GLSL_SAMPLER_DIM_2D:
1644 case GLSL_SAMPLER_DIM_EXTERNAL:
1645 case GLSL_SAMPLER_DIM_RECT:
1646 return MALI_TEX_2D;
1647
1648 case GLSL_SAMPLER_DIM_3D:
1649 return MALI_TEX_3D;
1650
1651 case GLSL_SAMPLER_DIM_CUBE:
1652 return MALI_TEX_CUBE;
1653
1654 default:
1655 DBG("Unknown sampler dim type\n");
1656 assert(0);
1657 return 0;
1658 }
1659 }
1660
1661 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1662 * was successful */
1663
1664 static bool
1665 pan_attach_constant_bias(
1666 compiler_context *ctx,
1667 nir_src lod,
1668 midgard_texture_word *word)
1669 {
1670 /* To attach as constant, it has to *be* constant */
1671
1672 if (!nir_src_is_const(lod))
1673 return false;
1674
1675 float f = nir_src_as_float(lod);
1676
1677 /* Break into fixed-point */
1678 signed lod_int = f;
1679 float lod_frac = f - lod_int;
1680
1681 /* Carry over negative fractions */
1682 if (lod_frac < 0.0) {
1683 lod_int--;
1684 lod_frac += 1.0;
1685 }
1686
1687 /* Encode */
1688 word->bias = float_to_ubyte(lod_frac);
1689 word->bias_int = lod_int;
1690
1691 return true;
1692 }
1693
1694 static void
1695 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1696 unsigned midgard_texop)
1697 {
1698 /* TODO */
1699 //assert (!instr->sampler);
1700
1701 int texture_index = instr->texture_index;
1702 int sampler_index = texture_index;
1703
1704 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1705 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1706
1707 midgard_instruction ins = {
1708 .type = TAG_TEXTURE_4,
1709 .mask = 0xF,
1710 .dest = nir_dest_index(&instr->dest),
1711 .src = { ~0, ~0, ~0, ~0 },
1712 .dest_type = dest_type,
1713 .swizzle = SWIZZLE_IDENTITY_4,
1714 .texture = {
1715 .op = midgard_texop,
1716 .format = midgard_tex_format(instr->sampler_dim),
1717 .texture_handle = texture_index,
1718 .sampler_handle = sampler_index,
1719 .shadow = instr->is_shadow,
1720 }
1721 };
1722
1723 if (instr->is_shadow && !instr->is_new_style_shadow)
1724 for (int i = 0; i < 4; ++i)
1725 ins.swizzle[0][i] = COMPONENT_X;
1726
1727 /* We may need a temporary for the coordinate */
1728
1729 bool needs_temp_coord =
1730 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1731 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1732 (instr->is_shadow);
1733
1734 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1735
1736 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1737 int index = nir_src_index(ctx, &instr->src[i].src);
1738 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1739 unsigned sz = nir_src_bit_size(instr->src[i].src);
1740 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1741
1742 switch (instr->src[i].src_type) {
1743 case nir_tex_src_coord: {
1744 emit_explicit_constant(ctx, index, index);
1745
1746 unsigned coord_mask = mask_of(instr->coord_components);
1747
1748 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1749
1750 if (flip_zw)
1751 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1752
1753 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1754 /* texelFetch is undefined on samplerCube */
1755 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1756
1757 /* For cubemaps, we use a special ld/st op to
1758 * select the face and copy the xy into the
1759 * texture register */
1760
1761 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1762 ld.src[1] = index;
1763 ld.src_types[1] = T;
1764 ld.mask = 0x3; /* xy */
1765 ld.load_store.arg_1 = 0x20;
1766 ld.swizzle[1][3] = COMPONENT_X;
1767 emit_mir_instruction(ctx, ld);
1768
1769 /* xyzw -> xyxx */
1770 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1771 ins.swizzle[1][3] = COMPONENT_X;
1772 } else if (needs_temp_coord) {
1773 /* mov coord_temp, coords */
1774 midgard_instruction mov = v_mov(index, coords);
1775 mov.mask = coord_mask;
1776
1777 if (flip_zw)
1778 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1779
1780 emit_mir_instruction(ctx, mov);
1781 } else {
1782 coords = index;
1783 }
1784
1785 ins.src[1] = coords;
1786 ins.src_types[1] = T;
1787
1788 /* Texelfetch coordinates uses all four elements
1789 * (xyz/index) regardless of texture dimensionality,
1790 * which means it's necessary to zero the unused
1791 * components to keep everything happy */
1792
1793 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1794 /* mov index.zw, #0, or generalized */
1795 midgard_instruction mov =
1796 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1797 mov.has_constants = true;
1798 mov.mask = coord_mask ^ 0xF;
1799 emit_mir_instruction(ctx, mov);
1800 }
1801
1802 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1803 /* Array component in w but NIR wants it in z,
1804 * but if we have a temp coord we already fixed
1805 * that up */
1806
1807 if (nr_components == 3) {
1808 ins.swizzle[1][2] = COMPONENT_Z;
1809 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1810 } else if (nr_components == 2) {
1811 ins.swizzle[1][2] =
1812 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1813 ins.swizzle[1][3] = COMPONENT_X;
1814 } else
1815 unreachable("Invalid texture 2D components");
1816 }
1817
1818 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1819 /* We zeroed */
1820 ins.swizzle[1][2] = COMPONENT_Z;
1821 ins.swizzle[1][3] = COMPONENT_W;
1822 }
1823
1824 break;
1825 }
1826
1827 case nir_tex_src_bias:
1828 case nir_tex_src_lod: {
1829 /* Try as a constant if we can */
1830
1831 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1832 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1833 break;
1834
1835 ins.texture.lod_register = true;
1836 ins.src[2] = index;
1837 ins.src_types[2] = T;
1838
1839 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1840 ins.swizzle[2][c] = COMPONENT_X;
1841
1842 emit_explicit_constant(ctx, index, index);
1843
1844 break;
1845 };
1846
1847 case nir_tex_src_offset: {
1848 ins.texture.offset_register = true;
1849 ins.src[3] = index;
1850 ins.src_types[3] = T;
1851
1852 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1853 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1854
1855 emit_explicit_constant(ctx, index, index);
1856 break;
1857 };
1858
1859 case nir_tex_src_comparator: {
1860 unsigned comp = COMPONENT_Z;
1861
1862 /* mov coord_temp.foo, coords */
1863 midgard_instruction mov = v_mov(index, coords);
1864 mov.mask = 1 << comp;
1865
1866 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1867 mov.swizzle[1][i] = COMPONENT_X;
1868
1869 emit_mir_instruction(ctx, mov);
1870 break;
1871 }
1872
1873 default: {
1874 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1875 assert(0);
1876 }
1877 }
1878 }
1879
1880 emit_mir_instruction(ctx, ins);
1881 }
1882
1883 static void
1884 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1885 {
1886 switch (instr->op) {
1887 case nir_texop_tex:
1888 case nir_texop_txb:
1889 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1890 break;
1891 case nir_texop_txl:
1892 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1893 break;
1894 case nir_texop_txf:
1895 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1896 break;
1897 case nir_texop_txs:
1898 emit_sysval_read(ctx, &instr->instr, 4, 0);
1899 break;
1900 default: {
1901 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1902 assert(0);
1903 }
1904 }
1905 }
1906
1907 static void
1908 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1909 {
1910 switch (instr->type) {
1911 case nir_jump_break: {
1912 /* Emit a branch out of the loop */
1913 struct midgard_instruction br = v_branch(false, false);
1914 br.branch.target_type = TARGET_BREAK;
1915 br.branch.target_break = ctx->current_loop_depth;
1916 emit_mir_instruction(ctx, br);
1917 break;
1918 }
1919
1920 default:
1921 DBG("Unknown jump type %d\n", instr->type);
1922 break;
1923 }
1924 }
1925
1926 static void
1927 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1928 {
1929 switch (instr->type) {
1930 case nir_instr_type_load_const:
1931 emit_load_const(ctx, nir_instr_as_load_const(instr));
1932 break;
1933
1934 case nir_instr_type_intrinsic:
1935 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1936 break;
1937
1938 case nir_instr_type_alu:
1939 emit_alu(ctx, nir_instr_as_alu(instr));
1940 break;
1941
1942 case nir_instr_type_tex:
1943 emit_tex(ctx, nir_instr_as_tex(instr));
1944 break;
1945
1946 case nir_instr_type_jump:
1947 emit_jump(ctx, nir_instr_as_jump(instr));
1948 break;
1949
1950 case nir_instr_type_ssa_undef:
1951 /* Spurious */
1952 break;
1953
1954 default:
1955 DBG("Unhandled instruction type\n");
1956 break;
1957 }
1958 }
1959
1960
1961 /* ALU instructions can inline or embed constants, which decreases register
1962 * pressure and saves space. */
1963
1964 #define CONDITIONAL_ATTACH(idx) { \
1965 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
1966 \
1967 if (entry) { \
1968 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
1969 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1970 } \
1971 }
1972
1973 static void
1974 inline_alu_constants(compiler_context *ctx, midgard_block *block)
1975 {
1976 mir_foreach_instr_in_block(block, alu) {
1977 /* Other instructions cannot inline constants */
1978 if (alu->type != TAG_ALU_4) continue;
1979 if (alu->compact_branch) continue;
1980
1981 /* If there is already a constant here, we can do nothing */
1982 if (alu->has_constants) continue;
1983
1984 CONDITIONAL_ATTACH(0);
1985
1986 if (!alu->has_constants) {
1987 CONDITIONAL_ATTACH(1)
1988 } else if (!alu->inline_constant) {
1989 /* Corner case: _two_ vec4 constants, for instance with a
1990 * csel. For this case, we can only use a constant
1991 * register for one, we'll have to emit a move for the
1992 * other. */
1993
1994 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
1995 unsigned scratch = make_compiler_temp(ctx);
1996
1997 if (entry) {
1998 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
1999 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2000
2001 /* Set the source */
2002 alu->src[1] = scratch;
2003
2004 /* Inject us -before- the last instruction which set r31 */
2005 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2006 }
2007 }
2008 }
2009 }
2010
2011 /* Midgard supports two types of constants, embedded constants (128-bit) and
2012 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2013 * constants can be demoted to inline constants, for space savings and
2014 * sometimes a performance boost */
2015
2016 static void
2017 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2018 {
2019 mir_foreach_instr_in_block(block, ins) {
2020 if (!ins->has_constants) continue;
2021 if (ins->has_inline_constant) continue;
2022
2023 /* Blend constants must not be inlined by definition */
2024 if (ins->has_blend_constant) continue;
2025
2026 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2027 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2028 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2029
2030 if (!(is_16 || is_32))
2031 continue;
2032
2033 /* src1 cannot be an inline constant due to encoding
2034 * restrictions. So, if possible we try to flip the arguments
2035 * in that case */
2036
2037 int op = ins->alu.op;
2038
2039 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2040 alu_opcode_props[op].props & OP_COMMUTES) {
2041 mir_flip(ins);
2042 }
2043
2044 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2045 /* Extract the source information */
2046
2047 midgard_vector_alu_src *src;
2048 int q = ins->alu.src2;
2049 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2050 src = m;
2051
2052 /* Component is from the swizzle. Take a nonzero component */
2053 assert(ins->mask);
2054 unsigned first_comp = ffs(ins->mask) - 1;
2055 unsigned component = ins->swizzle[1][first_comp];
2056
2057 /* Scale constant appropriately, if we can legally */
2058 uint16_t scaled_constant = 0;
2059
2060 if (is_16) {
2061 scaled_constant = ins->constants.u16[component];
2062 } else if (midgard_is_integer_op(op)) {
2063 scaled_constant = ins->constants.u32[component];
2064
2065 /* Constant overflow after resize */
2066 if (scaled_constant != ins->constants.u32[component])
2067 continue;
2068 } else {
2069 float original = ins->constants.f32[component];
2070 scaled_constant = _mesa_float_to_half(original);
2071
2072 /* Check for loss of precision. If this is
2073 * mediump, we don't care, but for a highp
2074 * shader, we need to pay attention. NIR
2075 * doesn't yet tell us which mode we're in!
2076 * Practically this prevents most constants
2077 * from being inlined, sadly. */
2078
2079 float fp32 = _mesa_half_to_float(scaled_constant);
2080
2081 if (fp32 != original)
2082 continue;
2083 }
2084
2085 /* We don't know how to handle these with a constant */
2086
2087 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2088 DBG("Bailing inline constant...\n");
2089 continue;
2090 }
2091
2092 /* Make sure that the constant is not itself a vector
2093 * by checking if all accessed values are the same. */
2094
2095 const midgard_constants *cons = &ins->constants;
2096 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2097
2098 bool is_vector = false;
2099 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2100
2101 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2102 /* We only care if this component is actually used */
2103 if (!(mask & (1 << c)))
2104 continue;
2105
2106 uint32_t test = is_16 ?
2107 cons->u16[ins->swizzle[1][c]] :
2108 cons->u32[ins->swizzle[1][c]];
2109
2110 if (test != value) {
2111 is_vector = true;
2112 break;
2113 }
2114 }
2115
2116 if (is_vector)
2117 continue;
2118
2119 /* Get rid of the embedded constant */
2120 ins->has_constants = false;
2121 ins->src[1] = ~0;
2122 ins->has_inline_constant = true;
2123 ins->inline_constant = scaled_constant;
2124 }
2125 }
2126 }
2127
2128 /* Dead code elimination for branches at the end of a block - only one branch
2129 * per block is legal semantically */
2130
2131 static void
2132 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2133 {
2134 bool branched = false;
2135
2136 mir_foreach_instr_in_block_safe(block, ins) {
2137 if (!midgard_is_branch_unit(ins->unit)) continue;
2138
2139 if (branched)
2140 mir_remove_instruction(ins);
2141
2142 branched = true;
2143 }
2144 }
2145
2146 static unsigned
2147 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2148 {
2149 /* Loop to ourselves */
2150 midgard_instruction *br = ctx->writeout_branch[rt];
2151 struct midgard_instruction ins = v_branch(false, false);
2152 ins.writeout = true;
2153 ins.writeout_depth = br->writeout_depth;
2154 ins.writeout_stencil = br->writeout_stencil;
2155 ins.branch.target_block = ctx->block_count - 1;
2156 ins.constants.u32[0] = br->constants.u32[0];
2157 emit_mir_instruction(ctx, ins);
2158
2159 ctx->current_block->epilogue = true;
2160 schedule_barrier(ctx);
2161 return ins.branch.target_block;
2162 }
2163
2164 static midgard_block *
2165 emit_block(compiler_context *ctx, nir_block *block)
2166 {
2167 midgard_block *this_block = ctx->after_block;
2168 ctx->after_block = NULL;
2169
2170 if (!this_block)
2171 this_block = create_empty_block(ctx);
2172
2173 list_addtail(&this_block->base.link, &ctx->blocks);
2174
2175 this_block->scheduled = false;
2176 ++ctx->block_count;
2177
2178 /* Set up current block */
2179 list_inithead(&this_block->base.instructions);
2180 ctx->current_block = this_block;
2181
2182 nir_foreach_instr(instr, block) {
2183 emit_instr(ctx, instr);
2184 ++ctx->instruction_count;
2185 }
2186
2187 return this_block;
2188 }
2189
2190 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2191
2192 static void
2193 emit_if(struct compiler_context *ctx, nir_if *nif)
2194 {
2195 midgard_block *before_block = ctx->current_block;
2196
2197 /* Speculatively emit the branch, but we can't fill it in until later */
2198 EMIT(branch, true, true);
2199 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2200 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2201 then_branch->src_types[0] = nir_type_uint32;
2202
2203 /* Emit the two subblocks. */
2204 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2205 midgard_block *end_then_block = ctx->current_block;
2206
2207 /* Emit a jump from the end of the then block to the end of the else */
2208 EMIT(branch, false, false);
2209 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2210
2211 /* Emit second block, and check if it's empty */
2212
2213 int else_idx = ctx->block_count;
2214 int count_in = ctx->instruction_count;
2215 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2216 midgard_block *end_else_block = ctx->current_block;
2217 int after_else_idx = ctx->block_count;
2218
2219 /* Now that we have the subblocks emitted, fix up the branches */
2220
2221 assert(then_block);
2222 assert(else_block);
2223
2224 if (ctx->instruction_count == count_in) {
2225 /* The else block is empty, so don't emit an exit jump */
2226 mir_remove_instruction(then_exit);
2227 then_branch->branch.target_block = after_else_idx;
2228 } else {
2229 then_branch->branch.target_block = else_idx;
2230 then_exit->branch.target_block = after_else_idx;
2231 }
2232
2233 /* Wire up the successors */
2234
2235 ctx->after_block = create_empty_block(ctx);
2236
2237 pan_block_add_successor(&before_block->base, &then_block->base);
2238 pan_block_add_successor(&before_block->base, &else_block->base);
2239
2240 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2241 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2242 }
2243
2244 static void
2245 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2246 {
2247 /* Remember where we are */
2248 midgard_block *start_block = ctx->current_block;
2249
2250 /* Allocate a loop number, growing the current inner loop depth */
2251 int loop_idx = ++ctx->current_loop_depth;
2252
2253 /* Get index from before the body so we can loop back later */
2254 int start_idx = ctx->block_count;
2255
2256 /* Emit the body itself */
2257 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2258
2259 /* Branch back to loop back */
2260 struct midgard_instruction br_back = v_branch(false, false);
2261 br_back.branch.target_block = start_idx;
2262 emit_mir_instruction(ctx, br_back);
2263
2264 /* Mark down that branch in the graph. */
2265 pan_block_add_successor(&start_block->base, &loop_block->base);
2266 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2267
2268 /* Find the index of the block about to follow us (note: we don't add
2269 * one; blocks are 0-indexed so we get a fencepost problem) */
2270 int break_block_idx = ctx->block_count;
2271
2272 /* Fix up the break statements we emitted to point to the right place,
2273 * now that we can allocate a block number for them */
2274 ctx->after_block = create_empty_block(ctx);
2275
2276 mir_foreach_block_from(ctx, start_block, _block) {
2277 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2278 if (ins->type != TAG_ALU_4) continue;
2279 if (!ins->compact_branch) continue;
2280
2281 /* We found a branch -- check the type to see if we need to do anything */
2282 if (ins->branch.target_type != TARGET_BREAK) continue;
2283
2284 /* It's a break! Check if it's our break */
2285 if (ins->branch.target_break != loop_idx) continue;
2286
2287 /* Okay, cool, we're breaking out of this loop.
2288 * Rewrite from a break to a goto */
2289
2290 ins->branch.target_type = TARGET_GOTO;
2291 ins->branch.target_block = break_block_idx;
2292
2293 pan_block_add_successor(_block, &ctx->after_block->base);
2294 }
2295 }
2296
2297 /* Now that we've finished emitting the loop, free up the depth again
2298 * so we play nice with recursion amid nested loops */
2299 --ctx->current_loop_depth;
2300
2301 /* Dump loop stats */
2302 ++ctx->loop_count;
2303 }
2304
2305 static midgard_block *
2306 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2307 {
2308 midgard_block *start_block = NULL;
2309
2310 foreach_list_typed(nir_cf_node, node, node, list) {
2311 switch (node->type) {
2312 case nir_cf_node_block: {
2313 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2314
2315 if (!start_block)
2316 start_block = block;
2317
2318 break;
2319 }
2320
2321 case nir_cf_node_if:
2322 emit_if(ctx, nir_cf_node_as_if(node));
2323 break;
2324
2325 case nir_cf_node_loop:
2326 emit_loop(ctx, nir_cf_node_as_loop(node));
2327 break;
2328
2329 case nir_cf_node_function:
2330 assert(0);
2331 break;
2332 }
2333 }
2334
2335 return start_block;
2336 }
2337
2338 /* Due to lookahead, we need to report the first tag executed in the command
2339 * stream and in branch targets. An initial block might be empty, so iterate
2340 * until we find one that 'works' */
2341
2342 static unsigned
2343 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2344 {
2345 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2346
2347 mir_foreach_block_from(ctx, initial_block, _v) {
2348 midgard_block *v = (midgard_block *) _v;
2349 if (v->quadword_count) {
2350 midgard_bundle *initial_bundle =
2351 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2352
2353 return initial_bundle->tag;
2354 }
2355 }
2356
2357 /* Default to a tag 1 which will break from the shader, in case we jump
2358 * to the exit block (i.e. `return` in a compute shader) */
2359
2360 return 1;
2361 }
2362
2363 /* For each fragment writeout instruction, generate a writeout loop to
2364 * associate with it */
2365
2366 static void
2367 mir_add_writeout_loops(compiler_context *ctx)
2368 {
2369 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2370 midgard_instruction *br = ctx->writeout_branch[rt];
2371 if (!br) continue;
2372
2373 unsigned popped = br->branch.target_block;
2374 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2375 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2376 br->branch.target_type = TARGET_GOTO;
2377
2378 /* If we have more RTs, we'll need to restore back after our
2379 * loop terminates */
2380
2381 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2382 midgard_instruction uncond = v_branch(false, false);
2383 uncond.branch.target_block = popped;
2384 uncond.branch.target_type = TARGET_GOTO;
2385 emit_mir_instruction(ctx, uncond);
2386 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2387 schedule_barrier(ctx);
2388 } else {
2389 /* We're last, so we can terminate here */
2390 br->last_writeout = true;
2391 }
2392 }
2393 }
2394
2395 int
2396 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2397 {
2398 struct util_dynarray *compiled = &program->compiled;
2399
2400 midgard_debug = debug_get_option_midgard_debug();
2401
2402 /* TODO: Bound against what? */
2403 compiler_context *ctx = rzalloc(NULL, compiler_context);
2404
2405 ctx->nir = nir;
2406 ctx->stage = nir->info.stage;
2407 ctx->is_blend = is_blend;
2408 ctx->alpha_ref = program->alpha_ref;
2409 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2410 ctx->quirks = midgard_get_quirks(gpu_id);
2411
2412 /* Start off with a safe cutoff, allowing usage of all 16 work
2413 * registers. Later, we'll promote uniform reads to uniform registers
2414 * if we determine it is beneficial to do so */
2415 ctx->uniform_cutoff = 8;
2416
2417 /* Initialize at a global (not block) level hash tables */
2418
2419 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2420 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2421
2422 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2423 * (so we don't accidentally duplicate the epilogue since mesa/st has
2424 * messed with our I/O quite a bit already) */
2425
2426 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2427
2428 if (ctx->stage == MESA_SHADER_VERTEX) {
2429 NIR_PASS_V(nir, nir_lower_viewport_transform);
2430 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2431 }
2432
2433 NIR_PASS_V(nir, nir_lower_var_copies);
2434 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2435 NIR_PASS_V(nir, nir_split_var_copies);
2436 NIR_PASS_V(nir, nir_lower_var_copies);
2437 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2438 NIR_PASS_V(nir, nir_lower_var_copies);
2439 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2440
2441 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2442 NIR_PASS_V(nir, nir_lower_ssbo);
2443 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2444
2445 /* Optimisation passes */
2446
2447 optimise_nir(nir, ctx->quirks);
2448
2449 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2450 nir_print_shader(nir, stdout);
2451 }
2452
2453 /* Assign sysvals and counts, now that we're sure
2454 * (post-optimisation) */
2455
2456 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2457 program->sysval_count = ctx->sysvals.sysval_count;
2458 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2459
2460 nir_foreach_function(func, nir) {
2461 if (!func->impl)
2462 continue;
2463
2464 list_inithead(&ctx->blocks);
2465 ctx->block_count = 0;
2466 ctx->func = func;
2467 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2468
2469 emit_cf_list(ctx, &func->impl->body);
2470 free(ctx->already_emitted);
2471 break; /* TODO: Multi-function shaders */
2472 }
2473
2474 util_dynarray_init(compiled, NULL);
2475
2476 /* Per-block lowering before opts */
2477
2478 mir_foreach_block(ctx, _block) {
2479 midgard_block *block = (midgard_block *) _block;
2480 inline_alu_constants(ctx, block);
2481 midgard_opt_promote_fmov(ctx, block);
2482 embedded_to_inline_constant(ctx, block);
2483 }
2484 /* MIR-level optimizations */
2485
2486 bool progress = false;
2487
2488 do {
2489 progress = false;
2490
2491 mir_foreach_block(ctx, _block) {
2492 midgard_block *block = (midgard_block *) _block;
2493 progress |= midgard_opt_copy_prop(ctx, block);
2494 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2495 progress |= midgard_opt_combine_projection(ctx, block);
2496 progress |= midgard_opt_varying_projection(ctx, block);
2497 progress |= midgard_opt_not_propagate(ctx, block);
2498 progress |= midgard_opt_fuse_src_invert(ctx, block);
2499 progress |= midgard_opt_fuse_dest_invert(ctx, block);
2500 progress |= midgard_opt_csel_invert(ctx, block);
2501 progress |= midgard_opt_drop_cmp_invert(ctx, block);
2502 progress |= midgard_opt_invert_branch(ctx, block);
2503 }
2504 } while (progress);
2505
2506 mir_foreach_block(ctx, _block) {
2507 midgard_block *block = (midgard_block *) _block;
2508 midgard_lower_invert(ctx, block);
2509 midgard_lower_derivatives(ctx, block);
2510 }
2511
2512 /* Nested control-flow can result in dead branches at the end of the
2513 * block. This messes with our analysis and is just dead code, so cull
2514 * them */
2515 mir_foreach_block(ctx, _block) {
2516 midgard_block *block = (midgard_block *) _block;
2517 midgard_cull_dead_branch(ctx, block);
2518 }
2519
2520 /* Ensure we were lowered */
2521 mir_foreach_instr_global(ctx, ins) {
2522 assert(!ins->invert);
2523 }
2524
2525 if (ctx->stage == MESA_SHADER_FRAGMENT)
2526 mir_add_writeout_loops(ctx);
2527
2528 /* Analyze now that the code is known but before scheduling creates
2529 * pipeline registers which are harder to track */
2530 mir_analyze_helper_terminate(ctx);
2531 mir_analyze_helper_requirements(ctx);
2532
2533 /* Schedule! */
2534 midgard_schedule_program(ctx);
2535 mir_ra(ctx);
2536
2537 /* Now that all the bundles are scheduled and we can calculate block
2538 * sizes, emit actual branch instructions rather than placeholders */
2539
2540 int br_block_idx = 0;
2541
2542 mir_foreach_block(ctx, _block) {
2543 midgard_block *block = (midgard_block *) _block;
2544 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2545 for (int c = 0; c < bundle->instruction_count; ++c) {
2546 midgard_instruction *ins = bundle->instructions[c];
2547
2548 if (!midgard_is_branch_unit(ins->unit)) continue;
2549
2550 /* Parse some basic branch info */
2551 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2552 bool is_conditional = ins->branch.conditional;
2553 bool is_inverted = ins->branch.invert_conditional;
2554 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2555 bool is_writeout = ins->writeout;
2556
2557 /* Determine the block we're jumping to */
2558 int target_number = ins->branch.target_block;
2559
2560 /* Report the destination tag */
2561 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2562
2563 /* Count up the number of quadwords we're
2564 * jumping over = number of quadwords until
2565 * (br_block_idx, target_number) */
2566
2567 int quadword_offset = 0;
2568
2569 if (is_discard) {
2570 /* Ignored */
2571 } else if (target_number > br_block_idx) {
2572 /* Jump forward */
2573
2574 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2575 midgard_block *blk = mir_get_block(ctx, idx);
2576 assert(blk);
2577
2578 quadword_offset += blk->quadword_count;
2579 }
2580 } else {
2581 /* Jump backwards */
2582
2583 for (int idx = br_block_idx; idx >= target_number; --idx) {
2584 midgard_block *blk = mir_get_block(ctx, idx);
2585 assert(blk);
2586
2587 quadword_offset -= blk->quadword_count;
2588 }
2589 }
2590
2591 /* Unconditional extended branches (far jumps)
2592 * have issues, so we always use a conditional
2593 * branch, setting the condition to always for
2594 * unconditional. For compact unconditional
2595 * branches, cond isn't used so it doesn't
2596 * matter what we pick. */
2597
2598 midgard_condition cond =
2599 !is_conditional ? midgard_condition_always :
2600 is_inverted ? midgard_condition_false :
2601 midgard_condition_true;
2602
2603 midgard_jmp_writeout_op op =
2604 is_discard ? midgard_jmp_writeout_op_discard :
2605 is_writeout ? midgard_jmp_writeout_op_writeout :
2606 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2607 midgard_jmp_writeout_op_branch_cond;
2608
2609 if (!is_compact) {
2610 midgard_branch_extended branch =
2611 midgard_create_branch_extended(
2612 cond, op,
2613 dest_tag,
2614 quadword_offset);
2615
2616 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2617 } else if (is_conditional || is_discard) {
2618 midgard_branch_cond branch = {
2619 .op = op,
2620 .dest_tag = dest_tag,
2621 .offset = quadword_offset,
2622 .cond = cond
2623 };
2624
2625 assert(branch.offset == quadword_offset);
2626
2627 memcpy(&ins->br_compact, &branch, sizeof(branch));
2628 } else {
2629 assert(op == midgard_jmp_writeout_op_branch_uncond);
2630
2631 midgard_branch_uncond branch = {
2632 .op = op,
2633 .dest_tag = dest_tag,
2634 .offset = quadword_offset,
2635 .unknown = 1
2636 };
2637
2638 assert(branch.offset == quadword_offset);
2639
2640 memcpy(&ins->br_compact, &branch, sizeof(branch));
2641 }
2642 }
2643 }
2644
2645 ++br_block_idx;
2646 }
2647
2648 /* Emit flat binary from the instruction arrays. Iterate each block in
2649 * sequence. Save instruction boundaries such that lookahead tags can
2650 * be assigned easily */
2651
2652 /* Cache _all_ bundles in source order for lookahead across failed branches */
2653
2654 int bundle_count = 0;
2655 mir_foreach_block(ctx, _block) {
2656 midgard_block *block = (midgard_block *) _block;
2657 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2658 }
2659 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2660 int bundle_idx = 0;
2661 mir_foreach_block(ctx, _block) {
2662 midgard_block *block = (midgard_block *) _block;
2663 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2664 source_order_bundles[bundle_idx++] = bundle;
2665 }
2666 }
2667
2668 int current_bundle = 0;
2669
2670 /* Midgard prefetches instruction types, so during emission we
2671 * need to lookahead. Unless this is the last instruction, in
2672 * which we return 1. */
2673
2674 mir_foreach_block(ctx, _block) {
2675 midgard_block *block = (midgard_block *) _block;
2676 mir_foreach_bundle_in_block(block, bundle) {
2677 int lookahead = 1;
2678
2679 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2680 lookahead = source_order_bundles[current_bundle + 1]->tag;
2681
2682 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2683 ++current_bundle;
2684 }
2685
2686 /* TODO: Free deeper */
2687 //util_dynarray_fini(&block->instructions);
2688 }
2689
2690 free(source_order_bundles);
2691
2692 /* Report the very first tag executed */
2693 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2694
2695 /* Deal with off-by-one related to the fencepost problem */
2696 program->work_register_count = ctx->work_registers + 1;
2697 program->uniform_cutoff = ctx->uniform_cutoff;
2698
2699 program->blend_patch_offset = ctx->blend_constant_offset;
2700 program->tls_size = ctx->tls_size;
2701
2702 if (midgard_debug & MIDGARD_DBG_SHADERS)
2703 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2704
2705 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2706 unsigned nr_bundles = 0, nr_ins = 0;
2707
2708 /* Count instructions and bundles */
2709
2710 mir_foreach_block(ctx, _block) {
2711 midgard_block *block = (midgard_block *) _block;
2712 nr_bundles += util_dynarray_num_elements(
2713 &block->bundles, midgard_bundle);
2714
2715 mir_foreach_bundle_in_block(block, bun)
2716 nr_ins += bun->instruction_count;
2717 }
2718
2719 /* Calculate thread count. There are certain cutoffs by
2720 * register count for thread count */
2721
2722 unsigned nr_registers = program->work_register_count;
2723
2724 unsigned nr_threads =
2725 (nr_registers <= 4) ? 4 :
2726 (nr_registers <= 8) ? 2 :
2727 1;
2728
2729 /* Dump stats */
2730
2731 fprintf(stderr, "shader%d - %s shader: "
2732 "%u inst, %u bundles, %u quadwords, "
2733 "%u registers, %u threads, %u loops, "
2734 "%u:%u spills:fills\n",
2735 SHADER_DB_COUNT++,
2736 gl_shader_stage_name(ctx->stage),
2737 nr_ins, nr_bundles, ctx->quadword_count,
2738 nr_registers, nr_threads,
2739 ctx->loop_count,
2740 ctx->spills, ctx->fills);
2741 }
2742
2743 ralloc_free(ctx);
2744
2745 return 0;
2746 }