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pan/midgard: Remove dest_override sysval argument
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
44
45 #include "midgard.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
49 #include "helpers.h"
50 #include "compiler.h"
51 #include "midgard_quirks.h"
52
53 #include "disassemble.h"
54
55 static const struct debug_named_value debug_options[] = {
56 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
57 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
58 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
59 DEBUG_NAMED_VALUE_END
60 };
61
62 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
63
64 unsigned SHADER_DB_COUNT = 0;
65
66 int midgard_debug = 0;
67
68 #define DBG(fmt, ...) \
69 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
70 fprintf(stderr, "%s:%d: "fmt, \
71 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
72 static midgard_block *
73 create_empty_block(compiler_context *ctx)
74 {
75 midgard_block *blk = rzalloc(ctx, midgard_block);
76
77 blk->predecessors = _mesa_set_create(blk,
78 _mesa_hash_pointer,
79 _mesa_key_pointer_equal);
80
81 blk->source_id = ctx->block_source_count++;
82
83 return blk;
84 }
85
86 static void
87 midgard_block_add_successor(midgard_block *block, midgard_block *successor)
88 {
89 assert(block);
90 assert(successor);
91
92 /* Deduplicate */
93 for (unsigned i = 0; i < block->nr_successors; ++i) {
94 if (block->successors[i] == successor)
95 return;
96 }
97
98 block->successors[block->nr_successors++] = successor;
99 assert(block->nr_successors <= ARRAY_SIZE(block->successors));
100
101 /* Note the predecessor in the other direction */
102 _mesa_set_add(successor->predecessors, block);
103 }
104
105 static void
106 schedule_barrier(compiler_context *ctx)
107 {
108 midgard_block *temp = ctx->after_block;
109 ctx->after_block = create_empty_block(ctx);
110 ctx->block_count++;
111 list_addtail(&ctx->after_block->link, &ctx->blocks);
112 list_inithead(&ctx->after_block->instructions);
113 midgard_block_add_successor(ctx->current_block, ctx->after_block);
114 ctx->current_block = ctx->after_block;
115 ctx->after_block = temp;
116 }
117
118 /* Helpers to generate midgard_instruction's using macro magic, since every
119 * driver seems to do it that way */
120
121 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
122
123 #define M_LOAD_STORE(name, store) \
124 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
125 midgard_instruction i = { \
126 .type = TAG_LOAD_STORE_4, \
127 .mask = 0xF, \
128 .dest = ~0, \
129 .src = { ~0, ~0, ~0, ~0 }, \
130 .swizzle = SWIZZLE_IDENTITY_4, \
131 .load_store = { \
132 .op = midgard_op_##name, \
133 .address = address \
134 } \
135 }; \
136 \
137 if (store) \
138 i.src[0] = ssa; \
139 else \
140 i.dest = ssa; \
141 \
142 return i; \
143 }
144
145 #define M_LOAD(name) M_LOAD_STORE(name, false)
146 #define M_STORE(name) M_LOAD_STORE(name, true)
147
148 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
149 * the corresponding Midgard source */
150
151 static midgard_vector_alu_src
152 vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
153 bool half, bool sext)
154 {
155 /* Figure out how many components there are so we can adjust.
156 * Specifically we want to broadcast the last channel so things like
157 * ball2/3 work.
158 */
159
160 if (broadcast_count && src) {
161 uint8_t last_component = src->swizzle[broadcast_count - 1];
162
163 for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) {
164 src->swizzle[c] = last_component;
165 }
166 }
167
168 midgard_vector_alu_src alu_src = {
169 .rep_low = 0,
170 .rep_high = 0,
171 .half = half
172 };
173
174 if (is_int) {
175 alu_src.mod = midgard_int_normal;
176
177 /* Sign/zero-extend if needed */
178
179 if (half) {
180 alu_src.mod = sext ?
181 midgard_int_sign_extend
182 : midgard_int_zero_extend;
183 }
184
185 /* These should have been lowered away */
186 if (src)
187 assert(!(src->abs || src->negate));
188 } else {
189 if (src)
190 alu_src.mod = (src->abs << 0) | (src->negate << 1);
191 }
192
193 return alu_src;
194 }
195
196 /* load/store instructions have both 32-bit and 16-bit variants, depending on
197 * whether we are using vectors composed of highp or mediump. At the moment, we
198 * don't support half-floats -- this requires changes in other parts of the
199 * compiler -- therefore the 16-bit versions are commented out. */
200
201 //M_LOAD(ld_attr_16);
202 M_LOAD(ld_attr_32);
203 //M_LOAD(ld_vary_16);
204 M_LOAD(ld_vary_32);
205 M_LOAD(ld_ubo_int4);
206 M_LOAD(ld_int4);
207 M_STORE(st_int4);
208 M_LOAD(ld_color_buffer_32u);
209 //M_STORE(st_vary_16);
210 M_STORE(st_vary_32);
211 M_LOAD(ld_cubemap_coords);
212 M_LOAD(ld_compute_id);
213
214 static midgard_instruction
215 v_branch(bool conditional, bool invert)
216 {
217 midgard_instruction ins = {
218 .type = TAG_ALU_4,
219 .unit = ALU_ENAB_BRANCH,
220 .compact_branch = true,
221 .branch = {
222 .conditional = conditional,
223 .invert_conditional = invert
224 },
225 .dest = ~0,
226 .src = { ~0, ~0, ~0, ~0 },
227 };
228
229 return ins;
230 }
231
232 static midgard_branch_extended
233 midgard_create_branch_extended( midgard_condition cond,
234 midgard_jmp_writeout_op op,
235 unsigned dest_tag,
236 signed quadword_offset)
237 {
238 /* The condition code is actually a LUT describing a function to
239 * combine multiple condition codes. However, we only support a single
240 * condition code at the moment, so we just duplicate over a bunch of
241 * times. */
242
243 uint16_t duplicated_cond =
244 (cond << 14) |
245 (cond << 12) |
246 (cond << 10) |
247 (cond << 8) |
248 (cond << 6) |
249 (cond << 4) |
250 (cond << 2) |
251 (cond << 0);
252
253 midgard_branch_extended branch = {
254 .op = op,
255 .dest_tag = dest_tag,
256 .offset = quadword_offset,
257 .cond = duplicated_cond
258 };
259
260 return branch;
261 }
262
263 static void
264 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
265 {
266 ins->has_constants = true;
267 memcpy(&ins->constants, constants, 16);
268 }
269
270 static int
271 glsl_type_size(const struct glsl_type *type, bool bindless)
272 {
273 return glsl_count_attribute_slots(type, false);
274 }
275
276 /* Lower fdot2 to a vector multiplication followed by channel addition */
277 static void
278 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
279 {
280 if (alu->op != nir_op_fdot2)
281 return;
282
283 b->cursor = nir_before_instr(&alu->instr);
284
285 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
286 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
287
288 nir_ssa_def *product = nir_fmul(b, src0, src1);
289
290 nir_ssa_def *sum = nir_fadd(b,
291 nir_channel(b, product, 0),
292 nir_channel(b, product, 1));
293
294 /* Replace the fdot2 with this sum */
295 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
296 }
297
298 /* TODO: ssbo_size */
299 static int
300 midgard_sysval_for_ssbo(nir_intrinsic_instr *instr)
301 {
302 nir_src index = instr->src[0];
303 assert(nir_src_is_const(index));
304 uint32_t uindex = nir_src_as_uint(index);
305
306 return PAN_SYSVAL(SSBO, uindex);
307 }
308
309 static int
310 midgard_sysval_for_sampler(nir_intrinsic_instr *instr)
311 {
312 /* TODO: indirect samplers !!! */
313 nir_src index = instr->src[0];
314 assert(nir_src_is_const(index));
315 uint32_t uindex = nir_src_as_uint(index);
316
317 return PAN_SYSVAL(SAMPLER, uindex);
318 }
319
320 static unsigned
321 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
322 {
323 switch (instr->intrinsic) {
324 case nir_intrinsic_load_viewport_scale:
325 return PAN_SYSVAL_VIEWPORT_SCALE;
326 case nir_intrinsic_load_viewport_offset:
327 return PAN_SYSVAL_VIEWPORT_OFFSET;
328 case nir_intrinsic_load_num_work_groups:
329 return PAN_SYSVAL_NUM_WORK_GROUPS;
330 case nir_intrinsic_load_ssbo_address:
331 case nir_intrinsic_get_buffer_size:
332 return midgard_sysval_for_ssbo(instr);
333 case nir_intrinsic_load_sampler_lod_parameters_pan:
334 return midgard_sysval_for_sampler(instr);
335 default:
336 return ~0;
337 }
338 }
339
340 static int
341 sysval_for_instr(nir_instr *instr, nir_dest *dest)
342 {
343 nir_intrinsic_instr *intr;
344 nir_dest *dst = NULL;
345 nir_tex_instr *tex;
346 unsigned sysval = ~0;
347
348 switch (instr->type) {
349 case nir_instr_type_intrinsic:
350 intr = nir_instr_as_intrinsic(instr);
351 sysval = midgard_nir_sysval_for_intrinsic(intr);
352 dst = &intr->dest;
353 break;
354 case nir_instr_type_tex:
355 tex = nir_instr_as_tex(instr);
356 if (tex->op != nir_texop_txs)
357 break;
358
359 sysval = PAN_SYSVAL(TEXTURE_SIZE,
360 PAN_TXS_SYSVAL_ID(tex->texture_index,
361 nir_tex_instr_dest_size(tex) -
362 (tex->is_array ? 1 : 0),
363 tex->is_array));
364 dst = &tex->dest;
365 break;
366 default:
367 break;
368 }
369
370 if (dest && dst)
371 *dest = *dst;
372
373 return sysval;
374 }
375
376 static void
377 midgard_nir_assign_sysval_body(struct panfrost_sysvals *ctx, nir_instr *instr)
378 {
379 int sysval = sysval_for_instr(instr, NULL);
380 if (sysval < 0)
381 return;
382
383 /* We have a sysval load; check if it's already been assigned */
384
385 if (_mesa_hash_table_u64_search(ctx->sysval_to_id, sysval))
386 return;
387
388 /* It hasn't -- so assign it now! */
389
390 unsigned id = ctx->sysval_count++;
391 _mesa_hash_table_u64_insert(ctx->sysval_to_id, sysval, (void *) ((uintptr_t) id + 1));
392 ctx->sysvals[id] = sysval;
393 }
394
395 static void
396 midgard_nir_assign_sysvals(struct panfrost_sysvals *ctx, nir_shader *shader)
397 {
398 ctx->sysval_count = 0;
399 ctx->sysval_to_id = _mesa_hash_table_u64_create(NULL);
400
401 nir_foreach_function(function, shader) {
402 if (!function->impl) continue;
403
404 nir_foreach_block(block, function->impl) {
405 nir_foreach_instr_safe(instr, block) {
406 midgard_nir_assign_sysval_body(ctx, instr);
407 }
408 }
409 }
410 }
411
412 static bool
413 midgard_nir_lower_fdot2(nir_shader *shader)
414 {
415 bool progress = false;
416
417 nir_foreach_function(function, shader) {
418 if (!function->impl) continue;
419
420 nir_builder _b;
421 nir_builder *b = &_b;
422 nir_builder_init(b, function->impl);
423
424 nir_foreach_block(block, function->impl) {
425 nir_foreach_instr_safe(instr, block) {
426 if (instr->type != nir_instr_type_alu) continue;
427
428 nir_alu_instr *alu = nir_instr_as_alu(instr);
429 midgard_nir_lower_fdot2_body(b, alu);
430
431 progress |= true;
432 }
433 }
434
435 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
436
437 }
438
439 return progress;
440 }
441
442 /* Midgard can't write depth and stencil separately. It has to happen in a
443 * single store operation containing both. Let's add a panfrost specific
444 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
445 * one.
446 */
447 static bool
448 midgard_nir_lower_zs_store(nir_shader *nir)
449 {
450 if (nir->info.stage != MESA_SHADER_FRAGMENT)
451 return false;
452
453 nir_variable *z_var = NULL, *s_var = NULL;
454
455 nir_foreach_variable(var, &nir->outputs) {
456 if (var->data.location == FRAG_RESULT_DEPTH)
457 z_var = var;
458 else if (var->data.location == FRAG_RESULT_STENCIL)
459 s_var = var;
460 }
461
462 if (!z_var && !s_var)
463 return false;
464
465 bool progress = false;
466
467 nir_foreach_function(function, nir) {
468 if (!function->impl) continue;
469
470 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
471
472 nir_foreach_block(block, function->impl) {
473 nir_foreach_instr_safe(instr, block) {
474 if (instr->type != nir_instr_type_intrinsic)
475 continue;
476
477 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
478 if (intr->intrinsic != nir_intrinsic_store_output)
479 continue;
480
481 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
482 assert(!z_store);
483 z_store = intr;
484 last_store = intr;
485 }
486
487 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
488 assert(!s_store);
489 s_store = intr;
490 last_store = intr;
491 }
492 }
493 }
494
495 if (!z_store && !s_store) continue;
496
497 nir_builder b;
498 nir_builder_init(&b, function->impl);
499
500 b.cursor = nir_before_instr(&last_store->instr);
501
502 nir_ssa_def *zs_store_src;
503
504 if (z_store && s_store) {
505 nir_ssa_def *srcs[2] = {
506 nir_ssa_for_src(&b, z_store->src[0], 1),
507 nir_ssa_for_src(&b, s_store->src[0], 1),
508 };
509
510 zs_store_src = nir_vec(&b, srcs, 2);
511 } else {
512 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
513 }
514
515 nir_intrinsic_instr *zs_store;
516
517 zs_store = nir_intrinsic_instr_create(b.shader,
518 nir_intrinsic_store_zs_output_pan);
519 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
520 zs_store->num_components = z_store && s_store ? 2 : 1;
521 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
522
523 /* Replace the Z and S store by a ZS store */
524 nir_builder_instr_insert(&b, &zs_store->instr);
525
526 if (z_store)
527 nir_instr_remove(&z_store->instr);
528
529 if (s_store)
530 nir_instr_remove(&s_store->instr);
531
532 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
533 progress = true;
534 }
535
536 return progress;
537 }
538
539 /* Flushes undefined values to zero */
540
541 static void
542 optimise_nir(nir_shader *nir, unsigned quirks)
543 {
544 bool progress;
545 unsigned lower_flrp =
546 (nir->options->lower_flrp16 ? 16 : 0) |
547 (nir->options->lower_flrp32 ? 32 : 0) |
548 (nir->options->lower_flrp64 ? 64 : 0);
549
550 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
551 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
552
553 nir_lower_tex_options lower_tex_options = {
554 .lower_txs_lod = true,
555 .lower_txp = ~0,
556 .lower_tex_without_implicit_lod =
557 (quirks & MIDGARD_EXPLICIT_LOD),
558
559 /* TODO: we have native gradient.. */
560 .lower_txd = true,
561 };
562
563 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
564
565 /* Must lower fdot2 after tex is lowered */
566 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
567
568 /* T720 is broken. */
569
570 if (quirks & MIDGARD_BROKEN_LOD)
571 NIR_PASS_V(nir, midgard_nir_lod_errata);
572
573 do {
574 progress = false;
575
576 NIR_PASS(progress, nir, nir_lower_var_copies);
577 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
578
579 NIR_PASS(progress, nir, nir_copy_prop);
580 NIR_PASS(progress, nir, nir_opt_remove_phis);
581 NIR_PASS(progress, nir, nir_opt_dce);
582 NIR_PASS(progress, nir, nir_opt_dead_cf);
583 NIR_PASS(progress, nir, nir_opt_cse);
584 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
585 NIR_PASS(progress, nir, nir_opt_algebraic);
586 NIR_PASS(progress, nir, nir_opt_constant_folding);
587
588 if (lower_flrp != 0) {
589 bool lower_flrp_progress = false;
590 NIR_PASS(lower_flrp_progress,
591 nir,
592 nir_lower_flrp,
593 lower_flrp,
594 false /* always_precise */,
595 nir->options->lower_ffma);
596 if (lower_flrp_progress) {
597 NIR_PASS(progress, nir,
598 nir_opt_constant_folding);
599 progress = true;
600 }
601
602 /* Nothing should rematerialize any flrps, so we only
603 * need to do this lowering once.
604 */
605 lower_flrp = 0;
606 }
607
608 NIR_PASS(progress, nir, nir_opt_undef);
609 NIR_PASS(progress, nir, nir_undef_to_zero);
610
611 NIR_PASS(progress, nir, nir_opt_loop_unroll,
612 nir_var_shader_in |
613 nir_var_shader_out |
614 nir_var_function_temp);
615
616 NIR_PASS(progress, nir, nir_opt_vectorize);
617 } while (progress);
618
619 /* Must be run at the end to prevent creation of fsin/fcos ops */
620 NIR_PASS(progress, nir, midgard_nir_scale_trig);
621
622 do {
623 progress = false;
624
625 NIR_PASS(progress, nir, nir_opt_dce);
626 NIR_PASS(progress, nir, nir_opt_algebraic);
627 NIR_PASS(progress, nir, nir_opt_constant_folding);
628 NIR_PASS(progress, nir, nir_copy_prop);
629 } while (progress);
630
631 NIR_PASS(progress, nir, nir_opt_algebraic_late);
632
633 /* We implement booleans as 32-bit 0/~0 */
634 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
635
636 /* Now that booleans are lowered, we can run out late opts */
637 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
638
639 /* Lower mods for float ops only. Integer ops don't support modifiers
640 * (saturate doesn't make sense on integers, neg/abs require dedicated
641 * instructions) */
642
643 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
644 NIR_PASS(progress, nir, nir_copy_prop);
645 NIR_PASS(progress, nir, nir_opt_dce);
646
647 /* Take us out of SSA */
648 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
649 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
650
651 /* We are a vector architecture; write combine where possible */
652 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
653 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
654
655 NIR_PASS(progress, nir, nir_opt_dce);
656 }
657
658 /* Do not actually emit a load; instead, cache the constant for inlining */
659
660 static void
661 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
662 {
663 nir_ssa_def def = instr->def;
664
665 midgard_constants *consts = rzalloc(NULL, midgard_constants);
666
667 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
668
669 #define RAW_CONST_COPY(bits) \
670 nir_const_value_to_array(consts->u##bits, instr->value, \
671 instr->def.num_components, u##bits)
672
673 switch (instr->def.bit_size) {
674 case 64:
675 RAW_CONST_COPY(64);
676 break;
677 case 32:
678 RAW_CONST_COPY(32);
679 break;
680 case 16:
681 RAW_CONST_COPY(16);
682 break;
683 case 8:
684 RAW_CONST_COPY(8);
685 break;
686 default:
687 unreachable("Invalid bit_size for load_const instruction\n");
688 }
689
690 /* Shifted for SSA, +1 for off-by-one */
691 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
692 }
693
694 /* Normally constants are embedded implicitly, but for I/O and such we have to
695 * explicitly emit a move with the constant source */
696
697 static void
698 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
699 {
700 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
701
702 if (constant_value) {
703 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
704 attach_constants(ctx, &ins, constant_value, node + 1);
705 emit_mir_instruction(ctx, ins);
706 }
707 }
708
709 static bool
710 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
711 {
712 unsigned comp = src->swizzle[0];
713
714 for (unsigned c = 1; c < nr_components; ++c) {
715 if (src->swizzle[c] != comp)
716 return true;
717 }
718
719 return false;
720 }
721
722 #define ALU_CASE(nir, _op) \
723 case nir_op_##nir: \
724 op = midgard_alu_op_##_op; \
725 assert(src_bitsize == dst_bitsize); \
726 break;
727
728 #define ALU_CASE_BCAST(nir, _op, count) \
729 case nir_op_##nir: \
730 op = midgard_alu_op_##_op; \
731 broadcast_swizzle = count; \
732 assert(src_bitsize == dst_bitsize); \
733 break;
734 static bool
735 nir_is_fzero_constant(nir_src src)
736 {
737 if (!nir_src_is_const(src))
738 return false;
739
740 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
741 if (nir_src_comp_as_float(src, c) != 0.0)
742 return false;
743 }
744
745 return true;
746 }
747
748 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
749 * special treatment override this anyway. */
750
751 static midgard_reg_mode
752 reg_mode_for_nir(nir_alu_instr *instr)
753 {
754 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
755
756 switch (src_bitsize) {
757 case 8:
758 return midgard_reg_mode_8;
759 case 16:
760 return midgard_reg_mode_16;
761 case 32:
762 return midgard_reg_mode_32;
763 case 64:
764 return midgard_reg_mode_64;
765 default:
766 unreachable("Invalid bit size");
767 }
768 }
769
770 static void
771 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
772 {
773 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
774 * is handled elsewhere */
775
776 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
777 midgard_emit_derivatives(ctx, instr);
778 return;
779 }
780
781 bool is_ssa = instr->dest.dest.is_ssa;
782
783 unsigned dest = nir_dest_index(&instr->dest.dest);
784 unsigned nr_components = nir_dest_num_components(instr->dest.dest);
785 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
786
787 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
788 * supported. A few do not and are commented for now. Also, there are a
789 * number of NIR ops which Midgard does not support and need to be
790 * lowered, also TODO. This switch block emits the opcode and calling
791 * convention of the Midgard instruction; actual packing is done in
792 * emit_alu below */
793
794 unsigned op;
795
796 /* Number of components valid to check for the instruction (the rest
797 * will be forced to the last), or 0 to use as-is. Relevant as
798 * ball-type instructions have a channel count in NIR but are all vec4
799 * in Midgard */
800
801 unsigned broadcast_swizzle = 0;
802
803 /* What register mode should we operate in? */
804 midgard_reg_mode reg_mode =
805 reg_mode_for_nir(instr);
806
807 /* Do we need a destination override? Used for inline
808 * type conversion */
809
810 midgard_dest_override dest_override =
811 midgard_dest_override_none;
812
813 /* Should we use a smaller respective source and sign-extend? */
814
815 bool half_1 = false, sext_1 = false;
816 bool half_2 = false, sext_2 = false;
817
818 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
819 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
820
821 switch (instr->op) {
822 ALU_CASE(fadd, fadd);
823 ALU_CASE(fmul, fmul);
824 ALU_CASE(fmin, fmin);
825 ALU_CASE(fmax, fmax);
826 ALU_CASE(imin, imin);
827 ALU_CASE(imax, imax);
828 ALU_CASE(umin, umin);
829 ALU_CASE(umax, umax);
830 ALU_CASE(ffloor, ffloor);
831 ALU_CASE(fround_even, froundeven);
832 ALU_CASE(ftrunc, ftrunc);
833 ALU_CASE(fceil, fceil);
834 ALU_CASE(fdot3, fdot3);
835 ALU_CASE(fdot4, fdot4);
836 ALU_CASE(iadd, iadd);
837 ALU_CASE(isub, isub);
838 ALU_CASE(imul, imul);
839
840 /* Zero shoved as second-arg */
841 ALU_CASE(iabs, iabsdiff);
842
843 ALU_CASE(mov, imov);
844
845 ALU_CASE(feq32, feq);
846 ALU_CASE(fne32, fne);
847 ALU_CASE(flt32, flt);
848 ALU_CASE(ieq32, ieq);
849 ALU_CASE(ine32, ine);
850 ALU_CASE(ilt32, ilt);
851 ALU_CASE(ult32, ult);
852
853 /* We don't have a native b2f32 instruction. Instead, like many
854 * GPUs, we exploit booleans as 0/~0 for false/true, and
855 * correspondingly AND
856 * by 1.0 to do the type conversion. For the moment, prime us
857 * to emit:
858 *
859 * iand [whatever], #0
860 *
861 * At the end of emit_alu (as MIR), we'll fix-up the constant
862 */
863
864 ALU_CASE(b2f32, iand);
865 ALU_CASE(b2i32, iand);
866
867 /* Likewise, we don't have a dedicated f2b32 instruction, but
868 * we can do a "not equal to 0.0" test. */
869
870 ALU_CASE(f2b32, fne);
871 ALU_CASE(i2b32, ine);
872
873 ALU_CASE(frcp, frcp);
874 ALU_CASE(frsq, frsqrt);
875 ALU_CASE(fsqrt, fsqrt);
876 ALU_CASE(fexp2, fexp2);
877 ALU_CASE(flog2, flog2);
878
879 ALU_CASE(f2i64, f2i_rtz);
880 ALU_CASE(f2u64, f2u_rtz);
881 ALU_CASE(i2f64, i2f_rtz);
882 ALU_CASE(u2f64, u2f_rtz);
883
884 ALU_CASE(f2i32, f2i_rtz);
885 ALU_CASE(f2u32, f2u_rtz);
886 ALU_CASE(i2f32, i2f_rtz);
887 ALU_CASE(u2f32, u2f_rtz);
888
889 ALU_CASE(f2i16, f2i_rtz);
890 ALU_CASE(f2u16, f2u_rtz);
891 ALU_CASE(i2f16, i2f_rtz);
892 ALU_CASE(u2f16, u2f_rtz);
893
894 ALU_CASE(fsin, fsin);
895 ALU_CASE(fcos, fcos);
896
897 /* We'll set invert */
898 ALU_CASE(inot, imov);
899 ALU_CASE(iand, iand);
900 ALU_CASE(ior, ior);
901 ALU_CASE(ixor, ixor);
902 ALU_CASE(ishl, ishl);
903 ALU_CASE(ishr, iasr);
904 ALU_CASE(ushr, ilsr);
905
906 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
907 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
908 ALU_CASE(b32all_fequal4, fball_eq);
909
910 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
911 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
912 ALU_CASE(b32any_fnequal4, fbany_neq);
913
914 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
915 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
916 ALU_CASE(b32all_iequal4, iball_eq);
917
918 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
919 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
920 ALU_CASE(b32any_inequal4, ibany_neq);
921
922 /* Source mods will be shoved in later */
923 ALU_CASE(fabs, fmov);
924 ALU_CASE(fneg, fmov);
925 ALU_CASE(fsat, fmov);
926
927 /* For size conversion, we use a move. Ideally though we would squash
928 * these ops together; maybe that has to happen after in NIR as part of
929 * propagation...? An earlier algebraic pass ensured we step down by
930 * only / exactly one size. If stepping down, we use a dest override to
931 * reduce the size; if stepping up, we use a larger-sized move with a
932 * half source and a sign/zero-extension modifier */
933
934 case nir_op_i2i8:
935 case nir_op_i2i16:
936 case nir_op_i2i32:
937 case nir_op_i2i64:
938 /* If we end up upscale, we'll need a sign-extend on the
939 * operand (the second argument) */
940
941 sext_2 = true;
942 /* fallthrough */
943 case nir_op_u2u8:
944 case nir_op_u2u16:
945 case nir_op_u2u32:
946 case nir_op_u2u64:
947 case nir_op_f2f16:
948 case nir_op_f2f32:
949 case nir_op_f2f64: {
950 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
951 instr->op == nir_op_f2f64)
952 op = midgard_alu_op_fmov;
953 else
954 op = midgard_alu_op_imov;
955
956 if (dst_bitsize == (src_bitsize * 2)) {
957 /* Converting up */
958 half_2 = true;
959
960 /* Use a greater register mode */
961 reg_mode++;
962 } else if (src_bitsize == (dst_bitsize * 2)) {
963 /* Converting down */
964 dest_override = midgard_dest_override_lower;
965 }
966
967 break;
968 }
969
970 /* For greater-or-equal, we lower to less-or-equal and flip the
971 * arguments */
972
973 case nir_op_fge:
974 case nir_op_fge32:
975 case nir_op_ige32:
976 case nir_op_uge32: {
977 op =
978 instr->op == nir_op_fge ? midgard_alu_op_fle :
979 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
980 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
981 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
982 0;
983
984 /* Swap via temporary */
985 nir_alu_src temp = instr->src[1];
986 instr->src[1] = instr->src[0];
987 instr->src[0] = temp;
988
989 break;
990 }
991
992 case nir_op_b32csel: {
993 /* Midgard features both fcsel and icsel, depending on
994 * the type of the arguments/output. However, as long
995 * as we're careful we can _always_ use icsel and
996 * _never_ need fcsel, since the latter does additional
997 * floating-point-specific processing whereas the
998 * former just moves bits on the wire. It's not obvious
999 * why these are separate opcodes, save for the ability
1000 * to do things like sat/pos/abs/neg for free */
1001
1002 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
1003 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
1004
1005 /* The condition is the first argument; move the other
1006 * arguments up one to be a binary instruction for
1007 * Midgard with the condition last */
1008
1009 nir_alu_src temp = instr->src[2];
1010
1011 instr->src[2] = instr->src[0];
1012 instr->src[0] = instr->src[1];
1013 instr->src[1] = temp;
1014
1015 break;
1016 }
1017
1018 default:
1019 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
1020 assert(0);
1021 return;
1022 }
1023
1024 /* Midgard can perform certain modifiers on output of an ALU op */
1025 unsigned outmod;
1026
1027 if (midgard_is_integer_out_op(op)) {
1028 outmod = midgard_outmod_int_wrap;
1029 } else {
1030 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
1031 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
1032 }
1033
1034 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
1035
1036 if (instr->op == nir_op_fmax) {
1037 if (nir_is_fzero_constant(instr->src[0].src)) {
1038 op = midgard_alu_op_fmov;
1039 nr_inputs = 1;
1040 outmod = midgard_outmod_pos;
1041 instr->src[0] = instr->src[1];
1042 } else if (nir_is_fzero_constant(instr->src[1].src)) {
1043 op = midgard_alu_op_fmov;
1044 nr_inputs = 1;
1045 outmod = midgard_outmod_pos;
1046 }
1047 }
1048
1049 /* Fetch unit, quirks, etc information */
1050 unsigned opcode_props = alu_opcode_props[op].props;
1051 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
1052
1053 /* src0 will always exist afaik, but src1 will not for 1-argument
1054 * instructions. The latter can only be fetched if the instruction
1055 * needs it, or else we may segfault. */
1056
1057 unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
1058 unsigned src1 = nr_inputs >= 2 ? nir_alu_src_index(ctx, &instr->src[1]) : ~0;
1059 unsigned src2 = nr_inputs == 3 ? nir_alu_src_index(ctx, &instr->src[2]) : ~0;
1060 assert(nr_inputs <= 3);
1061
1062 /* Rather than use the instruction generation helpers, we do it
1063 * ourselves here to avoid the mess */
1064
1065 midgard_instruction ins = {
1066 .type = TAG_ALU_4,
1067 .src = {
1068 quirk_flipped_r24 ? ~0 : src0,
1069 quirk_flipped_r24 ? src0 : src1,
1070 src2,
1071 ~0
1072 },
1073 .dest = dest,
1074 };
1075
1076 nir_alu_src *nirmods[3] = { NULL };
1077
1078 if (nr_inputs >= 2) {
1079 nirmods[0] = &instr->src[0];
1080 nirmods[1] = &instr->src[1];
1081 } else if (nr_inputs == 1) {
1082 nirmods[quirk_flipped_r24] = &instr->src[0];
1083 } else {
1084 assert(0);
1085 }
1086
1087 if (nr_inputs == 3)
1088 nirmods[2] = &instr->src[2];
1089
1090 /* These were lowered to a move, so apply the corresponding mod */
1091
1092 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1093 nir_alu_src *s = nirmods[quirk_flipped_r24];
1094
1095 if (instr->op == nir_op_fneg)
1096 s->negate = !s->negate;
1097
1098 if (instr->op == nir_op_fabs)
1099 s->abs = !s->abs;
1100 }
1101
1102 bool is_int = midgard_is_integer_op(op);
1103
1104 ins.mask = mask_of(nr_components);
1105
1106 midgard_vector_alu alu = {
1107 .op = op,
1108 .reg_mode = reg_mode,
1109 .dest_override = dest_override,
1110 .outmod = outmod,
1111
1112 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)),
1113 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)),
1114 };
1115
1116 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1117
1118 if (!is_ssa)
1119 ins.mask &= instr->dest.write_mask;
1120
1121 for (unsigned m = 0; m < 3; ++m) {
1122 if (!nirmods[m])
1123 continue;
1124
1125 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c)
1126 ins.swizzle[m][c] = nirmods[m]->swizzle[c];
1127
1128 /* Replicate. TODO: remove when vec16 lands */
1129 for (unsigned c = NIR_MAX_VEC_COMPONENTS; c < MIR_VEC_COMPONENTS; ++c)
1130 ins.swizzle[m][c] = nirmods[m]->swizzle[NIR_MAX_VEC_COMPONENTS - 1];
1131 }
1132
1133 if (nr_inputs == 3) {
1134 /* Conditions can't have mods */
1135 assert(!nirmods[2]->abs);
1136 assert(!nirmods[2]->negate);
1137 }
1138
1139 ins.alu = alu;
1140
1141 /* Late fixup for emulated instructions */
1142
1143 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1144 /* Presently, our second argument is an inline #0 constant.
1145 * Switch over to an embedded 1.0 constant (that can't fit
1146 * inline, since we're 32-bit, not 16-bit like the inline
1147 * constants) */
1148
1149 ins.has_inline_constant = false;
1150 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1151 ins.has_constants = true;
1152
1153 if (instr->op == nir_op_b2f32)
1154 ins.constants.f32[0] = 1.0f;
1155 else
1156 ins.constants.i32[0] = 1;
1157
1158 for (unsigned c = 0; c < 16; ++c)
1159 ins.swizzle[1][c] = 0;
1160 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1161 /* Lots of instructions need a 0 plonked in */
1162 ins.has_inline_constant = false;
1163 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1164 ins.has_constants = true;
1165 ins.constants.u32[0] = 0;
1166
1167 for (unsigned c = 0; c < 16; ++c)
1168 ins.swizzle[1][c] = 0;
1169 } else if (instr->op == nir_op_inot) {
1170 ins.invert = true;
1171 }
1172
1173 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1174 /* To avoid duplicating the lookup tables (probably), true LUT
1175 * instructions can only operate as if they were scalars. Lower
1176 * them here by changing the component. */
1177
1178 unsigned orig_mask = ins.mask;
1179
1180 for (int i = 0; i < nr_components; ++i) {
1181 /* Mask the associated component, dropping the
1182 * instruction if needed */
1183
1184 ins.mask = 1 << i;
1185 ins.mask &= orig_mask;
1186
1187 if (!ins.mask)
1188 continue;
1189
1190 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1191 ins.swizzle[0][j] = nirmods[0]->swizzle[i]; /* Pull from the correct component */
1192
1193 emit_mir_instruction(ctx, ins);
1194 }
1195 } else {
1196 emit_mir_instruction(ctx, ins);
1197 }
1198 }
1199
1200 #undef ALU_CASE
1201
1202 static void
1203 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1204 {
1205 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1206 unsigned nir_mask = 0;
1207 unsigned dsize = 0;
1208
1209 if (is_read) {
1210 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1211 dsize = nir_dest_bit_size(intr->dest);
1212 } else {
1213 nir_mask = nir_intrinsic_write_mask(intr);
1214 dsize = 32;
1215 }
1216
1217 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1218 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1219 mir_set_bytemask(ins, bytemask);
1220
1221 if (dsize == 64)
1222 ins->load_64 = true;
1223 }
1224
1225 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1226 * optimized) versions of UBO #0 */
1227
1228 static midgard_instruction *
1229 emit_ubo_read(
1230 compiler_context *ctx,
1231 nir_instr *instr,
1232 unsigned dest,
1233 unsigned offset,
1234 nir_src *indirect_offset,
1235 unsigned indirect_shift,
1236 unsigned index)
1237 {
1238 /* TODO: half-floats */
1239
1240 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1241 ins.constants.u32[0] = offset;
1242
1243 if (instr->type == nir_instr_type_intrinsic)
1244 mir_set_intr_mask(instr, &ins, true);
1245
1246 if (indirect_offset) {
1247 ins.src[2] = nir_src_index(ctx, indirect_offset);
1248 ins.load_store.arg_2 = (indirect_shift << 5);
1249 } else {
1250 ins.load_store.arg_2 = 0x1E;
1251 }
1252
1253 ins.load_store.arg_1 = index;
1254
1255 return emit_mir_instruction(ctx, ins);
1256 }
1257
1258 /* Globals are like UBOs if you squint. And shared memory is like globals if
1259 * you squint even harder */
1260
1261 static void
1262 emit_global(
1263 compiler_context *ctx,
1264 nir_instr *instr,
1265 bool is_read,
1266 unsigned srcdest,
1267 nir_src *offset,
1268 bool is_shared)
1269 {
1270 /* TODO: types */
1271
1272 midgard_instruction ins;
1273
1274 if (is_read)
1275 ins = m_ld_int4(srcdest, 0);
1276 else
1277 ins = m_st_int4(srcdest, 0);
1278
1279 mir_set_offset(ctx, &ins, offset, is_shared);
1280 mir_set_intr_mask(instr, &ins, is_read);
1281
1282 emit_mir_instruction(ctx, ins);
1283 }
1284
1285 static void
1286 emit_varying_read(
1287 compiler_context *ctx,
1288 unsigned dest, unsigned offset,
1289 unsigned nr_comp, unsigned component,
1290 nir_src *indirect_offset, nir_alu_type type, bool flat)
1291 {
1292 /* XXX: Half-floats? */
1293 /* TODO: swizzle, mask */
1294
1295 midgard_instruction ins = m_ld_vary_32(dest, offset);
1296 ins.mask = mask_of(nr_comp);
1297
1298 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1299 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1300
1301 midgard_varying_parameter p = {
1302 .is_varying = 1,
1303 .interpolation = midgard_interp_default,
1304 .flat = flat,
1305 };
1306
1307 unsigned u;
1308 memcpy(&u, &p, sizeof(p));
1309 ins.load_store.varying_parameters = u;
1310
1311 if (indirect_offset)
1312 ins.src[2] = nir_src_index(ctx, indirect_offset);
1313 else
1314 ins.load_store.arg_2 = 0x1E;
1315
1316 ins.load_store.arg_1 = 0x9E;
1317
1318 /* Use the type appropriate load */
1319 switch (type) {
1320 case nir_type_uint:
1321 case nir_type_bool:
1322 ins.load_store.op = midgard_op_ld_vary_32u;
1323 break;
1324 case nir_type_int:
1325 ins.load_store.op = midgard_op_ld_vary_32i;
1326 break;
1327 case nir_type_float:
1328 ins.load_store.op = midgard_op_ld_vary_32;
1329 break;
1330 default:
1331 unreachable("Attempted to load unknown type");
1332 break;
1333 }
1334
1335 emit_mir_instruction(ctx, ins);
1336 }
1337
1338 static void
1339 emit_attr_read(
1340 compiler_context *ctx,
1341 unsigned dest, unsigned offset,
1342 unsigned nr_comp, nir_alu_type t)
1343 {
1344 midgard_instruction ins = m_ld_attr_32(dest, offset);
1345 ins.load_store.arg_1 = 0x1E;
1346 ins.load_store.arg_2 = 0x1E;
1347 ins.mask = mask_of(nr_comp);
1348
1349 /* Use the type appropriate load */
1350 switch (t) {
1351 case nir_type_uint:
1352 case nir_type_bool:
1353 ins.load_store.op = midgard_op_ld_attr_32u;
1354 break;
1355 case nir_type_int:
1356 ins.load_store.op = midgard_op_ld_attr_32i;
1357 break;
1358 case nir_type_float:
1359 ins.load_store.op = midgard_op_ld_attr_32;
1360 break;
1361 default:
1362 unreachable("Attempted to load unknown type");
1363 break;
1364 }
1365
1366 emit_mir_instruction(ctx, ins);
1367 }
1368
1369 static void
1370 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1371 unsigned nr_components, unsigned offset)
1372 {
1373 nir_dest nir_dest;
1374
1375 /* Figure out which uniform this is */
1376 int sysval = sysval_for_instr(instr, &nir_dest);
1377 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1378
1379 unsigned dest = nir_dest_index(&nir_dest);
1380
1381 /* Sysvals are prefix uniforms */
1382 unsigned uniform = ((uintptr_t) val) - 1;
1383
1384 /* Emit the read itself -- this is never indirect */
1385 midgard_instruction *ins =
1386 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1387
1388 ins->mask = mask_of(nr_components);
1389 }
1390
1391 static unsigned
1392 compute_builtin_arg(nir_op op)
1393 {
1394 switch (op) {
1395 case nir_intrinsic_load_work_group_id:
1396 return 0x14;
1397 case nir_intrinsic_load_local_invocation_id:
1398 return 0x10;
1399 default:
1400 unreachable("Invalid compute paramater loaded");
1401 }
1402 }
1403
1404 static void
1405 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1406 {
1407 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1408
1409 midgard_instruction *br = ctx->writeout_branch[rt];
1410
1411 assert(!br);
1412
1413 emit_explicit_constant(ctx, src, src);
1414
1415 struct midgard_instruction ins =
1416 v_branch(false, false);
1417
1418 ins.writeout = true;
1419
1420 /* Add dependencies */
1421 ins.src[0] = src;
1422 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1423 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1424
1425 /* Emit the branch */
1426 br = emit_mir_instruction(ctx, ins);
1427 schedule_barrier(ctx);
1428 ctx->writeout_branch[rt] = br;
1429
1430 /* Push our current location = current block count - 1 = where we'll
1431 * jump to. Maybe a bit too clever for my own good */
1432
1433 br->branch.target_block = ctx->block_count - 1;
1434 }
1435
1436 static void
1437 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1438 {
1439 unsigned reg = nir_dest_index(&instr->dest);
1440 midgard_instruction ins = m_ld_compute_id(reg, 0);
1441 ins.mask = mask_of(3);
1442 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1443 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1444 emit_mir_instruction(ctx, ins);
1445 }
1446
1447 static unsigned
1448 vertex_builtin_arg(nir_op op)
1449 {
1450 switch (op) {
1451 case nir_intrinsic_load_vertex_id:
1452 return PAN_VERTEX_ID;
1453 case nir_intrinsic_load_instance_id:
1454 return PAN_INSTANCE_ID;
1455 default:
1456 unreachable("Invalid vertex builtin");
1457 }
1458 }
1459
1460 static void
1461 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1462 {
1463 unsigned reg = nir_dest_index(&instr->dest);
1464 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1465 }
1466
1467 static void
1468 emit_control_barrier(compiler_context *ctx)
1469 {
1470 midgard_instruction ins = {
1471 .type = TAG_TEXTURE_4,
1472 .src = { ~0, ~0, ~0, ~0 },
1473 .texture = {
1474 .op = TEXTURE_OP_BARRIER,
1475
1476 /* TODO: optimize */
1477 .barrier_buffer = 1,
1478 .barrier_shared = 1
1479 }
1480 };
1481
1482 emit_mir_instruction(ctx, ins);
1483 }
1484
1485 static const nir_variable *
1486 search_var(struct exec_list *vars, unsigned driver_loc)
1487 {
1488 nir_foreach_variable(var, vars) {
1489 if (var->data.driver_location == driver_loc)
1490 return var;
1491 }
1492
1493 return NULL;
1494 }
1495
1496 static void
1497 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1498 {
1499 unsigned offset = 0, reg;
1500
1501 switch (instr->intrinsic) {
1502 case nir_intrinsic_discard_if:
1503 case nir_intrinsic_discard: {
1504 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1505 struct midgard_instruction discard = v_branch(conditional, false);
1506 discard.branch.target_type = TARGET_DISCARD;
1507
1508 if (conditional)
1509 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1510
1511 emit_mir_instruction(ctx, discard);
1512 schedule_barrier(ctx);
1513
1514 break;
1515 }
1516
1517 case nir_intrinsic_load_uniform:
1518 case nir_intrinsic_load_ubo:
1519 case nir_intrinsic_load_global:
1520 case nir_intrinsic_load_shared:
1521 case nir_intrinsic_load_input:
1522 case nir_intrinsic_load_interpolated_input: {
1523 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1524 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1525 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1526 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1527 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1528 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1529
1530 /* Get the base type of the intrinsic */
1531 /* TODO: Infer type? Does it matter? */
1532 nir_alu_type t =
1533 (is_ubo || is_global || is_shared) ? nir_type_uint :
1534 (is_interp) ? nir_type_float :
1535 nir_intrinsic_type(instr);
1536
1537 t = nir_alu_type_get_base_type(t);
1538
1539 if (!(is_ubo || is_global)) {
1540 offset = nir_intrinsic_base(instr);
1541 }
1542
1543 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1544
1545 nir_src *src_offset = nir_get_io_offset_src(instr);
1546
1547 bool direct = nir_src_is_const(*src_offset);
1548 nir_src *indirect_offset = direct ? NULL : src_offset;
1549
1550 if (direct)
1551 offset += nir_src_as_uint(*src_offset);
1552
1553 /* We may need to apply a fractional offset */
1554 int component = (is_flat || is_interp) ?
1555 nir_intrinsic_component(instr) : 0;
1556 reg = nir_dest_index(&instr->dest);
1557
1558 if (is_uniform && !ctx->is_blend) {
1559 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1560 } else if (is_ubo) {
1561 nir_src index = instr->src[0];
1562
1563 /* TODO: Is indirect block number possible? */
1564 assert(nir_src_is_const(index));
1565
1566 uint32_t uindex = nir_src_as_uint(index) + 1;
1567 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1568 } else if (is_global || is_shared) {
1569 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1570 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1571 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1572 } else if (ctx->is_blend) {
1573 /* For blend shaders, load the input color, which is
1574 * preloaded to r0 */
1575
1576 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1577 emit_mir_instruction(ctx, move);
1578 schedule_barrier(ctx);
1579 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1580 emit_attr_read(ctx, reg, offset, nr_comp, t);
1581 } else {
1582 DBG("Unknown load\n");
1583 assert(0);
1584 }
1585
1586 break;
1587 }
1588
1589 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1590 case nir_intrinsic_load_barycentric_pixel:
1591 case nir_intrinsic_load_barycentric_centroid:
1592 break;
1593
1594 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1595
1596 case nir_intrinsic_load_raw_output_pan:
1597 case nir_intrinsic_load_output_u8_as_fp16_pan:
1598 reg = nir_dest_index(&instr->dest);
1599 assert(ctx->is_blend);
1600
1601 /* T720 and below use different blend opcodes with slightly
1602 * different semantics than T760 and up */
1603
1604 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1605 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1606
1607 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1608 ld.load_store.op = old_blend ?
1609 midgard_op_ld_color_buffer_u8_as_fp16_old :
1610 midgard_op_ld_color_buffer_u8_as_fp16;
1611
1612 if (old_blend) {
1613 ld.load_store.address = 1;
1614 ld.load_store.arg_2 = 0x1E;
1615 }
1616
1617 for (unsigned c = 2; c < 16; ++c)
1618 ld.swizzle[0][c] = 0;
1619 }
1620
1621 emit_mir_instruction(ctx, ld);
1622 break;
1623
1624 case nir_intrinsic_load_blend_const_color_rgba: {
1625 assert(ctx->is_blend);
1626 reg = nir_dest_index(&instr->dest);
1627
1628 /* Blend constants are embedded directly in the shader and
1629 * patched in, so we use some magic routing */
1630
1631 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1632 ins.has_constants = true;
1633 ins.has_blend_constant = true;
1634 emit_mir_instruction(ctx, ins);
1635 break;
1636 }
1637
1638 case nir_intrinsic_store_zs_output_pan: {
1639 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1640 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1641 MIDGARD_ZS_RT);
1642
1643 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1644
1645 if (!nir_intrinsic_component(instr))
1646 br->writeout_depth = true;
1647 if (nir_intrinsic_component(instr) ||
1648 instr->num_components)
1649 br->writeout_stencil = true;
1650 assert(br->writeout_depth | br->writeout_stencil);
1651 break;
1652 }
1653
1654 case nir_intrinsic_store_output:
1655 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1656
1657 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1658
1659 reg = nir_src_index(ctx, &instr->src[0]);
1660
1661 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1662 const nir_variable *var;
1663 enum midgard_rt_id rt;
1664
1665 var = search_var(&ctx->nir->outputs,
1666 nir_intrinsic_base(instr));
1667 assert(var);
1668 if (var->data.location == FRAG_RESULT_COLOR)
1669 rt = MIDGARD_COLOR_RT0;
1670 else if (var->data.location >= FRAG_RESULT_DATA0)
1671 rt = MIDGARD_COLOR_RT0 + var->data.location -
1672 FRAG_RESULT_DATA0;
1673 else
1674 assert(0);
1675
1676 emit_fragment_store(ctx, reg, rt);
1677 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1678 /* We should have been vectorized, though we don't
1679 * currently check that st_vary is emitted only once
1680 * per slot (this is relevant, since there's not a mask
1681 * parameter available on the store [set to 0 by the
1682 * blob]). We do respect the component by adjusting the
1683 * swizzle. If this is a constant source, we'll need to
1684 * emit that explicitly. */
1685
1686 emit_explicit_constant(ctx, reg, reg);
1687
1688 unsigned dst_component = nir_intrinsic_component(instr);
1689 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1690
1691 midgard_instruction st = m_st_vary_32(reg, offset);
1692 st.load_store.arg_1 = 0x9E;
1693 st.load_store.arg_2 = 0x1E;
1694
1695 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1696 case nir_type_uint:
1697 case nir_type_bool:
1698 st.load_store.op = midgard_op_st_vary_32u;
1699 break;
1700 case nir_type_int:
1701 st.load_store.op = midgard_op_st_vary_32i;
1702 break;
1703 case nir_type_float:
1704 st.load_store.op = midgard_op_st_vary_32;
1705 break;
1706 default:
1707 unreachable("Attempted to store unknown type");
1708 break;
1709 }
1710
1711 /* nir_intrinsic_component(store_intr) encodes the
1712 * destination component start. Source component offset
1713 * adjustment is taken care of in
1714 * install_registers_instr(), when offset_swizzle() is
1715 * called.
1716 */
1717 unsigned src_component = COMPONENT_X;
1718
1719 assert(nr_comp > 0);
1720 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1721 st.swizzle[0][i] = src_component;
1722 if (i >= dst_component && i < dst_component + nr_comp - 1)
1723 src_component++;
1724 }
1725
1726 emit_mir_instruction(ctx, st);
1727 } else {
1728 DBG("Unknown store\n");
1729 assert(0);
1730 }
1731
1732 break;
1733
1734 /* Special case of store_output for lowered blend shaders */
1735 case nir_intrinsic_store_raw_output_pan:
1736 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1737 reg = nir_src_index(ctx, &instr->src[0]);
1738
1739 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1740 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1741 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1742 * of:
1743 *
1744 * imov r0.xyzw, r0.xxxx
1745 */
1746
1747 unsigned expanded = make_compiler_temp(ctx);
1748
1749 midgard_instruction splatter = v_mov(reg, expanded);
1750
1751 for (unsigned c = 0; c < 16; ++c)
1752 splatter.swizzle[1][c] = 0;
1753
1754 emit_mir_instruction(ctx, splatter);
1755 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1756 } else
1757 emit_fragment_store(ctx, reg, ctx->blend_rt);
1758
1759 break;
1760
1761 case nir_intrinsic_store_global:
1762 case nir_intrinsic_store_shared:
1763 reg = nir_src_index(ctx, &instr->src[0]);
1764 emit_explicit_constant(ctx, reg, reg);
1765
1766 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1767 break;
1768
1769 case nir_intrinsic_load_ssbo_address:
1770 emit_sysval_read(ctx, &instr->instr, 1, 0);
1771 break;
1772
1773 case nir_intrinsic_get_buffer_size:
1774 emit_sysval_read(ctx, &instr->instr, 1, 8);
1775 break;
1776
1777 case nir_intrinsic_load_viewport_scale:
1778 case nir_intrinsic_load_viewport_offset:
1779 case nir_intrinsic_load_num_work_groups:
1780 case nir_intrinsic_load_sampler_lod_parameters_pan:
1781 emit_sysval_read(ctx, &instr->instr, 3, 0);
1782 break;
1783
1784 case nir_intrinsic_load_work_group_id:
1785 case nir_intrinsic_load_local_invocation_id:
1786 emit_compute_builtin(ctx, instr);
1787 break;
1788
1789 case nir_intrinsic_load_vertex_id:
1790 case nir_intrinsic_load_instance_id:
1791 emit_vertex_builtin(ctx, instr);
1792 break;
1793
1794 case nir_intrinsic_memory_barrier_buffer:
1795 case nir_intrinsic_memory_barrier_shared:
1796 break;
1797
1798 case nir_intrinsic_control_barrier:
1799 schedule_barrier(ctx);
1800 emit_control_barrier(ctx);
1801 schedule_barrier(ctx);
1802 break;
1803
1804 default:
1805 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1806 assert(0);
1807 break;
1808 }
1809 }
1810
1811 static unsigned
1812 midgard_tex_format(enum glsl_sampler_dim dim)
1813 {
1814 switch (dim) {
1815 case GLSL_SAMPLER_DIM_1D:
1816 case GLSL_SAMPLER_DIM_BUF:
1817 return MALI_TEX_1D;
1818
1819 case GLSL_SAMPLER_DIM_2D:
1820 case GLSL_SAMPLER_DIM_EXTERNAL:
1821 case GLSL_SAMPLER_DIM_RECT:
1822 return MALI_TEX_2D;
1823
1824 case GLSL_SAMPLER_DIM_3D:
1825 return MALI_TEX_3D;
1826
1827 case GLSL_SAMPLER_DIM_CUBE:
1828 return MALI_TEX_CUBE;
1829
1830 default:
1831 DBG("Unknown sampler dim type\n");
1832 assert(0);
1833 return 0;
1834 }
1835 }
1836
1837 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1838 * was successful */
1839
1840 static bool
1841 pan_attach_constant_bias(
1842 compiler_context *ctx,
1843 nir_src lod,
1844 midgard_texture_word *word)
1845 {
1846 /* To attach as constant, it has to *be* constant */
1847
1848 if (!nir_src_is_const(lod))
1849 return false;
1850
1851 float f = nir_src_as_float(lod);
1852
1853 /* Break into fixed-point */
1854 signed lod_int = f;
1855 float lod_frac = f - lod_int;
1856
1857 /* Carry over negative fractions */
1858 if (lod_frac < 0.0) {
1859 lod_int--;
1860 lod_frac += 1.0;
1861 }
1862
1863 /* Encode */
1864 word->bias = float_to_ubyte(lod_frac);
1865 word->bias_int = lod_int;
1866
1867 return true;
1868 }
1869
1870 static enum mali_sampler_type
1871 midgard_sampler_type(nir_alu_type t) {
1872 switch (nir_alu_type_get_base_type(t))
1873 {
1874 case nir_type_float:
1875 return MALI_SAMPLER_FLOAT;
1876 case nir_type_int:
1877 return MALI_SAMPLER_SIGNED;
1878 case nir_type_uint:
1879 return MALI_SAMPLER_UNSIGNED;
1880 default:
1881 unreachable("Unknown sampler type");
1882 }
1883 }
1884
1885 static void
1886 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1887 unsigned midgard_texop)
1888 {
1889 /* TODO */
1890 //assert (!instr->sampler);
1891
1892 int texture_index = instr->texture_index;
1893 int sampler_index = texture_index;
1894
1895 /* No helper to build texture words -- we do it all here */
1896 midgard_instruction ins = {
1897 .type = TAG_TEXTURE_4,
1898 .mask = 0xF,
1899 .dest = nir_dest_index(&instr->dest),
1900 .src = { ~0, ~0, ~0, ~0 },
1901 .swizzle = SWIZZLE_IDENTITY_4,
1902 .texture = {
1903 .op = midgard_texop,
1904 .format = midgard_tex_format(instr->sampler_dim),
1905 .texture_handle = texture_index,
1906 .sampler_handle = sampler_index,
1907
1908 /* TODO: half */
1909 .in_reg_full = 1,
1910 .out_full = 1,
1911
1912 .sampler_type = midgard_sampler_type(instr->dest_type),
1913 .shadow = instr->is_shadow,
1914 }
1915 };
1916
1917 /* We may need a temporary for the coordinate */
1918
1919 bool needs_temp_coord =
1920 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1921 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1922 (instr->is_shadow);
1923
1924 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1925
1926 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1927 int index = nir_src_index(ctx, &instr->src[i].src);
1928 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1929
1930 switch (instr->src[i].src_type) {
1931 case nir_tex_src_coord: {
1932 emit_explicit_constant(ctx, index, index);
1933
1934 unsigned coord_mask = mask_of(instr->coord_components);
1935
1936 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1937
1938 if (flip_zw)
1939 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1940
1941 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1942 /* texelFetch is undefined on samplerCube */
1943 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1944
1945 /* For cubemaps, we use a special ld/st op to
1946 * select the face and copy the xy into the
1947 * texture register */
1948
1949 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1950 ld.src[1] = index;
1951 ld.mask = 0x3; /* xy */
1952 ld.load_store.arg_1 = 0x20;
1953 ld.swizzle[1][3] = COMPONENT_X;
1954 emit_mir_instruction(ctx, ld);
1955
1956 /* xyzw -> xyxx */
1957 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1958 ins.swizzle[1][3] = COMPONENT_X;
1959 } else if (needs_temp_coord) {
1960 /* mov coord_temp, coords */
1961 midgard_instruction mov = v_mov(index, coords);
1962 mov.mask = coord_mask;
1963
1964 if (flip_zw)
1965 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1966
1967 emit_mir_instruction(ctx, mov);
1968 } else {
1969 coords = index;
1970 }
1971
1972 ins.src[1] = coords;
1973
1974 /* Texelfetch coordinates uses all four elements
1975 * (xyz/index) regardless of texture dimensionality,
1976 * which means it's necessary to zero the unused
1977 * components to keep everything happy */
1978
1979 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1980 /* mov index.zw, #0, or generalized */
1981 midgard_instruction mov =
1982 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1983 mov.has_constants = true;
1984 mov.mask = coord_mask ^ 0xF;
1985 emit_mir_instruction(ctx, mov);
1986 }
1987
1988 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1989 /* Array component in w but NIR wants it in z,
1990 * but if we have a temp coord we already fixed
1991 * that up */
1992
1993 if (nr_components == 3) {
1994 ins.swizzle[1][2] = COMPONENT_Z;
1995 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1996 } else if (nr_components == 2) {
1997 ins.swizzle[1][2] =
1998 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1999 ins.swizzle[1][3] = COMPONENT_X;
2000 } else
2001 unreachable("Invalid texture 2D components");
2002 }
2003
2004 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
2005 /* We zeroed */
2006 ins.swizzle[1][2] = COMPONENT_Z;
2007 ins.swizzle[1][3] = COMPONENT_W;
2008 }
2009
2010 break;
2011 }
2012
2013 case nir_tex_src_bias:
2014 case nir_tex_src_lod: {
2015 /* Try as a constant if we can */
2016
2017 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
2018 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
2019 break;
2020
2021 ins.texture.lod_register = true;
2022 ins.src[2] = index;
2023
2024 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2025 ins.swizzle[2][c] = COMPONENT_X;
2026
2027 emit_explicit_constant(ctx, index, index);
2028
2029 break;
2030 };
2031
2032 case nir_tex_src_offset: {
2033 ins.texture.offset_register = true;
2034 ins.src[3] = index;
2035
2036 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2037 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
2038
2039 emit_explicit_constant(ctx, index, index);
2040 break;
2041 };
2042
2043 case nir_tex_src_comparator: {
2044 unsigned comp = COMPONENT_Z;
2045
2046 /* mov coord_temp.foo, coords */
2047 midgard_instruction mov = v_mov(index, coords);
2048 mov.mask = 1 << comp;
2049
2050 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
2051 mov.swizzle[1][i] = COMPONENT_X;
2052
2053 emit_mir_instruction(ctx, mov);
2054 break;
2055 }
2056
2057 default: {
2058 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
2059 assert(0);
2060 }
2061 }
2062 }
2063
2064 emit_mir_instruction(ctx, ins);
2065
2066 /* Used for .cont and .last hinting */
2067 ctx->texture_op_count++;
2068 }
2069
2070 static void
2071 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2072 {
2073 switch (instr->op) {
2074 case nir_texop_tex:
2075 case nir_texop_txb:
2076 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2077 break;
2078 case nir_texop_txl:
2079 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2080 break;
2081 case nir_texop_txf:
2082 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2083 break;
2084 case nir_texop_txs:
2085 emit_sysval_read(ctx, &instr->instr, 4, 0);
2086 break;
2087 default: {
2088 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2089 assert(0);
2090 }
2091 }
2092 }
2093
2094 static void
2095 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2096 {
2097 switch (instr->type) {
2098 case nir_jump_break: {
2099 /* Emit a branch out of the loop */
2100 struct midgard_instruction br = v_branch(false, false);
2101 br.branch.target_type = TARGET_BREAK;
2102 br.branch.target_break = ctx->current_loop_depth;
2103 emit_mir_instruction(ctx, br);
2104 break;
2105 }
2106
2107 default:
2108 DBG("Unknown jump type %d\n", instr->type);
2109 break;
2110 }
2111 }
2112
2113 static void
2114 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2115 {
2116 switch (instr->type) {
2117 case nir_instr_type_load_const:
2118 emit_load_const(ctx, nir_instr_as_load_const(instr));
2119 break;
2120
2121 case nir_instr_type_intrinsic:
2122 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2123 break;
2124
2125 case nir_instr_type_alu:
2126 emit_alu(ctx, nir_instr_as_alu(instr));
2127 break;
2128
2129 case nir_instr_type_tex:
2130 emit_tex(ctx, nir_instr_as_tex(instr));
2131 break;
2132
2133 case nir_instr_type_jump:
2134 emit_jump(ctx, nir_instr_as_jump(instr));
2135 break;
2136
2137 case nir_instr_type_ssa_undef:
2138 /* Spurious */
2139 break;
2140
2141 default:
2142 DBG("Unhandled instruction type\n");
2143 break;
2144 }
2145 }
2146
2147
2148 /* ALU instructions can inline or embed constants, which decreases register
2149 * pressure and saves space. */
2150
2151 #define CONDITIONAL_ATTACH(idx) { \
2152 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2153 \
2154 if (entry) { \
2155 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2156 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2157 } \
2158 }
2159
2160 static void
2161 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2162 {
2163 mir_foreach_instr_in_block(block, alu) {
2164 /* Other instructions cannot inline constants */
2165 if (alu->type != TAG_ALU_4) continue;
2166 if (alu->compact_branch) continue;
2167
2168 /* If there is already a constant here, we can do nothing */
2169 if (alu->has_constants) continue;
2170
2171 CONDITIONAL_ATTACH(0);
2172
2173 if (!alu->has_constants) {
2174 CONDITIONAL_ATTACH(1)
2175 } else if (!alu->inline_constant) {
2176 /* Corner case: _two_ vec4 constants, for instance with a
2177 * csel. For this case, we can only use a constant
2178 * register for one, we'll have to emit a move for the
2179 * other. Note, if both arguments are constants, then
2180 * necessarily neither argument depends on the value of
2181 * any particular register. As the destination register
2182 * will be wiped, that means we can spill the constant
2183 * to the destination register.
2184 */
2185
2186 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2187 unsigned scratch = alu->dest;
2188
2189 if (entry) {
2190 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2191 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2192
2193 /* Set the source */
2194 alu->src[1] = scratch;
2195
2196 /* Inject us -before- the last instruction which set r31 */
2197 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2198 }
2199 }
2200 }
2201 }
2202
2203 /* Being a little silly with the names, but returns the op that is the bitwise
2204 * inverse of the op with the argument switched. I.e. (f and g are
2205 * contrapositives):
2206 *
2207 * f(a, b) = ~g(b, a)
2208 *
2209 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
2210 *
2211 * f(a, b) = ~g(b, a)
2212 * ~f(a, b) = g(b, a)
2213 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
2214 * f(a, b) = h(a, b)
2215 *
2216 * Thus we define this function in pairs.
2217 */
2218
2219 static inline midgard_alu_op
2220 mir_contrapositive(midgard_alu_op op)
2221 {
2222 switch (op) {
2223 case midgard_alu_op_flt:
2224 return midgard_alu_op_fle;
2225 case midgard_alu_op_fle:
2226 return midgard_alu_op_flt;
2227
2228 case midgard_alu_op_ilt:
2229 return midgard_alu_op_ile;
2230 case midgard_alu_op_ile:
2231 return midgard_alu_op_ilt;
2232
2233 default:
2234 unreachable("No known contrapositive");
2235 }
2236 }
2237
2238 /* Midgard supports two types of constants, embedded constants (128-bit) and
2239 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2240 * constants can be demoted to inline constants, for space savings and
2241 * sometimes a performance boost */
2242
2243 static void
2244 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2245 {
2246 mir_foreach_instr_in_block(block, ins) {
2247 if (!ins->has_constants) continue;
2248 if (ins->has_inline_constant) continue;
2249
2250 /* Blend constants must not be inlined by definition */
2251 if (ins->has_blend_constant) continue;
2252
2253 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2254 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2255 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2256
2257 if (!(is_16 || is_32))
2258 continue;
2259
2260 /* src1 cannot be an inline constant due to encoding
2261 * restrictions. So, if possible we try to flip the arguments
2262 * in that case */
2263
2264 int op = ins->alu.op;
2265
2266 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2267 bool flip = alu_opcode_props[op].props & OP_COMMUTES;
2268
2269 switch (op) {
2270 /* Conditionals can be inverted */
2271 case midgard_alu_op_flt:
2272 case midgard_alu_op_ilt:
2273 case midgard_alu_op_fle:
2274 case midgard_alu_op_ile:
2275 ins->alu.op = mir_contrapositive(ins->alu.op);
2276 ins->invert = true;
2277 flip = true;
2278 break;
2279
2280 case midgard_alu_op_fcsel:
2281 case midgard_alu_op_icsel:
2282 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
2283 default:
2284 break;
2285 }
2286
2287 if (flip)
2288 mir_flip(ins);
2289 }
2290
2291 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2292 /* Extract the source information */
2293
2294 midgard_vector_alu_src *src;
2295 int q = ins->alu.src2;
2296 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2297 src = m;
2298
2299 /* Component is from the swizzle. Take a nonzero component */
2300 assert(ins->mask);
2301 unsigned first_comp = ffs(ins->mask) - 1;
2302 unsigned component = ins->swizzle[1][first_comp];
2303
2304 /* Scale constant appropriately, if we can legally */
2305 uint16_t scaled_constant = 0;
2306
2307 if (is_16) {
2308 scaled_constant = ins->constants.u16[component];
2309 } else if (midgard_is_integer_op(op)) {
2310 scaled_constant = ins->constants.u32[component];
2311
2312 /* Constant overflow after resize */
2313 if (scaled_constant != ins->constants.u32[component])
2314 continue;
2315 } else {
2316 float original = ins->constants.f32[component];
2317 scaled_constant = _mesa_float_to_half(original);
2318
2319 /* Check for loss of precision. If this is
2320 * mediump, we don't care, but for a highp
2321 * shader, we need to pay attention. NIR
2322 * doesn't yet tell us which mode we're in!
2323 * Practically this prevents most constants
2324 * from being inlined, sadly. */
2325
2326 float fp32 = _mesa_half_to_float(scaled_constant);
2327
2328 if (fp32 != original)
2329 continue;
2330 }
2331
2332 /* We don't know how to handle these with a constant */
2333
2334 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2335 DBG("Bailing inline constant...\n");
2336 continue;
2337 }
2338
2339 /* Make sure that the constant is not itself a vector
2340 * by checking if all accessed values are the same. */
2341
2342 const midgard_constants *cons = &ins->constants;
2343 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2344
2345 bool is_vector = false;
2346 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2347
2348 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2349 /* We only care if this component is actually used */
2350 if (!(mask & (1 << c)))
2351 continue;
2352
2353 uint32_t test = is_16 ?
2354 cons->u16[ins->swizzle[1][c]] :
2355 cons->u32[ins->swizzle[1][c]];
2356
2357 if (test != value) {
2358 is_vector = true;
2359 break;
2360 }
2361 }
2362
2363 if (is_vector)
2364 continue;
2365
2366 /* Get rid of the embedded constant */
2367 ins->has_constants = false;
2368 ins->src[1] = ~0;
2369 ins->has_inline_constant = true;
2370 ins->inline_constant = scaled_constant;
2371 }
2372 }
2373 }
2374
2375 /* Dead code elimination for branches at the end of a block - only one branch
2376 * per block is legal semantically */
2377
2378 static void
2379 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2380 {
2381 bool branched = false;
2382
2383 mir_foreach_instr_in_block_safe(block, ins) {
2384 if (!midgard_is_branch_unit(ins->unit)) continue;
2385
2386 if (branched)
2387 mir_remove_instruction(ins);
2388
2389 branched = true;
2390 }
2391 }
2392
2393 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2394 * the move can be propagated away entirely */
2395
2396 static bool
2397 mir_compose_float_outmod(midgard_outmod_float *outmod, midgard_outmod_float comp)
2398 {
2399 /* Nothing to do */
2400 if (comp == midgard_outmod_none)
2401 return true;
2402
2403 if (*outmod == midgard_outmod_none) {
2404 *outmod = comp;
2405 return true;
2406 }
2407
2408 /* TODO: Compose rules */
2409 return false;
2410 }
2411
2412 static bool
2413 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
2414 {
2415 bool progress = false;
2416
2417 mir_foreach_instr_in_block_safe(block, ins) {
2418 if (ins->type != TAG_ALU_4) continue;
2419 if (ins->alu.op != midgard_alu_op_fmov) continue;
2420 if (ins->alu.outmod != midgard_outmod_pos) continue;
2421
2422 /* TODO: Registers? */
2423 unsigned src = ins->src[1];
2424 if (src & IS_REG) continue;
2425
2426 /* There might be a source modifier, too */
2427 if (mir_nontrivial_source2_mod(ins)) continue;
2428
2429 /* Backpropagate the modifier */
2430 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
2431 if (v->type != TAG_ALU_4) continue;
2432 if (v->dest != src) continue;
2433
2434 /* Can we even take a float outmod? */
2435 if (midgard_is_integer_out_op(v->alu.op)) continue;
2436
2437 midgard_outmod_float temp = v->alu.outmod;
2438 progress |= mir_compose_float_outmod(&temp, ins->alu.outmod);
2439
2440 /* Throw in the towel.. */
2441 if (!progress) break;
2442
2443 /* Otherwise, transfer the modifier */
2444 v->alu.outmod = temp;
2445 ins->alu.outmod = midgard_outmod_none;
2446
2447 break;
2448 }
2449 }
2450
2451 return progress;
2452 }
2453
2454 static unsigned
2455 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2456 {
2457 /* Loop to ourselves */
2458 midgard_instruction *br = ctx->writeout_branch[rt];
2459 struct midgard_instruction ins = v_branch(false, false);
2460 ins.writeout = true;
2461 ins.writeout_depth = br->writeout_depth;
2462 ins.writeout_stencil = br->writeout_stencil;
2463 ins.branch.target_block = ctx->block_count - 1;
2464 ins.constants.u32[0] = br->constants.u32[0];
2465 emit_mir_instruction(ctx, ins);
2466
2467 ctx->current_block->epilogue = true;
2468 schedule_barrier(ctx);
2469 return ins.branch.target_block;
2470 }
2471
2472 static midgard_block *
2473 emit_block(compiler_context *ctx, nir_block *block)
2474 {
2475 midgard_block *this_block = ctx->after_block;
2476 ctx->after_block = NULL;
2477
2478 if (!this_block)
2479 this_block = create_empty_block(ctx);
2480
2481 list_addtail(&this_block->link, &ctx->blocks);
2482
2483 this_block->is_scheduled = false;
2484 ++ctx->block_count;
2485
2486 /* Set up current block */
2487 list_inithead(&this_block->instructions);
2488 ctx->current_block = this_block;
2489
2490 nir_foreach_instr(instr, block) {
2491 emit_instr(ctx, instr);
2492 ++ctx->instruction_count;
2493 }
2494
2495 return this_block;
2496 }
2497
2498 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2499
2500 static void
2501 emit_if(struct compiler_context *ctx, nir_if *nif)
2502 {
2503 midgard_block *before_block = ctx->current_block;
2504
2505 /* Speculatively emit the branch, but we can't fill it in until later */
2506 EMIT(branch, true, true);
2507 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2508 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2509
2510 /* Emit the two subblocks. */
2511 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2512 midgard_block *end_then_block = ctx->current_block;
2513
2514 /* Emit a jump from the end of the then block to the end of the else */
2515 EMIT(branch, false, false);
2516 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2517
2518 /* Emit second block, and check if it's empty */
2519
2520 int else_idx = ctx->block_count;
2521 int count_in = ctx->instruction_count;
2522 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2523 midgard_block *end_else_block = ctx->current_block;
2524 int after_else_idx = ctx->block_count;
2525
2526 /* Now that we have the subblocks emitted, fix up the branches */
2527
2528 assert(then_block);
2529 assert(else_block);
2530
2531 if (ctx->instruction_count == count_in) {
2532 /* The else block is empty, so don't emit an exit jump */
2533 mir_remove_instruction(then_exit);
2534 then_branch->branch.target_block = after_else_idx;
2535 } else {
2536 then_branch->branch.target_block = else_idx;
2537 then_exit->branch.target_block = after_else_idx;
2538 }
2539
2540 /* Wire up the successors */
2541
2542 ctx->after_block = create_empty_block(ctx);
2543
2544 midgard_block_add_successor(before_block, then_block);
2545 midgard_block_add_successor(before_block, else_block);
2546
2547 midgard_block_add_successor(end_then_block, ctx->after_block);
2548 midgard_block_add_successor(end_else_block, ctx->after_block);
2549 }
2550
2551 static void
2552 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2553 {
2554 /* Remember where we are */
2555 midgard_block *start_block = ctx->current_block;
2556
2557 /* Allocate a loop number, growing the current inner loop depth */
2558 int loop_idx = ++ctx->current_loop_depth;
2559
2560 /* Get index from before the body so we can loop back later */
2561 int start_idx = ctx->block_count;
2562
2563 /* Emit the body itself */
2564 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2565
2566 /* Branch back to loop back */
2567 struct midgard_instruction br_back = v_branch(false, false);
2568 br_back.branch.target_block = start_idx;
2569 emit_mir_instruction(ctx, br_back);
2570
2571 /* Mark down that branch in the graph. */
2572 midgard_block_add_successor(start_block, loop_block);
2573 midgard_block_add_successor(ctx->current_block, loop_block);
2574
2575 /* Find the index of the block about to follow us (note: we don't add
2576 * one; blocks are 0-indexed so we get a fencepost problem) */
2577 int break_block_idx = ctx->block_count;
2578
2579 /* Fix up the break statements we emitted to point to the right place,
2580 * now that we can allocate a block number for them */
2581 ctx->after_block = create_empty_block(ctx);
2582
2583 list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
2584 mir_foreach_instr_in_block(block, ins) {
2585 if (ins->type != TAG_ALU_4) continue;
2586 if (!ins->compact_branch) continue;
2587
2588 /* We found a branch -- check the type to see if we need to do anything */
2589 if (ins->branch.target_type != TARGET_BREAK) continue;
2590
2591 /* It's a break! Check if it's our break */
2592 if (ins->branch.target_break != loop_idx) continue;
2593
2594 /* Okay, cool, we're breaking out of this loop.
2595 * Rewrite from a break to a goto */
2596
2597 ins->branch.target_type = TARGET_GOTO;
2598 ins->branch.target_block = break_block_idx;
2599
2600 midgard_block_add_successor(block, ctx->after_block);
2601 }
2602 }
2603
2604 /* Now that we've finished emitting the loop, free up the depth again
2605 * so we play nice with recursion amid nested loops */
2606 --ctx->current_loop_depth;
2607
2608 /* Dump loop stats */
2609 ++ctx->loop_count;
2610 }
2611
2612 static midgard_block *
2613 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2614 {
2615 midgard_block *start_block = NULL;
2616
2617 foreach_list_typed(nir_cf_node, node, node, list) {
2618 switch (node->type) {
2619 case nir_cf_node_block: {
2620 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2621
2622 if (!start_block)
2623 start_block = block;
2624
2625 break;
2626 }
2627
2628 case nir_cf_node_if:
2629 emit_if(ctx, nir_cf_node_as_if(node));
2630 break;
2631
2632 case nir_cf_node_loop:
2633 emit_loop(ctx, nir_cf_node_as_loop(node));
2634 break;
2635
2636 case nir_cf_node_function:
2637 assert(0);
2638 break;
2639 }
2640 }
2641
2642 return start_block;
2643 }
2644
2645 /* Due to lookahead, we need to report the first tag executed in the command
2646 * stream and in branch targets. An initial block might be empty, so iterate
2647 * until we find one that 'works' */
2648
2649 static unsigned
2650 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2651 {
2652 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2653
2654 mir_foreach_block_from(ctx, initial_block, v) {
2655 if (v->quadword_count) {
2656 midgard_bundle *initial_bundle =
2657 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2658
2659 return initial_bundle->tag;
2660 }
2661 }
2662
2663 /* Default to a tag 1 which will break from the shader, in case we jump
2664 * to the exit block (i.e. `return` in a compute shader) */
2665
2666 return 1;
2667 }
2668
2669 static unsigned
2670 pan_format_from_nir_base(nir_alu_type base)
2671 {
2672 switch (base) {
2673 case nir_type_int:
2674 return MALI_FORMAT_SINT;
2675 case nir_type_uint:
2676 case nir_type_bool:
2677 return MALI_FORMAT_UINT;
2678 case nir_type_float:
2679 return MALI_CHANNEL_FLOAT;
2680 default:
2681 unreachable("Invalid base");
2682 }
2683 }
2684
2685 static unsigned
2686 pan_format_from_nir_size(nir_alu_type base, unsigned size)
2687 {
2688 if (base == nir_type_float) {
2689 switch (size) {
2690 case 16: return MALI_FORMAT_SINT;
2691 case 32: return MALI_FORMAT_UNORM;
2692 default:
2693 unreachable("Invalid float size for format");
2694 }
2695 } else {
2696 switch (size) {
2697 case 1:
2698 case 8: return MALI_CHANNEL_8;
2699 case 16: return MALI_CHANNEL_16;
2700 case 32: return MALI_CHANNEL_32;
2701 default:
2702 unreachable("Invalid int size for format");
2703 }
2704 }
2705 }
2706
2707 static enum mali_format
2708 pan_format_from_glsl(const struct glsl_type *type)
2709 {
2710 enum glsl_base_type glsl_base = glsl_get_base_type(glsl_without_array(type));
2711 nir_alu_type t = nir_get_nir_type_for_glsl_base_type(glsl_base);
2712
2713 unsigned base = nir_alu_type_get_base_type(t);
2714 unsigned size = nir_alu_type_get_type_size(t);
2715
2716 return pan_format_from_nir_base(base) |
2717 pan_format_from_nir_size(base, size) |
2718 MALI_NR_CHANNELS(4);
2719 }
2720
2721 /* For each fragment writeout instruction, generate a writeout loop to
2722 * associate with it */
2723
2724 static void
2725 mir_add_writeout_loops(compiler_context *ctx)
2726 {
2727 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2728 midgard_instruction *br = ctx->writeout_branch[rt];
2729 if (!br) continue;
2730
2731 unsigned popped = br->branch.target_block;
2732 midgard_block_add_successor(mir_get_block(ctx, popped - 1), ctx->current_block);
2733 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2734
2735 /* If we have more RTs, we'll need to restore back after our
2736 * loop terminates */
2737
2738 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2739 midgard_instruction uncond = v_branch(false, false);
2740 uncond.branch.target_block = popped;
2741 emit_mir_instruction(ctx, uncond);
2742 midgard_block_add_successor(ctx->current_block, mir_get_block(ctx, popped));
2743 schedule_barrier(ctx);
2744 } else {
2745 /* We're last, so we can terminate here */
2746 br->last_writeout = true;
2747 }
2748 }
2749 }
2750
2751 int
2752 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2753 {
2754 struct util_dynarray *compiled = &program->compiled;
2755
2756 midgard_debug = debug_get_option_midgard_debug();
2757
2758 /* TODO: Bound against what? */
2759 compiler_context *ctx = rzalloc(NULL, compiler_context);
2760
2761 ctx->nir = nir;
2762 ctx->stage = nir->info.stage;
2763 ctx->is_blend = is_blend;
2764 ctx->alpha_ref = program->alpha_ref;
2765 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2766 ctx->quirks = midgard_get_quirks(gpu_id);
2767
2768 /* Start off with a safe cutoff, allowing usage of all 16 work
2769 * registers. Later, we'll promote uniform reads to uniform registers
2770 * if we determine it is beneficial to do so */
2771 ctx->uniform_cutoff = 8;
2772
2773 /* Initialize at a global (not block) level hash tables */
2774
2775 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2776 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2777
2778 /* Record the varying mapping for the command stream's bookkeeping */
2779
2780 struct exec_list *varyings =
2781 ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs;
2782
2783 unsigned max_varying = 0;
2784 nir_foreach_variable(var, varyings) {
2785 unsigned loc = var->data.driver_location;
2786 unsigned sz = glsl_type_size(var->type, FALSE);
2787
2788 for (int c = 0; c < sz; ++c) {
2789 program->varyings[loc + c] = var->data.location + c;
2790 program->varying_type[loc + c] = pan_format_from_glsl(var->type);
2791 max_varying = MAX2(max_varying, loc + c);
2792 }
2793 }
2794
2795 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2796 * (so we don't accidentally duplicate the epilogue since mesa/st has
2797 * messed with our I/O quite a bit already) */
2798
2799 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2800
2801 if (ctx->stage == MESA_SHADER_VERTEX) {
2802 NIR_PASS_V(nir, nir_lower_viewport_transform);
2803 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2804 }
2805
2806 NIR_PASS_V(nir, nir_lower_var_copies);
2807 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2808 NIR_PASS_V(nir, nir_split_var_copies);
2809 NIR_PASS_V(nir, nir_lower_var_copies);
2810 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2811 NIR_PASS_V(nir, nir_lower_var_copies);
2812 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2813
2814 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2815 NIR_PASS_V(nir, nir_lower_ssbo);
2816 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2817
2818 /* Optimisation passes */
2819
2820 optimise_nir(nir, ctx->quirks);
2821
2822 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2823 nir_print_shader(nir, stdout);
2824 }
2825
2826 /* Assign sysvals and counts, now that we're sure
2827 * (post-optimisation) */
2828
2829 midgard_nir_assign_sysvals(&ctx->sysvals, nir);
2830
2831 program->uniform_count = nir->num_uniforms;
2832 program->sysval_count = ctx->sysvals.sysval_count;
2833 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2834
2835 nir_foreach_function(func, nir) {
2836 if (!func->impl)
2837 continue;
2838
2839 list_inithead(&ctx->blocks);
2840 ctx->block_count = 0;
2841 ctx->func = func;
2842
2843 emit_cf_list(ctx, &func->impl->body);
2844 break; /* TODO: Multi-function shaders */
2845 }
2846
2847 util_dynarray_init(compiled, NULL);
2848
2849 /* Per-block lowering before opts */
2850
2851 mir_foreach_block(ctx, block) {
2852 inline_alu_constants(ctx, block);
2853 midgard_opt_promote_fmov(ctx, block);
2854 embedded_to_inline_constant(ctx, block);
2855 }
2856 /* MIR-level optimizations */
2857
2858 bool progress = false;
2859
2860 do {
2861 progress = false;
2862
2863 mir_foreach_block(ctx, block) {
2864 progress |= midgard_opt_pos_propagate(ctx, block);
2865 progress |= midgard_opt_copy_prop(ctx, block);
2866 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2867 progress |= midgard_opt_combine_projection(ctx, block);
2868 progress |= midgard_opt_varying_projection(ctx, block);
2869 progress |= midgard_opt_not_propagate(ctx, block);
2870 progress |= midgard_opt_fuse_src_invert(ctx, block);
2871 progress |= midgard_opt_fuse_dest_invert(ctx, block);
2872 progress |= midgard_opt_csel_invert(ctx, block);
2873 progress |= midgard_opt_drop_cmp_invert(ctx, block);
2874 progress |= midgard_opt_invert_branch(ctx, block);
2875 }
2876 } while (progress);
2877
2878 mir_foreach_block(ctx, block) {
2879 midgard_lower_invert(ctx, block);
2880 midgard_lower_derivatives(ctx, block);
2881 }
2882
2883 /* Nested control-flow can result in dead branches at the end of the
2884 * block. This messes with our analysis and is just dead code, so cull
2885 * them */
2886 mir_foreach_block(ctx, block) {
2887 midgard_opt_cull_dead_branch(ctx, block);
2888 }
2889
2890 /* Ensure we were lowered */
2891 mir_foreach_instr_global(ctx, ins) {
2892 assert(!ins->invert);
2893 }
2894
2895 if (ctx->stage == MESA_SHADER_FRAGMENT)
2896 mir_add_writeout_loops(ctx);
2897
2898 /* Schedule! */
2899 midgard_schedule_program(ctx);
2900 mir_ra(ctx);
2901
2902 /* Now that all the bundles are scheduled and we can calculate block
2903 * sizes, emit actual branch instructions rather than placeholders */
2904
2905 int br_block_idx = 0;
2906
2907 mir_foreach_block(ctx, block) {
2908 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2909 for (int c = 0; c < bundle->instruction_count; ++c) {
2910 midgard_instruction *ins = bundle->instructions[c];
2911
2912 if (!midgard_is_branch_unit(ins->unit)) continue;
2913
2914 /* Parse some basic branch info */
2915 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2916 bool is_conditional = ins->branch.conditional;
2917 bool is_inverted = ins->branch.invert_conditional;
2918 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2919 bool is_writeout = ins->writeout;
2920
2921 /* Determine the block we're jumping to */
2922 int target_number = ins->branch.target_block;
2923
2924 /* Report the destination tag */
2925 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2926
2927 /* Count up the number of quadwords we're
2928 * jumping over = number of quadwords until
2929 * (br_block_idx, target_number) */
2930
2931 int quadword_offset = 0;
2932
2933 if (is_discard) {
2934 /* Ignored */
2935 } else if (target_number > br_block_idx) {
2936 /* Jump forward */
2937
2938 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2939 midgard_block *blk = mir_get_block(ctx, idx);
2940 assert(blk);
2941
2942 quadword_offset += blk->quadword_count;
2943 }
2944 } else {
2945 /* Jump backwards */
2946
2947 for (int idx = br_block_idx; idx >= target_number; --idx) {
2948 midgard_block *blk = mir_get_block(ctx, idx);
2949 assert(blk);
2950
2951 quadword_offset -= blk->quadword_count;
2952 }
2953 }
2954
2955 /* Unconditional extended branches (far jumps)
2956 * have issues, so we always use a conditional
2957 * branch, setting the condition to always for
2958 * unconditional. For compact unconditional
2959 * branches, cond isn't used so it doesn't
2960 * matter what we pick. */
2961
2962 midgard_condition cond =
2963 !is_conditional ? midgard_condition_always :
2964 is_inverted ? midgard_condition_false :
2965 midgard_condition_true;
2966
2967 midgard_jmp_writeout_op op =
2968 is_discard ? midgard_jmp_writeout_op_discard :
2969 is_writeout ? midgard_jmp_writeout_op_writeout :
2970 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2971 midgard_jmp_writeout_op_branch_cond;
2972
2973 if (!is_compact) {
2974 midgard_branch_extended branch =
2975 midgard_create_branch_extended(
2976 cond, op,
2977 dest_tag,
2978 quadword_offset);
2979
2980 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2981 } else if (is_conditional || is_discard) {
2982 midgard_branch_cond branch = {
2983 .op = op,
2984 .dest_tag = dest_tag,
2985 .offset = quadword_offset,
2986 .cond = cond
2987 };
2988
2989 assert(branch.offset == quadword_offset);
2990
2991 memcpy(&ins->br_compact, &branch, sizeof(branch));
2992 } else {
2993 assert(op == midgard_jmp_writeout_op_branch_uncond);
2994
2995 midgard_branch_uncond branch = {
2996 .op = op,
2997 .dest_tag = dest_tag,
2998 .offset = quadword_offset,
2999 .unknown = 1
3000 };
3001
3002 assert(branch.offset == quadword_offset);
3003
3004 memcpy(&ins->br_compact, &branch, sizeof(branch));
3005 }
3006 }
3007 }
3008
3009 ++br_block_idx;
3010 }
3011
3012 /* Emit flat binary from the instruction arrays. Iterate each block in
3013 * sequence. Save instruction boundaries such that lookahead tags can
3014 * be assigned easily */
3015
3016 /* Cache _all_ bundles in source order for lookahead across failed branches */
3017
3018 int bundle_count = 0;
3019 mir_foreach_block(ctx, block) {
3020 bundle_count += block->bundles.size / sizeof(midgard_bundle);
3021 }
3022 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
3023 int bundle_idx = 0;
3024 mir_foreach_block(ctx, block) {
3025 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
3026 source_order_bundles[bundle_idx++] = bundle;
3027 }
3028 }
3029
3030 int current_bundle = 0;
3031
3032 /* Midgard prefetches instruction types, so during emission we
3033 * need to lookahead. Unless this is the last instruction, in
3034 * which we return 1. */
3035
3036 mir_foreach_block(ctx, block) {
3037 mir_foreach_bundle_in_block(block, bundle) {
3038 int lookahead = 1;
3039
3040 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
3041 lookahead = source_order_bundles[current_bundle + 1]->tag;
3042
3043 emit_binary_bundle(ctx, bundle, compiled, lookahead);
3044 ++current_bundle;
3045 }
3046
3047 /* TODO: Free deeper */
3048 //util_dynarray_fini(&block->instructions);
3049 }
3050
3051 free(source_order_bundles);
3052
3053 /* Report the very first tag executed */
3054 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
3055
3056 /* Deal with off-by-one related to the fencepost problem */
3057 program->work_register_count = ctx->work_registers + 1;
3058 program->uniform_cutoff = ctx->uniform_cutoff;
3059
3060 program->blend_patch_offset = ctx->blend_constant_offset;
3061 program->tls_size = ctx->tls_size;
3062
3063 if (midgard_debug & MIDGARD_DBG_SHADERS)
3064 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
3065
3066 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
3067 unsigned nr_bundles = 0, nr_ins = 0;
3068
3069 /* Count instructions and bundles */
3070
3071 mir_foreach_block(ctx, block) {
3072 nr_bundles += util_dynarray_num_elements(
3073 &block->bundles, midgard_bundle);
3074
3075 mir_foreach_bundle_in_block(block, bun)
3076 nr_ins += bun->instruction_count;
3077 }
3078
3079 /* Calculate thread count. There are certain cutoffs by
3080 * register count for thread count */
3081
3082 unsigned nr_registers = program->work_register_count;
3083
3084 unsigned nr_threads =
3085 (nr_registers <= 4) ? 4 :
3086 (nr_registers <= 8) ? 2 :
3087 1;
3088
3089 /* Dump stats */
3090
3091 fprintf(stderr, "shader%d - %s shader: "
3092 "%u inst, %u bundles, %u quadwords, "
3093 "%u registers, %u threads, %u loops, "
3094 "%u:%u spills:fills\n",
3095 SHADER_DB_COUNT++,
3096 gl_shader_stage_name(ctx->stage),
3097 nr_ins, nr_bundles, ctx->quadword_count,
3098 nr_registers, nr_threads,
3099 ctx->loop_count,
3100 ctx->spills, ctx->fills);
3101 }
3102
3103 ralloc_free(ctx);
3104
3105 return 0;
3106 }