2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
63 unsigned SHADER_DB_COUNT
= 0;
65 int midgard_debug
= 0;
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 midgard_is_branch_unit(unsigned unit
)
75 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
78 static midgard_block
*
79 create_empty_block(compiler_context
*ctx
)
81 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
83 blk
->predecessors
= _mesa_set_create(blk
,
85 _mesa_key_pointer_equal
);
87 blk
->source_id
= ctx
->block_source_count
++;
93 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
99 for (unsigned i
= 0; i
< block
->nr_successors
; ++i
) {
100 if (block
->successors
[i
] == successor
)
104 block
->successors
[block
->nr_successors
++] = successor
;
105 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
107 /* Note the predecessor in the other direction */
108 _mesa_set_add(successor
->predecessors
, block
);
112 schedule_barrier(compiler_context
*ctx
)
114 midgard_block
*temp
= ctx
->after_block
;
115 ctx
->after_block
= create_empty_block(ctx
);
117 list_addtail(&ctx
->after_block
->link
, &ctx
->blocks
);
118 list_inithead(&ctx
->after_block
->instructions
);
119 midgard_block_add_successor(ctx
->current_block
, ctx
->after_block
);
120 ctx
->current_block
= ctx
->after_block
;
121 ctx
->after_block
= temp
;
124 /* Helpers to generate midgard_instruction's using macro magic, since every
125 * driver seems to do it that way */
127 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
129 #define M_LOAD_STORE(name, store) \
130 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
131 midgard_instruction i = { \
132 .type = TAG_LOAD_STORE_4, \
135 .src = { ~0, ~0, ~0 }, \
137 .op = midgard_op_##name, \
138 .swizzle = SWIZZLE_XYZW, \
151 #define M_LOAD(name) M_LOAD_STORE(name, false)
152 #define M_STORE(name) M_LOAD_STORE(name, true)
154 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
155 * the corresponding Midgard source */
157 static midgard_vector_alu_src
158 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
159 bool half
, bool sext
)
161 if (!src
) return blank_alu_src
;
163 /* Figure out how many components there are so we can adjust the
164 * swizzle. Specifically we want to broadcast the last channel so
165 * things like ball2/3 work
168 if (broadcast_count
) {
169 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
171 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
172 src
->swizzle
[c
] = last_component
;
176 midgard_vector_alu_src alu_src
= {
180 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
184 alu_src
.mod
= midgard_int_normal
;
186 /* Sign/zero-extend if needed */
190 midgard_int_sign_extend
191 : midgard_int_zero_extend
;
194 /* These should have been lowered away */
195 assert(!(src
->abs
|| src
->negate
));
197 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
203 /* load/store instructions have both 32-bit and 16-bit variants, depending on
204 * whether we are using vectors composed of highp or mediump. At the moment, we
205 * don't support half-floats -- this requires changes in other parts of the
206 * compiler -- therefore the 16-bit versions are commented out. */
208 //M_LOAD(ld_attr_16);
210 //M_LOAD(ld_vary_16);
215 M_LOAD(ld_color_buffer_8
);
216 //M_STORE(st_vary_16);
218 M_LOAD(ld_cubemap_coords
);
219 M_LOAD(ld_compute_id
);
221 static midgard_instruction
222 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
224 midgard_branch_cond branch
= {
232 memcpy(&compact
, &branch
, sizeof(branch
));
234 midgard_instruction ins
= {
236 .unit
= ALU_ENAB_BR_COMPACT
,
237 .prepacked_branch
= true,
238 .compact_branch
= true,
239 .br_compact
= compact
,
241 .src
= { ~0, ~0, ~0 },
244 if (op
== midgard_jmp_writeout_op_writeout
)
250 static midgard_instruction
251 v_branch(bool conditional
, bool invert
)
253 midgard_instruction ins
= {
255 .unit
= ALU_ENAB_BRANCH
,
256 .compact_branch
= true,
258 .conditional
= conditional
,
259 .invert_conditional
= invert
262 .src
= { ~0, ~0, ~0 },
268 static midgard_branch_extended
269 midgard_create_branch_extended( midgard_condition cond
,
270 midgard_jmp_writeout_op op
,
272 signed quadword_offset
)
274 /* The condition code is actually a LUT describing a function to
275 * combine multiple condition codes. However, we only support a single
276 * condition code at the moment, so we just duplicate over a bunch of
279 uint16_t duplicated_cond
=
289 midgard_branch_extended branch
= {
291 .dest_tag
= dest_tag
,
292 .offset
= quadword_offset
,
293 .cond
= duplicated_cond
300 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
302 ins
->has_constants
= true;
303 memcpy(&ins
->constants
, constants
, 16);
307 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
309 return glsl_count_attribute_slots(type
, false);
312 /* Lower fdot2 to a vector multiplication followed by channel addition */
314 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
316 if (alu
->op
!= nir_op_fdot2
)
319 b
->cursor
= nir_before_instr(&alu
->instr
);
321 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
322 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
324 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
326 nir_ssa_def
*sum
= nir_fadd(b
,
327 nir_channel(b
, product
, 0),
328 nir_channel(b
, product
, 1));
330 /* Replace the fdot2 with this sum */
331 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
335 midgard_sysval_for_ssbo(nir_intrinsic_instr
*instr
)
337 /* This is way too meta */
338 bool is_store
= instr
->intrinsic
== nir_intrinsic_store_ssbo
;
339 unsigned idx_idx
= is_store
? 1 : 0;
341 nir_src index
= instr
->src
[idx_idx
];
342 assert(nir_src_is_const(index
));
343 uint32_t uindex
= nir_src_as_uint(index
);
345 return PAN_SYSVAL(SSBO
, uindex
);
349 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
351 switch (instr
->intrinsic
) {
352 case nir_intrinsic_load_viewport_scale
:
353 return PAN_SYSVAL_VIEWPORT_SCALE
;
354 case nir_intrinsic_load_viewport_offset
:
355 return PAN_SYSVAL_VIEWPORT_OFFSET
;
356 case nir_intrinsic_load_num_work_groups
:
357 return PAN_SYSVAL_NUM_WORK_GROUPS
;
358 case nir_intrinsic_load_ssbo
:
359 case nir_intrinsic_store_ssbo
:
360 return midgard_sysval_for_ssbo(instr
);
366 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
369 nir_intrinsic_instr
*intr
;
370 nir_dest
*dst
= NULL
;
374 bool is_store
= false;
376 switch (instr
->type
) {
377 case nir_instr_type_intrinsic
:
378 intr
= nir_instr_as_intrinsic(instr
);
379 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
381 is_store
|= intr
->intrinsic
== nir_intrinsic_store_ssbo
;
383 case nir_instr_type_tex
:
384 tex
= nir_instr_as_tex(instr
);
385 if (tex
->op
!= nir_texop_txs
)
388 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
389 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
390 nir_tex_instr_dest_size(tex
) -
391 (tex
->is_array
? 1 : 0),
399 if (dest
&& dst
&& !is_store
)
400 *dest
= nir_dest_index(ctx
, dst
);
406 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
410 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
414 /* We have a sysval load; check if it's already been assigned */
416 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
419 /* It hasn't -- so assign it now! */
421 unsigned id
= ctx
->sysval_count
++;
422 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
423 ctx
->sysvals
[id
] = sysval
;
427 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
429 ctx
->sysval_count
= 0;
431 nir_foreach_function(function
, shader
) {
432 if (!function
->impl
) continue;
434 nir_foreach_block(block
, function
->impl
) {
435 nir_foreach_instr_safe(instr
, block
) {
436 midgard_nir_assign_sysval_body(ctx
, instr
);
443 midgard_nir_lower_fdot2(nir_shader
*shader
)
445 bool progress
= false;
447 nir_foreach_function(function
, shader
) {
448 if (!function
->impl
) continue;
451 nir_builder
*b
= &_b
;
452 nir_builder_init(b
, function
->impl
);
454 nir_foreach_block(block
, function
->impl
) {
455 nir_foreach_instr_safe(instr
, block
) {
456 if (instr
->type
!= nir_instr_type_alu
) continue;
458 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
459 midgard_nir_lower_fdot2_body(b
, alu
);
465 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
472 /* Flushes undefined values to zero */
475 optimise_nir(nir_shader
*nir
)
478 unsigned lower_flrp
=
479 (nir
->options
->lower_flrp16
? 16 : 0) |
480 (nir
->options
->lower_flrp32
? 32 : 0) |
481 (nir
->options
->lower_flrp64
? 64 : 0);
483 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
484 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
485 NIR_PASS(progress
, nir
, nir_lower_idiv
);
487 nir_lower_tex_options lower_tex_options
= {
488 .lower_txs_lod
= true,
492 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
497 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
498 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
500 NIR_PASS(progress
, nir
, nir_copy_prop
);
501 NIR_PASS(progress
, nir
, nir_opt_dce
);
502 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
503 NIR_PASS(progress
, nir
, nir_opt_cse
);
504 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
505 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
506 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
508 if (lower_flrp
!= 0) {
509 bool lower_flrp_progress
= false;
510 NIR_PASS(lower_flrp_progress
,
514 false /* always_precise */,
515 nir
->options
->lower_ffma
);
516 if (lower_flrp_progress
) {
517 NIR_PASS(progress
, nir
,
518 nir_opt_constant_folding
);
522 /* Nothing should rematerialize any flrps, so we only
523 * need to do this lowering once.
528 NIR_PASS(progress
, nir
, nir_opt_undef
);
529 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
531 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
534 nir_var_function_temp
);
536 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
539 /* Must be run at the end to prevent creation of fsin/fcos ops */
540 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
545 NIR_PASS(progress
, nir
, nir_opt_dce
);
546 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
547 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
548 NIR_PASS(progress
, nir
, nir_copy_prop
);
551 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
553 /* We implement booleans as 32-bit 0/~0 */
554 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
556 /* Now that booleans are lowered, we can run out late opts */
557 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
559 /* Lower mods for float ops only. Integer ops don't support modifiers
560 * (saturate doesn't make sense on integers, neg/abs require dedicated
563 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
564 NIR_PASS(progress
, nir
, nir_copy_prop
);
565 NIR_PASS(progress
, nir
, nir_opt_dce
);
567 /* Take us out of SSA */
568 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
569 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
571 /* We are a vector architecture; write combine where possible */
572 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
573 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
575 NIR_PASS(progress
, nir
, nir_opt_dce
);
578 /* Do not actually emit a load; instead, cache the constant for inlining */
581 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
583 nir_ssa_def def
= instr
->def
;
585 float *v
= rzalloc_array(NULL
, float, 4);
586 nir_const_value_to_array(v
, instr
->value
, instr
->def
.num_components
, f32
);
588 /* Shifted for SSA, +1 for off-by-one */
589 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, v
);
592 /* Normally constants are embedded implicitly, but for I/O and such we have to
593 * explicitly emit a move with the constant source */
596 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
598 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
600 if (constant_value
) {
601 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, to
);
602 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
603 emit_mir_instruction(ctx
, ins
);
608 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
610 unsigned comp
= src
->swizzle
[0];
612 for (unsigned c
= 1; c
< nr_components
; ++c
) {
613 if (src
->swizzle
[c
] != comp
)
620 #define ALU_CASE(nir, _op) \
622 op = midgard_alu_op_##_op; \
623 assert(src_bitsize == dst_bitsize); \
626 #define ALU_CASE_BCAST(nir, _op, count) \
628 op = midgard_alu_op_##_op; \
629 broadcast_swizzle = count; \
630 assert(src_bitsize == dst_bitsize); \
633 nir_is_fzero_constant(nir_src src
)
635 if (!nir_src_is_const(src
))
638 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
639 if (nir_src_comp_as_float(src
, c
) != 0.0)
646 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
647 * special treatment override this anyway. */
649 static midgard_reg_mode
650 reg_mode_for_nir(nir_alu_instr
*instr
)
652 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
654 switch (src_bitsize
) {
656 return midgard_reg_mode_8
;
658 return midgard_reg_mode_16
;
660 return midgard_reg_mode_32
;
662 return midgard_reg_mode_64
;
664 unreachable("Invalid bit size");
669 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
671 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
672 * is handled elsewhere */
674 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
675 midgard_emit_derivatives(ctx
, instr
);
679 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
681 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
682 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
683 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
685 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
686 * supported. A few do not and are commented for now. Also, there are a
687 * number of NIR ops which Midgard does not support and need to be
688 * lowered, also TODO. This switch block emits the opcode and calling
689 * convention of the Midgard instruction; actual packing is done in
694 /* Number of components valid to check for the instruction (the rest
695 * will be forced to the last), or 0 to use as-is. Relevant as
696 * ball-type instructions have a channel count in NIR but are all vec4
699 unsigned broadcast_swizzle
= 0;
701 /* What register mode should we operate in? */
702 midgard_reg_mode reg_mode
=
703 reg_mode_for_nir(instr
);
705 /* Do we need a destination override? Used for inline
708 midgard_dest_override dest_override
=
709 midgard_dest_override_none
;
711 /* Should we use a smaller respective source and sign-extend? */
713 bool half_1
= false, sext_1
= false;
714 bool half_2
= false, sext_2
= false;
716 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
717 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
720 ALU_CASE(fadd
, fadd
);
721 ALU_CASE(fmul
, fmul
);
722 ALU_CASE(fmin
, fmin
);
723 ALU_CASE(fmax
, fmax
);
724 ALU_CASE(imin
, imin
);
725 ALU_CASE(imax
, imax
);
726 ALU_CASE(umin
, umin
);
727 ALU_CASE(umax
, umax
);
728 ALU_CASE(ffloor
, ffloor
);
729 ALU_CASE(fround_even
, froundeven
);
730 ALU_CASE(ftrunc
, ftrunc
);
731 ALU_CASE(fceil
, fceil
);
732 ALU_CASE(fdot3
, fdot3
);
733 ALU_CASE(fdot4
, fdot4
);
734 ALU_CASE(iadd
, iadd
);
735 ALU_CASE(isub
, isub
);
736 ALU_CASE(imul
, imul
);
738 /* Zero shoved as second-arg */
739 ALU_CASE(iabs
, iabsdiff
);
743 ALU_CASE(feq32
, feq
);
744 ALU_CASE(fne32
, fne
);
745 ALU_CASE(flt32
, flt
);
746 ALU_CASE(ieq32
, ieq
);
747 ALU_CASE(ine32
, ine
);
748 ALU_CASE(ilt32
, ilt
);
749 ALU_CASE(ult32
, ult
);
751 /* We don't have a native b2f32 instruction. Instead, like many
752 * GPUs, we exploit booleans as 0/~0 for false/true, and
753 * correspondingly AND
754 * by 1.0 to do the type conversion. For the moment, prime us
757 * iand [whatever], #0
759 * At the end of emit_alu (as MIR), we'll fix-up the constant
762 ALU_CASE(b2f32
, iand
);
763 ALU_CASE(b2i32
, iand
);
765 /* Likewise, we don't have a dedicated f2b32 instruction, but
766 * we can do a "not equal to 0.0" test. */
768 ALU_CASE(f2b32
, fne
);
769 ALU_CASE(i2b32
, ine
);
771 ALU_CASE(frcp
, frcp
);
772 ALU_CASE(frsq
, frsqrt
);
773 ALU_CASE(fsqrt
, fsqrt
);
774 ALU_CASE(fexp2
, fexp2
);
775 ALU_CASE(flog2
, flog2
);
777 ALU_CASE(f2i32
, f2i_rtz
);
778 ALU_CASE(f2u32
, f2u_rtz
);
779 ALU_CASE(i2f32
, i2f_rtz
);
780 ALU_CASE(u2f32
, u2f_rtz
);
782 ALU_CASE(f2i16
, f2i_rtz
);
783 ALU_CASE(f2u16
, f2u_rtz
);
784 ALU_CASE(i2f16
, i2f_rtz
);
785 ALU_CASE(u2f16
, u2f_rtz
);
787 ALU_CASE(fsin
, fsin
);
788 ALU_CASE(fcos
, fcos
);
790 /* We'll set invert */
791 ALU_CASE(inot
, imov
);
792 ALU_CASE(iand
, iand
);
794 ALU_CASE(ixor
, ixor
);
795 ALU_CASE(ishl
, ishl
);
796 ALU_CASE(ishr
, iasr
);
797 ALU_CASE(ushr
, ilsr
);
799 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
800 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
801 ALU_CASE(b32all_fequal4
, fball_eq
);
803 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
804 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
805 ALU_CASE(b32any_fnequal4
, fbany_neq
);
807 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
808 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
809 ALU_CASE(b32all_iequal4
, iball_eq
);
811 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
812 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
813 ALU_CASE(b32any_inequal4
, ibany_neq
);
815 /* Source mods will be shoved in later */
816 ALU_CASE(fabs
, fmov
);
817 ALU_CASE(fneg
, fmov
);
818 ALU_CASE(fsat
, fmov
);
820 /* For size conversion, we use a move. Ideally though we would squash
821 * these ops together; maybe that has to happen after in NIR as part of
822 * propagation...? An earlier algebraic pass ensured we step down by
823 * only / exactly one size. If stepping down, we use a dest override to
824 * reduce the size; if stepping up, we use a larger-sized move with a
825 * half source and a sign/zero-extension modifier */
830 /* If we end up upscale, we'll need a sign-extend on the
831 * operand (the second argument) */
838 op
= midgard_alu_op_imov
;
840 if (dst_bitsize
== (src_bitsize
* 2)) {
844 /* Use a greater register mode */
846 } else if (src_bitsize
== (dst_bitsize
* 2)) {
847 /* Converting down */
848 dest_override
= midgard_dest_override_lower
;
855 assert(src_bitsize
== 32);
857 op
= midgard_alu_op_fmov
;
858 dest_override
= midgard_dest_override_lower
;
863 assert(src_bitsize
== 16);
865 op
= midgard_alu_op_fmov
;
872 /* For greater-or-equal, we lower to less-or-equal and flip the
880 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
881 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
882 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
883 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
886 /* Swap via temporary */
887 nir_alu_src temp
= instr
->src
[1];
888 instr
->src
[1] = instr
->src
[0];
889 instr
->src
[0] = temp
;
894 case nir_op_b32csel
: {
895 /* Midgard features both fcsel and icsel, depending on
896 * the type of the arguments/output. However, as long
897 * as we're careful we can _always_ use icsel and
898 * _never_ need fcsel, since the latter does additional
899 * floating-point-specific processing whereas the
900 * former just moves bits on the wire. It's not obvious
901 * why these are separate opcodes, save for the ability
902 * to do things like sat/pos/abs/neg for free */
904 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
905 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
907 /* The condition is the first argument; move the other
908 * arguments up one to be a binary instruction for
909 * Midgard with the condition last */
911 nir_alu_src temp
= instr
->src
[2];
913 instr
->src
[2] = instr
->src
[0];
914 instr
->src
[0] = instr
->src
[1];
915 instr
->src
[1] = temp
;
921 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
926 /* Midgard can perform certain modifiers on output of an ALU op */
929 if (midgard_is_integer_out_op(op
)) {
930 outmod
= midgard_outmod_int_wrap
;
932 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
933 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
936 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
938 if (instr
->op
== nir_op_fmax
) {
939 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
940 op
= midgard_alu_op_fmov
;
942 outmod
= midgard_outmod_pos
;
943 instr
->src
[0] = instr
->src
[1];
944 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
945 op
= midgard_alu_op_fmov
;
947 outmod
= midgard_outmod_pos
;
951 /* Fetch unit, quirks, etc information */
952 unsigned opcode_props
= alu_opcode_props
[op
].props
;
953 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
955 /* src0 will always exist afaik, but src1 will not for 1-argument
956 * instructions. The latter can only be fetched if the instruction
957 * needs it, or else we may segfault. */
959 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
960 unsigned src1
= nr_inputs
>= 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : ~0;
961 unsigned src2
= nr_inputs
== 3 ? nir_alu_src_index(ctx
, &instr
->src
[2]) : ~0;
963 /* Rather than use the instruction generation helpers, we do it
964 * ourselves here to avoid the mess */
966 midgard_instruction ins
= {
969 quirk_flipped_r24
? ~0 : src0
,
970 quirk_flipped_r24
? src0
: src1
,
976 nir_alu_src
*nirmods
[3] = { NULL
};
978 if (nr_inputs
>= 2) {
979 nirmods
[0] = &instr
->src
[0];
980 nirmods
[1] = &instr
->src
[1];
981 } else if (nr_inputs
== 1) {
982 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
988 nirmods
[2] = &instr
->src
[2];
990 /* These were lowered to a move, so apply the corresponding mod */
992 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
993 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
995 if (instr
->op
== nir_op_fneg
)
996 s
->negate
= !s
->negate
;
998 if (instr
->op
== nir_op_fabs
)
1002 bool is_int
= midgard_is_integer_op(op
);
1004 ins
.mask
= mask_of(nr_components
);
1006 midgard_vector_alu alu
= {
1008 .reg_mode
= reg_mode
,
1009 .dest_override
= dest_override
,
1012 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1013 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1016 if (nr_inputs
== 3) {
1017 ins
.cond_swizzle
= SWIZZLE_FROM_ARRAY(nirmods
[2]->swizzle
);
1018 assert(!nirmods
[2]->abs
);
1019 assert(!nirmods
[2]->negate
);
1022 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1025 ins
.mask
&= instr
->dest
.write_mask
;
1029 /* Late fixup for emulated instructions */
1031 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1032 /* Presently, our second argument is an inline #0 constant.
1033 * Switch over to an embedded 1.0 constant (that can't fit
1034 * inline, since we're 32-bit, not 16-bit like the inline
1037 ins
.has_inline_constant
= false;
1038 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1039 ins
.has_constants
= true;
1041 if (instr
->op
== nir_op_b2f32
) {
1043 memcpy(&ins
.constants
, &f
, sizeof(float));
1045 ins
.constants
[0] = 1;
1048 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1049 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1050 /* Lots of instructions need a 0 plonked in */
1051 ins
.has_inline_constant
= false;
1052 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1053 ins
.has_constants
= true;
1054 ins
.constants
[0] = 0;
1055 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1056 } else if (instr
->op
== nir_op_inot
) {
1060 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1061 /* To avoid duplicating the lookup tables (probably), true LUT
1062 * instructions can only operate as if they were scalars. Lower
1063 * them here by changing the component. */
1065 uint8_t original_swizzle
[4];
1066 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1067 unsigned orig_mask
= ins
.mask
;
1069 for (int i
= 0; i
< nr_components
; ++i
) {
1070 /* Mask the associated component, dropping the
1071 * instruction if needed */
1074 ins
.mask
&= orig_mask
;
1079 for (int j
= 0; j
< 4; ++j
)
1080 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1082 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, false));
1083 emit_mir_instruction(ctx
, ins
);
1086 emit_mir_instruction(ctx
, ins
);
1093 mir_mask_for_intr(nir_instr
*instr
, bool is_read
)
1095 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1098 return mask_of(nir_intrinsic_dest_components(intr
));
1100 return nir_intrinsic_write_mask(intr
);
1103 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1104 * optimized) versions of UBO #0 */
1106 midgard_instruction
*
1108 compiler_context
*ctx
,
1112 nir_src
*indirect_offset
,
1115 /* TODO: half-floats */
1117 midgard_instruction ins
= m_ld_ubo_int4(dest
, offset
);
1119 assert((offset
& 0xF) == 0);
1122 /* TODO: Don't split */
1123 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1124 ins
.load_store
.address
= offset
>> 3;
1125 ins
.mask
= mir_mask_for_intr(instr
, true);
1127 if (indirect_offset
) {
1128 ins
.src
[1] = nir_src_index(ctx
, indirect_offset
);
1129 ins
.load_store
.arg_2
= 0x80;
1131 ins
.load_store
.arg_2
= 0x1E;
1134 ins
.load_store
.arg_1
= index
;
1136 return emit_mir_instruction(ctx
, ins
);
1139 /* SSBO reads are like UBO reads if you squint */
1143 compiler_context
*ctx
,
1148 nir_src
*indirect_offset
,
1153 midgard_instruction ins
;
1156 ins
= m_ld_int4(srcdest
, offset
);
1158 ins
= m_st_int4(srcdest
, offset
);
1160 /* SSBO reads use a generic memory read interface, so we need the
1161 * address of the SSBO as the first argument. This is a sysval. */
1163 unsigned addr
= make_compiler_temp(ctx
);
1164 emit_sysval_read(ctx
, instr
, addr
, 2);
1166 /* The source array is a bit of a leaky abstraction for SSBOs.
1167 * Nevertheless, for loads:
1173 * Whereas for stores:
1179 * We would like arg_1 = the address and
1180 * arg_2 = the offset.
1183 ins
.src
[is_read
? 0 : 1] = addr
;
1185 /* TODO: What is this? It looks superficially like a shift << 5, but
1186 * arg_1 doesn't take a shift Should it be E0 or A0? We also need the
1187 * indirect offset. */
1189 if (indirect_offset
) {
1190 ins
.load_store
.arg_1
|= 0xE0;
1191 ins
.src
[is_read
? 1 : 2] = nir_src_index(ctx
, indirect_offset
);
1193 ins
.load_store
.arg_2
= 0x7E;
1196 /* TODO: Bounds check */
1198 /* Finally, we emit the direct offset */
1200 ins
.load_store
.varying_parameters
= (offset
& 0x1FF) << 1;
1201 ins
.load_store
.address
= (offset
>> 9);
1202 ins
.mask
= mir_mask_for_intr(instr
, is_read
);
1204 emit_mir_instruction(ctx
, ins
);
1209 compiler_context
*ctx
,
1210 unsigned dest
, unsigned offset
,
1211 unsigned nr_comp
, unsigned component
,
1212 nir_src
*indirect_offset
, nir_alu_type type
)
1214 /* XXX: Half-floats? */
1215 /* TODO: swizzle, mask */
1217 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1218 ins
.mask
= mask_of(nr_comp
);
1219 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1221 midgard_varying_parameter p
= {
1223 .interpolation
= midgard_interp_default
,
1224 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1228 memcpy(&u
, &p
, sizeof(p
));
1229 ins
.load_store
.varying_parameters
= u
;
1231 if (indirect_offset
)
1232 ins
.src
[1] = nir_src_index(ctx
, indirect_offset
);
1234 ins
.load_store
.arg_2
= 0x1E;
1236 ins
.load_store
.arg_1
= 0x9E;
1238 /* Use the type appropriate load */
1242 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1245 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1247 case nir_type_float
:
1248 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1251 unreachable("Attempted to load unknown type");
1255 emit_mir_instruction(ctx
, ins
);
1259 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
, signed dest_override
,
1260 unsigned nr_components
)
1264 /* Figure out which uniform this is */
1265 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1266 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1268 if (dest_override
>= 0)
1269 dest
= dest_override
;
1271 /* Sysvals are prefix uniforms */
1272 unsigned uniform
= ((uintptr_t) val
) - 1;
1274 /* Emit the read itself -- this is never indirect */
1275 midgard_instruction
*ins
=
1276 emit_ubo_read(ctx
, instr
, dest
, uniform
* 16, NULL
, 0);
1278 ins
->mask
= mask_of(nr_components
);
1282 compute_builtin_arg(nir_op op
)
1285 case nir_intrinsic_load_work_group_id
:
1287 case nir_intrinsic_load_local_invocation_id
:
1290 unreachable("Invalid compute paramater loaded");
1294 /* Emit store for a fragment shader, which is encoded via a fancy branch. TODO:
1295 * Handle MRT here */
1298 emit_fragment_store(compiler_context
*ctx
, unsigned src
, unsigned rt
)
1300 emit_explicit_constant(ctx
, src
, src
);
1302 /* If we're doing MRT, we need to specify the render target */
1304 midgard_instruction rt_move
= {
1309 /* We'll write to r1.z */
1310 rt_move
= v_mov(~0, blank_alu_src
, SSA_FIXED_REGISTER(1));
1311 rt_move
.mask
= 1 << COMPONENT_Z
;
1312 rt_move
.unit
= UNIT_SADD
;
1314 /* r1.z = (rt * 0x100) */
1315 rt_move
.has_inline_constant
= true;
1316 rt_move
.inline_constant
= (rt
* 0x100);
1319 ctx
->work_registers
= MAX2(ctx
->work_registers
, 1);
1322 emit_mir_instruction(ctx
, rt_move
);
1325 /* Next, generate the branch. For R render targets in the writeout, the
1326 * i'th render target jumps to pseudo-offset [2(R-1) + i] */
1328 unsigned outputs
= ctx
->is_blend
? 1 : ctx
->nir
->num_outputs
;
1329 unsigned offset
= (2 * (outputs
- 1)) + rt
;
1331 struct midgard_instruction ins
=
1332 v_alu_br_compact_cond(midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, offset
, midgard_condition_always
);
1334 /* Add dependencies */
1336 ins
.src
[1] = rt_move
.dest
;
1338 /* Emit the branch */
1339 emit_mir_instruction(ctx
, ins
);
1343 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1345 unsigned reg
= nir_dest_index(ctx
, &instr
->dest
);
1346 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1347 ins
.mask
= mask_of(3);
1348 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1349 emit_mir_instruction(ctx
, ins
);
1352 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1354 unsigned offset
= 0, reg
;
1356 switch (instr
->intrinsic
) {
1357 case nir_intrinsic_discard_if
:
1358 case nir_intrinsic_discard
: {
1359 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1360 struct midgard_instruction discard
= v_branch(conditional
, false);
1361 discard
.branch
.target_type
= TARGET_DISCARD
;
1364 discard
.src
[0] = nir_src_index(ctx
, &instr
->src
[0]);
1366 emit_mir_instruction(ctx
, discard
);
1367 schedule_barrier(ctx
);
1372 case nir_intrinsic_load_uniform
:
1373 case nir_intrinsic_load_ubo
:
1374 case nir_intrinsic_load_ssbo
:
1375 case nir_intrinsic_load_input
: {
1376 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1377 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1378 bool is_ssbo
= instr
->intrinsic
== nir_intrinsic_load_ssbo
;
1380 /* Get the base type of the intrinsic */
1381 /* TODO: Infer type? Does it matter? */
1383 (is_ubo
|| is_ssbo
) ? nir_type_uint
: nir_intrinsic_type(instr
);
1384 t
= nir_alu_type_get_base_type(t
);
1386 if (!(is_ubo
|| is_ssbo
)) {
1387 offset
= nir_intrinsic_base(instr
);
1390 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1392 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1394 bool direct
= nir_src_is_const(*src_offset
);
1395 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1398 offset
+= nir_src_as_uint(*src_offset
);
1400 /* We may need to apply a fractional offset */
1401 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1402 nir_intrinsic_component(instr
) : 0;
1403 reg
= nir_dest_index(ctx
, &instr
->dest
);
1405 if (is_uniform
&& !ctx
->is_blend
) {
1406 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysval_count
+ offset
) * 16, indirect_offset
, 0);
1407 } else if (is_ubo
) {
1408 nir_src index
= instr
->src
[0];
1410 /* We don't yet support indirect UBOs. For indirect
1411 * block numbers (if that's possible), we don't know
1412 * enough about the hardware yet. For indirect sources,
1413 * we know what we need but we need to add some NIR
1414 * support for lowering correctly with respect to
1417 assert(nir_src_is_const(index
));
1418 assert(nir_src_is_const(*src_offset
));
1420 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1421 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, NULL
, uindex
);
1422 } else if (is_ssbo
) {
1423 nir_src index
= instr
->src
[0];
1424 assert(nir_src_is_const(index
));
1425 uint32_t uindex
= nir_src_as_uint(index
);
1427 emit_ssbo_access(ctx
, &instr
->instr
, true, reg
, offset
, indirect_offset
, uindex
);
1428 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1429 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
, t
);
1430 } else if (ctx
->is_blend
) {
1431 /* For blend shaders, load the input color, which is
1432 * preloaded to r0 */
1434 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), blank_alu_src
, reg
);
1435 emit_mir_instruction(ctx
, move
);
1436 schedule_barrier(ctx
);
1437 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1438 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1439 ins
.load_store
.arg_1
= 0x1E;
1440 ins
.load_store
.arg_2
= 0x1E;
1441 ins
.mask
= mask_of(nr_comp
);
1443 /* Use the type appropriate load */
1447 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1450 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1452 case nir_type_float
:
1453 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1456 unreachable("Attempted to load unknown type");
1460 emit_mir_instruction(ctx
, ins
);
1462 DBG("Unknown load\n");
1469 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1471 case nir_intrinsic_load_raw_output_pan
:
1472 reg
= nir_dest_index(ctx
, &instr
->dest
);
1473 assert(ctx
->is_blend
);
1475 midgard_instruction ld
= m_ld_color_buffer_8(reg
, 0);
1476 emit_mir_instruction(ctx
, ld
);
1479 case nir_intrinsic_load_blend_const_color_rgba
: {
1480 assert(ctx
->is_blend
);
1481 reg
= nir_dest_index(ctx
, &instr
->dest
);
1483 /* Blend constants are embedded directly in the shader and
1484 * patched in, so we use some magic routing */
1486 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1487 ins
.has_constants
= true;
1488 ins
.has_blend_constant
= true;
1489 emit_mir_instruction(ctx
, ins
);
1493 case nir_intrinsic_store_output
:
1494 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1496 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1498 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1500 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1501 /* Determine number of render targets */
1502 emit_fragment_store(ctx
, reg
, offset
);
1503 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1504 /* We should have been vectorized, though we don't
1505 * currently check that st_vary is emitted only once
1506 * per slot (this is relevant, since there's not a mask
1507 * parameter available on the store [set to 0 by the
1508 * blob]). We do respect the component by adjusting the
1509 * swizzle. If this is a constant source, we'll need to
1510 * emit that explicitly. */
1512 emit_explicit_constant(ctx
, reg
, reg
);
1514 unsigned component
= nir_intrinsic_component(instr
);
1515 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1517 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1518 st
.load_store
.arg_1
= 0x9E;
1519 st
.load_store
.arg_2
= 0x1E;
1520 st
.load_store
.swizzle
= swizzle_of(nr_comp
) << (2*component
);
1521 emit_mir_instruction(ctx
, st
);
1523 DBG("Unknown store\n");
1529 /* Special case of store_output for lowered blend shaders */
1530 case nir_intrinsic_store_raw_output_pan
:
1531 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1532 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1533 emit_fragment_store(ctx
, reg
, 0);
1537 case nir_intrinsic_store_ssbo
:
1538 assert(nir_src_is_const(instr
->src
[1]));
1540 bool direct_offset
= nir_src_is_const(instr
->src
[2]);
1541 offset
= direct_offset
? nir_src_as_uint(instr
->src
[2]) : 0;
1542 nir_src
*indirect_offset
= direct_offset
? NULL
: &instr
->src
[2];
1543 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1545 uint32_t uindex
= nir_src_as_uint(instr
->src
[1]);
1547 emit_explicit_constant(ctx
, reg
, reg
);
1548 emit_ssbo_access(ctx
, &instr
->instr
, false, reg
, offset
, indirect_offset
, uindex
);
1551 case nir_intrinsic_load_alpha_ref_float
:
1552 assert(instr
->dest
.is_ssa
);
1554 float ref_value
= ctx
->alpha_ref
;
1556 /* See emit_load_const */
1557 float *v
= ralloc_array(NULL
, float, 4);
1558 memcpy(v
, &ref_value
, sizeof(float));
1559 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (instr
->dest
.ssa
.index
<< 1) + 1, v
);
1562 case nir_intrinsic_load_viewport_scale
:
1563 case nir_intrinsic_load_viewport_offset
:
1564 case nir_intrinsic_load_num_work_groups
:
1565 emit_sysval_read(ctx
, &instr
->instr
, ~0, 3);
1568 case nir_intrinsic_load_work_group_id
:
1569 case nir_intrinsic_load_local_invocation_id
:
1570 emit_compute_builtin(ctx
, instr
);
1574 printf ("Unhandled intrinsic\n");
1581 midgard_tex_format(enum glsl_sampler_dim dim
)
1584 case GLSL_SAMPLER_DIM_1D
:
1585 case GLSL_SAMPLER_DIM_BUF
:
1588 case GLSL_SAMPLER_DIM_2D
:
1589 case GLSL_SAMPLER_DIM_EXTERNAL
:
1590 case GLSL_SAMPLER_DIM_RECT
:
1593 case GLSL_SAMPLER_DIM_3D
:
1596 case GLSL_SAMPLER_DIM_CUBE
:
1597 return MALI_TEX_CUBE
;
1600 DBG("Unknown sampler dim type\n");
1606 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1610 pan_attach_constant_bias(
1611 compiler_context
*ctx
,
1613 midgard_texture_word
*word
)
1615 /* To attach as constant, it has to *be* constant */
1617 if (!nir_src_is_const(lod
))
1620 float f
= nir_src_as_float(lod
);
1622 /* Break into fixed-point */
1624 float lod_frac
= f
- lod_int
;
1626 /* Carry over negative fractions */
1627 if (lod_frac
< 0.0) {
1633 word
->bias
= float_to_ubyte(lod_frac
);
1634 word
->bias_int
= lod_int
;
1639 static enum mali_sampler_type
1640 midgard_sampler_type(nir_alu_type t
) {
1641 switch (nir_alu_type_get_base_type(t
))
1643 case nir_type_float
:
1644 return MALI_SAMPLER_FLOAT
;
1646 return MALI_SAMPLER_SIGNED
;
1648 return MALI_SAMPLER_UNSIGNED
;
1650 unreachable("Unknown sampler type");
1655 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1656 unsigned midgard_texop
)
1659 //assert (!instr->sampler);
1660 //assert (!instr->texture_array_size);
1662 int texture_index
= instr
->texture_index
;
1663 int sampler_index
= texture_index
;
1665 /* No helper to build texture words -- we do it all here */
1666 midgard_instruction ins
= {
1667 .type
= TAG_TEXTURE_4
,
1669 .dest
= nir_dest_index(ctx
, &instr
->dest
),
1670 .src
= { ~0, ~0, ~0 },
1672 .op
= midgard_texop
,
1673 .format
= midgard_tex_format(instr
->sampler_dim
),
1674 .texture_handle
= texture_index
,
1675 .sampler_handle
= sampler_index
,
1676 .swizzle
= SWIZZLE_XYZW
,
1677 .in_reg_swizzle
= SWIZZLE_XYZW
,
1683 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1687 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1688 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1689 midgard_vector_alu_src alu_src
= blank_alu_src
;
1690 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
1692 switch (instr
->src
[i
].src_type
) {
1693 case nir_tex_src_coord
: {
1694 emit_explicit_constant(ctx
, index
, index
);
1696 /* Texelfetch coordinates uses all four elements
1697 * (xyz/index) regardless of texture dimensionality,
1698 * which means it's necessary to zero the unused
1699 * components to keep everything happy */
1701 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1702 unsigned old_index
= index
;
1704 index
= make_compiler_temp(ctx
);
1706 /* mov index, old_index */
1707 midgard_instruction mov
= v_mov(old_index
, blank_alu_src
, index
);
1709 emit_mir_instruction(ctx
, mov
);
1711 /* mov index.zw, #0 */
1712 mov
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
),
1713 blank_alu_src
, index
);
1714 mov
.has_constants
= true;
1715 mov
.mask
= (1 << COMPONENT_Z
) | (1 << COMPONENT_W
);
1716 emit_mir_instruction(ctx
, mov
);
1719 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1720 /* texelFetch is undefined on samplerCube */
1721 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1723 /* For cubemaps, we use a special ld/st op to
1724 * select the face and copy the xy into the
1725 * texture register */
1727 unsigned temp
= make_compiler_temp(ctx
);
1728 midgard_instruction ld
= m_ld_cubemap_coords(temp
, 0);
1730 ld
.mask
= 0x3; /* xy */
1731 ld
.load_store
.arg_1
= 0x20;
1732 ld
.load_store
.swizzle
= alu_src
.swizzle
;
1733 emit_mir_instruction(ctx
, ld
);
1736 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYXX
;
1741 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1742 /* Array component in w but NIR wants it in z */
1743 if (nr_components
== 3)
1744 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYZZ
;
1745 else if (nr_components
== 2)
1746 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYXX
;
1748 unreachable("Invalid texture 2D components");
1754 case nir_tex_src_bias
:
1755 case nir_tex_src_lod
: {
1756 /* Try as a constant if we can */
1758 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1759 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1762 ins
.texture
.lod_register
= true;
1764 emit_explicit_constant(ctx
, index
, index
);
1770 unreachable("Unknown texture source type\n");
1774 emit_mir_instruction(ctx
, ins
);
1776 /* Used for .cont and .last hinting */
1777 ctx
->texture_op_count
++;
1781 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1783 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1784 * generic tex in some cases (which confuses the hardware) */
1786 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1788 if (is_vertex
&& instr
->op
== nir_texop_tex
)
1789 instr
->op
= nir_texop_txl
;
1791 switch (instr
->op
) {
1794 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1797 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1800 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1803 emit_sysval_read(ctx
, &instr
->instr
, ~0, 4);
1806 unreachable("Unhanlded texture op");
1811 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1813 switch (instr
->type
) {
1814 case nir_jump_break
: {
1815 /* Emit a branch out of the loop */
1816 struct midgard_instruction br
= v_branch(false, false);
1817 br
.branch
.target_type
= TARGET_BREAK
;
1818 br
.branch
.target_break
= ctx
->current_loop_depth
;
1819 emit_mir_instruction(ctx
, br
);
1824 DBG("Unknown jump type %d\n", instr
->type
);
1830 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1832 switch (instr
->type
) {
1833 case nir_instr_type_load_const
:
1834 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1837 case nir_instr_type_intrinsic
:
1838 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1841 case nir_instr_type_alu
:
1842 emit_alu(ctx
, nir_instr_as_alu(instr
));
1845 case nir_instr_type_tex
:
1846 emit_tex(ctx
, nir_instr_as_tex(instr
));
1849 case nir_instr_type_jump
:
1850 emit_jump(ctx
, nir_instr_as_jump(instr
));
1853 case nir_instr_type_ssa_undef
:
1858 DBG("Unhandled instruction type\n");
1864 /* ALU instructions can inline or embed constants, which decreases register
1865 * pressure and saves space. */
1867 #define CONDITIONAL_ATTACH(idx) { \
1868 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
1871 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
1872 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1877 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
1879 mir_foreach_instr_in_block(block
, alu
) {
1880 /* Other instructions cannot inline constants */
1881 if (alu
->type
!= TAG_ALU_4
) continue;
1882 if (alu
->compact_branch
) continue;
1884 /* If there is already a constant here, we can do nothing */
1885 if (alu
->has_constants
) continue;
1887 CONDITIONAL_ATTACH(0);
1889 if (!alu
->has_constants
) {
1890 CONDITIONAL_ATTACH(1)
1891 } else if (!alu
->inline_constant
) {
1892 /* Corner case: _two_ vec4 constants, for instance with a
1893 * csel. For this case, we can only use a constant
1894 * register for one, we'll have to emit a move for the
1895 * other. Note, if both arguments are constants, then
1896 * necessarily neither argument depends on the value of
1897 * any particular register. As the destination register
1898 * will be wiped, that means we can spill the constant
1899 * to the destination register.
1902 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
1903 unsigned scratch
= alu
->dest
;
1906 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1907 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
1909 /* Set the source */
1910 alu
->src
[1] = scratch
;
1912 /* Inject us -before- the last instruction which set r31 */
1913 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
1919 /* Being a little silly with the names, but returns the op that is the bitwise
1920 * inverse of the op with the argument switched. I.e. (f and g are
1923 * f(a, b) = ~g(b, a)
1925 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
1927 * f(a, b) = ~g(b, a)
1928 * ~f(a, b) = g(b, a)
1929 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
1932 * Thus we define this function in pairs.
1935 static inline midgard_alu_op
1936 mir_contrapositive(midgard_alu_op op
)
1939 case midgard_alu_op_flt
:
1940 return midgard_alu_op_fle
;
1941 case midgard_alu_op_fle
:
1942 return midgard_alu_op_flt
;
1944 case midgard_alu_op_ilt
:
1945 return midgard_alu_op_ile
;
1946 case midgard_alu_op_ile
:
1947 return midgard_alu_op_ilt
;
1950 unreachable("No known contrapositive");
1954 /* Midgard supports two types of constants, embedded constants (128-bit) and
1955 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1956 * constants can be demoted to inline constants, for space savings and
1957 * sometimes a performance boost */
1960 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
1962 mir_foreach_instr_in_block(block
, ins
) {
1963 if (!ins
->has_constants
) continue;
1964 if (ins
->has_inline_constant
) continue;
1966 /* Blend constants must not be inlined by definition */
1967 if (ins
->has_blend_constant
) continue;
1969 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
1970 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
1971 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
1973 if (!(is_16
|| is_32
))
1976 /* src1 cannot be an inline constant due to encoding
1977 * restrictions. So, if possible we try to flip the arguments
1980 int op
= ins
->alu
.op
;
1982 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1983 bool flip
= alu_opcode_props
[op
].props
& OP_COMMUTES
;
1986 /* Conditionals can be inverted */
1987 case midgard_alu_op_flt
:
1988 case midgard_alu_op_ilt
:
1989 case midgard_alu_op_fle
:
1990 case midgard_alu_op_ile
:
1991 ins
->alu
.op
= mir_contrapositive(ins
->alu
.op
);
1996 case midgard_alu_op_fcsel
:
1997 case midgard_alu_op_icsel
:
1998 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
2004 /* Flip the SSA numbers */
2005 ins
->src
[0] = ins
->src
[1];
2006 ins
->src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2008 /* And flip the modifiers */
2012 src_temp
= ins
->alu
.src2
;
2013 ins
->alu
.src2
= ins
->alu
.src1
;
2014 ins
->alu
.src1
= src_temp
;
2018 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2019 /* Extract the source information */
2021 midgard_vector_alu_src
*src
;
2022 int q
= ins
->alu
.src2
;
2023 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2026 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2027 int component
= src
->swizzle
& 3;
2029 /* Scale constant appropriately, if we can legally */
2030 uint16_t scaled_constant
= 0;
2032 if (midgard_is_integer_op(op
) || is_16
) {
2033 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2034 scaled_constant
= (uint16_t) iconstants
[component
];
2036 /* Constant overflow after resize */
2037 if (scaled_constant
!= iconstants
[component
])
2040 float *f
= (float *) ins
->constants
;
2041 float original
= f
[component
];
2042 scaled_constant
= _mesa_float_to_half(original
);
2044 /* Check for loss of precision. If this is
2045 * mediump, we don't care, but for a highp
2046 * shader, we need to pay attention. NIR
2047 * doesn't yet tell us which mode we're in!
2048 * Practically this prevents most constants
2049 * from being inlined, sadly. */
2051 float fp32
= _mesa_half_to_float(scaled_constant
);
2053 if (fp32
!= original
)
2057 /* We don't know how to handle these with a constant */
2059 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
2060 DBG("Bailing inline constant...\n");
2064 /* Make sure that the constant is not itself a
2065 * vector by checking if all accessed values
2066 * (by the swizzle) are the same. */
2068 uint32_t *cons
= ins
->constants
;
2069 uint32_t value
= cons
[component
];
2071 bool is_vector
= false;
2072 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2074 for (int c
= 1; c
< 4; ++c
) {
2075 /* We only care if this component is actually used */
2076 if (!(mask
& (1 << c
)))
2079 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2081 if (test
!= value
) {
2090 /* Get rid of the embedded constant */
2091 ins
->has_constants
= false;
2093 ins
->has_inline_constant
= true;
2094 ins
->inline_constant
= scaled_constant
;
2099 /* Dead code elimination for branches at the end of a block - only one branch
2100 * per block is legal semantically */
2103 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2105 bool branched
= false;
2107 mir_foreach_instr_in_block_safe(block
, ins
) {
2108 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2111 mir_remove_instruction(ins
);
2117 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2118 * the move can be propagated away entirely */
2121 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2124 if (comp
== midgard_outmod_none
)
2127 if (*outmod
== midgard_outmod_none
) {
2132 /* TODO: Compose rules */
2137 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2139 bool progress
= false;
2141 mir_foreach_instr_in_block_safe(block
, ins
) {
2142 if (ins
->type
!= TAG_ALU_4
) continue;
2143 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2144 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2146 /* TODO: Registers? */
2147 unsigned src
= ins
->src
[1];
2148 if (src
& IS_REG
) continue;
2150 /* There might be a source modifier, too */
2151 if (mir_nontrivial_source2_mod(ins
)) continue;
2153 /* Backpropagate the modifier */
2154 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2155 if (v
->type
!= TAG_ALU_4
) continue;
2156 if (v
->dest
!= src
) continue;
2158 /* Can we even take a float outmod? */
2159 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2161 midgard_outmod_float temp
= v
->alu
.outmod
;
2162 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2164 /* Throw in the towel.. */
2165 if (!progress
) break;
2167 /* Otherwise, transfer the modifier */
2168 v
->alu
.outmod
= temp
;
2169 ins
->alu
.outmod
= midgard_outmod_none
;
2179 emit_fragment_epilogue(compiler_context
*ctx
)
2181 /* Just emit the last chunk with the branch */
2182 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, ~0, midgard_condition_always
);
2185 static midgard_block
*
2186 emit_block(compiler_context
*ctx
, nir_block
*block
)
2188 midgard_block
*this_block
= ctx
->after_block
;
2189 ctx
->after_block
= NULL
;
2192 this_block
= create_empty_block(ctx
);
2194 list_addtail(&this_block
->link
, &ctx
->blocks
);
2196 this_block
->is_scheduled
= false;
2199 /* Set up current block */
2200 list_inithead(&this_block
->instructions
);
2201 ctx
->current_block
= this_block
;
2203 nir_foreach_instr(instr
, block
) {
2204 emit_instr(ctx
, instr
);
2205 ++ctx
->instruction_count
;
2211 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2214 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2216 midgard_block
*before_block
= ctx
->current_block
;
2218 /* Speculatively emit the branch, but we can't fill it in until later */
2219 EMIT(branch
, true, true);
2220 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2221 then_branch
->src
[0] = nir_src_index(ctx
, &nif
->condition
);
2223 /* Emit the two subblocks. */
2224 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2225 midgard_block
*end_then_block
= ctx
->current_block
;
2227 /* Emit a jump from the end of the then block to the end of the else */
2228 EMIT(branch
, false, false);
2229 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2231 /* Emit second block, and check if it's empty */
2233 int else_idx
= ctx
->block_count
;
2234 int count_in
= ctx
->instruction_count
;
2235 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2236 midgard_block
*end_else_block
= ctx
->current_block
;
2237 int after_else_idx
= ctx
->block_count
;
2239 /* Now that we have the subblocks emitted, fix up the branches */
2244 if (ctx
->instruction_count
== count_in
) {
2245 /* The else block is empty, so don't emit an exit jump */
2246 mir_remove_instruction(then_exit
);
2247 then_branch
->branch
.target_block
= after_else_idx
;
2249 then_branch
->branch
.target_block
= else_idx
;
2250 then_exit
->branch
.target_block
= after_else_idx
;
2253 /* Wire up the successors */
2255 ctx
->after_block
= create_empty_block(ctx
);
2257 midgard_block_add_successor(before_block
, then_block
);
2258 midgard_block_add_successor(before_block
, else_block
);
2260 midgard_block_add_successor(end_then_block
, ctx
->after_block
);
2261 midgard_block_add_successor(end_else_block
, ctx
->after_block
);
2265 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2267 /* Remember where we are */
2268 midgard_block
*start_block
= ctx
->current_block
;
2270 /* Allocate a loop number, growing the current inner loop depth */
2271 int loop_idx
= ++ctx
->current_loop_depth
;
2273 /* Get index from before the body so we can loop back later */
2274 int start_idx
= ctx
->block_count
;
2276 /* Emit the body itself */
2277 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2279 /* Branch back to loop back */
2280 struct midgard_instruction br_back
= v_branch(false, false);
2281 br_back
.branch
.target_block
= start_idx
;
2282 emit_mir_instruction(ctx
, br_back
);
2284 /* Mark down that branch in the graph. */
2285 midgard_block_add_successor(start_block
, loop_block
);
2286 midgard_block_add_successor(ctx
->current_block
, loop_block
);
2288 /* Find the index of the block about to follow us (note: we don't add
2289 * one; blocks are 0-indexed so we get a fencepost problem) */
2290 int break_block_idx
= ctx
->block_count
;
2292 /* Fix up the break statements we emitted to point to the right place,
2293 * now that we can allocate a block number for them */
2294 ctx
->after_block
= create_empty_block(ctx
);
2296 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2297 mir_foreach_instr_in_block(block
, ins
) {
2298 if (ins
->type
!= TAG_ALU_4
) continue;
2299 if (!ins
->compact_branch
) continue;
2300 if (ins
->prepacked_branch
) continue;
2302 /* We found a branch -- check the type to see if we need to do anything */
2303 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2305 /* It's a break! Check if it's our break */
2306 if (ins
->branch
.target_break
!= loop_idx
) continue;
2308 /* Okay, cool, we're breaking out of this loop.
2309 * Rewrite from a break to a goto */
2311 ins
->branch
.target_type
= TARGET_GOTO
;
2312 ins
->branch
.target_block
= break_block_idx
;
2314 midgard_block_add_successor(block
, ctx
->after_block
);
2318 /* Now that we've finished emitting the loop, free up the depth again
2319 * so we play nice with recursion amid nested loops */
2320 --ctx
->current_loop_depth
;
2322 /* Dump loop stats */
2326 static midgard_block
*
2327 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2329 midgard_block
*start_block
= NULL
;
2331 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2332 switch (node
->type
) {
2333 case nir_cf_node_block
: {
2334 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2337 start_block
= block
;
2342 case nir_cf_node_if
:
2343 emit_if(ctx
, nir_cf_node_as_if(node
));
2346 case nir_cf_node_loop
:
2347 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2350 case nir_cf_node_function
:
2359 /* Due to lookahead, we need to report the first tag executed in the command
2360 * stream and in branch targets. An initial block might be empty, so iterate
2361 * until we find one that 'works' */
2364 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2366 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2368 unsigned first_tag
= 0;
2370 mir_foreach_block_from(ctx
, initial_block
, v
) {
2371 midgard_bundle
*initial_bundle
=
2372 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2374 if (initial_bundle
) {
2375 first_tag
= initial_bundle
->tag
;
2384 midgard_compile_shader_nir(struct midgard_screen
*screen
, nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2386 struct util_dynarray
*compiled
= &program
->compiled
;
2388 midgard_debug
= debug_get_option_midgard_debug();
2390 /* TODO: Bound against what? */
2391 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2394 ctx
->screen
= screen
;
2395 ctx
->stage
= nir
->info
.stage
;
2396 ctx
->is_blend
= is_blend
;
2397 ctx
->alpha_ref
= program
->alpha_ref
;
2399 /* Start off with a safe cutoff, allowing usage of all 16 work
2400 * registers. Later, we'll promote uniform reads to uniform registers
2401 * if we determine it is beneficial to do so */
2402 ctx
->uniform_cutoff
= 8;
2404 /* Initialize at a global (not block) level hash tables */
2406 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2407 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2408 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2410 /* Record the varying mapping for the command stream's bookkeeping */
2412 struct exec_list
*varyings
=
2413 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2415 unsigned max_varying
= 0;
2416 nir_foreach_variable(var
, varyings
) {
2417 unsigned loc
= var
->data
.driver_location
;
2418 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2420 for (int c
= 0; c
< sz
; ++c
) {
2421 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2422 max_varying
= MAX2(max_varying
, loc
+ c
);
2426 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2427 * (so we don't accidentally duplicate the epilogue since mesa/st has
2428 * messed with our I/O quite a bit already) */
2430 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2432 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2433 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2434 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2437 NIR_PASS_V(nir
, nir_lower_var_copies
);
2438 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2439 NIR_PASS_V(nir
, nir_split_var_copies
);
2440 NIR_PASS_V(nir
, nir_lower_var_copies
);
2441 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2442 NIR_PASS_V(nir
, nir_lower_var_copies
);
2443 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2445 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2447 /* Optimisation passes */
2451 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2452 nir_print_shader(nir
, stdout
);
2455 /* Assign sysvals and counts, now that we're sure
2456 * (post-optimisation) */
2458 midgard_nir_assign_sysvals(ctx
, nir
);
2460 program
->uniform_count
= nir
->num_uniforms
;
2461 program
->sysval_count
= ctx
->sysval_count
;
2462 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2464 nir_foreach_function(func
, nir
) {
2468 list_inithead(&ctx
->blocks
);
2469 ctx
->block_count
= 0;
2472 emit_cf_list(ctx
, &func
->impl
->body
);
2474 /* Emit empty exit block with successor */
2476 struct midgard_block
*semi_end
= ctx
->current_block
;
2478 struct midgard_block
*end
=
2479 emit_block(ctx
, func
->impl
->end_block
);
2481 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2482 emit_fragment_epilogue(ctx
);
2484 midgard_block_add_successor(semi_end
, end
);
2486 break; /* TODO: Multi-function shaders */
2489 util_dynarray_init(compiled
, NULL
);
2491 /* Per-block lowering before opts */
2493 mir_foreach_block(ctx
, block
) {
2494 inline_alu_constants(ctx
, block
);
2495 midgard_opt_promote_fmov(ctx
, block
);
2496 embedded_to_inline_constant(ctx
, block
);
2498 /* MIR-level optimizations */
2500 bool progress
= false;
2505 mir_foreach_block(ctx
, block
) {
2506 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2507 progress
|= midgard_opt_copy_prop(ctx
, block
);
2508 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2509 progress
|= midgard_opt_combine_projection(ctx
, block
);
2510 progress
|= midgard_opt_varying_projection(ctx
, block
);
2511 progress
|= midgard_opt_not_propagate(ctx
, block
);
2512 progress
|= midgard_opt_fuse_src_invert(ctx
, block
);
2513 progress
|= midgard_opt_fuse_dest_invert(ctx
, block
);
2514 progress
|= midgard_opt_csel_invert(ctx
, block
);
2518 mir_foreach_block(ctx
, block
) {
2519 midgard_lower_invert(ctx
, block
);
2520 midgard_lower_derivatives(ctx
, block
);
2523 /* Nested control-flow can result in dead branches at the end of the
2524 * block. This messes with our analysis and is just dead code, so cull
2526 mir_foreach_block(ctx
, block
) {
2527 midgard_opt_cull_dead_branch(ctx
, block
);
2530 /* Ensure we were lowered */
2531 mir_foreach_instr_global(ctx
, ins
) {
2532 assert(!ins
->invert
);
2536 schedule_program(ctx
);
2538 /* Now that all the bundles are scheduled and we can calculate block
2539 * sizes, emit actual branch instructions rather than placeholders */
2541 int br_block_idx
= 0;
2543 mir_foreach_block(ctx
, block
) {
2544 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2545 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2546 midgard_instruction
*ins
= bundle
->instructions
[c
];
2548 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2550 if (ins
->prepacked_branch
) continue;
2552 /* Parse some basic branch info */
2553 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2554 bool is_conditional
= ins
->branch
.conditional
;
2555 bool is_inverted
= ins
->branch
.invert_conditional
;
2556 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2558 /* Determine the block we're jumping to */
2559 int target_number
= ins
->branch
.target_block
;
2561 /* Report the destination tag */
2562 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2564 /* Count up the number of quadwords we're
2565 * jumping over = number of quadwords until
2566 * (br_block_idx, target_number) */
2568 int quadword_offset
= 0;
2572 } else if (target_number
> br_block_idx
) {
2575 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2576 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2579 quadword_offset
+= blk
->quadword_count
;
2582 /* Jump backwards */
2584 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2585 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2588 quadword_offset
-= blk
->quadword_count
;
2592 /* Unconditional extended branches (far jumps)
2593 * have issues, so we always use a conditional
2594 * branch, setting the condition to always for
2595 * unconditional. For compact unconditional
2596 * branches, cond isn't used so it doesn't
2597 * matter what we pick. */
2599 midgard_condition cond
=
2600 !is_conditional
? midgard_condition_always
:
2601 is_inverted
? midgard_condition_false
:
2602 midgard_condition_true
;
2604 midgard_jmp_writeout_op op
=
2605 is_discard
? midgard_jmp_writeout_op_discard
:
2606 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2607 midgard_jmp_writeout_op_branch_cond
;
2610 midgard_branch_extended branch
=
2611 midgard_create_branch_extended(
2616 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2617 } else if (is_conditional
|| is_discard
) {
2618 midgard_branch_cond branch
= {
2620 .dest_tag
= dest_tag
,
2621 .offset
= quadword_offset
,
2625 assert(branch
.offset
== quadword_offset
);
2627 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2629 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2631 midgard_branch_uncond branch
= {
2633 .dest_tag
= dest_tag
,
2634 .offset
= quadword_offset
,
2638 assert(branch
.offset
== quadword_offset
);
2640 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2648 /* Emit flat binary from the instruction arrays. Iterate each block in
2649 * sequence. Save instruction boundaries such that lookahead tags can
2650 * be assigned easily */
2652 /* Cache _all_ bundles in source order for lookahead across failed branches */
2654 int bundle_count
= 0;
2655 mir_foreach_block(ctx
, block
) {
2656 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2658 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2660 mir_foreach_block(ctx
, block
) {
2661 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2662 source_order_bundles
[bundle_idx
++] = bundle
;
2666 int current_bundle
= 0;
2668 /* Midgard prefetches instruction types, so during emission we
2669 * need to lookahead. Unless this is the last instruction, in
2670 * which we return 1. Or if this is the second to last and the
2671 * last is an ALU, then it's also 1... */
2673 mir_foreach_block(ctx
, block
) {
2674 mir_foreach_bundle_in_block(block
, bundle
) {
2677 if (current_bundle
+ 1 < bundle_count
) {
2678 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2680 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2687 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2691 /* TODO: Free deeper */
2692 //util_dynarray_fini(&block->instructions);
2695 free(source_order_bundles
);
2697 /* Report the very first tag executed */
2698 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2700 /* Deal with off-by-one related to the fencepost problem */
2701 program
->work_register_count
= ctx
->work_registers
+ 1;
2702 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2704 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2705 program
->tls_size
= ctx
->tls_size
;
2707 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2708 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);
2710 if (midgard_debug
& MIDGARD_DBG_SHADERDB
) {
2711 unsigned nr_bundles
= 0, nr_ins
= 0;
2713 /* Count instructions and bundles */
2715 mir_foreach_block(ctx
, block
) {
2716 nr_bundles
+= util_dynarray_num_elements(
2717 &block
->bundles
, midgard_bundle
);
2719 mir_foreach_bundle_in_block(block
, bun
)
2720 nr_ins
+= bun
->instruction_count
;
2723 /* Calculate thread count. There are certain cutoffs by
2724 * register count for thread count */
2726 unsigned nr_registers
= program
->work_register_count
;
2728 unsigned nr_threads
=
2729 (nr_registers
<= 4) ? 4 :
2730 (nr_registers
<= 8) ? 2 :
2735 fprintf(stderr
, "shader%d - %s shader: "
2736 "%u inst, %u bundles, %u quadwords, "
2737 "%u registers, %u threads, %u loops, "
2738 "%u:%u spills:fills\n",
2740 gl_shader_stage_name(ctx
->stage
),
2741 nr_ins
, nr_bundles
, ctx
->quadword_count
,
2742 nr_registers
, nr_threads
,
2744 ctx
->spills
, ctx
->fills
);