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pan/midgard: Set xyzx swizzle for load_compute_arg
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
44
45 #include "midgard.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
49 #include "helpers.h"
50 #include "compiler.h"
51 #include "midgard_quirks.h"
52
53 #include "disassemble.h"
54
55 static const struct debug_named_value debug_options[] = {
56 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
57 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
58 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
59 DEBUG_NAMED_VALUE_END
60 };
61
62 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
63
64 unsigned SHADER_DB_COUNT = 0;
65
66 int midgard_debug = 0;
67
68 #define DBG(fmt, ...) \
69 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
70 fprintf(stderr, "%s:%d: "fmt, \
71 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
72 static midgard_block *
73 create_empty_block(compiler_context *ctx)
74 {
75 midgard_block *blk = rzalloc(ctx, midgard_block);
76
77 blk->predecessors = _mesa_set_create(blk,
78 _mesa_hash_pointer,
79 _mesa_key_pointer_equal);
80
81 blk->source_id = ctx->block_source_count++;
82
83 return blk;
84 }
85
86 static void
87 midgard_block_add_successor(midgard_block *block, midgard_block *successor)
88 {
89 assert(block);
90 assert(successor);
91
92 /* Deduplicate */
93 for (unsigned i = 0; i < block->nr_successors; ++i) {
94 if (block->successors[i] == successor)
95 return;
96 }
97
98 block->successors[block->nr_successors++] = successor;
99 assert(block->nr_successors <= ARRAY_SIZE(block->successors));
100
101 /* Note the predecessor in the other direction */
102 _mesa_set_add(successor->predecessors, block);
103 }
104
105 static void
106 schedule_barrier(compiler_context *ctx)
107 {
108 midgard_block *temp = ctx->after_block;
109 ctx->after_block = create_empty_block(ctx);
110 ctx->block_count++;
111 list_addtail(&ctx->after_block->link, &ctx->blocks);
112 list_inithead(&ctx->after_block->instructions);
113 midgard_block_add_successor(ctx->current_block, ctx->after_block);
114 ctx->current_block = ctx->after_block;
115 ctx->after_block = temp;
116 }
117
118 /* Helpers to generate midgard_instruction's using macro magic, since every
119 * driver seems to do it that way */
120
121 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
122
123 #define M_LOAD_STORE(name, store) \
124 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
125 midgard_instruction i = { \
126 .type = TAG_LOAD_STORE_4, \
127 .mask = 0xF, \
128 .dest = ~0, \
129 .src = { ~0, ~0, ~0, ~0 }, \
130 .swizzle = SWIZZLE_IDENTITY_4, \
131 .load_store = { \
132 .op = midgard_op_##name, \
133 .address = address \
134 } \
135 }; \
136 \
137 if (store) \
138 i.src[0] = ssa; \
139 else \
140 i.dest = ssa; \
141 \
142 return i; \
143 }
144
145 #define M_LOAD(name) M_LOAD_STORE(name, false)
146 #define M_STORE(name) M_LOAD_STORE(name, true)
147
148 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
149 * the corresponding Midgard source */
150
151 static midgard_vector_alu_src
152 vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
153 bool half, bool sext)
154 {
155 /* Figure out how many components there are so we can adjust.
156 * Specifically we want to broadcast the last channel so things like
157 * ball2/3 work.
158 */
159
160 if (broadcast_count && src) {
161 uint8_t last_component = src->swizzle[broadcast_count - 1];
162
163 for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) {
164 src->swizzle[c] = last_component;
165 }
166 }
167
168 midgard_vector_alu_src alu_src = {
169 .rep_low = 0,
170 .rep_high = 0,
171 .half = half
172 };
173
174 if (is_int) {
175 alu_src.mod = midgard_int_normal;
176
177 /* Sign/zero-extend if needed */
178
179 if (half) {
180 alu_src.mod = sext ?
181 midgard_int_sign_extend
182 : midgard_int_zero_extend;
183 }
184
185 /* These should have been lowered away */
186 if (src)
187 assert(!(src->abs || src->negate));
188 } else {
189 if (src)
190 alu_src.mod = (src->abs << 0) | (src->negate << 1);
191 }
192
193 return alu_src;
194 }
195
196 /* load/store instructions have both 32-bit and 16-bit variants, depending on
197 * whether we are using vectors composed of highp or mediump. At the moment, we
198 * don't support half-floats -- this requires changes in other parts of the
199 * compiler -- therefore the 16-bit versions are commented out. */
200
201 //M_LOAD(ld_attr_16);
202 M_LOAD(ld_attr_32);
203 //M_LOAD(ld_vary_16);
204 M_LOAD(ld_vary_32);
205 M_LOAD(ld_ubo_int4);
206 M_LOAD(ld_int4);
207 M_STORE(st_int4);
208 M_LOAD(ld_color_buffer_32u);
209 //M_STORE(st_vary_16);
210 M_STORE(st_vary_32);
211 M_LOAD(ld_cubemap_coords);
212 M_LOAD(ld_compute_id);
213
214 static midgard_instruction
215 v_branch(bool conditional, bool invert)
216 {
217 midgard_instruction ins = {
218 .type = TAG_ALU_4,
219 .unit = ALU_ENAB_BRANCH,
220 .compact_branch = true,
221 .branch = {
222 .conditional = conditional,
223 .invert_conditional = invert
224 },
225 .dest = ~0,
226 .src = { ~0, ~0, ~0, ~0 },
227 };
228
229 return ins;
230 }
231
232 static midgard_branch_extended
233 midgard_create_branch_extended( midgard_condition cond,
234 midgard_jmp_writeout_op op,
235 unsigned dest_tag,
236 signed quadword_offset)
237 {
238 /* The condition code is actually a LUT describing a function to
239 * combine multiple condition codes. However, we only support a single
240 * condition code at the moment, so we just duplicate over a bunch of
241 * times. */
242
243 uint16_t duplicated_cond =
244 (cond << 14) |
245 (cond << 12) |
246 (cond << 10) |
247 (cond << 8) |
248 (cond << 6) |
249 (cond << 4) |
250 (cond << 2) |
251 (cond << 0);
252
253 midgard_branch_extended branch = {
254 .op = op,
255 .dest_tag = dest_tag,
256 .offset = quadword_offset,
257 .cond = duplicated_cond
258 };
259
260 return branch;
261 }
262
263 static void
264 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
265 {
266 ins->has_constants = true;
267 memcpy(&ins->constants, constants, 16);
268 }
269
270 static int
271 glsl_type_size(const struct glsl_type *type, bool bindless)
272 {
273 return glsl_count_attribute_slots(type, false);
274 }
275
276 /* Lower fdot2 to a vector multiplication followed by channel addition */
277 static void
278 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
279 {
280 if (alu->op != nir_op_fdot2)
281 return;
282
283 b->cursor = nir_before_instr(&alu->instr);
284
285 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
286 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
287
288 nir_ssa_def *product = nir_fmul(b, src0, src1);
289
290 nir_ssa_def *sum = nir_fadd(b,
291 nir_channel(b, product, 0),
292 nir_channel(b, product, 1));
293
294 /* Replace the fdot2 with this sum */
295 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
296 }
297
298 static int
299 midgard_sysval_for_ssbo(nir_intrinsic_instr *instr)
300 {
301 /* This is way too meta */
302 bool is_store = instr->intrinsic == nir_intrinsic_store_ssbo;
303 unsigned idx_idx = is_store ? 1 : 0;
304
305 nir_src index = instr->src[idx_idx];
306 assert(nir_src_is_const(index));
307 uint32_t uindex = nir_src_as_uint(index);
308
309 return PAN_SYSVAL(SSBO, uindex);
310 }
311
312 static int
313 midgard_sysval_for_sampler(nir_intrinsic_instr *instr)
314 {
315 /* TODO: indirect samplers !!! */
316 nir_src index = instr->src[0];
317 assert(nir_src_is_const(index));
318 uint32_t uindex = nir_src_as_uint(index);
319
320 return PAN_SYSVAL(SAMPLER, uindex);
321 }
322
323 static int
324 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
325 {
326 switch (instr->intrinsic) {
327 case nir_intrinsic_load_viewport_scale:
328 return PAN_SYSVAL_VIEWPORT_SCALE;
329 case nir_intrinsic_load_viewport_offset:
330 return PAN_SYSVAL_VIEWPORT_OFFSET;
331 case nir_intrinsic_load_num_work_groups:
332 return PAN_SYSVAL_NUM_WORK_GROUPS;
333 case nir_intrinsic_load_ssbo:
334 case nir_intrinsic_store_ssbo:
335 return midgard_sysval_for_ssbo(instr);
336 case nir_intrinsic_load_sampler_lod_parameters_pan:
337 return midgard_sysval_for_sampler(instr);
338 default:
339 return ~0;
340 }
341 }
342
343 static int sysval_for_instr(compiler_context *ctx, nir_instr *instr,
344 unsigned *dest)
345 {
346 nir_intrinsic_instr *intr;
347 nir_dest *dst = NULL;
348 nir_tex_instr *tex;
349 int sysval = -1;
350
351 bool is_store = false;
352
353 switch (instr->type) {
354 case nir_instr_type_intrinsic:
355 intr = nir_instr_as_intrinsic(instr);
356 sysval = midgard_nir_sysval_for_intrinsic(intr);
357 dst = &intr->dest;
358 is_store |= intr->intrinsic == nir_intrinsic_store_ssbo;
359 break;
360 case nir_instr_type_tex:
361 tex = nir_instr_as_tex(instr);
362 if (tex->op != nir_texop_txs)
363 break;
364
365 sysval = PAN_SYSVAL(TEXTURE_SIZE,
366 PAN_TXS_SYSVAL_ID(tex->texture_index,
367 nir_tex_instr_dest_size(tex) -
368 (tex->is_array ? 1 : 0),
369 tex->is_array));
370 dst = &tex->dest;
371 break;
372 default:
373 break;
374 }
375
376 if (dest && dst && !is_store)
377 *dest = nir_dest_index(ctx, dst);
378
379 return sysval;
380 }
381
382 static void
383 midgard_nir_assign_sysval_body(compiler_context *ctx, nir_instr *instr)
384 {
385 int sysval;
386
387 sysval = sysval_for_instr(ctx, instr, NULL);
388 if (sysval < 0)
389 return;
390
391 /* We have a sysval load; check if it's already been assigned */
392
393 if (_mesa_hash_table_u64_search(ctx->sysval_to_id, sysval))
394 return;
395
396 /* It hasn't -- so assign it now! */
397
398 unsigned id = ctx->sysval_count++;
399 _mesa_hash_table_u64_insert(ctx->sysval_to_id, sysval, (void *) ((uintptr_t) id + 1));
400 ctx->sysvals[id] = sysval;
401 }
402
403 static void
404 midgard_nir_assign_sysvals(compiler_context *ctx, nir_shader *shader)
405 {
406 ctx->sysval_count = 0;
407
408 nir_foreach_function(function, shader) {
409 if (!function->impl) continue;
410
411 nir_foreach_block(block, function->impl) {
412 nir_foreach_instr_safe(instr, block) {
413 midgard_nir_assign_sysval_body(ctx, instr);
414 }
415 }
416 }
417 }
418
419 static bool
420 midgard_nir_lower_fdot2(nir_shader *shader)
421 {
422 bool progress = false;
423
424 nir_foreach_function(function, shader) {
425 if (!function->impl) continue;
426
427 nir_builder _b;
428 nir_builder *b = &_b;
429 nir_builder_init(b, function->impl);
430
431 nir_foreach_block(block, function->impl) {
432 nir_foreach_instr_safe(instr, block) {
433 if (instr->type != nir_instr_type_alu) continue;
434
435 nir_alu_instr *alu = nir_instr_as_alu(instr);
436 midgard_nir_lower_fdot2_body(b, alu);
437
438 progress |= true;
439 }
440 }
441
442 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
443
444 }
445
446 return progress;
447 }
448
449 /* Midgard can't write depth and stencil separately. It has to happen in a
450 * single store operation containing both. Let's add a panfrost specific
451 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
452 * one.
453 */
454 static bool
455 midgard_nir_lower_zs_store(nir_shader *nir)
456 {
457 if (nir->info.stage != MESA_SHADER_FRAGMENT)
458 return false;
459
460 nir_variable *z_var = NULL, *s_var = NULL;
461
462 nir_foreach_variable(var, &nir->outputs) {
463 if (var->data.location == FRAG_RESULT_DEPTH)
464 z_var = var;
465 else if (var->data.location == FRAG_RESULT_STENCIL)
466 s_var = var;
467 }
468
469 if (!z_var && !s_var)
470 return false;
471
472 bool progress = false;
473
474 nir_foreach_function(function, nir) {
475 if (!function->impl) continue;
476
477 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
478
479 nir_foreach_block(block, function->impl) {
480 nir_foreach_instr_safe(instr, block) {
481 if (instr->type != nir_instr_type_intrinsic)
482 continue;
483
484 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
485 if (intr->intrinsic != nir_intrinsic_store_output)
486 continue;
487
488 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
489 assert(!z_store);
490 z_store = intr;
491 last_store = intr;
492 }
493
494 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
495 assert(!s_store);
496 s_store = intr;
497 last_store = intr;
498 }
499 }
500 }
501
502 if (!z_store && !s_store) continue;
503
504 nir_builder b;
505 nir_builder_init(&b, function->impl);
506
507 b.cursor = nir_before_instr(&last_store->instr);
508
509 nir_ssa_def *zs_store_src;
510
511 if (z_store && s_store) {
512 nir_ssa_def *srcs[2] = {
513 nir_ssa_for_src(&b, z_store->src[0], 1),
514 nir_ssa_for_src(&b, s_store->src[0], 1),
515 };
516
517 zs_store_src = nir_vec(&b, srcs, 2);
518 } else {
519 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
520 }
521
522 nir_intrinsic_instr *zs_store;
523
524 zs_store = nir_intrinsic_instr_create(b.shader,
525 nir_intrinsic_store_zs_output_pan);
526 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
527 zs_store->num_components = z_store && s_store ? 2 : 1;
528 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
529
530 /* Replace the Z and S store by a ZS store */
531 nir_builder_instr_insert(&b, &zs_store->instr);
532
533 if (z_store)
534 nir_instr_remove(&z_store->instr);
535
536 if (s_store)
537 nir_instr_remove(&s_store->instr);
538
539 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
540 progress = true;
541 }
542
543 return progress;
544 }
545
546 /* Flushes undefined values to zero */
547
548 static void
549 optimise_nir(nir_shader *nir, unsigned quirks)
550 {
551 bool progress;
552 unsigned lower_flrp =
553 (nir->options->lower_flrp16 ? 16 : 0) |
554 (nir->options->lower_flrp32 ? 32 : 0) |
555 (nir->options->lower_flrp64 ? 64 : 0);
556
557 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
558 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
559
560 nir_lower_tex_options lower_tex_options = {
561 .lower_txs_lod = true,
562 .lower_txp = ~0,
563 .lower_tex_without_implicit_lod =
564 (quirks & MIDGARD_EXPLICIT_LOD),
565
566 /* TODO: we have native gradient.. */
567 .lower_txd = true,
568 };
569
570 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
571
572 /* Must lower fdot2 after tex is lowered */
573 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
574
575 /* T720 is broken. */
576
577 if (quirks & MIDGARD_BROKEN_LOD)
578 NIR_PASS_V(nir, midgard_nir_lod_errata);
579
580 do {
581 progress = false;
582
583 NIR_PASS(progress, nir, nir_lower_var_copies);
584 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
585
586 NIR_PASS(progress, nir, nir_copy_prop);
587 NIR_PASS(progress, nir, nir_opt_remove_phis);
588 NIR_PASS(progress, nir, nir_opt_dce);
589 NIR_PASS(progress, nir, nir_opt_dead_cf);
590 NIR_PASS(progress, nir, nir_opt_cse);
591 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
592 NIR_PASS(progress, nir, nir_opt_algebraic);
593 NIR_PASS(progress, nir, nir_opt_constant_folding);
594
595 if (lower_flrp != 0) {
596 bool lower_flrp_progress = false;
597 NIR_PASS(lower_flrp_progress,
598 nir,
599 nir_lower_flrp,
600 lower_flrp,
601 false /* always_precise */,
602 nir->options->lower_ffma);
603 if (lower_flrp_progress) {
604 NIR_PASS(progress, nir,
605 nir_opt_constant_folding);
606 progress = true;
607 }
608
609 /* Nothing should rematerialize any flrps, so we only
610 * need to do this lowering once.
611 */
612 lower_flrp = 0;
613 }
614
615 NIR_PASS(progress, nir, nir_opt_undef);
616 NIR_PASS(progress, nir, nir_undef_to_zero);
617
618 NIR_PASS(progress, nir, nir_opt_loop_unroll,
619 nir_var_shader_in |
620 nir_var_shader_out |
621 nir_var_function_temp);
622
623 NIR_PASS(progress, nir, nir_opt_vectorize);
624 } while (progress);
625
626 /* Must be run at the end to prevent creation of fsin/fcos ops */
627 NIR_PASS(progress, nir, midgard_nir_scale_trig);
628
629 do {
630 progress = false;
631
632 NIR_PASS(progress, nir, nir_opt_dce);
633 NIR_PASS(progress, nir, nir_opt_algebraic);
634 NIR_PASS(progress, nir, nir_opt_constant_folding);
635 NIR_PASS(progress, nir, nir_copy_prop);
636 } while (progress);
637
638 NIR_PASS(progress, nir, nir_opt_algebraic_late);
639
640 /* We implement booleans as 32-bit 0/~0 */
641 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
642
643 /* Now that booleans are lowered, we can run out late opts */
644 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
645
646 /* Lower mods for float ops only. Integer ops don't support modifiers
647 * (saturate doesn't make sense on integers, neg/abs require dedicated
648 * instructions) */
649
650 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
651 NIR_PASS(progress, nir, nir_copy_prop);
652 NIR_PASS(progress, nir, nir_opt_dce);
653
654 /* Take us out of SSA */
655 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
656 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
657
658 /* We are a vector architecture; write combine where possible */
659 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
660 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
661
662 NIR_PASS(progress, nir, nir_opt_dce);
663 }
664
665 /* Do not actually emit a load; instead, cache the constant for inlining */
666
667 static void
668 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
669 {
670 nir_ssa_def def = instr->def;
671
672 midgard_constants *consts = rzalloc(NULL, midgard_constants);
673
674 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
675
676 #define RAW_CONST_COPY(bits) \
677 nir_const_value_to_array(consts->u##bits, instr->value, \
678 instr->def.num_components, u##bits)
679
680 switch (instr->def.bit_size) {
681 case 64:
682 RAW_CONST_COPY(64);
683 break;
684 case 32:
685 RAW_CONST_COPY(32);
686 break;
687 case 16:
688 RAW_CONST_COPY(16);
689 break;
690 case 8:
691 RAW_CONST_COPY(8);
692 break;
693 default:
694 unreachable("Invalid bit_size for load_const instruction\n");
695 }
696
697 /* Shifted for SSA, +1 for off-by-one */
698 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
699 }
700
701 /* Normally constants are embedded implicitly, but for I/O and such we have to
702 * explicitly emit a move with the constant source */
703
704 static void
705 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
706 {
707 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
708
709 if (constant_value) {
710 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
711 attach_constants(ctx, &ins, constant_value, node + 1);
712 emit_mir_instruction(ctx, ins);
713 }
714 }
715
716 static bool
717 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
718 {
719 unsigned comp = src->swizzle[0];
720
721 for (unsigned c = 1; c < nr_components; ++c) {
722 if (src->swizzle[c] != comp)
723 return true;
724 }
725
726 return false;
727 }
728
729 #define ALU_CASE(nir, _op) \
730 case nir_op_##nir: \
731 op = midgard_alu_op_##_op; \
732 assert(src_bitsize == dst_bitsize); \
733 break;
734
735 #define ALU_CASE_BCAST(nir, _op, count) \
736 case nir_op_##nir: \
737 op = midgard_alu_op_##_op; \
738 broadcast_swizzle = count; \
739 assert(src_bitsize == dst_bitsize); \
740 break;
741 static bool
742 nir_is_fzero_constant(nir_src src)
743 {
744 if (!nir_src_is_const(src))
745 return false;
746
747 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
748 if (nir_src_comp_as_float(src, c) != 0.0)
749 return false;
750 }
751
752 return true;
753 }
754
755 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
756 * special treatment override this anyway. */
757
758 static midgard_reg_mode
759 reg_mode_for_nir(nir_alu_instr *instr)
760 {
761 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
762
763 switch (src_bitsize) {
764 case 8:
765 return midgard_reg_mode_8;
766 case 16:
767 return midgard_reg_mode_16;
768 case 32:
769 return midgard_reg_mode_32;
770 case 64:
771 return midgard_reg_mode_64;
772 default:
773 unreachable("Invalid bit size");
774 }
775 }
776
777 static void
778 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
779 {
780 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
781 * is handled elsewhere */
782
783 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
784 midgard_emit_derivatives(ctx, instr);
785 return;
786 }
787
788 bool is_ssa = instr->dest.dest.is_ssa;
789
790 unsigned dest = nir_dest_index(ctx, &instr->dest.dest);
791 unsigned nr_components = nir_dest_num_components(instr->dest.dest);
792 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
793
794 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
795 * supported. A few do not and are commented for now. Also, there are a
796 * number of NIR ops which Midgard does not support and need to be
797 * lowered, also TODO. This switch block emits the opcode and calling
798 * convention of the Midgard instruction; actual packing is done in
799 * emit_alu below */
800
801 unsigned op;
802
803 /* Number of components valid to check for the instruction (the rest
804 * will be forced to the last), or 0 to use as-is. Relevant as
805 * ball-type instructions have a channel count in NIR but are all vec4
806 * in Midgard */
807
808 unsigned broadcast_swizzle = 0;
809
810 /* What register mode should we operate in? */
811 midgard_reg_mode reg_mode =
812 reg_mode_for_nir(instr);
813
814 /* Do we need a destination override? Used for inline
815 * type conversion */
816
817 midgard_dest_override dest_override =
818 midgard_dest_override_none;
819
820 /* Should we use a smaller respective source and sign-extend? */
821
822 bool half_1 = false, sext_1 = false;
823 bool half_2 = false, sext_2 = false;
824
825 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
826 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
827
828 switch (instr->op) {
829 ALU_CASE(fadd, fadd);
830 ALU_CASE(fmul, fmul);
831 ALU_CASE(fmin, fmin);
832 ALU_CASE(fmax, fmax);
833 ALU_CASE(imin, imin);
834 ALU_CASE(imax, imax);
835 ALU_CASE(umin, umin);
836 ALU_CASE(umax, umax);
837 ALU_CASE(ffloor, ffloor);
838 ALU_CASE(fround_even, froundeven);
839 ALU_CASE(ftrunc, ftrunc);
840 ALU_CASE(fceil, fceil);
841 ALU_CASE(fdot3, fdot3);
842 ALU_CASE(fdot4, fdot4);
843 ALU_CASE(iadd, iadd);
844 ALU_CASE(isub, isub);
845 ALU_CASE(imul, imul);
846
847 /* Zero shoved as second-arg */
848 ALU_CASE(iabs, iabsdiff);
849
850 ALU_CASE(mov, imov);
851
852 ALU_CASE(feq32, feq);
853 ALU_CASE(fne32, fne);
854 ALU_CASE(flt32, flt);
855 ALU_CASE(ieq32, ieq);
856 ALU_CASE(ine32, ine);
857 ALU_CASE(ilt32, ilt);
858 ALU_CASE(ult32, ult);
859
860 /* We don't have a native b2f32 instruction. Instead, like many
861 * GPUs, we exploit booleans as 0/~0 for false/true, and
862 * correspondingly AND
863 * by 1.0 to do the type conversion. For the moment, prime us
864 * to emit:
865 *
866 * iand [whatever], #0
867 *
868 * At the end of emit_alu (as MIR), we'll fix-up the constant
869 */
870
871 ALU_CASE(b2f32, iand);
872 ALU_CASE(b2i32, iand);
873
874 /* Likewise, we don't have a dedicated f2b32 instruction, but
875 * we can do a "not equal to 0.0" test. */
876
877 ALU_CASE(f2b32, fne);
878 ALU_CASE(i2b32, ine);
879
880 ALU_CASE(frcp, frcp);
881 ALU_CASE(frsq, frsqrt);
882 ALU_CASE(fsqrt, fsqrt);
883 ALU_CASE(fexp2, fexp2);
884 ALU_CASE(flog2, flog2);
885
886 ALU_CASE(f2i64, f2i_rtz);
887 ALU_CASE(f2u64, f2u_rtz);
888 ALU_CASE(i2f64, i2f_rtz);
889 ALU_CASE(u2f64, u2f_rtz);
890
891 ALU_CASE(f2i32, f2i_rtz);
892 ALU_CASE(f2u32, f2u_rtz);
893 ALU_CASE(i2f32, i2f_rtz);
894 ALU_CASE(u2f32, u2f_rtz);
895
896 ALU_CASE(f2i16, f2i_rtz);
897 ALU_CASE(f2u16, f2u_rtz);
898 ALU_CASE(i2f16, i2f_rtz);
899 ALU_CASE(u2f16, u2f_rtz);
900
901 ALU_CASE(fsin, fsin);
902 ALU_CASE(fcos, fcos);
903
904 /* We'll set invert */
905 ALU_CASE(inot, imov);
906 ALU_CASE(iand, iand);
907 ALU_CASE(ior, ior);
908 ALU_CASE(ixor, ixor);
909 ALU_CASE(ishl, ishl);
910 ALU_CASE(ishr, iasr);
911 ALU_CASE(ushr, ilsr);
912
913 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
914 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
915 ALU_CASE(b32all_fequal4, fball_eq);
916
917 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
918 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
919 ALU_CASE(b32any_fnequal4, fbany_neq);
920
921 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
922 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
923 ALU_CASE(b32all_iequal4, iball_eq);
924
925 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
926 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
927 ALU_CASE(b32any_inequal4, ibany_neq);
928
929 /* Source mods will be shoved in later */
930 ALU_CASE(fabs, fmov);
931 ALU_CASE(fneg, fmov);
932 ALU_CASE(fsat, fmov);
933
934 /* For size conversion, we use a move. Ideally though we would squash
935 * these ops together; maybe that has to happen after in NIR as part of
936 * propagation...? An earlier algebraic pass ensured we step down by
937 * only / exactly one size. If stepping down, we use a dest override to
938 * reduce the size; if stepping up, we use a larger-sized move with a
939 * half source and a sign/zero-extension modifier */
940
941 case nir_op_i2i8:
942 case nir_op_i2i16:
943 case nir_op_i2i32:
944 case nir_op_i2i64:
945 /* If we end up upscale, we'll need a sign-extend on the
946 * operand (the second argument) */
947
948 sext_2 = true;
949 /* fallthrough */
950 case nir_op_u2u8:
951 case nir_op_u2u16:
952 case nir_op_u2u32:
953 case nir_op_u2u64:
954 case nir_op_f2f16:
955 case nir_op_f2f32:
956 case nir_op_f2f64: {
957 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
958 instr->op == nir_op_f2f64)
959 op = midgard_alu_op_fmov;
960 else
961 op = midgard_alu_op_imov;
962
963 if (dst_bitsize == (src_bitsize * 2)) {
964 /* Converting up */
965 half_2 = true;
966
967 /* Use a greater register mode */
968 reg_mode++;
969 } else if (src_bitsize == (dst_bitsize * 2)) {
970 /* Converting down */
971 dest_override = midgard_dest_override_lower;
972 }
973
974 break;
975 }
976
977 /* For greater-or-equal, we lower to less-or-equal and flip the
978 * arguments */
979
980 case nir_op_fge:
981 case nir_op_fge32:
982 case nir_op_ige32:
983 case nir_op_uge32: {
984 op =
985 instr->op == nir_op_fge ? midgard_alu_op_fle :
986 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
987 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
988 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
989 0;
990
991 /* Swap via temporary */
992 nir_alu_src temp = instr->src[1];
993 instr->src[1] = instr->src[0];
994 instr->src[0] = temp;
995
996 break;
997 }
998
999 case nir_op_b32csel: {
1000 /* Midgard features both fcsel and icsel, depending on
1001 * the type of the arguments/output. However, as long
1002 * as we're careful we can _always_ use icsel and
1003 * _never_ need fcsel, since the latter does additional
1004 * floating-point-specific processing whereas the
1005 * former just moves bits on the wire. It's not obvious
1006 * why these are separate opcodes, save for the ability
1007 * to do things like sat/pos/abs/neg for free */
1008
1009 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
1010 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
1011
1012 /* The condition is the first argument; move the other
1013 * arguments up one to be a binary instruction for
1014 * Midgard with the condition last */
1015
1016 nir_alu_src temp = instr->src[2];
1017
1018 instr->src[2] = instr->src[0];
1019 instr->src[0] = instr->src[1];
1020 instr->src[1] = temp;
1021
1022 break;
1023 }
1024
1025 default:
1026 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
1027 assert(0);
1028 return;
1029 }
1030
1031 /* Midgard can perform certain modifiers on output of an ALU op */
1032 unsigned outmod;
1033
1034 if (midgard_is_integer_out_op(op)) {
1035 outmod = midgard_outmod_int_wrap;
1036 } else {
1037 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
1038 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
1039 }
1040
1041 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
1042
1043 if (instr->op == nir_op_fmax) {
1044 if (nir_is_fzero_constant(instr->src[0].src)) {
1045 op = midgard_alu_op_fmov;
1046 nr_inputs = 1;
1047 outmod = midgard_outmod_pos;
1048 instr->src[0] = instr->src[1];
1049 } else if (nir_is_fzero_constant(instr->src[1].src)) {
1050 op = midgard_alu_op_fmov;
1051 nr_inputs = 1;
1052 outmod = midgard_outmod_pos;
1053 }
1054 }
1055
1056 /* Fetch unit, quirks, etc information */
1057 unsigned opcode_props = alu_opcode_props[op].props;
1058 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
1059
1060 /* src0 will always exist afaik, but src1 will not for 1-argument
1061 * instructions. The latter can only be fetched if the instruction
1062 * needs it, or else we may segfault. */
1063
1064 unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
1065 unsigned src1 = nr_inputs >= 2 ? nir_alu_src_index(ctx, &instr->src[1]) : ~0;
1066 unsigned src2 = nr_inputs == 3 ? nir_alu_src_index(ctx, &instr->src[2]) : ~0;
1067 assert(nr_inputs <= 3);
1068
1069 /* Rather than use the instruction generation helpers, we do it
1070 * ourselves here to avoid the mess */
1071
1072 midgard_instruction ins = {
1073 .type = TAG_ALU_4,
1074 .src = {
1075 quirk_flipped_r24 ? ~0 : src0,
1076 quirk_flipped_r24 ? src0 : src1,
1077 src2,
1078 ~0
1079 },
1080 .dest = dest,
1081 };
1082
1083 nir_alu_src *nirmods[3] = { NULL };
1084
1085 if (nr_inputs >= 2) {
1086 nirmods[0] = &instr->src[0];
1087 nirmods[1] = &instr->src[1];
1088 } else if (nr_inputs == 1) {
1089 nirmods[quirk_flipped_r24] = &instr->src[0];
1090 } else {
1091 assert(0);
1092 }
1093
1094 if (nr_inputs == 3)
1095 nirmods[2] = &instr->src[2];
1096
1097 /* These were lowered to a move, so apply the corresponding mod */
1098
1099 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1100 nir_alu_src *s = nirmods[quirk_flipped_r24];
1101
1102 if (instr->op == nir_op_fneg)
1103 s->negate = !s->negate;
1104
1105 if (instr->op == nir_op_fabs)
1106 s->abs = !s->abs;
1107 }
1108
1109 bool is_int = midgard_is_integer_op(op);
1110
1111 ins.mask = mask_of(nr_components);
1112
1113 midgard_vector_alu alu = {
1114 .op = op,
1115 .reg_mode = reg_mode,
1116 .dest_override = dest_override,
1117 .outmod = outmod,
1118
1119 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)),
1120 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)),
1121 };
1122
1123 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1124
1125 if (!is_ssa)
1126 ins.mask &= instr->dest.write_mask;
1127
1128 for (unsigned m = 0; m < 3; ++m) {
1129 if (!nirmods[m])
1130 continue;
1131
1132 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c)
1133 ins.swizzle[m][c] = nirmods[m]->swizzle[c];
1134
1135 /* Replicate. TODO: remove when vec16 lands */
1136 for (unsigned c = NIR_MAX_VEC_COMPONENTS; c < MIR_VEC_COMPONENTS; ++c)
1137 ins.swizzle[m][c] = nirmods[m]->swizzle[NIR_MAX_VEC_COMPONENTS - 1];
1138 }
1139
1140 if (nr_inputs == 3) {
1141 /* Conditions can't have mods */
1142 assert(!nirmods[2]->abs);
1143 assert(!nirmods[2]->negate);
1144 }
1145
1146 ins.alu = alu;
1147
1148 /* Late fixup for emulated instructions */
1149
1150 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1151 /* Presently, our second argument is an inline #0 constant.
1152 * Switch over to an embedded 1.0 constant (that can't fit
1153 * inline, since we're 32-bit, not 16-bit like the inline
1154 * constants) */
1155
1156 ins.has_inline_constant = false;
1157 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1158 ins.has_constants = true;
1159
1160 if (instr->op == nir_op_b2f32)
1161 ins.constants.f32[0] = 1.0f;
1162 else
1163 ins.constants.i32[0] = 1;
1164
1165 for (unsigned c = 0; c < 16; ++c)
1166 ins.swizzle[1][c] = 0;
1167 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1168 /* Lots of instructions need a 0 plonked in */
1169 ins.has_inline_constant = false;
1170 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1171 ins.has_constants = true;
1172 ins.constants.u32[0] = 0;
1173
1174 for (unsigned c = 0; c < 16; ++c)
1175 ins.swizzle[1][c] = 0;
1176 } else if (instr->op == nir_op_inot) {
1177 ins.invert = true;
1178 }
1179
1180 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1181 /* To avoid duplicating the lookup tables (probably), true LUT
1182 * instructions can only operate as if they were scalars. Lower
1183 * them here by changing the component. */
1184
1185 unsigned orig_mask = ins.mask;
1186
1187 for (int i = 0; i < nr_components; ++i) {
1188 /* Mask the associated component, dropping the
1189 * instruction if needed */
1190
1191 ins.mask = 1 << i;
1192 ins.mask &= orig_mask;
1193
1194 if (!ins.mask)
1195 continue;
1196
1197 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1198 ins.swizzle[0][j] = nirmods[0]->swizzle[i]; /* Pull from the correct component */
1199
1200 emit_mir_instruction(ctx, ins);
1201 }
1202 } else {
1203 emit_mir_instruction(ctx, ins);
1204 }
1205 }
1206
1207 #undef ALU_CASE
1208
1209 static void
1210 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1211 {
1212 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1213 unsigned nir_mask = 0;
1214 unsigned dsize = 0;
1215
1216 if (is_read) {
1217 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1218 dsize = nir_dest_bit_size(intr->dest);
1219 } else {
1220 nir_mask = nir_intrinsic_write_mask(intr);
1221 dsize = 32;
1222 }
1223
1224 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1225 unsigned bytemask = mir_to_bytemask(mir_mode_for_destsize(dsize), nir_mask);
1226 mir_set_bytemask(ins, bytemask);
1227
1228 if (dsize == 64)
1229 ins->load_64 = true;
1230 }
1231
1232 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1233 * optimized) versions of UBO #0 */
1234
1235 static midgard_instruction *
1236 emit_ubo_read(
1237 compiler_context *ctx,
1238 nir_instr *instr,
1239 unsigned dest,
1240 unsigned offset,
1241 nir_src *indirect_offset,
1242 unsigned indirect_shift,
1243 unsigned index)
1244 {
1245 /* TODO: half-floats */
1246
1247 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1248 ins.constants.u32[0] = offset;
1249
1250 if (instr->type == nir_instr_type_intrinsic)
1251 mir_set_intr_mask(instr, &ins, true);
1252
1253 if (indirect_offset) {
1254 ins.src[2] = nir_src_index(ctx, indirect_offset);
1255 ins.load_store.arg_2 = (indirect_shift << 5);
1256 } else {
1257 ins.load_store.arg_2 = 0x1E;
1258 }
1259
1260 ins.load_store.arg_1 = index;
1261
1262 return emit_mir_instruction(ctx, ins);
1263 }
1264
1265 /* SSBO reads are like UBO reads if you squint */
1266
1267 static void
1268 emit_ssbo_access(
1269 compiler_context *ctx,
1270 nir_instr *instr,
1271 bool is_read,
1272 unsigned srcdest,
1273 unsigned offset,
1274 nir_src *indirect_offset,
1275 unsigned index)
1276 {
1277 /* TODO: types */
1278
1279 midgard_instruction ins;
1280
1281 if (is_read)
1282 ins = m_ld_int4(srcdest, offset);
1283 else
1284 ins = m_st_int4(srcdest, offset);
1285
1286 /* SSBO reads use a generic memory read interface, so we need the
1287 * address of the SSBO as the first argument. This is a sysval. */
1288
1289 unsigned addr = make_compiler_temp(ctx);
1290 emit_sysval_read(ctx, instr, addr, 2);
1291
1292 /* The source array:
1293 *
1294 * src[0] = store ? value : unused
1295 * src[1] = arg_1
1296 * src[2] = arg_2
1297 *
1298 * We would like arg_1 = the address and
1299 * arg_2 = the offset.
1300 */
1301
1302 ins.src[1] = addr;
1303
1304 /* TODO: What is this? It looks superficially like a shift << 5, but
1305 * arg_1 doesn't take a shift Should it be E0 or A0? We also need the
1306 * indirect offset. */
1307
1308 if (indirect_offset) {
1309 ins.load_store.arg_1 |= 0xE0;
1310 ins.src[2] = nir_src_index(ctx, indirect_offset);
1311 } else {
1312 ins.load_store.arg_2 = 0x7E;
1313 }
1314
1315 /* TODO: Bounds check */
1316
1317 /* Finally, we emit the direct offset */
1318
1319 ins.load_store.varying_parameters = (offset & 0x1FF) << 1;
1320 ins.load_store.address = (offset >> 9);
1321 mir_set_intr_mask(instr, &ins, is_read);
1322
1323 emit_mir_instruction(ctx, ins);
1324 }
1325
1326 static void
1327 emit_varying_read(
1328 compiler_context *ctx,
1329 unsigned dest, unsigned offset,
1330 unsigned nr_comp, unsigned component,
1331 nir_src *indirect_offset, nir_alu_type type, bool flat)
1332 {
1333 /* XXX: Half-floats? */
1334 /* TODO: swizzle, mask */
1335
1336 midgard_instruction ins = m_ld_vary_32(dest, offset);
1337 ins.mask = mask_of(nr_comp);
1338
1339 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1340 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1341
1342 midgard_varying_parameter p = {
1343 .is_varying = 1,
1344 .interpolation = midgard_interp_default,
1345 .flat = flat,
1346 };
1347
1348 unsigned u;
1349 memcpy(&u, &p, sizeof(p));
1350 ins.load_store.varying_parameters = u;
1351
1352 if (indirect_offset)
1353 ins.src[2] = nir_src_index(ctx, indirect_offset);
1354 else
1355 ins.load_store.arg_2 = 0x1E;
1356
1357 ins.load_store.arg_1 = 0x9E;
1358
1359 /* Use the type appropriate load */
1360 switch (type) {
1361 case nir_type_uint:
1362 case nir_type_bool:
1363 ins.load_store.op = midgard_op_ld_vary_32u;
1364 break;
1365 case nir_type_int:
1366 ins.load_store.op = midgard_op_ld_vary_32i;
1367 break;
1368 case nir_type_float:
1369 ins.load_store.op = midgard_op_ld_vary_32;
1370 break;
1371 default:
1372 unreachable("Attempted to load unknown type");
1373 break;
1374 }
1375
1376 emit_mir_instruction(ctx, ins);
1377 }
1378
1379 static void
1380 emit_attr_read(
1381 compiler_context *ctx,
1382 unsigned dest, unsigned offset,
1383 unsigned nr_comp, nir_alu_type t)
1384 {
1385 midgard_instruction ins = m_ld_attr_32(dest, offset);
1386 ins.load_store.arg_1 = 0x1E;
1387 ins.load_store.arg_2 = 0x1E;
1388 ins.mask = mask_of(nr_comp);
1389
1390 /* Use the type appropriate load */
1391 switch (t) {
1392 case nir_type_uint:
1393 case nir_type_bool:
1394 ins.load_store.op = midgard_op_ld_attr_32u;
1395 break;
1396 case nir_type_int:
1397 ins.load_store.op = midgard_op_ld_attr_32i;
1398 break;
1399 case nir_type_float:
1400 ins.load_store.op = midgard_op_ld_attr_32;
1401 break;
1402 default:
1403 unreachable("Attempted to load unknown type");
1404 break;
1405 }
1406
1407 emit_mir_instruction(ctx, ins);
1408 }
1409
1410 void
1411 emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override,
1412 unsigned nr_components)
1413 {
1414 unsigned dest = 0;
1415
1416 /* Figure out which uniform this is */
1417 int sysval = sysval_for_instr(ctx, instr, &dest);
1418 void *val = _mesa_hash_table_u64_search(ctx->sysval_to_id, sysval);
1419
1420 if (dest_override >= 0)
1421 dest = dest_override;
1422
1423 /* Sysvals are prefix uniforms */
1424 unsigned uniform = ((uintptr_t) val) - 1;
1425
1426 /* Emit the read itself -- this is never indirect */
1427 midgard_instruction *ins =
1428 emit_ubo_read(ctx, instr, dest, uniform * 16, NULL, 0, 0);
1429
1430 ins->mask = mask_of(nr_components);
1431 }
1432
1433 static unsigned
1434 compute_builtin_arg(nir_op op)
1435 {
1436 switch (op) {
1437 case nir_intrinsic_load_work_group_id:
1438 return 0x14;
1439 case nir_intrinsic_load_local_invocation_id:
1440 return 0x10;
1441 default:
1442 unreachable("Invalid compute paramater loaded");
1443 }
1444 }
1445
1446 static void
1447 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1448 {
1449 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1450
1451 midgard_instruction *br = ctx->writeout_branch[rt];
1452
1453 assert(!br);
1454
1455 emit_explicit_constant(ctx, src, src);
1456
1457 struct midgard_instruction ins =
1458 v_branch(false, false);
1459
1460 ins.writeout = true;
1461
1462 /* Add dependencies */
1463 ins.src[0] = src;
1464 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1465 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1466
1467 /* Emit the branch */
1468 br = emit_mir_instruction(ctx, ins);
1469 schedule_barrier(ctx);
1470 ctx->writeout_branch[rt] = br;
1471
1472 /* Push our current location = current block count - 1 = where we'll
1473 * jump to. Maybe a bit too clever for my own good */
1474
1475 br->branch.target_block = ctx->block_count - 1;
1476 }
1477
1478 static void
1479 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1480 {
1481 unsigned reg = nir_dest_index(ctx, &instr->dest);
1482 midgard_instruction ins = m_ld_compute_id(reg, 0);
1483 ins.mask = mask_of(3);
1484 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1485 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1486 emit_mir_instruction(ctx, ins);
1487 }
1488
1489 static unsigned
1490 vertex_builtin_arg(nir_op op)
1491 {
1492 switch (op) {
1493 case nir_intrinsic_load_vertex_id:
1494 return PAN_VERTEX_ID;
1495 case nir_intrinsic_load_instance_id:
1496 return PAN_INSTANCE_ID;
1497 default:
1498 unreachable("Invalid vertex builtin");
1499 }
1500 }
1501
1502 static void
1503 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1504 {
1505 unsigned reg = nir_dest_index(ctx, &instr->dest);
1506 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1507 }
1508
1509 static void
1510 emit_control_barrier(compiler_context *ctx)
1511 {
1512 midgard_instruction ins = {
1513 .type = TAG_TEXTURE_4,
1514 .src = { ~0, ~0, ~0, ~0 },
1515 .texture = {
1516 .op = TEXTURE_OP_BARRIER,
1517
1518 /* TODO: optimize */
1519 .barrier_buffer = 1,
1520 .barrier_shared = 1
1521 }
1522 };
1523
1524 emit_mir_instruction(ctx, ins);
1525 }
1526
1527 static const nir_variable *
1528 search_var(struct exec_list *vars, unsigned driver_loc)
1529 {
1530 nir_foreach_variable(var, vars) {
1531 if (var->data.driver_location == driver_loc)
1532 return var;
1533 }
1534
1535 return NULL;
1536 }
1537
1538 static void
1539 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1540 {
1541 unsigned offset = 0, reg;
1542
1543 switch (instr->intrinsic) {
1544 case nir_intrinsic_discard_if:
1545 case nir_intrinsic_discard: {
1546 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1547 struct midgard_instruction discard = v_branch(conditional, false);
1548 discard.branch.target_type = TARGET_DISCARD;
1549
1550 if (conditional)
1551 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1552
1553 emit_mir_instruction(ctx, discard);
1554 schedule_barrier(ctx);
1555
1556 break;
1557 }
1558
1559 case nir_intrinsic_load_uniform:
1560 case nir_intrinsic_load_ubo:
1561 case nir_intrinsic_load_ssbo:
1562 case nir_intrinsic_load_input:
1563 case nir_intrinsic_load_interpolated_input: {
1564 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1565 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1566 bool is_ssbo = instr->intrinsic == nir_intrinsic_load_ssbo;
1567 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1568 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1569
1570 /* Get the base type of the intrinsic */
1571 /* TODO: Infer type? Does it matter? */
1572 nir_alu_type t =
1573 (is_ubo || is_ssbo) ? nir_type_uint :
1574 (is_interp) ? nir_type_float :
1575 nir_intrinsic_type(instr);
1576
1577 t = nir_alu_type_get_base_type(t);
1578
1579 if (!(is_ubo || is_ssbo)) {
1580 offset = nir_intrinsic_base(instr);
1581 }
1582
1583 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1584
1585 nir_src *src_offset = nir_get_io_offset_src(instr);
1586
1587 bool direct = nir_src_is_const(*src_offset);
1588 nir_src *indirect_offset = direct ? NULL : src_offset;
1589
1590 if (direct)
1591 offset += nir_src_as_uint(*src_offset);
1592
1593 /* We may need to apply a fractional offset */
1594 int component = (is_flat || is_interp) ?
1595 nir_intrinsic_component(instr) : 0;
1596 reg = nir_dest_index(ctx, &instr->dest);
1597
1598 if (is_uniform && !ctx->is_blend) {
1599 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysval_count + offset) * 16, indirect_offset, 4, 0);
1600 } else if (is_ubo) {
1601 nir_src index = instr->src[0];
1602
1603 /* TODO: Is indirect block number possible? */
1604 assert(nir_src_is_const(index));
1605
1606 uint32_t uindex = nir_src_as_uint(index) + 1;
1607 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1608 } else if (is_ssbo) {
1609 nir_src index = instr->src[0];
1610 assert(nir_src_is_const(index));
1611 uint32_t uindex = nir_src_as_uint(index);
1612
1613 emit_ssbo_access(ctx, &instr->instr, true, reg, offset, indirect_offset, uindex);
1614 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1615 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1616 } else if (ctx->is_blend) {
1617 /* For blend shaders, load the input color, which is
1618 * preloaded to r0 */
1619
1620 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1621 emit_mir_instruction(ctx, move);
1622 schedule_barrier(ctx);
1623 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1624 emit_attr_read(ctx, reg, offset, nr_comp, t);
1625 } else {
1626 DBG("Unknown load\n");
1627 assert(0);
1628 }
1629
1630 break;
1631 }
1632
1633 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1634 case nir_intrinsic_load_barycentric_pixel:
1635 case nir_intrinsic_load_barycentric_centroid:
1636 break;
1637
1638 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1639
1640 case nir_intrinsic_load_raw_output_pan:
1641 case nir_intrinsic_load_output_u8_as_fp16_pan:
1642 reg = nir_dest_index(ctx, &instr->dest);
1643 assert(ctx->is_blend);
1644
1645 /* T720 and below use different blend opcodes with slightly
1646 * different semantics than T760 and up */
1647
1648 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1649 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1650
1651 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1652 ld.load_store.op = old_blend ?
1653 midgard_op_ld_color_buffer_u8_as_fp16_old :
1654 midgard_op_ld_color_buffer_u8_as_fp16;
1655
1656 if (old_blend) {
1657 ld.load_store.address = 1;
1658 ld.load_store.arg_2 = 0x1E;
1659 }
1660
1661 for (unsigned c = 2; c < 16; ++c)
1662 ld.swizzle[0][c] = 0;
1663 }
1664
1665 emit_mir_instruction(ctx, ld);
1666 break;
1667
1668 case nir_intrinsic_load_blend_const_color_rgba: {
1669 assert(ctx->is_blend);
1670 reg = nir_dest_index(ctx, &instr->dest);
1671
1672 /* Blend constants are embedded directly in the shader and
1673 * patched in, so we use some magic routing */
1674
1675 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1676 ins.has_constants = true;
1677 ins.has_blend_constant = true;
1678 emit_mir_instruction(ctx, ins);
1679 break;
1680 }
1681
1682 case nir_intrinsic_store_zs_output_pan: {
1683 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1684 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1685 MIDGARD_ZS_RT);
1686
1687 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1688
1689 if (!nir_intrinsic_component(instr))
1690 br->writeout_depth = true;
1691 if (nir_intrinsic_component(instr) ||
1692 instr->num_components)
1693 br->writeout_stencil = true;
1694 assert(br->writeout_depth | br->writeout_stencil);
1695 break;
1696 }
1697
1698 case nir_intrinsic_store_output:
1699 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1700
1701 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1702
1703 reg = nir_src_index(ctx, &instr->src[0]);
1704
1705 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1706 const nir_variable *var;
1707 enum midgard_rt_id rt;
1708
1709 var = search_var(&ctx->nir->outputs,
1710 nir_intrinsic_base(instr));
1711 assert(var);
1712 if (var->data.location == FRAG_RESULT_COLOR)
1713 rt = MIDGARD_COLOR_RT0;
1714 else if (var->data.location >= FRAG_RESULT_DATA0)
1715 rt = MIDGARD_COLOR_RT0 + var->data.location -
1716 FRAG_RESULT_DATA0;
1717 else
1718 assert(0);
1719
1720 emit_fragment_store(ctx, reg, rt);
1721 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1722 /* We should have been vectorized, though we don't
1723 * currently check that st_vary is emitted only once
1724 * per slot (this is relevant, since there's not a mask
1725 * parameter available on the store [set to 0 by the
1726 * blob]). We do respect the component by adjusting the
1727 * swizzle. If this is a constant source, we'll need to
1728 * emit that explicitly. */
1729
1730 emit_explicit_constant(ctx, reg, reg);
1731
1732 unsigned dst_component = nir_intrinsic_component(instr);
1733 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1734
1735 midgard_instruction st = m_st_vary_32(reg, offset);
1736 st.load_store.arg_1 = 0x9E;
1737 st.load_store.arg_2 = 0x1E;
1738
1739 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1740 case nir_type_uint:
1741 case nir_type_bool:
1742 st.load_store.op = midgard_op_st_vary_32u;
1743 break;
1744 case nir_type_int:
1745 st.load_store.op = midgard_op_st_vary_32i;
1746 break;
1747 case nir_type_float:
1748 st.load_store.op = midgard_op_st_vary_32;
1749 break;
1750 default:
1751 unreachable("Attempted to store unknown type");
1752 break;
1753 }
1754
1755 /* nir_intrinsic_component(store_intr) encodes the
1756 * destination component start. Source component offset
1757 * adjustment is taken care of in
1758 * install_registers_instr(), when offset_swizzle() is
1759 * called.
1760 */
1761 unsigned src_component = COMPONENT_X;
1762
1763 assert(nr_comp > 0);
1764 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1765 st.swizzle[0][i] = src_component;
1766 if (i >= dst_component && i < dst_component + nr_comp - 1)
1767 src_component++;
1768 }
1769
1770 emit_mir_instruction(ctx, st);
1771 } else {
1772 DBG("Unknown store\n");
1773 assert(0);
1774 }
1775
1776 break;
1777
1778 /* Special case of store_output for lowered blend shaders */
1779 case nir_intrinsic_store_raw_output_pan:
1780 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1781 reg = nir_src_index(ctx, &instr->src[0]);
1782
1783 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1784 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1785 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1786 * of:
1787 *
1788 * imov r0.xyzw, r0.xxxx
1789 */
1790
1791 unsigned expanded = make_compiler_temp(ctx);
1792
1793 midgard_instruction splatter = v_mov(reg, expanded);
1794
1795 for (unsigned c = 0; c < 16; ++c)
1796 splatter.swizzle[1][c] = 0;
1797
1798 emit_mir_instruction(ctx, splatter);
1799 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1800 } else
1801 emit_fragment_store(ctx, reg, ctx->blend_rt);
1802
1803 break;
1804
1805 case nir_intrinsic_store_ssbo:
1806 assert(nir_src_is_const(instr->src[1]));
1807
1808 bool direct_offset = nir_src_is_const(instr->src[2]);
1809 offset = direct_offset ? nir_src_as_uint(instr->src[2]) : 0;
1810 nir_src *indirect_offset = direct_offset ? NULL : &instr->src[2];
1811 reg = nir_src_index(ctx, &instr->src[0]);
1812
1813 uint32_t uindex = nir_src_as_uint(instr->src[1]);
1814
1815 emit_explicit_constant(ctx, reg, reg);
1816 emit_ssbo_access(ctx, &instr->instr, false, reg, offset, indirect_offset, uindex);
1817 break;
1818
1819 case nir_intrinsic_load_viewport_scale:
1820 case nir_intrinsic_load_viewport_offset:
1821 case nir_intrinsic_load_num_work_groups:
1822 case nir_intrinsic_load_sampler_lod_parameters_pan:
1823 emit_sysval_read(ctx, &instr->instr, ~0, 3);
1824 break;
1825
1826 case nir_intrinsic_load_work_group_id:
1827 case nir_intrinsic_load_local_invocation_id:
1828 emit_compute_builtin(ctx, instr);
1829 break;
1830
1831 case nir_intrinsic_load_vertex_id:
1832 case nir_intrinsic_load_instance_id:
1833 emit_vertex_builtin(ctx, instr);
1834 break;
1835
1836 case nir_intrinsic_memory_barrier_buffer:
1837 case nir_intrinsic_memory_barrier_shared:
1838 break;
1839
1840 case nir_intrinsic_control_barrier:
1841 schedule_barrier(ctx);
1842 emit_control_barrier(ctx);
1843 schedule_barrier(ctx);
1844 break;
1845
1846 default:
1847 printf ("Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1848 assert(0);
1849 break;
1850 }
1851 }
1852
1853 static unsigned
1854 midgard_tex_format(enum glsl_sampler_dim dim)
1855 {
1856 switch (dim) {
1857 case GLSL_SAMPLER_DIM_1D:
1858 case GLSL_SAMPLER_DIM_BUF:
1859 return MALI_TEX_1D;
1860
1861 case GLSL_SAMPLER_DIM_2D:
1862 case GLSL_SAMPLER_DIM_EXTERNAL:
1863 case GLSL_SAMPLER_DIM_RECT:
1864 return MALI_TEX_2D;
1865
1866 case GLSL_SAMPLER_DIM_3D:
1867 return MALI_TEX_3D;
1868
1869 case GLSL_SAMPLER_DIM_CUBE:
1870 return MALI_TEX_CUBE;
1871
1872 default:
1873 DBG("Unknown sampler dim type\n");
1874 assert(0);
1875 return 0;
1876 }
1877 }
1878
1879 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1880 * was successful */
1881
1882 static bool
1883 pan_attach_constant_bias(
1884 compiler_context *ctx,
1885 nir_src lod,
1886 midgard_texture_word *word)
1887 {
1888 /* To attach as constant, it has to *be* constant */
1889
1890 if (!nir_src_is_const(lod))
1891 return false;
1892
1893 float f = nir_src_as_float(lod);
1894
1895 /* Break into fixed-point */
1896 signed lod_int = f;
1897 float lod_frac = f - lod_int;
1898
1899 /* Carry over negative fractions */
1900 if (lod_frac < 0.0) {
1901 lod_int--;
1902 lod_frac += 1.0;
1903 }
1904
1905 /* Encode */
1906 word->bias = float_to_ubyte(lod_frac);
1907 word->bias_int = lod_int;
1908
1909 return true;
1910 }
1911
1912 static enum mali_sampler_type
1913 midgard_sampler_type(nir_alu_type t) {
1914 switch (nir_alu_type_get_base_type(t))
1915 {
1916 case nir_type_float:
1917 return MALI_SAMPLER_FLOAT;
1918 case nir_type_int:
1919 return MALI_SAMPLER_SIGNED;
1920 case nir_type_uint:
1921 return MALI_SAMPLER_UNSIGNED;
1922 default:
1923 unreachable("Unknown sampler type");
1924 }
1925 }
1926
1927 static void
1928 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1929 unsigned midgard_texop)
1930 {
1931 /* TODO */
1932 //assert (!instr->sampler);
1933 //assert (!instr->texture_array_size);
1934
1935 int texture_index = instr->texture_index;
1936 int sampler_index = texture_index;
1937
1938 /* No helper to build texture words -- we do it all here */
1939 midgard_instruction ins = {
1940 .type = TAG_TEXTURE_4,
1941 .mask = 0xF,
1942 .dest = nir_dest_index(ctx, &instr->dest),
1943 .src = { ~0, ~0, ~0, ~0 },
1944 .swizzle = SWIZZLE_IDENTITY_4,
1945 .texture = {
1946 .op = midgard_texop,
1947 .format = midgard_tex_format(instr->sampler_dim),
1948 .texture_handle = texture_index,
1949 .sampler_handle = sampler_index,
1950
1951 /* TODO: half */
1952 .in_reg_full = 1,
1953 .out_full = 1,
1954
1955 .sampler_type = midgard_sampler_type(instr->dest_type),
1956 .shadow = instr->is_shadow,
1957 }
1958 };
1959
1960 /* We may need a temporary for the coordinate */
1961
1962 bool needs_temp_coord =
1963 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1964 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1965 (instr->is_shadow);
1966
1967 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1968
1969 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1970 int index = nir_src_index(ctx, &instr->src[i].src);
1971 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1972
1973 switch (instr->src[i].src_type) {
1974 case nir_tex_src_coord: {
1975 emit_explicit_constant(ctx, index, index);
1976
1977 unsigned coord_mask = mask_of(instr->coord_components);
1978
1979 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1980
1981 if (flip_zw)
1982 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1983
1984 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1985 /* texelFetch is undefined on samplerCube */
1986 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1987
1988 /* For cubemaps, we use a special ld/st op to
1989 * select the face and copy the xy into the
1990 * texture register */
1991
1992 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1993 ld.src[1] = index;
1994 ld.mask = 0x3; /* xy */
1995 ld.load_store.arg_1 = 0x20;
1996 ld.swizzle[1][3] = COMPONENT_X;
1997 emit_mir_instruction(ctx, ld);
1998
1999 /* xyzw -> xyxx */
2000 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
2001 ins.swizzle[1][3] = COMPONENT_X;
2002 } else if (needs_temp_coord) {
2003 /* mov coord_temp, coords */
2004 midgard_instruction mov = v_mov(index, coords);
2005 mov.mask = coord_mask;
2006
2007 if (flip_zw)
2008 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
2009
2010 emit_mir_instruction(ctx, mov);
2011 } else {
2012 coords = index;
2013 }
2014
2015 ins.src[1] = coords;
2016
2017 /* Texelfetch coordinates uses all four elements
2018 * (xyz/index) regardless of texture dimensionality,
2019 * which means it's necessary to zero the unused
2020 * components to keep everything happy */
2021
2022 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
2023 /* mov index.zw, #0, or generalized */
2024 midgard_instruction mov =
2025 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
2026 mov.has_constants = true;
2027 mov.mask = coord_mask ^ 0xF;
2028 emit_mir_instruction(ctx, mov);
2029 }
2030
2031 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
2032 /* Array component in w but NIR wants it in z,
2033 * but if we have a temp coord we already fixed
2034 * that up */
2035
2036 if (nr_components == 3) {
2037 ins.swizzle[1][2] = COMPONENT_Z;
2038 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
2039 } else if (nr_components == 2) {
2040 ins.swizzle[1][2] =
2041 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
2042 ins.swizzle[1][3] = COMPONENT_X;
2043 } else
2044 unreachable("Invalid texture 2D components");
2045 }
2046
2047 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
2048 /* We zeroed */
2049 ins.swizzle[1][2] = COMPONENT_Z;
2050 ins.swizzle[1][3] = COMPONENT_W;
2051 }
2052
2053 break;
2054 }
2055
2056 case nir_tex_src_bias:
2057 case nir_tex_src_lod: {
2058 /* Try as a constant if we can */
2059
2060 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
2061 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
2062 break;
2063
2064 ins.texture.lod_register = true;
2065 ins.src[2] = index;
2066
2067 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2068 ins.swizzle[2][c] = COMPONENT_X;
2069
2070 emit_explicit_constant(ctx, index, index);
2071
2072 break;
2073 };
2074
2075 case nir_tex_src_offset: {
2076 ins.texture.offset_register = true;
2077 ins.src[3] = index;
2078
2079 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2080 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
2081
2082 emit_explicit_constant(ctx, index, index);
2083 break;
2084 };
2085
2086 case nir_tex_src_comparator: {
2087 unsigned comp = COMPONENT_Z;
2088
2089 /* mov coord_temp.foo, coords */
2090 midgard_instruction mov = v_mov(index, coords);
2091 mov.mask = 1 << comp;
2092
2093 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
2094 mov.swizzle[1][i] = COMPONENT_X;
2095
2096 emit_mir_instruction(ctx, mov);
2097 break;
2098 }
2099
2100 default: {
2101 printf ("Unknown texture source type: %d\n", instr->src[i].src_type);
2102 assert(0);
2103 }
2104 }
2105 }
2106
2107 emit_mir_instruction(ctx, ins);
2108
2109 /* Used for .cont and .last hinting */
2110 ctx->texture_op_count++;
2111 }
2112
2113 static void
2114 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2115 {
2116 switch (instr->op) {
2117 case nir_texop_tex:
2118 case nir_texop_txb:
2119 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2120 break;
2121 case nir_texop_txl:
2122 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2123 break;
2124 case nir_texop_txf:
2125 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2126 break;
2127 case nir_texop_txs:
2128 emit_sysval_read(ctx, &instr->instr, ~0, 4);
2129 break;
2130 default: {
2131 printf ("Unhandled texture op: %d\n", instr->op);
2132 assert(0);
2133 }
2134 }
2135 }
2136
2137 static void
2138 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2139 {
2140 switch (instr->type) {
2141 case nir_jump_break: {
2142 /* Emit a branch out of the loop */
2143 struct midgard_instruction br = v_branch(false, false);
2144 br.branch.target_type = TARGET_BREAK;
2145 br.branch.target_break = ctx->current_loop_depth;
2146 emit_mir_instruction(ctx, br);
2147 break;
2148 }
2149
2150 default:
2151 DBG("Unknown jump type %d\n", instr->type);
2152 break;
2153 }
2154 }
2155
2156 static void
2157 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2158 {
2159 switch (instr->type) {
2160 case nir_instr_type_load_const:
2161 emit_load_const(ctx, nir_instr_as_load_const(instr));
2162 break;
2163
2164 case nir_instr_type_intrinsic:
2165 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2166 break;
2167
2168 case nir_instr_type_alu:
2169 emit_alu(ctx, nir_instr_as_alu(instr));
2170 break;
2171
2172 case nir_instr_type_tex:
2173 emit_tex(ctx, nir_instr_as_tex(instr));
2174 break;
2175
2176 case nir_instr_type_jump:
2177 emit_jump(ctx, nir_instr_as_jump(instr));
2178 break;
2179
2180 case nir_instr_type_ssa_undef:
2181 /* Spurious */
2182 break;
2183
2184 default:
2185 DBG("Unhandled instruction type\n");
2186 break;
2187 }
2188 }
2189
2190
2191 /* ALU instructions can inline or embed constants, which decreases register
2192 * pressure and saves space. */
2193
2194 #define CONDITIONAL_ATTACH(idx) { \
2195 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2196 \
2197 if (entry) { \
2198 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2199 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2200 } \
2201 }
2202
2203 static void
2204 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2205 {
2206 mir_foreach_instr_in_block(block, alu) {
2207 /* Other instructions cannot inline constants */
2208 if (alu->type != TAG_ALU_4) continue;
2209 if (alu->compact_branch) continue;
2210
2211 /* If there is already a constant here, we can do nothing */
2212 if (alu->has_constants) continue;
2213
2214 CONDITIONAL_ATTACH(0);
2215
2216 if (!alu->has_constants) {
2217 CONDITIONAL_ATTACH(1)
2218 } else if (!alu->inline_constant) {
2219 /* Corner case: _two_ vec4 constants, for instance with a
2220 * csel. For this case, we can only use a constant
2221 * register for one, we'll have to emit a move for the
2222 * other. Note, if both arguments are constants, then
2223 * necessarily neither argument depends on the value of
2224 * any particular register. As the destination register
2225 * will be wiped, that means we can spill the constant
2226 * to the destination register.
2227 */
2228
2229 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2230 unsigned scratch = alu->dest;
2231
2232 if (entry) {
2233 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2234 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2235
2236 /* Set the source */
2237 alu->src[1] = scratch;
2238
2239 /* Inject us -before- the last instruction which set r31 */
2240 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2241 }
2242 }
2243 }
2244 }
2245
2246 /* Being a little silly with the names, but returns the op that is the bitwise
2247 * inverse of the op with the argument switched. I.e. (f and g are
2248 * contrapositives):
2249 *
2250 * f(a, b) = ~g(b, a)
2251 *
2252 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
2253 *
2254 * f(a, b) = ~g(b, a)
2255 * ~f(a, b) = g(b, a)
2256 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
2257 * f(a, b) = h(a, b)
2258 *
2259 * Thus we define this function in pairs.
2260 */
2261
2262 static inline midgard_alu_op
2263 mir_contrapositive(midgard_alu_op op)
2264 {
2265 switch (op) {
2266 case midgard_alu_op_flt:
2267 return midgard_alu_op_fle;
2268 case midgard_alu_op_fle:
2269 return midgard_alu_op_flt;
2270
2271 case midgard_alu_op_ilt:
2272 return midgard_alu_op_ile;
2273 case midgard_alu_op_ile:
2274 return midgard_alu_op_ilt;
2275
2276 default:
2277 unreachable("No known contrapositive");
2278 }
2279 }
2280
2281 /* Midgard supports two types of constants, embedded constants (128-bit) and
2282 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2283 * constants can be demoted to inline constants, for space savings and
2284 * sometimes a performance boost */
2285
2286 static void
2287 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2288 {
2289 mir_foreach_instr_in_block(block, ins) {
2290 if (!ins->has_constants) continue;
2291 if (ins->has_inline_constant) continue;
2292
2293 /* Blend constants must not be inlined by definition */
2294 if (ins->has_blend_constant) continue;
2295
2296 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2297 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2298 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2299
2300 if (!(is_16 || is_32))
2301 continue;
2302
2303 /* src1 cannot be an inline constant due to encoding
2304 * restrictions. So, if possible we try to flip the arguments
2305 * in that case */
2306
2307 int op = ins->alu.op;
2308
2309 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2310 bool flip = alu_opcode_props[op].props & OP_COMMUTES;
2311
2312 switch (op) {
2313 /* Conditionals can be inverted */
2314 case midgard_alu_op_flt:
2315 case midgard_alu_op_ilt:
2316 case midgard_alu_op_fle:
2317 case midgard_alu_op_ile:
2318 ins->alu.op = mir_contrapositive(ins->alu.op);
2319 ins->invert = true;
2320 flip = true;
2321 break;
2322
2323 case midgard_alu_op_fcsel:
2324 case midgard_alu_op_icsel:
2325 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
2326 default:
2327 break;
2328 }
2329
2330 if (flip)
2331 mir_flip(ins);
2332 }
2333
2334 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2335 /* Extract the source information */
2336
2337 midgard_vector_alu_src *src;
2338 int q = ins->alu.src2;
2339 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2340 src = m;
2341
2342 /* Component is from the swizzle. Take a nonzero component */
2343 assert(ins->mask);
2344 unsigned first_comp = ffs(ins->mask) - 1;
2345 unsigned component = ins->swizzle[1][first_comp];
2346
2347 /* Scale constant appropriately, if we can legally */
2348 uint16_t scaled_constant = 0;
2349
2350 if (is_16) {
2351 scaled_constant = ins->constants.u16[component];
2352 } else if (midgard_is_integer_op(op)) {
2353 scaled_constant = ins->constants.u32[component];
2354
2355 /* Constant overflow after resize */
2356 if (scaled_constant != ins->constants.u32[component])
2357 continue;
2358 } else {
2359 float original = ins->constants.f32[component];
2360 scaled_constant = _mesa_float_to_half(original);
2361
2362 /* Check for loss of precision. If this is
2363 * mediump, we don't care, but for a highp
2364 * shader, we need to pay attention. NIR
2365 * doesn't yet tell us which mode we're in!
2366 * Practically this prevents most constants
2367 * from being inlined, sadly. */
2368
2369 float fp32 = _mesa_half_to_float(scaled_constant);
2370
2371 if (fp32 != original)
2372 continue;
2373 }
2374
2375 /* We don't know how to handle these with a constant */
2376
2377 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2378 DBG("Bailing inline constant...\n");
2379 continue;
2380 }
2381
2382 /* Make sure that the constant is not itself a vector
2383 * by checking if all accessed values are the same. */
2384
2385 const midgard_constants *cons = &ins->constants;
2386 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2387
2388 bool is_vector = false;
2389 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2390
2391 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2392 /* We only care if this component is actually used */
2393 if (!(mask & (1 << c)))
2394 continue;
2395
2396 uint32_t test = is_16 ?
2397 cons->u16[ins->swizzle[1][c]] :
2398 cons->u32[ins->swizzle[1][c]];
2399
2400 if (test != value) {
2401 is_vector = true;
2402 break;
2403 }
2404 }
2405
2406 if (is_vector)
2407 continue;
2408
2409 /* Get rid of the embedded constant */
2410 ins->has_constants = false;
2411 ins->src[1] = ~0;
2412 ins->has_inline_constant = true;
2413 ins->inline_constant = scaled_constant;
2414 }
2415 }
2416 }
2417
2418 /* Dead code elimination for branches at the end of a block - only one branch
2419 * per block is legal semantically */
2420
2421 static void
2422 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2423 {
2424 bool branched = false;
2425
2426 mir_foreach_instr_in_block_safe(block, ins) {
2427 if (!midgard_is_branch_unit(ins->unit)) continue;
2428
2429 if (branched)
2430 mir_remove_instruction(ins);
2431
2432 branched = true;
2433 }
2434 }
2435
2436 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2437 * the move can be propagated away entirely */
2438
2439 static bool
2440 mir_compose_float_outmod(midgard_outmod_float *outmod, midgard_outmod_float comp)
2441 {
2442 /* Nothing to do */
2443 if (comp == midgard_outmod_none)
2444 return true;
2445
2446 if (*outmod == midgard_outmod_none) {
2447 *outmod = comp;
2448 return true;
2449 }
2450
2451 /* TODO: Compose rules */
2452 return false;
2453 }
2454
2455 static bool
2456 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
2457 {
2458 bool progress = false;
2459
2460 mir_foreach_instr_in_block_safe(block, ins) {
2461 if (ins->type != TAG_ALU_4) continue;
2462 if (ins->alu.op != midgard_alu_op_fmov) continue;
2463 if (ins->alu.outmod != midgard_outmod_pos) continue;
2464
2465 /* TODO: Registers? */
2466 unsigned src = ins->src[1];
2467 if (src & IS_REG) continue;
2468
2469 /* There might be a source modifier, too */
2470 if (mir_nontrivial_source2_mod(ins)) continue;
2471
2472 /* Backpropagate the modifier */
2473 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
2474 if (v->type != TAG_ALU_4) continue;
2475 if (v->dest != src) continue;
2476
2477 /* Can we even take a float outmod? */
2478 if (midgard_is_integer_out_op(v->alu.op)) continue;
2479
2480 midgard_outmod_float temp = v->alu.outmod;
2481 progress |= mir_compose_float_outmod(&temp, ins->alu.outmod);
2482
2483 /* Throw in the towel.. */
2484 if (!progress) break;
2485
2486 /* Otherwise, transfer the modifier */
2487 v->alu.outmod = temp;
2488 ins->alu.outmod = midgard_outmod_none;
2489
2490 break;
2491 }
2492 }
2493
2494 return progress;
2495 }
2496
2497 static unsigned
2498 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2499 {
2500 /* Loop to ourselves */
2501 midgard_instruction *br = ctx->writeout_branch[rt];
2502 struct midgard_instruction ins = v_branch(false, false);
2503 ins.writeout = true;
2504 ins.writeout_depth = br->writeout_depth;
2505 ins.writeout_stencil = br->writeout_stencil;
2506 ins.branch.target_block = ctx->block_count - 1;
2507 ins.constants.u32[0] = br->constants.u32[0];
2508 emit_mir_instruction(ctx, ins);
2509
2510 ctx->current_block->epilogue = true;
2511 schedule_barrier(ctx);
2512 return ins.branch.target_block;
2513 }
2514
2515 static midgard_block *
2516 emit_block(compiler_context *ctx, nir_block *block)
2517 {
2518 midgard_block *this_block = ctx->after_block;
2519 ctx->after_block = NULL;
2520
2521 if (!this_block)
2522 this_block = create_empty_block(ctx);
2523
2524 list_addtail(&this_block->link, &ctx->blocks);
2525
2526 this_block->is_scheduled = false;
2527 ++ctx->block_count;
2528
2529 /* Set up current block */
2530 list_inithead(&this_block->instructions);
2531 ctx->current_block = this_block;
2532
2533 nir_foreach_instr(instr, block) {
2534 emit_instr(ctx, instr);
2535 ++ctx->instruction_count;
2536 }
2537
2538 return this_block;
2539 }
2540
2541 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2542
2543 static void
2544 emit_if(struct compiler_context *ctx, nir_if *nif)
2545 {
2546 midgard_block *before_block = ctx->current_block;
2547
2548 /* Speculatively emit the branch, but we can't fill it in until later */
2549 EMIT(branch, true, true);
2550 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2551 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2552
2553 /* Emit the two subblocks. */
2554 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2555 midgard_block *end_then_block = ctx->current_block;
2556
2557 /* Emit a jump from the end of the then block to the end of the else */
2558 EMIT(branch, false, false);
2559 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2560
2561 /* Emit second block, and check if it's empty */
2562
2563 int else_idx = ctx->block_count;
2564 int count_in = ctx->instruction_count;
2565 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2566 midgard_block *end_else_block = ctx->current_block;
2567 int after_else_idx = ctx->block_count;
2568
2569 /* Now that we have the subblocks emitted, fix up the branches */
2570
2571 assert(then_block);
2572 assert(else_block);
2573
2574 if (ctx->instruction_count == count_in) {
2575 /* The else block is empty, so don't emit an exit jump */
2576 mir_remove_instruction(then_exit);
2577 then_branch->branch.target_block = after_else_idx;
2578 } else {
2579 then_branch->branch.target_block = else_idx;
2580 then_exit->branch.target_block = after_else_idx;
2581 }
2582
2583 /* Wire up the successors */
2584
2585 ctx->after_block = create_empty_block(ctx);
2586
2587 midgard_block_add_successor(before_block, then_block);
2588 midgard_block_add_successor(before_block, else_block);
2589
2590 midgard_block_add_successor(end_then_block, ctx->after_block);
2591 midgard_block_add_successor(end_else_block, ctx->after_block);
2592 }
2593
2594 static void
2595 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2596 {
2597 /* Remember where we are */
2598 midgard_block *start_block = ctx->current_block;
2599
2600 /* Allocate a loop number, growing the current inner loop depth */
2601 int loop_idx = ++ctx->current_loop_depth;
2602
2603 /* Get index from before the body so we can loop back later */
2604 int start_idx = ctx->block_count;
2605
2606 /* Emit the body itself */
2607 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2608
2609 /* Branch back to loop back */
2610 struct midgard_instruction br_back = v_branch(false, false);
2611 br_back.branch.target_block = start_idx;
2612 emit_mir_instruction(ctx, br_back);
2613
2614 /* Mark down that branch in the graph. */
2615 midgard_block_add_successor(start_block, loop_block);
2616 midgard_block_add_successor(ctx->current_block, loop_block);
2617
2618 /* Find the index of the block about to follow us (note: we don't add
2619 * one; blocks are 0-indexed so we get a fencepost problem) */
2620 int break_block_idx = ctx->block_count;
2621
2622 /* Fix up the break statements we emitted to point to the right place,
2623 * now that we can allocate a block number for them */
2624 ctx->after_block = create_empty_block(ctx);
2625
2626 list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
2627 mir_foreach_instr_in_block(block, ins) {
2628 if (ins->type != TAG_ALU_4) continue;
2629 if (!ins->compact_branch) continue;
2630
2631 /* We found a branch -- check the type to see if we need to do anything */
2632 if (ins->branch.target_type != TARGET_BREAK) continue;
2633
2634 /* It's a break! Check if it's our break */
2635 if (ins->branch.target_break != loop_idx) continue;
2636
2637 /* Okay, cool, we're breaking out of this loop.
2638 * Rewrite from a break to a goto */
2639
2640 ins->branch.target_type = TARGET_GOTO;
2641 ins->branch.target_block = break_block_idx;
2642
2643 midgard_block_add_successor(block, ctx->after_block);
2644 }
2645 }
2646
2647 /* Now that we've finished emitting the loop, free up the depth again
2648 * so we play nice with recursion amid nested loops */
2649 --ctx->current_loop_depth;
2650
2651 /* Dump loop stats */
2652 ++ctx->loop_count;
2653 }
2654
2655 static midgard_block *
2656 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2657 {
2658 midgard_block *start_block = NULL;
2659
2660 foreach_list_typed(nir_cf_node, node, node, list) {
2661 switch (node->type) {
2662 case nir_cf_node_block: {
2663 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2664
2665 if (!start_block)
2666 start_block = block;
2667
2668 break;
2669 }
2670
2671 case nir_cf_node_if:
2672 emit_if(ctx, nir_cf_node_as_if(node));
2673 break;
2674
2675 case nir_cf_node_loop:
2676 emit_loop(ctx, nir_cf_node_as_loop(node));
2677 break;
2678
2679 case nir_cf_node_function:
2680 assert(0);
2681 break;
2682 }
2683 }
2684
2685 return start_block;
2686 }
2687
2688 /* Due to lookahead, we need to report the first tag executed in the command
2689 * stream and in branch targets. An initial block might be empty, so iterate
2690 * until we find one that 'works' */
2691
2692 static unsigned
2693 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2694 {
2695 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2696
2697 mir_foreach_block_from(ctx, initial_block, v) {
2698 if (v->quadword_count) {
2699 midgard_bundle *initial_bundle =
2700 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2701
2702 return initial_bundle->tag;
2703 }
2704 }
2705
2706 /* Default to a tag 1 which will break from the shader, in case we jump
2707 * to the exit block (i.e. `return` in a compute shader) */
2708
2709 return 1;
2710 }
2711
2712 static unsigned
2713 pan_format_from_nir_base(nir_alu_type base)
2714 {
2715 switch (base) {
2716 case nir_type_int:
2717 return MALI_FORMAT_SINT;
2718 case nir_type_uint:
2719 case nir_type_bool:
2720 return MALI_FORMAT_UINT;
2721 case nir_type_float:
2722 return MALI_CHANNEL_FLOAT;
2723 default:
2724 unreachable("Invalid base");
2725 }
2726 }
2727
2728 static unsigned
2729 pan_format_from_nir_size(nir_alu_type base, unsigned size)
2730 {
2731 if (base == nir_type_float) {
2732 switch (size) {
2733 case 16: return MALI_FORMAT_SINT;
2734 case 32: return MALI_FORMAT_UNORM;
2735 default:
2736 unreachable("Invalid float size for format");
2737 }
2738 } else {
2739 switch (size) {
2740 case 1:
2741 case 8: return MALI_CHANNEL_8;
2742 case 16: return MALI_CHANNEL_16;
2743 case 32: return MALI_CHANNEL_32;
2744 default:
2745 unreachable("Invalid int size for format");
2746 }
2747 }
2748 }
2749
2750 static enum mali_format
2751 pan_format_from_glsl(const struct glsl_type *type)
2752 {
2753 enum glsl_base_type glsl_base = glsl_get_base_type(glsl_without_array(type));
2754 nir_alu_type t = nir_get_nir_type_for_glsl_base_type(glsl_base);
2755
2756 unsigned base = nir_alu_type_get_base_type(t);
2757 unsigned size = nir_alu_type_get_type_size(t);
2758
2759 return pan_format_from_nir_base(base) |
2760 pan_format_from_nir_size(base, size) |
2761 MALI_NR_CHANNELS(4);
2762 }
2763
2764 /* For each fragment writeout instruction, generate a writeout loop to
2765 * associate with it */
2766
2767 static void
2768 mir_add_writeout_loops(compiler_context *ctx)
2769 {
2770 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2771 midgard_instruction *br = ctx->writeout_branch[rt];
2772 if (!br) continue;
2773
2774 unsigned popped = br->branch.target_block;
2775 midgard_block_add_successor(mir_get_block(ctx, popped - 1), ctx->current_block);
2776 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2777
2778 /* If we have more RTs, we'll need to restore back after our
2779 * loop terminates */
2780
2781 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2782 midgard_instruction uncond = v_branch(false, false);
2783 uncond.branch.target_block = popped;
2784 emit_mir_instruction(ctx, uncond);
2785 midgard_block_add_successor(ctx->current_block, mir_get_block(ctx, popped));
2786 schedule_barrier(ctx);
2787 } else {
2788 /* We're last, so we can terminate here */
2789 br->last_writeout = true;
2790 }
2791 }
2792 }
2793
2794 int
2795 midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2796 {
2797 struct util_dynarray *compiled = &program->compiled;
2798
2799 midgard_debug = debug_get_option_midgard_debug();
2800
2801 /* TODO: Bound against what? */
2802 compiler_context *ctx = rzalloc(NULL, compiler_context);
2803
2804 ctx->nir = nir;
2805 ctx->stage = nir->info.stage;
2806 ctx->is_blend = is_blend;
2807 ctx->alpha_ref = program->alpha_ref;
2808 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2809 ctx->quirks = midgard_get_quirks(gpu_id);
2810
2811 /* Start off with a safe cutoff, allowing usage of all 16 work
2812 * registers. Later, we'll promote uniform reads to uniform registers
2813 * if we determine it is beneficial to do so */
2814 ctx->uniform_cutoff = 8;
2815
2816 /* Initialize at a global (not block) level hash tables */
2817
2818 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2819 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2820 ctx->sysval_to_id = _mesa_hash_table_u64_create(NULL);
2821
2822 /* Record the varying mapping for the command stream's bookkeeping */
2823
2824 struct exec_list *varyings =
2825 ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs;
2826
2827 unsigned max_varying = 0;
2828 nir_foreach_variable(var, varyings) {
2829 unsigned loc = var->data.driver_location;
2830 unsigned sz = glsl_type_size(var->type, FALSE);
2831
2832 for (int c = 0; c < sz; ++c) {
2833 program->varyings[loc + c] = var->data.location + c;
2834 program->varying_type[loc + c] = pan_format_from_glsl(var->type);
2835 max_varying = MAX2(max_varying, loc + c);
2836 }
2837 }
2838
2839 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2840 * (so we don't accidentally duplicate the epilogue since mesa/st has
2841 * messed with our I/O quite a bit already) */
2842
2843 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2844
2845 if (ctx->stage == MESA_SHADER_VERTEX) {
2846 NIR_PASS_V(nir, nir_lower_viewport_transform);
2847 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2848 }
2849
2850 NIR_PASS_V(nir, nir_lower_var_copies);
2851 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2852 NIR_PASS_V(nir, nir_split_var_copies);
2853 NIR_PASS_V(nir, nir_lower_var_copies);
2854 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2855 NIR_PASS_V(nir, nir_lower_var_copies);
2856 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2857
2858 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2859 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2860
2861 /* Optimisation passes */
2862
2863 optimise_nir(nir, ctx->quirks);
2864
2865 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2866 nir_print_shader(nir, stdout);
2867 }
2868
2869 /* Assign sysvals and counts, now that we're sure
2870 * (post-optimisation) */
2871
2872 midgard_nir_assign_sysvals(ctx, nir);
2873
2874 program->uniform_count = nir->num_uniforms;
2875 program->sysval_count = ctx->sysval_count;
2876 memcpy(program->sysvals, ctx->sysvals, sizeof(ctx->sysvals[0]) * ctx->sysval_count);
2877
2878 nir_foreach_function(func, nir) {
2879 if (!func->impl)
2880 continue;
2881
2882 list_inithead(&ctx->blocks);
2883 ctx->block_count = 0;
2884 ctx->func = func;
2885
2886 emit_cf_list(ctx, &func->impl->body);
2887 break; /* TODO: Multi-function shaders */
2888 }
2889
2890 util_dynarray_init(compiled, NULL);
2891
2892 /* Per-block lowering before opts */
2893
2894 mir_foreach_block(ctx, block) {
2895 inline_alu_constants(ctx, block);
2896 midgard_opt_promote_fmov(ctx, block);
2897 embedded_to_inline_constant(ctx, block);
2898 }
2899 /* MIR-level optimizations */
2900
2901 bool progress = false;
2902
2903 do {
2904 progress = false;
2905
2906 mir_foreach_block(ctx, block) {
2907 progress |= midgard_opt_pos_propagate(ctx, block);
2908 progress |= midgard_opt_copy_prop(ctx, block);
2909 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2910 progress |= midgard_opt_combine_projection(ctx, block);
2911 progress |= midgard_opt_varying_projection(ctx, block);
2912 progress |= midgard_opt_not_propagate(ctx, block);
2913 progress |= midgard_opt_fuse_src_invert(ctx, block);
2914 progress |= midgard_opt_fuse_dest_invert(ctx, block);
2915 progress |= midgard_opt_csel_invert(ctx, block);
2916 progress |= midgard_opt_drop_cmp_invert(ctx, block);
2917 progress |= midgard_opt_invert_branch(ctx, block);
2918 }
2919 } while (progress);
2920
2921 mir_foreach_block(ctx, block) {
2922 midgard_lower_invert(ctx, block);
2923 midgard_lower_derivatives(ctx, block);
2924 }
2925
2926 /* Nested control-flow can result in dead branches at the end of the
2927 * block. This messes with our analysis and is just dead code, so cull
2928 * them */
2929 mir_foreach_block(ctx, block) {
2930 midgard_opt_cull_dead_branch(ctx, block);
2931 }
2932
2933 /* Ensure we were lowered */
2934 mir_foreach_instr_global(ctx, ins) {
2935 assert(!ins->invert);
2936 }
2937
2938 if (ctx->stage == MESA_SHADER_FRAGMENT)
2939 mir_add_writeout_loops(ctx);
2940
2941 /* Schedule! */
2942 midgard_schedule_program(ctx);
2943 mir_ra(ctx);
2944
2945 /* Now that all the bundles are scheduled and we can calculate block
2946 * sizes, emit actual branch instructions rather than placeholders */
2947
2948 int br_block_idx = 0;
2949
2950 mir_foreach_block(ctx, block) {
2951 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2952 for (int c = 0; c < bundle->instruction_count; ++c) {
2953 midgard_instruction *ins = bundle->instructions[c];
2954
2955 if (!midgard_is_branch_unit(ins->unit)) continue;
2956
2957 /* Parse some basic branch info */
2958 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2959 bool is_conditional = ins->branch.conditional;
2960 bool is_inverted = ins->branch.invert_conditional;
2961 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2962 bool is_writeout = ins->writeout;
2963
2964 /* Determine the block we're jumping to */
2965 int target_number = ins->branch.target_block;
2966
2967 /* Report the destination tag */
2968 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2969
2970 /* Count up the number of quadwords we're
2971 * jumping over = number of quadwords until
2972 * (br_block_idx, target_number) */
2973
2974 int quadword_offset = 0;
2975
2976 if (is_discard) {
2977 /* Ignored */
2978 } else if (target_number > br_block_idx) {
2979 /* Jump forward */
2980
2981 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2982 midgard_block *blk = mir_get_block(ctx, idx);
2983 assert(blk);
2984
2985 quadword_offset += blk->quadword_count;
2986 }
2987 } else {
2988 /* Jump backwards */
2989
2990 for (int idx = br_block_idx; idx >= target_number; --idx) {
2991 midgard_block *blk = mir_get_block(ctx, idx);
2992 assert(blk);
2993
2994 quadword_offset -= blk->quadword_count;
2995 }
2996 }
2997
2998 /* Unconditional extended branches (far jumps)
2999 * have issues, so we always use a conditional
3000 * branch, setting the condition to always for
3001 * unconditional. For compact unconditional
3002 * branches, cond isn't used so it doesn't
3003 * matter what we pick. */
3004
3005 midgard_condition cond =
3006 !is_conditional ? midgard_condition_always :
3007 is_inverted ? midgard_condition_false :
3008 midgard_condition_true;
3009
3010 midgard_jmp_writeout_op op =
3011 is_discard ? midgard_jmp_writeout_op_discard :
3012 is_writeout ? midgard_jmp_writeout_op_writeout :
3013 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
3014 midgard_jmp_writeout_op_branch_cond;
3015
3016 if (!is_compact) {
3017 midgard_branch_extended branch =
3018 midgard_create_branch_extended(
3019 cond, op,
3020 dest_tag,
3021 quadword_offset);
3022
3023 memcpy(&ins->branch_extended, &branch, sizeof(branch));
3024 } else if (is_conditional || is_discard) {
3025 midgard_branch_cond branch = {
3026 .op = op,
3027 .dest_tag = dest_tag,
3028 .offset = quadword_offset,
3029 .cond = cond
3030 };
3031
3032 assert(branch.offset == quadword_offset);
3033
3034 memcpy(&ins->br_compact, &branch, sizeof(branch));
3035 } else {
3036 assert(op == midgard_jmp_writeout_op_branch_uncond);
3037
3038 midgard_branch_uncond branch = {
3039 .op = op,
3040 .dest_tag = dest_tag,
3041 .offset = quadword_offset,
3042 .unknown = 1
3043 };
3044
3045 assert(branch.offset == quadword_offset);
3046
3047 memcpy(&ins->br_compact, &branch, sizeof(branch));
3048 }
3049 }
3050 }
3051
3052 ++br_block_idx;
3053 }
3054
3055 /* Emit flat binary from the instruction arrays. Iterate each block in
3056 * sequence. Save instruction boundaries such that lookahead tags can
3057 * be assigned easily */
3058
3059 /* Cache _all_ bundles in source order for lookahead across failed branches */
3060
3061 int bundle_count = 0;
3062 mir_foreach_block(ctx, block) {
3063 bundle_count += block->bundles.size / sizeof(midgard_bundle);
3064 }
3065 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
3066 int bundle_idx = 0;
3067 mir_foreach_block(ctx, block) {
3068 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
3069 source_order_bundles[bundle_idx++] = bundle;
3070 }
3071 }
3072
3073 int current_bundle = 0;
3074
3075 /* Midgard prefetches instruction types, so during emission we
3076 * need to lookahead. Unless this is the last instruction, in
3077 * which we return 1. */
3078
3079 mir_foreach_block(ctx, block) {
3080 mir_foreach_bundle_in_block(block, bundle) {
3081 int lookahead = 1;
3082
3083 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
3084 lookahead = source_order_bundles[current_bundle + 1]->tag;
3085
3086 emit_binary_bundle(ctx, bundle, compiled, lookahead);
3087 ++current_bundle;
3088 }
3089
3090 /* TODO: Free deeper */
3091 //util_dynarray_fini(&block->instructions);
3092 }
3093
3094 free(source_order_bundles);
3095
3096 /* Report the very first tag executed */
3097 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
3098
3099 /* Deal with off-by-one related to the fencepost problem */
3100 program->work_register_count = ctx->work_registers + 1;
3101 program->uniform_cutoff = ctx->uniform_cutoff;
3102
3103 program->blend_patch_offset = ctx->blend_constant_offset;
3104 program->tls_size = ctx->tls_size;
3105
3106 if (midgard_debug & MIDGARD_DBG_SHADERS)
3107 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
3108
3109 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
3110 unsigned nr_bundles = 0, nr_ins = 0;
3111
3112 /* Count instructions and bundles */
3113
3114 mir_foreach_block(ctx, block) {
3115 nr_bundles += util_dynarray_num_elements(
3116 &block->bundles, midgard_bundle);
3117
3118 mir_foreach_bundle_in_block(block, bun)
3119 nr_ins += bun->instruction_count;
3120 }
3121
3122 /* Calculate thread count. There are certain cutoffs by
3123 * register count for thread count */
3124
3125 unsigned nr_registers = program->work_register_count;
3126
3127 unsigned nr_threads =
3128 (nr_registers <= 4) ? 4 :
3129 (nr_registers <= 8) ? 2 :
3130 1;
3131
3132 /* Dump stats */
3133
3134 fprintf(stderr, "shader%d - %s shader: "
3135 "%u inst, %u bundles, %u quadwords, "
3136 "%u registers, %u threads, %u loops, "
3137 "%u:%u spills:fills\n",
3138 SHADER_DB_COUNT++,
3139 gl_shader_stage_name(ctx->stage),
3140 nr_ins, nr_bundles, ctx->quadword_count,
3141 nr_registers, nr_threads,
3142 ctx->loop_count,
3143 ctx->spills, ctx->fills);
3144 }
3145
3146 ralloc_free(ctx);
3147
3148 return 0;
3149 }