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pan/mdg: Remove goofy 16-bit comment
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) \
118 i.src[0] = ssa; \
119 else \
120 i.dest = ssa; \
121 \
122 return i; \
123 }
124
125 #define M_LOAD(name) M_LOAD_STORE(name, false)
126 #define M_STORE(name) M_LOAD_STORE(name, true)
127
128 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
129 * the corresponding Midgard source */
130
131 static midgard_vector_alu_src
132 vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
133 bool half, bool sext)
134 {
135 /* Figure out how many components there are so we can adjust.
136 * Specifically we want to broadcast the last channel so things like
137 * ball2/3 work.
138 */
139
140 if (broadcast_count && src) {
141 uint8_t last_component = src->swizzle[broadcast_count - 1];
142
143 for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) {
144 src->swizzle[c] = last_component;
145 }
146 }
147
148 midgard_vector_alu_src alu_src = {
149 .rep_low = 0,
150 .rep_high = 0,
151 .half = half
152 };
153
154 if (is_int) {
155 alu_src.mod = midgard_int_normal;
156
157 /* Sign/zero-extend if needed */
158
159 if (half) {
160 alu_src.mod = sext ?
161 midgard_int_sign_extend
162 : midgard_int_zero_extend;
163 }
164
165 /* These should have been lowered away */
166 if (src)
167 assert(!(src->abs || src->negate));
168 } else {
169 if (src)
170 alu_src.mod = (src->abs << 0) | (src->negate << 1);
171 }
172
173 return alu_src;
174 }
175
176 M_LOAD(ld_attr_32);
177 M_LOAD(ld_vary_32);
178 M_LOAD(ld_ubo_int4);
179 M_LOAD(ld_int4);
180 M_STORE(st_int4);
181 M_LOAD(ld_color_buffer_32u);
182 M_STORE(st_vary_32);
183 M_LOAD(ld_cubemap_coords);
184 M_LOAD(ld_compute_id);
185
186 static midgard_instruction
187 v_branch(bool conditional, bool invert)
188 {
189 midgard_instruction ins = {
190 .type = TAG_ALU_4,
191 .unit = ALU_ENAB_BRANCH,
192 .compact_branch = true,
193 .branch = {
194 .conditional = conditional,
195 .invert_conditional = invert
196 },
197 .dest = ~0,
198 .src = { ~0, ~0, ~0, ~0 },
199 };
200
201 return ins;
202 }
203
204 static midgard_branch_extended
205 midgard_create_branch_extended( midgard_condition cond,
206 midgard_jmp_writeout_op op,
207 unsigned dest_tag,
208 signed quadword_offset)
209 {
210 /* The condition code is actually a LUT describing a function to
211 * combine multiple condition codes. However, we only support a single
212 * condition code at the moment, so we just duplicate over a bunch of
213 * times. */
214
215 uint16_t duplicated_cond =
216 (cond << 14) |
217 (cond << 12) |
218 (cond << 10) |
219 (cond << 8) |
220 (cond << 6) |
221 (cond << 4) |
222 (cond << 2) |
223 (cond << 0);
224
225 midgard_branch_extended branch = {
226 .op = op,
227 .dest_tag = dest_tag,
228 .offset = quadword_offset,
229 .cond = duplicated_cond
230 };
231
232 return branch;
233 }
234
235 static void
236 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
237 {
238 ins->has_constants = true;
239 memcpy(&ins->constants, constants, 16);
240 }
241
242 static int
243 glsl_type_size(const struct glsl_type *type, bool bindless)
244 {
245 return glsl_count_attribute_slots(type, false);
246 }
247
248 /* Lower fdot2 to a vector multiplication followed by channel addition */
249 static void
250 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
251 {
252 if (alu->op != nir_op_fdot2)
253 return;
254
255 b->cursor = nir_before_instr(&alu->instr);
256
257 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
258 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
259
260 nir_ssa_def *product = nir_fmul(b, src0, src1);
261
262 nir_ssa_def *sum = nir_fadd(b,
263 nir_channel(b, product, 0),
264 nir_channel(b, product, 1));
265
266 /* Replace the fdot2 with this sum */
267 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
268 }
269
270 static bool
271 midgard_nir_lower_fdot2(nir_shader *shader)
272 {
273 bool progress = false;
274
275 nir_foreach_function(function, shader) {
276 if (!function->impl) continue;
277
278 nir_builder _b;
279 nir_builder *b = &_b;
280 nir_builder_init(b, function->impl);
281
282 nir_foreach_block(block, function->impl) {
283 nir_foreach_instr_safe(instr, block) {
284 if (instr->type != nir_instr_type_alu) continue;
285
286 nir_alu_instr *alu = nir_instr_as_alu(instr);
287 midgard_nir_lower_fdot2_body(b, alu);
288
289 progress |= true;
290 }
291 }
292
293 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
294
295 }
296
297 return progress;
298 }
299
300 /* Midgard can't write depth and stencil separately. It has to happen in a
301 * single store operation containing both. Let's add a panfrost specific
302 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
303 * one.
304 */
305 static bool
306 midgard_nir_lower_zs_store(nir_shader *nir)
307 {
308 if (nir->info.stage != MESA_SHADER_FRAGMENT)
309 return false;
310
311 nir_variable *z_var = NULL, *s_var = NULL;
312
313 nir_foreach_variable(var, &nir->outputs) {
314 if (var->data.location == FRAG_RESULT_DEPTH)
315 z_var = var;
316 else if (var->data.location == FRAG_RESULT_STENCIL)
317 s_var = var;
318 }
319
320 if (!z_var && !s_var)
321 return false;
322
323 bool progress = false;
324
325 nir_foreach_function(function, nir) {
326 if (!function->impl) continue;
327
328 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
329
330 nir_foreach_block(block, function->impl) {
331 nir_foreach_instr_safe(instr, block) {
332 if (instr->type != nir_instr_type_intrinsic)
333 continue;
334
335 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
336 if (intr->intrinsic != nir_intrinsic_store_output)
337 continue;
338
339 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
340 assert(!z_store);
341 z_store = intr;
342 last_store = intr;
343 }
344
345 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
346 assert(!s_store);
347 s_store = intr;
348 last_store = intr;
349 }
350 }
351 }
352
353 if (!z_store && !s_store) continue;
354
355 nir_builder b;
356 nir_builder_init(&b, function->impl);
357
358 b.cursor = nir_before_instr(&last_store->instr);
359
360 nir_ssa_def *zs_store_src;
361
362 if (z_store && s_store) {
363 nir_ssa_def *srcs[2] = {
364 nir_ssa_for_src(&b, z_store->src[0], 1),
365 nir_ssa_for_src(&b, s_store->src[0], 1),
366 };
367
368 zs_store_src = nir_vec(&b, srcs, 2);
369 } else {
370 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
371 }
372
373 nir_intrinsic_instr *zs_store;
374
375 zs_store = nir_intrinsic_instr_create(b.shader,
376 nir_intrinsic_store_zs_output_pan);
377 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
378 zs_store->num_components = z_store && s_store ? 2 : 1;
379 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
380
381 /* Replace the Z and S store by a ZS store */
382 nir_builder_instr_insert(&b, &zs_store->instr);
383
384 if (z_store)
385 nir_instr_remove(&z_store->instr);
386
387 if (s_store)
388 nir_instr_remove(&s_store->instr);
389
390 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
391 progress = true;
392 }
393
394 return progress;
395 }
396
397 /* Flushes undefined values to zero */
398
399 static void
400 optimise_nir(nir_shader *nir, unsigned quirks)
401 {
402 bool progress;
403 unsigned lower_flrp =
404 (nir->options->lower_flrp16 ? 16 : 0) |
405 (nir->options->lower_flrp32 ? 32 : 0) |
406 (nir->options->lower_flrp64 ? 64 : 0);
407
408 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
409 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
410
411 nir_lower_tex_options lower_tex_options = {
412 .lower_txs_lod = true,
413 .lower_txp = ~0,
414 .lower_tex_without_implicit_lod =
415 (quirks & MIDGARD_EXPLICIT_LOD),
416
417 /* TODO: we have native gradient.. */
418 .lower_txd = true,
419 };
420
421 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
422
423 /* Must lower fdot2 after tex is lowered */
424 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
425
426 /* T720 is broken. */
427
428 if (quirks & MIDGARD_BROKEN_LOD)
429 NIR_PASS_V(nir, midgard_nir_lod_errata);
430
431 do {
432 progress = false;
433
434 NIR_PASS(progress, nir, nir_lower_var_copies);
435 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
436
437 NIR_PASS(progress, nir, nir_copy_prop);
438 NIR_PASS(progress, nir, nir_opt_remove_phis);
439 NIR_PASS(progress, nir, nir_opt_dce);
440 NIR_PASS(progress, nir, nir_opt_dead_cf);
441 NIR_PASS(progress, nir, nir_opt_cse);
442 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
443 NIR_PASS(progress, nir, nir_opt_algebraic);
444 NIR_PASS(progress, nir, nir_opt_constant_folding);
445
446 if (lower_flrp != 0) {
447 bool lower_flrp_progress = false;
448 NIR_PASS(lower_flrp_progress,
449 nir,
450 nir_lower_flrp,
451 lower_flrp,
452 false /* always_precise */,
453 nir->options->lower_ffma);
454 if (lower_flrp_progress) {
455 NIR_PASS(progress, nir,
456 nir_opt_constant_folding);
457 progress = true;
458 }
459
460 /* Nothing should rematerialize any flrps, so we only
461 * need to do this lowering once.
462 */
463 lower_flrp = 0;
464 }
465
466 NIR_PASS(progress, nir, nir_opt_undef);
467 NIR_PASS(progress, nir, nir_undef_to_zero);
468
469 NIR_PASS(progress, nir, nir_opt_loop_unroll,
470 nir_var_shader_in |
471 nir_var_shader_out |
472 nir_var_function_temp);
473
474 NIR_PASS(progress, nir, nir_opt_vectorize);
475 } while (progress);
476
477 /* Must be run at the end to prevent creation of fsin/fcos ops */
478 NIR_PASS(progress, nir, midgard_nir_scale_trig);
479
480 do {
481 progress = false;
482
483 NIR_PASS(progress, nir, nir_opt_dce);
484 NIR_PASS(progress, nir, nir_opt_algebraic);
485 NIR_PASS(progress, nir, nir_opt_constant_folding);
486 NIR_PASS(progress, nir, nir_copy_prop);
487 } while (progress);
488
489 NIR_PASS(progress, nir, nir_opt_algebraic_late);
490
491 /* We implement booleans as 32-bit 0/~0 */
492 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
493
494 /* Now that booleans are lowered, we can run out late opts */
495 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
496
497 /* Lower mods for float ops only. Integer ops don't support modifiers
498 * (saturate doesn't make sense on integers, neg/abs require dedicated
499 * instructions) */
500
501 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
502 NIR_PASS(progress, nir, nir_copy_prop);
503 NIR_PASS(progress, nir, nir_opt_dce);
504
505 /* Take us out of SSA */
506 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
507 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
508
509 /* We are a vector architecture; write combine where possible */
510 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
511 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
512
513 NIR_PASS(progress, nir, nir_opt_dce);
514 }
515
516 /* Do not actually emit a load; instead, cache the constant for inlining */
517
518 static void
519 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
520 {
521 nir_ssa_def def = instr->def;
522
523 midgard_constants *consts = rzalloc(NULL, midgard_constants);
524
525 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
526
527 #define RAW_CONST_COPY(bits) \
528 nir_const_value_to_array(consts->u##bits, instr->value, \
529 instr->def.num_components, u##bits)
530
531 switch (instr->def.bit_size) {
532 case 64:
533 RAW_CONST_COPY(64);
534 break;
535 case 32:
536 RAW_CONST_COPY(32);
537 break;
538 case 16:
539 RAW_CONST_COPY(16);
540 break;
541 case 8:
542 RAW_CONST_COPY(8);
543 break;
544 default:
545 unreachable("Invalid bit_size for load_const instruction\n");
546 }
547
548 /* Shifted for SSA, +1 for off-by-one */
549 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
550 }
551
552 /* Normally constants are embedded implicitly, but for I/O and such we have to
553 * explicitly emit a move with the constant source */
554
555 static void
556 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
557 {
558 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
559
560 if (constant_value) {
561 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
562 attach_constants(ctx, &ins, constant_value, node + 1);
563 emit_mir_instruction(ctx, ins);
564 }
565 }
566
567 static bool
568 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
569 {
570 unsigned comp = src->swizzle[0];
571
572 for (unsigned c = 1; c < nr_components; ++c) {
573 if (src->swizzle[c] != comp)
574 return true;
575 }
576
577 return false;
578 }
579
580 #define ALU_CASE(nir, _op) \
581 case nir_op_##nir: \
582 op = midgard_alu_op_##_op; \
583 assert(src_bitsize == dst_bitsize); \
584 break;
585
586 #define ALU_CASE_BCAST(nir, _op, count) \
587 case nir_op_##nir: \
588 op = midgard_alu_op_##_op; \
589 broadcast_swizzle = count; \
590 assert(src_bitsize == dst_bitsize); \
591 break;
592 static bool
593 nir_is_fzero_constant(nir_src src)
594 {
595 if (!nir_src_is_const(src))
596 return false;
597
598 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
599 if (nir_src_comp_as_float(src, c) != 0.0)
600 return false;
601 }
602
603 return true;
604 }
605
606 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
607 * special treatment override this anyway. */
608
609 static midgard_reg_mode
610 reg_mode_for_nir(nir_alu_instr *instr)
611 {
612 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
613
614 switch (src_bitsize) {
615 case 8:
616 return midgard_reg_mode_8;
617 case 16:
618 return midgard_reg_mode_16;
619 case 32:
620 return midgard_reg_mode_32;
621 case 64:
622 return midgard_reg_mode_64;
623 default:
624 unreachable("Invalid bit size");
625 }
626 }
627
628 static void
629 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
630 {
631 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
632 * is handled elsewhere */
633
634 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
635 midgard_emit_derivatives(ctx, instr);
636 return;
637 }
638
639 bool is_ssa = instr->dest.dest.is_ssa;
640
641 unsigned dest = nir_dest_index(&instr->dest.dest);
642 unsigned nr_components = nir_dest_num_components(instr->dest.dest);
643 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
644
645 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
646 * supported. A few do not and are commented for now. Also, there are a
647 * number of NIR ops which Midgard does not support and need to be
648 * lowered, also TODO. This switch block emits the opcode and calling
649 * convention of the Midgard instruction; actual packing is done in
650 * emit_alu below */
651
652 unsigned op;
653
654 /* Number of components valid to check for the instruction (the rest
655 * will be forced to the last), or 0 to use as-is. Relevant as
656 * ball-type instructions have a channel count in NIR but are all vec4
657 * in Midgard */
658
659 unsigned broadcast_swizzle = 0;
660
661 /* What register mode should we operate in? */
662 midgard_reg_mode reg_mode =
663 reg_mode_for_nir(instr);
664
665 /* Do we need a destination override? Used for inline
666 * type conversion */
667
668 midgard_dest_override dest_override =
669 midgard_dest_override_none;
670
671 /* Should we use a smaller respective source and sign-extend? */
672
673 bool half_1 = false, sext_1 = false;
674 bool half_2 = false, sext_2 = false;
675
676 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
677 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
678
679 switch (instr->op) {
680 ALU_CASE(fadd, fadd);
681 ALU_CASE(fmul, fmul);
682 ALU_CASE(fmin, fmin);
683 ALU_CASE(fmax, fmax);
684 ALU_CASE(imin, imin);
685 ALU_CASE(imax, imax);
686 ALU_CASE(umin, umin);
687 ALU_CASE(umax, umax);
688 ALU_CASE(ffloor, ffloor);
689 ALU_CASE(fround_even, froundeven);
690 ALU_CASE(ftrunc, ftrunc);
691 ALU_CASE(fceil, fceil);
692 ALU_CASE(fdot3, fdot3);
693 ALU_CASE(fdot4, fdot4);
694 ALU_CASE(iadd, iadd);
695 ALU_CASE(isub, isub);
696 ALU_CASE(imul, imul);
697
698 /* Zero shoved as second-arg */
699 ALU_CASE(iabs, iabsdiff);
700
701 ALU_CASE(mov, imov);
702
703 ALU_CASE(feq32, feq);
704 ALU_CASE(fne32, fne);
705 ALU_CASE(flt32, flt);
706 ALU_CASE(ieq32, ieq);
707 ALU_CASE(ine32, ine);
708 ALU_CASE(ilt32, ilt);
709 ALU_CASE(ult32, ult);
710
711 /* We don't have a native b2f32 instruction. Instead, like many
712 * GPUs, we exploit booleans as 0/~0 for false/true, and
713 * correspondingly AND
714 * by 1.0 to do the type conversion. For the moment, prime us
715 * to emit:
716 *
717 * iand [whatever], #0
718 *
719 * At the end of emit_alu (as MIR), we'll fix-up the constant
720 */
721
722 ALU_CASE(b2f32, iand);
723 ALU_CASE(b2i32, iand);
724
725 /* Likewise, we don't have a dedicated f2b32 instruction, but
726 * we can do a "not equal to 0.0" test. */
727
728 ALU_CASE(f2b32, fne);
729 ALU_CASE(i2b32, ine);
730
731 ALU_CASE(frcp, frcp);
732 ALU_CASE(frsq, frsqrt);
733 ALU_CASE(fsqrt, fsqrt);
734 ALU_CASE(fexp2, fexp2);
735 ALU_CASE(flog2, flog2);
736
737 ALU_CASE(f2i64, f2i_rtz);
738 ALU_CASE(f2u64, f2u_rtz);
739 ALU_CASE(i2f64, i2f_rtz);
740 ALU_CASE(u2f64, u2f_rtz);
741
742 ALU_CASE(f2i32, f2i_rtz);
743 ALU_CASE(f2u32, f2u_rtz);
744 ALU_CASE(i2f32, i2f_rtz);
745 ALU_CASE(u2f32, u2f_rtz);
746
747 ALU_CASE(f2i16, f2i_rtz);
748 ALU_CASE(f2u16, f2u_rtz);
749 ALU_CASE(i2f16, i2f_rtz);
750 ALU_CASE(u2f16, u2f_rtz);
751
752 ALU_CASE(fsin, fsin);
753 ALU_CASE(fcos, fcos);
754
755 /* We'll set invert */
756 ALU_CASE(inot, imov);
757 ALU_CASE(iand, iand);
758 ALU_CASE(ior, ior);
759 ALU_CASE(ixor, ixor);
760 ALU_CASE(ishl, ishl);
761 ALU_CASE(ishr, iasr);
762 ALU_CASE(ushr, ilsr);
763
764 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
765 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
766 ALU_CASE(b32all_fequal4, fball_eq);
767
768 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
769 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
770 ALU_CASE(b32any_fnequal4, fbany_neq);
771
772 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
773 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
774 ALU_CASE(b32all_iequal4, iball_eq);
775
776 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
777 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
778 ALU_CASE(b32any_inequal4, ibany_neq);
779
780 /* Source mods will be shoved in later */
781 ALU_CASE(fabs, fmov);
782 ALU_CASE(fneg, fmov);
783 ALU_CASE(fsat, fmov);
784
785 /* For size conversion, we use a move. Ideally though we would squash
786 * these ops together; maybe that has to happen after in NIR as part of
787 * propagation...? An earlier algebraic pass ensured we step down by
788 * only / exactly one size. If stepping down, we use a dest override to
789 * reduce the size; if stepping up, we use a larger-sized move with a
790 * half source and a sign/zero-extension modifier */
791
792 case nir_op_i2i8:
793 case nir_op_i2i16:
794 case nir_op_i2i32:
795 case nir_op_i2i64:
796 /* If we end up upscale, we'll need a sign-extend on the
797 * operand (the second argument) */
798
799 sext_2 = true;
800 /* fallthrough */
801 case nir_op_u2u8:
802 case nir_op_u2u16:
803 case nir_op_u2u32:
804 case nir_op_u2u64:
805 case nir_op_f2f16:
806 case nir_op_f2f32:
807 case nir_op_f2f64: {
808 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
809 instr->op == nir_op_f2f64)
810 op = midgard_alu_op_fmov;
811 else
812 op = midgard_alu_op_imov;
813
814 if (dst_bitsize == (src_bitsize * 2)) {
815 /* Converting up */
816 half_2 = true;
817
818 /* Use a greater register mode */
819 reg_mode++;
820 } else if (src_bitsize == (dst_bitsize * 2)) {
821 /* Converting down */
822 dest_override = midgard_dest_override_lower;
823 }
824
825 break;
826 }
827
828 /* For greater-or-equal, we lower to less-or-equal and flip the
829 * arguments */
830
831 case nir_op_fge:
832 case nir_op_fge32:
833 case nir_op_ige32:
834 case nir_op_uge32: {
835 op =
836 instr->op == nir_op_fge ? midgard_alu_op_fle :
837 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
838 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
839 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
840 0;
841
842 /* Swap via temporary */
843 nir_alu_src temp = instr->src[1];
844 instr->src[1] = instr->src[0];
845 instr->src[0] = temp;
846
847 break;
848 }
849
850 case nir_op_b32csel: {
851 /* Midgard features both fcsel and icsel, depending on
852 * the type of the arguments/output. However, as long
853 * as we're careful we can _always_ use icsel and
854 * _never_ need fcsel, since the latter does additional
855 * floating-point-specific processing whereas the
856 * former just moves bits on the wire. It's not obvious
857 * why these are separate opcodes, save for the ability
858 * to do things like sat/pos/abs/neg for free */
859
860 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
861 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
862
863 /* The condition is the first argument; move the other
864 * arguments up one to be a binary instruction for
865 * Midgard with the condition last */
866
867 nir_alu_src temp = instr->src[2];
868
869 instr->src[2] = instr->src[0];
870 instr->src[0] = instr->src[1];
871 instr->src[1] = temp;
872
873 break;
874 }
875
876 default:
877 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
878 assert(0);
879 return;
880 }
881
882 /* Midgard can perform certain modifiers on output of an ALU op */
883 unsigned outmod;
884
885 if (midgard_is_integer_out_op(op)) {
886 outmod = midgard_outmod_int_wrap;
887 } else {
888 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
889 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
890 }
891
892 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
893
894 if (instr->op == nir_op_fmax) {
895 if (nir_is_fzero_constant(instr->src[0].src)) {
896 op = midgard_alu_op_fmov;
897 nr_inputs = 1;
898 outmod = midgard_outmod_pos;
899 instr->src[0] = instr->src[1];
900 } else if (nir_is_fzero_constant(instr->src[1].src)) {
901 op = midgard_alu_op_fmov;
902 nr_inputs = 1;
903 outmod = midgard_outmod_pos;
904 }
905 }
906
907 /* Fetch unit, quirks, etc information */
908 unsigned opcode_props = alu_opcode_props[op].props;
909 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
910
911 /* src0 will always exist afaik, but src1 will not for 1-argument
912 * instructions. The latter can only be fetched if the instruction
913 * needs it, or else we may segfault. */
914
915 unsigned src0 = nir_src_index(ctx, &instr->src[0].src);
916 unsigned src1 = nr_inputs >= 2 ? nir_src_index(ctx, &instr->src[1].src) : ~0;
917 unsigned src2 = nr_inputs == 3 ? nir_src_index(ctx, &instr->src[2].src) : ~0;
918 assert(nr_inputs <= 3);
919
920 /* Rather than use the instruction generation helpers, we do it
921 * ourselves here to avoid the mess */
922
923 midgard_instruction ins = {
924 .type = TAG_ALU_4,
925 .src = {
926 quirk_flipped_r24 ? ~0 : src0,
927 quirk_flipped_r24 ? src0 : src1,
928 src2,
929 ~0
930 },
931 .dest = dest,
932 };
933
934 nir_alu_src *nirmods[3] = { NULL };
935
936 if (nr_inputs >= 2) {
937 nirmods[0] = &instr->src[0];
938 nirmods[1] = &instr->src[1];
939 } else if (nr_inputs == 1) {
940 nirmods[quirk_flipped_r24] = &instr->src[0];
941 } else {
942 assert(0);
943 }
944
945 if (nr_inputs == 3)
946 nirmods[2] = &instr->src[2];
947
948 /* These were lowered to a move, so apply the corresponding mod */
949
950 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
951 nir_alu_src *s = nirmods[quirk_flipped_r24];
952
953 if (instr->op == nir_op_fneg)
954 s->negate = !s->negate;
955
956 if (instr->op == nir_op_fabs)
957 s->abs = !s->abs;
958 }
959
960 bool is_int = midgard_is_integer_op(op);
961
962 ins.mask = mask_of(nr_components);
963
964 midgard_vector_alu alu = {
965 .op = op,
966 .reg_mode = reg_mode,
967 .dest_override = dest_override,
968 .outmod = outmod,
969
970 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)),
971 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)),
972 };
973
974 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
975
976 if (!is_ssa)
977 ins.mask &= instr->dest.write_mask;
978
979 for (unsigned m = 0; m < 3; ++m) {
980 if (!nirmods[m])
981 continue;
982
983 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c)
984 ins.swizzle[m][c] = nirmods[m]->swizzle[c];
985
986 /* Replicate. TODO: remove when vec16 lands */
987 for (unsigned c = NIR_MAX_VEC_COMPONENTS; c < MIR_VEC_COMPONENTS; ++c)
988 ins.swizzle[m][c] = nirmods[m]->swizzle[NIR_MAX_VEC_COMPONENTS - 1];
989 }
990
991 if (nr_inputs == 3) {
992 /* Conditions can't have mods */
993 assert(!nirmods[2]->abs);
994 assert(!nirmods[2]->negate);
995 }
996
997 ins.alu = alu;
998
999 /* Late fixup for emulated instructions */
1000
1001 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1002 /* Presently, our second argument is an inline #0 constant.
1003 * Switch over to an embedded 1.0 constant (that can't fit
1004 * inline, since we're 32-bit, not 16-bit like the inline
1005 * constants) */
1006
1007 ins.has_inline_constant = false;
1008 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1009 ins.has_constants = true;
1010
1011 if (instr->op == nir_op_b2f32)
1012 ins.constants.f32[0] = 1.0f;
1013 else
1014 ins.constants.i32[0] = 1;
1015
1016 for (unsigned c = 0; c < 16; ++c)
1017 ins.swizzle[1][c] = 0;
1018 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1019 /* Lots of instructions need a 0 plonked in */
1020 ins.has_inline_constant = false;
1021 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1022 ins.has_constants = true;
1023 ins.constants.u32[0] = 0;
1024
1025 for (unsigned c = 0; c < 16; ++c)
1026 ins.swizzle[1][c] = 0;
1027 } else if (instr->op == nir_op_inot) {
1028 ins.invert = true;
1029 }
1030
1031 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1032 /* To avoid duplicating the lookup tables (probably), true LUT
1033 * instructions can only operate as if they were scalars. Lower
1034 * them here by changing the component. */
1035
1036 unsigned orig_mask = ins.mask;
1037
1038 for (int i = 0; i < nr_components; ++i) {
1039 /* Mask the associated component, dropping the
1040 * instruction if needed */
1041
1042 ins.mask = 1 << i;
1043 ins.mask &= orig_mask;
1044
1045 if (!ins.mask)
1046 continue;
1047
1048 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1049 ins.swizzle[0][j] = nirmods[0]->swizzle[i]; /* Pull from the correct component */
1050
1051 emit_mir_instruction(ctx, ins);
1052 }
1053 } else {
1054 emit_mir_instruction(ctx, ins);
1055 }
1056 }
1057
1058 #undef ALU_CASE
1059
1060 static void
1061 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1062 {
1063 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1064 unsigned nir_mask = 0;
1065 unsigned dsize = 0;
1066
1067 if (is_read) {
1068 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1069 dsize = nir_dest_bit_size(intr->dest);
1070 } else {
1071 nir_mask = nir_intrinsic_write_mask(intr);
1072 dsize = 32;
1073 }
1074
1075 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1076 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1077 mir_set_bytemask(ins, bytemask);
1078
1079 if (dsize == 64)
1080 ins->load_64 = true;
1081 }
1082
1083 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1084 * optimized) versions of UBO #0 */
1085
1086 static midgard_instruction *
1087 emit_ubo_read(
1088 compiler_context *ctx,
1089 nir_instr *instr,
1090 unsigned dest,
1091 unsigned offset,
1092 nir_src *indirect_offset,
1093 unsigned indirect_shift,
1094 unsigned index)
1095 {
1096 /* TODO: half-floats */
1097
1098 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1099 ins.constants.u32[0] = offset;
1100
1101 if (instr->type == nir_instr_type_intrinsic)
1102 mir_set_intr_mask(instr, &ins, true);
1103
1104 if (indirect_offset) {
1105 ins.src[2] = nir_src_index(ctx, indirect_offset);
1106 ins.load_store.arg_2 = (indirect_shift << 5);
1107 } else {
1108 ins.load_store.arg_2 = 0x1E;
1109 }
1110
1111 ins.load_store.arg_1 = index;
1112
1113 return emit_mir_instruction(ctx, ins);
1114 }
1115
1116 /* Globals are like UBOs if you squint. And shared memory is like globals if
1117 * you squint even harder */
1118
1119 static void
1120 emit_global(
1121 compiler_context *ctx,
1122 nir_instr *instr,
1123 bool is_read,
1124 unsigned srcdest,
1125 nir_src *offset,
1126 bool is_shared)
1127 {
1128 /* TODO: types */
1129
1130 midgard_instruction ins;
1131
1132 if (is_read)
1133 ins = m_ld_int4(srcdest, 0);
1134 else
1135 ins = m_st_int4(srcdest, 0);
1136
1137 mir_set_offset(ctx, &ins, offset, is_shared);
1138 mir_set_intr_mask(instr, &ins, is_read);
1139
1140 emit_mir_instruction(ctx, ins);
1141 }
1142
1143 static void
1144 emit_varying_read(
1145 compiler_context *ctx,
1146 unsigned dest, unsigned offset,
1147 unsigned nr_comp, unsigned component,
1148 nir_src *indirect_offset, nir_alu_type type, bool flat)
1149 {
1150 /* XXX: Half-floats? */
1151 /* TODO: swizzle, mask */
1152
1153 midgard_instruction ins = m_ld_vary_32(dest, offset);
1154 ins.mask = mask_of(nr_comp);
1155
1156 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1157 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1158
1159 midgard_varying_parameter p = {
1160 .is_varying = 1,
1161 .interpolation = midgard_interp_default,
1162 .flat = flat,
1163 };
1164
1165 unsigned u;
1166 memcpy(&u, &p, sizeof(p));
1167 ins.load_store.varying_parameters = u;
1168
1169 if (indirect_offset)
1170 ins.src[2] = nir_src_index(ctx, indirect_offset);
1171 else
1172 ins.load_store.arg_2 = 0x1E;
1173
1174 ins.load_store.arg_1 = 0x9E;
1175
1176 /* Use the type appropriate load */
1177 switch (type) {
1178 case nir_type_uint:
1179 case nir_type_bool:
1180 ins.load_store.op = midgard_op_ld_vary_32u;
1181 break;
1182 case nir_type_int:
1183 ins.load_store.op = midgard_op_ld_vary_32i;
1184 break;
1185 case nir_type_float:
1186 ins.load_store.op = midgard_op_ld_vary_32;
1187 break;
1188 default:
1189 unreachable("Attempted to load unknown type");
1190 break;
1191 }
1192
1193 emit_mir_instruction(ctx, ins);
1194 }
1195
1196 static void
1197 emit_attr_read(
1198 compiler_context *ctx,
1199 unsigned dest, unsigned offset,
1200 unsigned nr_comp, nir_alu_type t)
1201 {
1202 midgard_instruction ins = m_ld_attr_32(dest, offset);
1203 ins.load_store.arg_1 = 0x1E;
1204 ins.load_store.arg_2 = 0x1E;
1205 ins.mask = mask_of(nr_comp);
1206
1207 /* Use the type appropriate load */
1208 switch (t) {
1209 case nir_type_uint:
1210 case nir_type_bool:
1211 ins.load_store.op = midgard_op_ld_attr_32u;
1212 break;
1213 case nir_type_int:
1214 ins.load_store.op = midgard_op_ld_attr_32i;
1215 break;
1216 case nir_type_float:
1217 ins.load_store.op = midgard_op_ld_attr_32;
1218 break;
1219 default:
1220 unreachable("Attempted to load unknown type");
1221 break;
1222 }
1223
1224 emit_mir_instruction(ctx, ins);
1225 }
1226
1227 static void
1228 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1229 unsigned nr_components, unsigned offset)
1230 {
1231 nir_dest nir_dest;
1232
1233 /* Figure out which uniform this is */
1234 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1235 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1236
1237 unsigned dest = nir_dest_index(&nir_dest);
1238
1239 /* Sysvals are prefix uniforms */
1240 unsigned uniform = ((uintptr_t) val) - 1;
1241
1242 /* Emit the read itself -- this is never indirect */
1243 midgard_instruction *ins =
1244 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1245
1246 ins->mask = mask_of(nr_components);
1247 }
1248
1249 static unsigned
1250 compute_builtin_arg(nir_op op)
1251 {
1252 switch (op) {
1253 case nir_intrinsic_load_work_group_id:
1254 return 0x14;
1255 case nir_intrinsic_load_local_invocation_id:
1256 return 0x10;
1257 default:
1258 unreachable("Invalid compute paramater loaded");
1259 }
1260 }
1261
1262 static void
1263 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1264 {
1265 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1266
1267 midgard_instruction *br = ctx->writeout_branch[rt];
1268
1269 assert(!br);
1270
1271 emit_explicit_constant(ctx, src, src);
1272
1273 struct midgard_instruction ins =
1274 v_branch(false, false);
1275
1276 ins.writeout = true;
1277
1278 /* Add dependencies */
1279 ins.src[0] = src;
1280 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1281 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1282
1283 /* Emit the branch */
1284 br = emit_mir_instruction(ctx, ins);
1285 schedule_barrier(ctx);
1286 ctx->writeout_branch[rt] = br;
1287
1288 /* Push our current location = current block count - 1 = where we'll
1289 * jump to. Maybe a bit too clever for my own good */
1290
1291 br->branch.target_block = ctx->block_count - 1;
1292 }
1293
1294 static void
1295 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1296 {
1297 unsigned reg = nir_dest_index(&instr->dest);
1298 midgard_instruction ins = m_ld_compute_id(reg, 0);
1299 ins.mask = mask_of(3);
1300 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1301 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1302 emit_mir_instruction(ctx, ins);
1303 }
1304
1305 static unsigned
1306 vertex_builtin_arg(nir_op op)
1307 {
1308 switch (op) {
1309 case nir_intrinsic_load_vertex_id:
1310 return PAN_VERTEX_ID;
1311 case nir_intrinsic_load_instance_id:
1312 return PAN_INSTANCE_ID;
1313 default:
1314 unreachable("Invalid vertex builtin");
1315 }
1316 }
1317
1318 static void
1319 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1320 {
1321 unsigned reg = nir_dest_index(&instr->dest);
1322 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1323 }
1324
1325 static void
1326 emit_control_barrier(compiler_context *ctx)
1327 {
1328 midgard_instruction ins = {
1329 .type = TAG_TEXTURE_4,
1330 .src = { ~0, ~0, ~0, ~0 },
1331 .texture = {
1332 .op = TEXTURE_OP_BARRIER,
1333
1334 /* TODO: optimize */
1335 .barrier_buffer = 1,
1336 .barrier_shared = 1
1337 }
1338 };
1339
1340 emit_mir_instruction(ctx, ins);
1341 }
1342
1343 static const nir_variable *
1344 search_var(struct exec_list *vars, unsigned driver_loc)
1345 {
1346 nir_foreach_variable(var, vars) {
1347 if (var->data.driver_location == driver_loc)
1348 return var;
1349 }
1350
1351 return NULL;
1352 }
1353
1354 static void
1355 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1356 {
1357 unsigned offset = 0, reg;
1358
1359 switch (instr->intrinsic) {
1360 case nir_intrinsic_discard_if:
1361 case nir_intrinsic_discard: {
1362 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1363 struct midgard_instruction discard = v_branch(conditional, false);
1364 discard.branch.target_type = TARGET_DISCARD;
1365
1366 if (conditional)
1367 discard.src[0] = nir_src_index(ctx, &instr->src[0]);
1368
1369 emit_mir_instruction(ctx, discard);
1370 schedule_barrier(ctx);
1371
1372 break;
1373 }
1374
1375 case nir_intrinsic_load_uniform:
1376 case nir_intrinsic_load_ubo:
1377 case nir_intrinsic_load_global:
1378 case nir_intrinsic_load_shared:
1379 case nir_intrinsic_load_input:
1380 case nir_intrinsic_load_interpolated_input: {
1381 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1382 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1383 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1384 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1385 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1386 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1387
1388 /* Get the base type of the intrinsic */
1389 /* TODO: Infer type? Does it matter? */
1390 nir_alu_type t =
1391 (is_ubo || is_global || is_shared) ? nir_type_uint :
1392 (is_interp) ? nir_type_float :
1393 nir_intrinsic_type(instr);
1394
1395 t = nir_alu_type_get_base_type(t);
1396
1397 if (!(is_ubo || is_global)) {
1398 offset = nir_intrinsic_base(instr);
1399 }
1400
1401 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1402
1403 nir_src *src_offset = nir_get_io_offset_src(instr);
1404
1405 bool direct = nir_src_is_const(*src_offset);
1406 nir_src *indirect_offset = direct ? NULL : src_offset;
1407
1408 if (direct)
1409 offset += nir_src_as_uint(*src_offset);
1410
1411 /* We may need to apply a fractional offset */
1412 int component = (is_flat || is_interp) ?
1413 nir_intrinsic_component(instr) : 0;
1414 reg = nir_dest_index(&instr->dest);
1415
1416 if (is_uniform && !ctx->is_blend) {
1417 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1418 } else if (is_ubo) {
1419 nir_src index = instr->src[0];
1420
1421 /* TODO: Is indirect block number possible? */
1422 assert(nir_src_is_const(index));
1423
1424 uint32_t uindex = nir_src_as_uint(index) + 1;
1425 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1426 } else if (is_global || is_shared) {
1427 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1428 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1429 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1430 } else if (ctx->is_blend) {
1431 /* For blend shaders, load the input color, which is
1432 * preloaded to r0 */
1433
1434 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1435 emit_mir_instruction(ctx, move);
1436 schedule_barrier(ctx);
1437 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1438 emit_attr_read(ctx, reg, offset, nr_comp, t);
1439 } else {
1440 DBG("Unknown load\n");
1441 assert(0);
1442 }
1443
1444 break;
1445 }
1446
1447 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1448 case nir_intrinsic_load_barycentric_pixel:
1449 case nir_intrinsic_load_barycentric_centroid:
1450 break;
1451
1452 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1453
1454 case nir_intrinsic_load_raw_output_pan:
1455 case nir_intrinsic_load_output_u8_as_fp16_pan:
1456 reg = nir_dest_index(&instr->dest);
1457 assert(ctx->is_blend);
1458
1459 /* T720 and below use different blend opcodes with slightly
1460 * different semantics than T760 and up */
1461
1462 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1463 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1464
1465 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1466 ld.load_store.op = old_blend ?
1467 midgard_op_ld_color_buffer_u8_as_fp16_old :
1468 midgard_op_ld_color_buffer_u8_as_fp16;
1469
1470 if (old_blend) {
1471 ld.load_store.address = 1;
1472 ld.load_store.arg_2 = 0x1E;
1473 }
1474
1475 for (unsigned c = 2; c < 16; ++c)
1476 ld.swizzle[0][c] = 0;
1477 }
1478
1479 emit_mir_instruction(ctx, ld);
1480 break;
1481
1482 case nir_intrinsic_load_blend_const_color_rgba: {
1483 assert(ctx->is_blend);
1484 reg = nir_dest_index(&instr->dest);
1485
1486 /* Blend constants are embedded directly in the shader and
1487 * patched in, so we use some magic routing */
1488
1489 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1490 ins.has_constants = true;
1491 ins.has_blend_constant = true;
1492 emit_mir_instruction(ctx, ins);
1493 break;
1494 }
1495
1496 case nir_intrinsic_store_zs_output_pan: {
1497 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1498 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1499 MIDGARD_ZS_RT);
1500
1501 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1502
1503 if (!nir_intrinsic_component(instr))
1504 br->writeout_depth = true;
1505 if (nir_intrinsic_component(instr) ||
1506 instr->num_components)
1507 br->writeout_stencil = true;
1508 assert(br->writeout_depth | br->writeout_stencil);
1509 break;
1510 }
1511
1512 case nir_intrinsic_store_output:
1513 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1514
1515 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1516
1517 reg = nir_src_index(ctx, &instr->src[0]);
1518
1519 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1520 const nir_variable *var;
1521 enum midgard_rt_id rt;
1522
1523 var = search_var(&ctx->nir->outputs,
1524 nir_intrinsic_base(instr));
1525 assert(var);
1526 if (var->data.location == FRAG_RESULT_COLOR)
1527 rt = MIDGARD_COLOR_RT0;
1528 else if (var->data.location >= FRAG_RESULT_DATA0)
1529 rt = MIDGARD_COLOR_RT0 + var->data.location -
1530 FRAG_RESULT_DATA0;
1531 else
1532 assert(0);
1533
1534 emit_fragment_store(ctx, reg, rt);
1535 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1536 /* We should have been vectorized, though we don't
1537 * currently check that st_vary is emitted only once
1538 * per slot (this is relevant, since there's not a mask
1539 * parameter available on the store [set to 0 by the
1540 * blob]). We do respect the component by adjusting the
1541 * swizzle. If this is a constant source, we'll need to
1542 * emit that explicitly. */
1543
1544 emit_explicit_constant(ctx, reg, reg);
1545
1546 unsigned dst_component = nir_intrinsic_component(instr);
1547 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1548
1549 midgard_instruction st = m_st_vary_32(reg, offset);
1550 st.load_store.arg_1 = 0x9E;
1551 st.load_store.arg_2 = 0x1E;
1552
1553 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1554 case nir_type_uint:
1555 case nir_type_bool:
1556 st.load_store.op = midgard_op_st_vary_32u;
1557 break;
1558 case nir_type_int:
1559 st.load_store.op = midgard_op_st_vary_32i;
1560 break;
1561 case nir_type_float:
1562 st.load_store.op = midgard_op_st_vary_32;
1563 break;
1564 default:
1565 unreachable("Attempted to store unknown type");
1566 break;
1567 }
1568
1569 /* nir_intrinsic_component(store_intr) encodes the
1570 * destination component start. Source component offset
1571 * adjustment is taken care of in
1572 * install_registers_instr(), when offset_swizzle() is
1573 * called.
1574 */
1575 unsigned src_component = COMPONENT_X;
1576
1577 assert(nr_comp > 0);
1578 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1579 st.swizzle[0][i] = src_component;
1580 if (i >= dst_component && i < dst_component + nr_comp - 1)
1581 src_component++;
1582 }
1583
1584 emit_mir_instruction(ctx, st);
1585 } else {
1586 DBG("Unknown store\n");
1587 assert(0);
1588 }
1589
1590 break;
1591
1592 /* Special case of store_output for lowered blend shaders */
1593 case nir_intrinsic_store_raw_output_pan:
1594 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1595 reg = nir_src_index(ctx, &instr->src[0]);
1596
1597 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1598 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1599 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1600 * of:
1601 *
1602 * imov r0.xyzw, r0.xxxx
1603 */
1604
1605 unsigned expanded = make_compiler_temp(ctx);
1606
1607 midgard_instruction splatter = v_mov(reg, expanded);
1608
1609 for (unsigned c = 0; c < 16; ++c)
1610 splatter.swizzle[1][c] = 0;
1611
1612 emit_mir_instruction(ctx, splatter);
1613 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1614 } else
1615 emit_fragment_store(ctx, reg, ctx->blend_rt);
1616
1617 break;
1618
1619 case nir_intrinsic_store_global:
1620 case nir_intrinsic_store_shared:
1621 reg = nir_src_index(ctx, &instr->src[0]);
1622 emit_explicit_constant(ctx, reg, reg);
1623
1624 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1625 break;
1626
1627 case nir_intrinsic_load_ssbo_address:
1628 emit_sysval_read(ctx, &instr->instr, 1, 0);
1629 break;
1630
1631 case nir_intrinsic_get_buffer_size:
1632 emit_sysval_read(ctx, &instr->instr, 1, 8);
1633 break;
1634
1635 case nir_intrinsic_load_viewport_scale:
1636 case nir_intrinsic_load_viewport_offset:
1637 case nir_intrinsic_load_num_work_groups:
1638 case nir_intrinsic_load_sampler_lod_parameters_pan:
1639 emit_sysval_read(ctx, &instr->instr, 3, 0);
1640 break;
1641
1642 case nir_intrinsic_load_work_group_id:
1643 case nir_intrinsic_load_local_invocation_id:
1644 emit_compute_builtin(ctx, instr);
1645 break;
1646
1647 case nir_intrinsic_load_vertex_id:
1648 case nir_intrinsic_load_instance_id:
1649 emit_vertex_builtin(ctx, instr);
1650 break;
1651
1652 case nir_intrinsic_memory_barrier_buffer:
1653 case nir_intrinsic_memory_barrier_shared:
1654 break;
1655
1656 case nir_intrinsic_control_barrier:
1657 schedule_barrier(ctx);
1658 emit_control_barrier(ctx);
1659 schedule_barrier(ctx);
1660 break;
1661
1662 default:
1663 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1664 assert(0);
1665 break;
1666 }
1667 }
1668
1669 static unsigned
1670 midgard_tex_format(enum glsl_sampler_dim dim)
1671 {
1672 switch (dim) {
1673 case GLSL_SAMPLER_DIM_1D:
1674 case GLSL_SAMPLER_DIM_BUF:
1675 return MALI_TEX_1D;
1676
1677 case GLSL_SAMPLER_DIM_2D:
1678 case GLSL_SAMPLER_DIM_EXTERNAL:
1679 case GLSL_SAMPLER_DIM_RECT:
1680 return MALI_TEX_2D;
1681
1682 case GLSL_SAMPLER_DIM_3D:
1683 return MALI_TEX_3D;
1684
1685 case GLSL_SAMPLER_DIM_CUBE:
1686 return MALI_TEX_CUBE;
1687
1688 default:
1689 DBG("Unknown sampler dim type\n");
1690 assert(0);
1691 return 0;
1692 }
1693 }
1694
1695 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1696 * was successful */
1697
1698 static bool
1699 pan_attach_constant_bias(
1700 compiler_context *ctx,
1701 nir_src lod,
1702 midgard_texture_word *word)
1703 {
1704 /* To attach as constant, it has to *be* constant */
1705
1706 if (!nir_src_is_const(lod))
1707 return false;
1708
1709 float f = nir_src_as_float(lod);
1710
1711 /* Break into fixed-point */
1712 signed lod_int = f;
1713 float lod_frac = f - lod_int;
1714
1715 /* Carry over negative fractions */
1716 if (lod_frac < 0.0) {
1717 lod_int--;
1718 lod_frac += 1.0;
1719 }
1720
1721 /* Encode */
1722 word->bias = float_to_ubyte(lod_frac);
1723 word->bias_int = lod_int;
1724
1725 return true;
1726 }
1727
1728 static enum mali_sampler_type
1729 midgard_sampler_type(nir_alu_type t) {
1730 switch (nir_alu_type_get_base_type(t))
1731 {
1732 case nir_type_float:
1733 return MALI_SAMPLER_FLOAT;
1734 case nir_type_int:
1735 return MALI_SAMPLER_SIGNED;
1736 case nir_type_uint:
1737 return MALI_SAMPLER_UNSIGNED;
1738 default:
1739 unreachable("Unknown sampler type");
1740 }
1741 }
1742
1743 static void
1744 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1745 unsigned midgard_texop)
1746 {
1747 /* TODO */
1748 //assert (!instr->sampler);
1749
1750 int texture_index = instr->texture_index;
1751 int sampler_index = texture_index;
1752
1753 /* No helper to build texture words -- we do it all here */
1754 midgard_instruction ins = {
1755 .type = TAG_TEXTURE_4,
1756 .mask = 0xF,
1757 .dest = nir_dest_index(&instr->dest),
1758 .src = { ~0, ~0, ~0, ~0 },
1759 .swizzle = SWIZZLE_IDENTITY_4,
1760 .texture = {
1761 .op = midgard_texop,
1762 .format = midgard_tex_format(instr->sampler_dim),
1763 .texture_handle = texture_index,
1764 .sampler_handle = sampler_index,
1765
1766 /* TODO: half */
1767 .in_reg_full = 1,
1768 .out_full = 1,
1769
1770 .sampler_type = midgard_sampler_type(instr->dest_type),
1771 .shadow = instr->is_shadow,
1772 }
1773 };
1774
1775 /* We may need a temporary for the coordinate */
1776
1777 bool needs_temp_coord =
1778 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1779 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1780 (instr->is_shadow);
1781
1782 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1783
1784 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1785 int index = nir_src_index(ctx, &instr->src[i].src);
1786 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1787
1788 switch (instr->src[i].src_type) {
1789 case nir_tex_src_coord: {
1790 emit_explicit_constant(ctx, index, index);
1791
1792 unsigned coord_mask = mask_of(instr->coord_components);
1793
1794 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1795
1796 if (flip_zw)
1797 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1798
1799 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1800 /* texelFetch is undefined on samplerCube */
1801 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1802
1803 /* For cubemaps, we use a special ld/st op to
1804 * select the face and copy the xy into the
1805 * texture register */
1806
1807 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1808 ld.src[1] = index;
1809 ld.mask = 0x3; /* xy */
1810 ld.load_store.arg_1 = 0x20;
1811 ld.swizzle[1][3] = COMPONENT_X;
1812 emit_mir_instruction(ctx, ld);
1813
1814 /* xyzw -> xyxx */
1815 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1816 ins.swizzle[1][3] = COMPONENT_X;
1817 } else if (needs_temp_coord) {
1818 /* mov coord_temp, coords */
1819 midgard_instruction mov = v_mov(index, coords);
1820 mov.mask = coord_mask;
1821
1822 if (flip_zw)
1823 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1824
1825 emit_mir_instruction(ctx, mov);
1826 } else {
1827 coords = index;
1828 }
1829
1830 ins.src[1] = coords;
1831
1832 /* Texelfetch coordinates uses all four elements
1833 * (xyz/index) regardless of texture dimensionality,
1834 * which means it's necessary to zero the unused
1835 * components to keep everything happy */
1836
1837 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1838 /* mov index.zw, #0, or generalized */
1839 midgard_instruction mov =
1840 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1841 mov.has_constants = true;
1842 mov.mask = coord_mask ^ 0xF;
1843 emit_mir_instruction(ctx, mov);
1844 }
1845
1846 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1847 /* Array component in w but NIR wants it in z,
1848 * but if we have a temp coord we already fixed
1849 * that up */
1850
1851 if (nr_components == 3) {
1852 ins.swizzle[1][2] = COMPONENT_Z;
1853 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1854 } else if (nr_components == 2) {
1855 ins.swizzle[1][2] =
1856 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1857 ins.swizzle[1][3] = COMPONENT_X;
1858 } else
1859 unreachable("Invalid texture 2D components");
1860 }
1861
1862 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1863 /* We zeroed */
1864 ins.swizzle[1][2] = COMPONENT_Z;
1865 ins.swizzle[1][3] = COMPONENT_W;
1866 }
1867
1868 break;
1869 }
1870
1871 case nir_tex_src_bias:
1872 case nir_tex_src_lod: {
1873 /* Try as a constant if we can */
1874
1875 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1876 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1877 break;
1878
1879 ins.texture.lod_register = true;
1880 ins.src[2] = index;
1881
1882 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1883 ins.swizzle[2][c] = COMPONENT_X;
1884
1885 emit_explicit_constant(ctx, index, index);
1886
1887 break;
1888 };
1889
1890 case nir_tex_src_offset: {
1891 ins.texture.offset_register = true;
1892 ins.src[3] = index;
1893
1894 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1895 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
1896
1897 emit_explicit_constant(ctx, index, index);
1898 break;
1899 };
1900
1901 case nir_tex_src_comparator: {
1902 unsigned comp = COMPONENT_Z;
1903
1904 /* mov coord_temp.foo, coords */
1905 midgard_instruction mov = v_mov(index, coords);
1906 mov.mask = 1 << comp;
1907
1908 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
1909 mov.swizzle[1][i] = COMPONENT_X;
1910
1911 emit_mir_instruction(ctx, mov);
1912 break;
1913 }
1914
1915 default: {
1916 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
1917 assert(0);
1918 }
1919 }
1920 }
1921
1922 emit_mir_instruction(ctx, ins);
1923
1924 /* Used for .cont and .last hinting */
1925 ctx->texture_op_count++;
1926 }
1927
1928 static void
1929 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1930 {
1931 switch (instr->op) {
1932 case nir_texop_tex:
1933 case nir_texop_txb:
1934 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
1935 break;
1936 case nir_texop_txl:
1937 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
1938 break;
1939 case nir_texop_txf:
1940 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
1941 break;
1942 case nir_texop_txs:
1943 emit_sysval_read(ctx, &instr->instr, 4, 0);
1944 break;
1945 default: {
1946 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
1947 assert(0);
1948 }
1949 }
1950 }
1951
1952 static void
1953 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1954 {
1955 switch (instr->type) {
1956 case nir_jump_break: {
1957 /* Emit a branch out of the loop */
1958 struct midgard_instruction br = v_branch(false, false);
1959 br.branch.target_type = TARGET_BREAK;
1960 br.branch.target_break = ctx->current_loop_depth;
1961 emit_mir_instruction(ctx, br);
1962 break;
1963 }
1964
1965 default:
1966 DBG("Unknown jump type %d\n", instr->type);
1967 break;
1968 }
1969 }
1970
1971 static void
1972 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1973 {
1974 switch (instr->type) {
1975 case nir_instr_type_load_const:
1976 emit_load_const(ctx, nir_instr_as_load_const(instr));
1977 break;
1978
1979 case nir_instr_type_intrinsic:
1980 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1981 break;
1982
1983 case nir_instr_type_alu:
1984 emit_alu(ctx, nir_instr_as_alu(instr));
1985 break;
1986
1987 case nir_instr_type_tex:
1988 emit_tex(ctx, nir_instr_as_tex(instr));
1989 break;
1990
1991 case nir_instr_type_jump:
1992 emit_jump(ctx, nir_instr_as_jump(instr));
1993 break;
1994
1995 case nir_instr_type_ssa_undef:
1996 /* Spurious */
1997 break;
1998
1999 default:
2000 DBG("Unhandled instruction type\n");
2001 break;
2002 }
2003 }
2004
2005
2006 /* ALU instructions can inline or embed constants, which decreases register
2007 * pressure and saves space. */
2008
2009 #define CONDITIONAL_ATTACH(idx) { \
2010 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2011 \
2012 if (entry) { \
2013 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2014 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2015 } \
2016 }
2017
2018 static void
2019 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2020 {
2021 mir_foreach_instr_in_block(block, alu) {
2022 /* Other instructions cannot inline constants */
2023 if (alu->type != TAG_ALU_4) continue;
2024 if (alu->compact_branch) continue;
2025
2026 /* If there is already a constant here, we can do nothing */
2027 if (alu->has_constants) continue;
2028
2029 CONDITIONAL_ATTACH(0);
2030
2031 if (!alu->has_constants) {
2032 CONDITIONAL_ATTACH(1)
2033 } else if (!alu->inline_constant) {
2034 /* Corner case: _two_ vec4 constants, for instance with a
2035 * csel. For this case, we can only use a constant
2036 * register for one, we'll have to emit a move for the
2037 * other. */
2038
2039 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2040 unsigned scratch = make_compiler_temp(ctx);
2041
2042 if (entry) {
2043 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2044 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2045
2046 /* Set the source */
2047 alu->src[1] = scratch;
2048
2049 /* Inject us -before- the last instruction which set r31 */
2050 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2051 }
2052 }
2053 }
2054 }
2055
2056 /* Being a little silly with the names, but returns the op that is the bitwise
2057 * inverse of the op with the argument switched. I.e. (f and g are
2058 * contrapositives):
2059 *
2060 * f(a, b) = ~g(b, a)
2061 *
2062 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
2063 *
2064 * f(a, b) = ~g(b, a)
2065 * ~f(a, b) = g(b, a)
2066 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
2067 * f(a, b) = h(a, b)
2068 *
2069 * Thus we define this function in pairs.
2070 */
2071
2072 static inline midgard_alu_op
2073 mir_contrapositive(midgard_alu_op op)
2074 {
2075 switch (op) {
2076 case midgard_alu_op_flt:
2077 return midgard_alu_op_fle;
2078 case midgard_alu_op_fle:
2079 return midgard_alu_op_flt;
2080
2081 case midgard_alu_op_ilt:
2082 return midgard_alu_op_ile;
2083 case midgard_alu_op_ile:
2084 return midgard_alu_op_ilt;
2085
2086 default:
2087 unreachable("No known contrapositive");
2088 }
2089 }
2090
2091 /* Midgard supports two types of constants, embedded constants (128-bit) and
2092 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2093 * constants can be demoted to inline constants, for space savings and
2094 * sometimes a performance boost */
2095
2096 static void
2097 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2098 {
2099 mir_foreach_instr_in_block(block, ins) {
2100 if (!ins->has_constants) continue;
2101 if (ins->has_inline_constant) continue;
2102
2103 /* Blend constants must not be inlined by definition */
2104 if (ins->has_blend_constant) continue;
2105
2106 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2107 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2108 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2109
2110 if (!(is_16 || is_32))
2111 continue;
2112
2113 /* src1 cannot be an inline constant due to encoding
2114 * restrictions. So, if possible we try to flip the arguments
2115 * in that case */
2116
2117 int op = ins->alu.op;
2118
2119 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2120 bool flip = alu_opcode_props[op].props & OP_COMMUTES;
2121
2122 switch (op) {
2123 /* Conditionals can be inverted */
2124 case midgard_alu_op_flt:
2125 case midgard_alu_op_ilt:
2126 case midgard_alu_op_fle:
2127 case midgard_alu_op_ile:
2128 ins->alu.op = mir_contrapositive(ins->alu.op);
2129 ins->invert = true;
2130 flip = true;
2131 break;
2132
2133 case midgard_alu_op_fcsel:
2134 case midgard_alu_op_icsel:
2135 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
2136 default:
2137 break;
2138 }
2139
2140 if (flip)
2141 mir_flip(ins);
2142 }
2143
2144 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2145 /* Extract the source information */
2146
2147 midgard_vector_alu_src *src;
2148 int q = ins->alu.src2;
2149 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2150 src = m;
2151
2152 /* Component is from the swizzle. Take a nonzero component */
2153 assert(ins->mask);
2154 unsigned first_comp = ffs(ins->mask) - 1;
2155 unsigned component = ins->swizzle[1][first_comp];
2156
2157 /* Scale constant appropriately, if we can legally */
2158 uint16_t scaled_constant = 0;
2159
2160 if (is_16) {
2161 scaled_constant = ins->constants.u16[component];
2162 } else if (midgard_is_integer_op(op)) {
2163 scaled_constant = ins->constants.u32[component];
2164
2165 /* Constant overflow after resize */
2166 if (scaled_constant != ins->constants.u32[component])
2167 continue;
2168 } else {
2169 float original = ins->constants.f32[component];
2170 scaled_constant = _mesa_float_to_half(original);
2171
2172 /* Check for loss of precision. If this is
2173 * mediump, we don't care, but for a highp
2174 * shader, we need to pay attention. NIR
2175 * doesn't yet tell us which mode we're in!
2176 * Practically this prevents most constants
2177 * from being inlined, sadly. */
2178
2179 float fp32 = _mesa_half_to_float(scaled_constant);
2180
2181 if (fp32 != original)
2182 continue;
2183 }
2184
2185 /* We don't know how to handle these with a constant */
2186
2187 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2188 DBG("Bailing inline constant...\n");
2189 continue;
2190 }
2191
2192 /* Make sure that the constant is not itself a vector
2193 * by checking if all accessed values are the same. */
2194
2195 const midgard_constants *cons = &ins->constants;
2196 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2197
2198 bool is_vector = false;
2199 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2200
2201 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2202 /* We only care if this component is actually used */
2203 if (!(mask & (1 << c)))
2204 continue;
2205
2206 uint32_t test = is_16 ?
2207 cons->u16[ins->swizzle[1][c]] :
2208 cons->u32[ins->swizzle[1][c]];
2209
2210 if (test != value) {
2211 is_vector = true;
2212 break;
2213 }
2214 }
2215
2216 if (is_vector)
2217 continue;
2218
2219 /* Get rid of the embedded constant */
2220 ins->has_constants = false;
2221 ins->src[1] = ~0;
2222 ins->has_inline_constant = true;
2223 ins->inline_constant = scaled_constant;
2224 }
2225 }
2226 }
2227
2228 /* Dead code elimination for branches at the end of a block - only one branch
2229 * per block is legal semantically */
2230
2231 static void
2232 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2233 {
2234 bool branched = false;
2235
2236 mir_foreach_instr_in_block_safe(block, ins) {
2237 if (!midgard_is_branch_unit(ins->unit)) continue;
2238
2239 if (branched)
2240 mir_remove_instruction(ins);
2241
2242 branched = true;
2243 }
2244 }
2245
2246 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2247 * the move can be propagated away entirely */
2248
2249 static bool
2250 mir_compose_float_outmod(midgard_outmod_float *outmod, midgard_outmod_float comp)
2251 {
2252 /* Nothing to do */
2253 if (comp == midgard_outmod_none)
2254 return true;
2255
2256 if (*outmod == midgard_outmod_none) {
2257 *outmod = comp;
2258 return true;
2259 }
2260
2261 /* TODO: Compose rules */
2262 return false;
2263 }
2264
2265 static bool
2266 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
2267 {
2268 bool progress = false;
2269
2270 mir_foreach_instr_in_block_safe(block, ins) {
2271 if (ins->type != TAG_ALU_4) continue;
2272 if (ins->alu.op != midgard_alu_op_fmov) continue;
2273 if (ins->alu.outmod != midgard_outmod_pos) continue;
2274
2275 /* TODO: Registers? */
2276 unsigned src = ins->src[1];
2277 if (src & PAN_IS_REG) continue;
2278
2279 /* There might be a source modifier, too */
2280 if (mir_nontrivial_source2_mod(ins)) continue;
2281
2282 /* Backpropagate the modifier */
2283 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
2284 if (v->type != TAG_ALU_4) continue;
2285 if (v->dest != src) continue;
2286
2287 /* Can we even take a float outmod? */
2288 if (midgard_is_integer_out_op(v->alu.op)) continue;
2289
2290 midgard_outmod_float temp = v->alu.outmod;
2291 progress |= mir_compose_float_outmod(&temp, ins->alu.outmod);
2292
2293 /* Throw in the towel.. */
2294 if (!progress) break;
2295
2296 /* Otherwise, transfer the modifier */
2297 v->alu.outmod = temp;
2298 ins->alu.outmod = midgard_outmod_none;
2299
2300 break;
2301 }
2302 }
2303
2304 return progress;
2305 }
2306
2307 static unsigned
2308 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2309 {
2310 /* Loop to ourselves */
2311 midgard_instruction *br = ctx->writeout_branch[rt];
2312 struct midgard_instruction ins = v_branch(false, false);
2313 ins.writeout = true;
2314 ins.writeout_depth = br->writeout_depth;
2315 ins.writeout_stencil = br->writeout_stencil;
2316 ins.branch.target_block = ctx->block_count - 1;
2317 ins.constants.u32[0] = br->constants.u32[0];
2318 emit_mir_instruction(ctx, ins);
2319
2320 ctx->current_block->epilogue = true;
2321 schedule_barrier(ctx);
2322 return ins.branch.target_block;
2323 }
2324
2325 static midgard_block *
2326 emit_block(compiler_context *ctx, nir_block *block)
2327 {
2328 midgard_block *this_block = ctx->after_block;
2329 ctx->after_block = NULL;
2330
2331 if (!this_block)
2332 this_block = create_empty_block(ctx);
2333
2334 list_addtail(&this_block->base.link, &ctx->blocks);
2335
2336 this_block->scheduled = false;
2337 ++ctx->block_count;
2338
2339 /* Set up current block */
2340 list_inithead(&this_block->base.instructions);
2341 ctx->current_block = this_block;
2342
2343 nir_foreach_instr(instr, block) {
2344 emit_instr(ctx, instr);
2345 ++ctx->instruction_count;
2346 }
2347
2348 return this_block;
2349 }
2350
2351 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2352
2353 static void
2354 emit_if(struct compiler_context *ctx, nir_if *nif)
2355 {
2356 midgard_block *before_block = ctx->current_block;
2357
2358 /* Speculatively emit the branch, but we can't fill it in until later */
2359 EMIT(branch, true, true);
2360 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2361 then_branch->src[0] = nir_src_index(ctx, &nif->condition);
2362
2363 /* Emit the two subblocks. */
2364 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2365 midgard_block *end_then_block = ctx->current_block;
2366
2367 /* Emit a jump from the end of the then block to the end of the else */
2368 EMIT(branch, false, false);
2369 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2370
2371 /* Emit second block, and check if it's empty */
2372
2373 int else_idx = ctx->block_count;
2374 int count_in = ctx->instruction_count;
2375 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2376 midgard_block *end_else_block = ctx->current_block;
2377 int after_else_idx = ctx->block_count;
2378
2379 /* Now that we have the subblocks emitted, fix up the branches */
2380
2381 assert(then_block);
2382 assert(else_block);
2383
2384 if (ctx->instruction_count == count_in) {
2385 /* The else block is empty, so don't emit an exit jump */
2386 mir_remove_instruction(then_exit);
2387 then_branch->branch.target_block = after_else_idx;
2388 } else {
2389 then_branch->branch.target_block = else_idx;
2390 then_exit->branch.target_block = after_else_idx;
2391 }
2392
2393 /* Wire up the successors */
2394
2395 ctx->after_block = create_empty_block(ctx);
2396
2397 pan_block_add_successor(&before_block->base, &then_block->base);
2398 pan_block_add_successor(&before_block->base, &else_block->base);
2399
2400 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2401 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2402 }
2403
2404 static void
2405 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2406 {
2407 /* Remember where we are */
2408 midgard_block *start_block = ctx->current_block;
2409
2410 /* Allocate a loop number, growing the current inner loop depth */
2411 int loop_idx = ++ctx->current_loop_depth;
2412
2413 /* Get index from before the body so we can loop back later */
2414 int start_idx = ctx->block_count;
2415
2416 /* Emit the body itself */
2417 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2418
2419 /* Branch back to loop back */
2420 struct midgard_instruction br_back = v_branch(false, false);
2421 br_back.branch.target_block = start_idx;
2422 emit_mir_instruction(ctx, br_back);
2423
2424 /* Mark down that branch in the graph. */
2425 pan_block_add_successor(&start_block->base, &loop_block->base);
2426 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2427
2428 /* Find the index of the block about to follow us (note: we don't add
2429 * one; blocks are 0-indexed so we get a fencepost problem) */
2430 int break_block_idx = ctx->block_count;
2431
2432 /* Fix up the break statements we emitted to point to the right place,
2433 * now that we can allocate a block number for them */
2434 ctx->after_block = create_empty_block(ctx);
2435
2436 mir_foreach_block_from(ctx, start_block, _block) {
2437 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2438 if (ins->type != TAG_ALU_4) continue;
2439 if (!ins->compact_branch) continue;
2440
2441 /* We found a branch -- check the type to see if we need to do anything */
2442 if (ins->branch.target_type != TARGET_BREAK) continue;
2443
2444 /* It's a break! Check if it's our break */
2445 if (ins->branch.target_break != loop_idx) continue;
2446
2447 /* Okay, cool, we're breaking out of this loop.
2448 * Rewrite from a break to a goto */
2449
2450 ins->branch.target_type = TARGET_GOTO;
2451 ins->branch.target_block = break_block_idx;
2452
2453 pan_block_add_successor(_block, &ctx->after_block->base);
2454 }
2455 }
2456
2457 /* Now that we've finished emitting the loop, free up the depth again
2458 * so we play nice with recursion amid nested loops */
2459 --ctx->current_loop_depth;
2460
2461 /* Dump loop stats */
2462 ++ctx->loop_count;
2463 }
2464
2465 static midgard_block *
2466 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2467 {
2468 midgard_block *start_block = NULL;
2469
2470 foreach_list_typed(nir_cf_node, node, node, list) {
2471 switch (node->type) {
2472 case nir_cf_node_block: {
2473 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2474
2475 if (!start_block)
2476 start_block = block;
2477
2478 break;
2479 }
2480
2481 case nir_cf_node_if:
2482 emit_if(ctx, nir_cf_node_as_if(node));
2483 break;
2484
2485 case nir_cf_node_loop:
2486 emit_loop(ctx, nir_cf_node_as_loop(node));
2487 break;
2488
2489 case nir_cf_node_function:
2490 assert(0);
2491 break;
2492 }
2493 }
2494
2495 return start_block;
2496 }
2497
2498 /* Due to lookahead, we need to report the first tag executed in the command
2499 * stream and in branch targets. An initial block might be empty, so iterate
2500 * until we find one that 'works' */
2501
2502 static unsigned
2503 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2504 {
2505 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2506
2507 mir_foreach_block_from(ctx, initial_block, _v) {
2508 midgard_block *v = (midgard_block *) _v;
2509 if (v->quadword_count) {
2510 midgard_bundle *initial_bundle =
2511 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2512
2513 return initial_bundle->tag;
2514 }
2515 }
2516
2517 /* Default to a tag 1 which will break from the shader, in case we jump
2518 * to the exit block (i.e. `return` in a compute shader) */
2519
2520 return 1;
2521 }
2522
2523 /* For each fragment writeout instruction, generate a writeout loop to
2524 * associate with it */
2525
2526 static void
2527 mir_add_writeout_loops(compiler_context *ctx)
2528 {
2529 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2530 midgard_instruction *br = ctx->writeout_branch[rt];
2531 if (!br) continue;
2532
2533 unsigned popped = br->branch.target_block;
2534 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2535 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2536
2537 /* If we have more RTs, we'll need to restore back after our
2538 * loop terminates */
2539
2540 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2541 midgard_instruction uncond = v_branch(false, false);
2542 uncond.branch.target_block = popped;
2543 emit_mir_instruction(ctx, uncond);
2544 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2545 schedule_barrier(ctx);
2546 } else {
2547 /* We're last, so we can terminate here */
2548 br->last_writeout = true;
2549 }
2550 }
2551 }
2552
2553 int
2554 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2555 {
2556 struct util_dynarray *compiled = &program->compiled;
2557
2558 midgard_debug = debug_get_option_midgard_debug();
2559
2560 /* TODO: Bound against what? */
2561 compiler_context *ctx = rzalloc(NULL, compiler_context);
2562
2563 ctx->nir = nir;
2564 ctx->stage = nir->info.stage;
2565 ctx->is_blend = is_blend;
2566 ctx->alpha_ref = program->alpha_ref;
2567 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2568 ctx->quirks = midgard_get_quirks(gpu_id);
2569
2570 /* Start off with a safe cutoff, allowing usage of all 16 work
2571 * registers. Later, we'll promote uniform reads to uniform registers
2572 * if we determine it is beneficial to do so */
2573 ctx->uniform_cutoff = 8;
2574
2575 /* Initialize at a global (not block) level hash tables */
2576
2577 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2578 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2579
2580 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2581 * (so we don't accidentally duplicate the epilogue since mesa/st has
2582 * messed with our I/O quite a bit already) */
2583
2584 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2585
2586 if (ctx->stage == MESA_SHADER_VERTEX) {
2587 NIR_PASS_V(nir, nir_lower_viewport_transform);
2588 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2589 }
2590
2591 NIR_PASS_V(nir, nir_lower_var_copies);
2592 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2593 NIR_PASS_V(nir, nir_split_var_copies);
2594 NIR_PASS_V(nir, nir_lower_var_copies);
2595 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2596 NIR_PASS_V(nir, nir_lower_var_copies);
2597 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2598
2599 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2600 NIR_PASS_V(nir, nir_lower_ssbo);
2601 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2602
2603 /* Optimisation passes */
2604
2605 optimise_nir(nir, ctx->quirks);
2606
2607 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2608 nir_print_shader(nir, stdout);
2609 }
2610
2611 /* Assign sysvals and counts, now that we're sure
2612 * (post-optimisation) */
2613
2614 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2615 program->sysval_count = ctx->sysvals.sysval_count;
2616 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2617
2618 nir_foreach_function(func, nir) {
2619 if (!func->impl)
2620 continue;
2621
2622 list_inithead(&ctx->blocks);
2623 ctx->block_count = 0;
2624 ctx->func = func;
2625
2626 emit_cf_list(ctx, &func->impl->body);
2627 break; /* TODO: Multi-function shaders */
2628 }
2629
2630 util_dynarray_init(compiled, NULL);
2631
2632 /* Per-block lowering before opts */
2633
2634 mir_foreach_block(ctx, _block) {
2635 midgard_block *block = (midgard_block *) _block;
2636 inline_alu_constants(ctx, block);
2637 midgard_opt_promote_fmov(ctx, block);
2638 embedded_to_inline_constant(ctx, block);
2639 }
2640 /* MIR-level optimizations */
2641
2642 bool progress = false;
2643
2644 do {
2645 progress = false;
2646
2647 mir_foreach_block(ctx, _block) {
2648 midgard_block *block = (midgard_block *) _block;
2649 progress |= midgard_opt_pos_propagate(ctx, block);
2650 progress |= midgard_opt_copy_prop(ctx, block);
2651 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2652 progress |= midgard_opt_combine_projection(ctx, block);
2653 progress |= midgard_opt_varying_projection(ctx, block);
2654 progress |= midgard_opt_not_propagate(ctx, block);
2655 progress |= midgard_opt_fuse_src_invert(ctx, block);
2656 progress |= midgard_opt_fuse_dest_invert(ctx, block);
2657 progress |= midgard_opt_csel_invert(ctx, block);
2658 progress |= midgard_opt_drop_cmp_invert(ctx, block);
2659 progress |= midgard_opt_invert_branch(ctx, block);
2660 }
2661 } while (progress);
2662
2663 mir_foreach_block(ctx, _block) {
2664 midgard_block *block = (midgard_block *) _block;
2665 midgard_lower_invert(ctx, block);
2666 midgard_lower_derivatives(ctx, block);
2667 }
2668
2669 /* Nested control-flow can result in dead branches at the end of the
2670 * block. This messes with our analysis and is just dead code, so cull
2671 * them */
2672 mir_foreach_block(ctx, _block) {
2673 midgard_block *block = (midgard_block *) _block;
2674 midgard_opt_cull_dead_branch(ctx, block);
2675 }
2676
2677 /* Ensure we were lowered */
2678 mir_foreach_instr_global(ctx, ins) {
2679 assert(!ins->invert);
2680 }
2681
2682 if (ctx->stage == MESA_SHADER_FRAGMENT)
2683 mir_add_writeout_loops(ctx);
2684
2685 /* Schedule! */
2686 midgard_schedule_program(ctx);
2687 mir_ra(ctx);
2688
2689 /* Now that all the bundles are scheduled and we can calculate block
2690 * sizes, emit actual branch instructions rather than placeholders */
2691
2692 int br_block_idx = 0;
2693
2694 mir_foreach_block(ctx, _block) {
2695 midgard_block *block = (midgard_block *) _block;
2696 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2697 for (int c = 0; c < bundle->instruction_count; ++c) {
2698 midgard_instruction *ins = bundle->instructions[c];
2699
2700 if (!midgard_is_branch_unit(ins->unit)) continue;
2701
2702 /* Parse some basic branch info */
2703 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2704 bool is_conditional = ins->branch.conditional;
2705 bool is_inverted = ins->branch.invert_conditional;
2706 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2707 bool is_writeout = ins->writeout;
2708
2709 /* Determine the block we're jumping to */
2710 int target_number = ins->branch.target_block;
2711
2712 /* Report the destination tag */
2713 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2714
2715 /* Count up the number of quadwords we're
2716 * jumping over = number of quadwords until
2717 * (br_block_idx, target_number) */
2718
2719 int quadword_offset = 0;
2720
2721 if (is_discard) {
2722 /* Ignored */
2723 } else if (target_number > br_block_idx) {
2724 /* Jump forward */
2725
2726 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2727 midgard_block *blk = mir_get_block(ctx, idx);
2728 assert(blk);
2729
2730 quadword_offset += blk->quadword_count;
2731 }
2732 } else {
2733 /* Jump backwards */
2734
2735 for (int idx = br_block_idx; idx >= target_number; --idx) {
2736 midgard_block *blk = mir_get_block(ctx, idx);
2737 assert(blk);
2738
2739 quadword_offset -= blk->quadword_count;
2740 }
2741 }
2742
2743 /* Unconditional extended branches (far jumps)
2744 * have issues, so we always use a conditional
2745 * branch, setting the condition to always for
2746 * unconditional. For compact unconditional
2747 * branches, cond isn't used so it doesn't
2748 * matter what we pick. */
2749
2750 midgard_condition cond =
2751 !is_conditional ? midgard_condition_always :
2752 is_inverted ? midgard_condition_false :
2753 midgard_condition_true;
2754
2755 midgard_jmp_writeout_op op =
2756 is_discard ? midgard_jmp_writeout_op_discard :
2757 is_writeout ? midgard_jmp_writeout_op_writeout :
2758 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2759 midgard_jmp_writeout_op_branch_cond;
2760
2761 if (!is_compact) {
2762 midgard_branch_extended branch =
2763 midgard_create_branch_extended(
2764 cond, op,
2765 dest_tag,
2766 quadword_offset);
2767
2768 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2769 } else if (is_conditional || is_discard) {
2770 midgard_branch_cond branch = {
2771 .op = op,
2772 .dest_tag = dest_tag,
2773 .offset = quadword_offset,
2774 .cond = cond
2775 };
2776
2777 assert(branch.offset == quadword_offset);
2778
2779 memcpy(&ins->br_compact, &branch, sizeof(branch));
2780 } else {
2781 assert(op == midgard_jmp_writeout_op_branch_uncond);
2782
2783 midgard_branch_uncond branch = {
2784 .op = op,
2785 .dest_tag = dest_tag,
2786 .offset = quadword_offset,
2787 .unknown = 1
2788 };
2789
2790 assert(branch.offset == quadword_offset);
2791
2792 memcpy(&ins->br_compact, &branch, sizeof(branch));
2793 }
2794 }
2795 }
2796
2797 ++br_block_idx;
2798 }
2799
2800 /* Emit flat binary from the instruction arrays. Iterate each block in
2801 * sequence. Save instruction boundaries such that lookahead tags can
2802 * be assigned easily */
2803
2804 /* Cache _all_ bundles in source order for lookahead across failed branches */
2805
2806 int bundle_count = 0;
2807 mir_foreach_block(ctx, _block) {
2808 midgard_block *block = (midgard_block *) _block;
2809 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2810 }
2811 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2812 int bundle_idx = 0;
2813 mir_foreach_block(ctx, _block) {
2814 midgard_block *block = (midgard_block *) _block;
2815 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2816 source_order_bundles[bundle_idx++] = bundle;
2817 }
2818 }
2819
2820 int current_bundle = 0;
2821
2822 /* Midgard prefetches instruction types, so during emission we
2823 * need to lookahead. Unless this is the last instruction, in
2824 * which we return 1. */
2825
2826 mir_foreach_block(ctx, _block) {
2827 midgard_block *block = (midgard_block *) _block;
2828 mir_foreach_bundle_in_block(block, bundle) {
2829 int lookahead = 1;
2830
2831 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2832 lookahead = source_order_bundles[current_bundle + 1]->tag;
2833
2834 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2835 ++current_bundle;
2836 }
2837
2838 /* TODO: Free deeper */
2839 //util_dynarray_fini(&block->instructions);
2840 }
2841
2842 free(source_order_bundles);
2843
2844 /* Report the very first tag executed */
2845 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2846
2847 /* Deal with off-by-one related to the fencepost problem */
2848 program->work_register_count = ctx->work_registers + 1;
2849 program->uniform_cutoff = ctx->uniform_cutoff;
2850
2851 program->blend_patch_offset = ctx->blend_constant_offset;
2852 program->tls_size = ctx->tls_size;
2853
2854 if (midgard_debug & MIDGARD_DBG_SHADERS)
2855 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2856
2857 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2858 unsigned nr_bundles = 0, nr_ins = 0;
2859
2860 /* Count instructions and bundles */
2861
2862 mir_foreach_block(ctx, _block) {
2863 midgard_block *block = (midgard_block *) _block;
2864 nr_bundles += util_dynarray_num_elements(
2865 &block->bundles, midgard_bundle);
2866
2867 mir_foreach_bundle_in_block(block, bun)
2868 nr_ins += bun->instruction_count;
2869 }
2870
2871 /* Calculate thread count. There are certain cutoffs by
2872 * register count for thread count */
2873
2874 unsigned nr_registers = program->work_register_count;
2875
2876 unsigned nr_threads =
2877 (nr_registers <= 4) ? 4 :
2878 (nr_registers <= 8) ? 2 :
2879 1;
2880
2881 /* Dump stats */
2882
2883 fprintf(stderr, "shader%d - %s shader: "
2884 "%u inst, %u bundles, %u quadwords, "
2885 "%u registers, %u threads, %u loops, "
2886 "%u:%u spills:fills\n",
2887 SHADER_DB_COUNT++,
2888 gl_shader_stage_name(ctx->stage),
2889 nr_ins, nr_bundles, ctx->quadword_count,
2890 nr_registers, nr_threads,
2891 ctx->loop_count,
2892 ctx->spills, ctx->fills);
2893 }
2894
2895 ralloc_free(ctx);
2896
2897 return 0;
2898 }