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pan/mdg: Handle comparisons in fp16 path
[mesa.git] / src / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50 #include "midgard_quirks.h"
51
52 #include "disassemble.h"
53
54 static const struct debug_named_value debug_options[] = {
55 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"},
58 DEBUG_NAMED_VALUE_END
59 };
60
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
62
63 unsigned SHADER_DB_COUNT = 0;
64
65 int midgard_debug = 0;
66
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block *
72 create_empty_block(compiler_context *ctx)
73 {
74 midgard_block *blk = rzalloc(ctx, midgard_block);
75
76 blk->base.predecessors = _mesa_set_create(blk,
77 _mesa_hash_pointer,
78 _mesa_key_pointer_equal);
79
80 blk->base.name = ctx->block_source_count++;
81
82 return blk;
83 }
84
85 static void
86 schedule_barrier(compiler_context *ctx)
87 {
88 midgard_block *temp = ctx->after_block;
89 ctx->after_block = create_empty_block(ctx);
90 ctx->block_count++;
91 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
92 list_inithead(&ctx->after_block->base.instructions);
93 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
94 ctx->current_block = ctx->after_block;
95 ctx->after_block = temp;
96 }
97
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
100
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
102
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
107 .mask = 0xF, \
108 .dest = ~0, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
111 .load_store = { \
112 .op = midgard_op_##name, \
113 .address = address \
114 } \
115 }; \
116 \
117 if (store) { \
118 i.src[0] = ssa; \
119 i.src_types[0] = T; \
120 } else { \
121 i.dest = ssa; \
122 i.dest_type = T; \
123 } \
124 return i; \
125 }
126
127 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
128 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
129
130 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
131 * the corresponding Midgard source */
132
133 static midgard_vector_alu_src
134 vector_alu_modifiers(bool abs, bool neg, bool is_int,
135 bool half, bool sext)
136 {
137 /* Figure out how many components there are so we can adjust.
138 * Specifically we want to broadcast the last channel so things like
139 * ball2/3 work.
140 */
141
142 midgard_vector_alu_src alu_src = {
143 .rep_low = 0,
144 .rep_high = 0,
145 .half = half
146 };
147
148 if (is_int) {
149 alu_src.mod = midgard_int_normal;
150
151 /* Sign/zero-extend if needed */
152
153 if (half) {
154 alu_src.mod = sext ?
155 midgard_int_sign_extend
156 : midgard_int_zero_extend;
157 }
158
159 /* These should have been lowered away */
160 assert(!(abs || neg));
161 } else {
162 alu_src.mod = (abs << 0) | (neg << 1);
163 }
164
165 return alu_src;
166 }
167
168 M_LOAD(ld_attr_32, nir_type_uint32);
169 M_LOAD(ld_vary_32, nir_type_uint32);
170 M_LOAD(ld_ubo_int4, nir_type_uint32);
171 M_LOAD(ld_int4, nir_type_uint32);
172 M_STORE(st_int4, nir_type_uint32);
173 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
174 M_STORE(st_vary_32, nir_type_uint32);
175 M_LOAD(ld_cubemap_coords, nir_type_uint32);
176 M_LOAD(ld_compute_id, nir_type_uint32);
177
178 static midgard_instruction
179 v_branch(bool conditional, bool invert)
180 {
181 midgard_instruction ins = {
182 .type = TAG_ALU_4,
183 .unit = ALU_ENAB_BRANCH,
184 .compact_branch = true,
185 .branch = {
186 .conditional = conditional,
187 .invert_conditional = invert
188 },
189 .dest = ~0,
190 .src = { ~0, ~0, ~0, ~0 },
191 };
192
193 return ins;
194 }
195
196 static midgard_branch_extended
197 midgard_create_branch_extended( midgard_condition cond,
198 midgard_jmp_writeout_op op,
199 unsigned dest_tag,
200 signed quadword_offset)
201 {
202 /* The condition code is actually a LUT describing a function to
203 * combine multiple condition codes. However, we only support a single
204 * condition code at the moment, so we just duplicate over a bunch of
205 * times. */
206
207 uint16_t duplicated_cond =
208 (cond << 14) |
209 (cond << 12) |
210 (cond << 10) |
211 (cond << 8) |
212 (cond << 6) |
213 (cond << 4) |
214 (cond << 2) |
215 (cond << 0);
216
217 midgard_branch_extended branch = {
218 .op = op,
219 .dest_tag = dest_tag,
220 .offset = quadword_offset,
221 .cond = duplicated_cond
222 };
223
224 return branch;
225 }
226
227 static void
228 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
229 {
230 ins->has_constants = true;
231 memcpy(&ins->constants, constants, 16);
232 }
233
234 static int
235 glsl_type_size(const struct glsl_type *type, bool bindless)
236 {
237 return glsl_count_attribute_slots(type, false);
238 }
239
240 /* Lower fdot2 to a vector multiplication followed by channel addition */
241 static void
242 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
243 {
244 if (alu->op != nir_op_fdot2)
245 return;
246
247 b->cursor = nir_before_instr(&alu->instr);
248
249 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
250 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
251
252 nir_ssa_def *product = nir_fmul(b, src0, src1);
253
254 nir_ssa_def *sum = nir_fadd(b,
255 nir_channel(b, product, 0),
256 nir_channel(b, product, 1));
257
258 /* Replace the fdot2 with this sum */
259 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
260 }
261
262 static bool
263 midgard_nir_lower_fdot2(nir_shader *shader)
264 {
265 bool progress = false;
266
267 nir_foreach_function(function, shader) {
268 if (!function->impl) continue;
269
270 nir_builder _b;
271 nir_builder *b = &_b;
272 nir_builder_init(b, function->impl);
273
274 nir_foreach_block(block, function->impl) {
275 nir_foreach_instr_safe(instr, block) {
276 if (instr->type != nir_instr_type_alu) continue;
277
278 nir_alu_instr *alu = nir_instr_as_alu(instr);
279 midgard_nir_lower_fdot2_body(b, alu);
280
281 progress |= true;
282 }
283 }
284
285 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
286
287 }
288
289 return progress;
290 }
291
292 /* Midgard can't write depth and stencil separately. It has to happen in a
293 * single store operation containing both. Let's add a panfrost specific
294 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
295 * one.
296 */
297 static bool
298 midgard_nir_lower_zs_store(nir_shader *nir)
299 {
300 if (nir->info.stage != MESA_SHADER_FRAGMENT)
301 return false;
302
303 nir_variable *z_var = NULL, *s_var = NULL;
304
305 nir_foreach_variable(var, &nir->outputs) {
306 if (var->data.location == FRAG_RESULT_DEPTH)
307 z_var = var;
308 else if (var->data.location == FRAG_RESULT_STENCIL)
309 s_var = var;
310 }
311
312 if (!z_var && !s_var)
313 return false;
314
315 bool progress = false;
316
317 nir_foreach_function(function, nir) {
318 if (!function->impl) continue;
319
320 nir_intrinsic_instr *z_store = NULL, *s_store = NULL, *last_store = NULL;
321
322 nir_foreach_block(block, function->impl) {
323 nir_foreach_instr_safe(instr, block) {
324 if (instr->type != nir_instr_type_intrinsic)
325 continue;
326
327 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
328 if (intr->intrinsic != nir_intrinsic_store_output)
329 continue;
330
331 if (z_var && nir_intrinsic_base(intr) == z_var->data.driver_location) {
332 assert(!z_store);
333 z_store = intr;
334 last_store = intr;
335 }
336
337 if (s_var && nir_intrinsic_base(intr) == s_var->data.driver_location) {
338 assert(!s_store);
339 s_store = intr;
340 last_store = intr;
341 }
342 }
343 }
344
345 if (!z_store && !s_store) continue;
346
347 nir_builder b;
348 nir_builder_init(&b, function->impl);
349
350 b.cursor = nir_before_instr(&last_store->instr);
351
352 nir_ssa_def *zs_store_src;
353
354 if (z_store && s_store) {
355 nir_ssa_def *srcs[2] = {
356 nir_ssa_for_src(&b, z_store->src[0], 1),
357 nir_ssa_for_src(&b, s_store->src[0], 1),
358 };
359
360 zs_store_src = nir_vec(&b, srcs, 2);
361 } else {
362 zs_store_src = nir_ssa_for_src(&b, last_store->src[0], 1);
363 }
364
365 nir_intrinsic_instr *zs_store;
366
367 zs_store = nir_intrinsic_instr_create(b.shader,
368 nir_intrinsic_store_zs_output_pan);
369 zs_store->src[0] = nir_src_for_ssa(zs_store_src);
370 zs_store->num_components = z_store && s_store ? 2 : 1;
371 nir_intrinsic_set_component(zs_store, z_store ? 0 : 1);
372
373 /* Replace the Z and S store by a ZS store */
374 nir_builder_instr_insert(&b, &zs_store->instr);
375
376 if (z_store)
377 nir_instr_remove(&z_store->instr);
378
379 if (s_store)
380 nir_instr_remove(&s_store->instr);
381
382 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
383 progress = true;
384 }
385
386 return progress;
387 }
388
389 /* Flushes undefined values to zero */
390
391 static void
392 optimise_nir(nir_shader *nir, unsigned quirks)
393 {
394 bool progress;
395 unsigned lower_flrp =
396 (nir->options->lower_flrp16 ? 16 : 0) |
397 (nir->options->lower_flrp32 ? 32 : 0) |
398 (nir->options->lower_flrp64 ? 64 : 0);
399
400 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
401 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
402
403 nir_lower_tex_options lower_tex_options = {
404 .lower_txs_lod = true,
405 .lower_txp = ~0,
406 .lower_tex_without_implicit_lod =
407 (quirks & MIDGARD_EXPLICIT_LOD),
408
409 /* TODO: we have native gradient.. */
410 .lower_txd = true,
411 };
412
413 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
414
415 /* Must lower fdot2 after tex is lowered */
416 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
417
418 /* T720 is broken. */
419
420 if (quirks & MIDGARD_BROKEN_LOD)
421 NIR_PASS_V(nir, midgard_nir_lod_errata);
422
423 do {
424 progress = false;
425
426 NIR_PASS(progress, nir, nir_lower_var_copies);
427 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
428
429 NIR_PASS(progress, nir, nir_copy_prop);
430 NIR_PASS(progress, nir, nir_opt_remove_phis);
431 NIR_PASS(progress, nir, nir_opt_dce);
432 NIR_PASS(progress, nir, nir_opt_dead_cf);
433 NIR_PASS(progress, nir, nir_opt_cse);
434 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
435 NIR_PASS(progress, nir, nir_opt_algebraic);
436 NIR_PASS(progress, nir, nir_opt_constant_folding);
437
438 if (lower_flrp != 0) {
439 bool lower_flrp_progress = false;
440 NIR_PASS(lower_flrp_progress,
441 nir,
442 nir_lower_flrp,
443 lower_flrp,
444 false /* always_precise */,
445 nir->options->lower_ffma);
446 if (lower_flrp_progress) {
447 NIR_PASS(progress, nir,
448 nir_opt_constant_folding);
449 progress = true;
450 }
451
452 /* Nothing should rematerialize any flrps, so we only
453 * need to do this lowering once.
454 */
455 lower_flrp = 0;
456 }
457
458 NIR_PASS(progress, nir, nir_opt_undef);
459 NIR_PASS(progress, nir, nir_undef_to_zero);
460
461 NIR_PASS(progress, nir, nir_opt_loop_unroll,
462 nir_var_shader_in |
463 nir_var_shader_out |
464 nir_var_function_temp);
465
466 NIR_PASS(progress, nir, nir_opt_vectorize);
467 } while (progress);
468
469 /* Must be run at the end to prevent creation of fsin/fcos ops */
470 NIR_PASS(progress, nir, midgard_nir_scale_trig);
471
472 do {
473 progress = false;
474
475 NIR_PASS(progress, nir, nir_opt_dce);
476 NIR_PASS(progress, nir, nir_opt_algebraic);
477 NIR_PASS(progress, nir, nir_opt_constant_folding);
478 NIR_PASS(progress, nir, nir_copy_prop);
479 } while (progress);
480
481 NIR_PASS(progress, nir, nir_opt_algebraic_late);
482 NIR_PASS(progress, nir, nir_opt_algebraic_distribute_src_mods);
483
484 /* We implement booleans as 32-bit 0/~0 */
485 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
486
487 /* Now that booleans are lowered, we can run out late opts */
488 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
489 NIR_PASS(progress, nir, midgard_nir_cancel_inot);
490
491 NIR_PASS(progress, nir, nir_copy_prop);
492 NIR_PASS(progress, nir, nir_opt_dce);
493
494 /* Take us out of SSA */
495 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
496 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
497
498 /* We are a vector architecture; write combine where possible */
499 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
500 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
501
502 NIR_PASS(progress, nir, nir_opt_dce);
503 }
504
505 /* Do not actually emit a load; instead, cache the constant for inlining */
506
507 static void
508 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
509 {
510 nir_ssa_def def = instr->def;
511
512 midgard_constants *consts = rzalloc(NULL, midgard_constants);
513
514 assert(instr->def.num_components * instr->def.bit_size <= sizeof(*consts) * 8);
515
516 #define RAW_CONST_COPY(bits) \
517 nir_const_value_to_array(consts->u##bits, instr->value, \
518 instr->def.num_components, u##bits)
519
520 switch (instr->def.bit_size) {
521 case 64:
522 RAW_CONST_COPY(64);
523 break;
524 case 32:
525 RAW_CONST_COPY(32);
526 break;
527 case 16:
528 RAW_CONST_COPY(16);
529 break;
530 case 8:
531 RAW_CONST_COPY(8);
532 break;
533 default:
534 unreachable("Invalid bit_size for load_const instruction\n");
535 }
536
537 /* Shifted for SSA, +1 for off-by-one */
538 _mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, consts);
539 }
540
541 /* Normally constants are embedded implicitly, but for I/O and such we have to
542 * explicitly emit a move with the constant source */
543
544 static void
545 emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
546 {
547 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
548
549 if (constant_value) {
550 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
551 attach_constants(ctx, &ins, constant_value, node + 1);
552 emit_mir_instruction(ctx, ins);
553 }
554 }
555
556 static bool
557 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
558 {
559 unsigned comp = src->swizzle[0];
560
561 for (unsigned c = 1; c < nr_components; ++c) {
562 if (src->swizzle[c] != comp)
563 return true;
564 }
565
566 return false;
567 }
568
569 #define ALU_CASE(nir, _op) \
570 case nir_op_##nir: \
571 op = midgard_alu_op_##_op; \
572 assert(src_bitsize == dst_bitsize); \
573 break;
574
575 #define ALU_CASE_BCAST(nir, _op, count) \
576 case nir_op_##nir: \
577 op = midgard_alu_op_##_op; \
578 broadcast_swizzle = count; \
579 assert(src_bitsize == dst_bitsize); \
580 break;
581
582 #define ALU_CHECK_CMP(sext) \
583 if (src_bitsize == 16 && dst_bitsize == 32) { \
584 half_1 = true; \
585 half_2 = true; \
586 sext_1 = sext; \
587 sext_2 = sext; \
588 } else { \
589 assert(src_bitsize == dst_bitsize); \
590 } \
591
592 #define ALU_CASE_CMP(nir, _op, sext) \
593 case nir_op_##nir: \
594 op = midgard_alu_op_##_op; \
595 ALU_CHECK_CMP(sext); \
596 break;
597
598 /* Analyze the sizes of the dest and inputs to determine reg mode. */
599
600 static midgard_reg_mode
601 reg_mode_for_nir(nir_alu_instr *instr)
602 {
603 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
604 unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
605 unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
606
607 switch (max_bitsize) {
608 case 8:
609 return midgard_reg_mode_8;
610 case 16:
611 return midgard_reg_mode_16;
612 case 32:
613 return midgard_reg_mode_32;
614 case 64:
615 return midgard_reg_mode_64;
616 default:
617 unreachable("Invalid bit size");
618 }
619 }
620
621 /* Compare mir_lower_invert */
622 static bool
623 nir_accepts_inot(nir_op op, unsigned src)
624 {
625 switch (op) {
626 case nir_op_ior:
627 case nir_op_iand:
628 case nir_op_ixor:
629 return true;
630 case nir_op_b32csel:
631 /* Only the condition */
632 return (src == 0);
633 default:
634 return false;
635 }
636 }
637
638 static bool
639 mir_accept_dest_mod(compiler_context *ctx, nir_dest **dest, nir_op op)
640 {
641 if (pan_has_dest_mod(dest, op)) {
642 assert((*dest)->is_ssa);
643 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index);
644 return true;
645 }
646
647 return false;
648 }
649
650 static void
651 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, bool is_int, unsigned bcast_count)
652 {
653 nir_alu_src src = instr->src[i];
654
655 if (!is_int) {
656 if (pan_has_source_mod(&src, nir_op_fneg))
657 *neg = !(*neg);
658
659 if (pan_has_source_mod(&src, nir_op_fabs))
660 *abs = true;
661 }
662
663 if (nir_accepts_inot(instr->op, i) && pan_has_source_mod(&src, nir_op_inot))
664 *not = true;
665
666 unsigned bits = nir_src_bit_size(src.src);
667
668 ins->src[to] = nir_src_index(NULL, &src.src);
669 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
670
671 for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c) {
672 ins->swizzle[to][c] = src.swizzle[
673 (!bcast_count || c < bcast_count) ? c :
674 (bcast_count - 1)];
675 }
676 }
677
678 /* Midgard features both fcsel and icsel, depending on whether you want int or
679 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
680 * we should emit an int or float csel depending on what modifiers could be
681 * placed. In the absense of modifiers, this is probably arbitrary. */
682
683 static bool
684 mir_is_bcsel_float(nir_alu_instr *instr)
685 {
686 nir_op intmods[] = {
687 nir_op_i2i8, nir_op_i2i16,
688 nir_op_i2i32, nir_op_i2i64
689 };
690
691 nir_op floatmods[] = {
692 nir_op_fabs, nir_op_fneg,
693 nir_op_f2f16, nir_op_f2f32,
694 nir_op_f2f64
695 };
696
697 nir_op floatdestmods[] = {
698 nir_op_fsat, nir_op_fsat_signed, nir_op_fclamp_pos,
699 nir_op_f2f16, nir_op_f2f32
700 };
701
702 signed score = 0;
703
704 for (unsigned i = 1; i < 3; ++i) {
705 nir_alu_src s = instr->src[i];
706 for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
707 if (pan_has_source_mod(&s, intmods[q]))
708 score--;
709 }
710 }
711
712 for (unsigned i = 1; i < 3; ++i) {
713 nir_alu_src s = instr->src[i];
714 for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
715 if (pan_has_source_mod(&s, floatmods[q]))
716 score++;
717 }
718 }
719
720 for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
721 nir_dest *dest = &instr->dest.dest;
722 if (pan_has_dest_mod(&dest, floatdestmods[q]))
723 score++;
724 }
725
726 return (score > 0);
727 }
728
729 static void
730 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
731 {
732 nir_dest *dest = &instr->dest.dest;
733
734 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index))
735 return;
736
737 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
738 * is handled elsewhere */
739
740 if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
741 midgard_emit_derivatives(ctx, instr);
742 return;
743 }
744
745 bool is_ssa = dest->is_ssa;
746
747 unsigned nr_components = nir_dest_num_components(*dest);
748 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
749 unsigned op = 0;
750
751 /* Number of components valid to check for the instruction (the rest
752 * will be forced to the last), or 0 to use as-is. Relevant as
753 * ball-type instructions have a channel count in NIR but are all vec4
754 * in Midgard */
755
756 unsigned broadcast_swizzle = 0;
757
758 /* What register mode should we operate in? */
759 midgard_reg_mode reg_mode =
760 reg_mode_for_nir(instr);
761
762 /* Do we need a destination override? Used for inline
763 * type conversion */
764
765 midgard_dest_override dest_override =
766 midgard_dest_override_none;
767
768 /* Should we use a smaller respective source and sign-extend? */
769
770 bool half_1 = false, sext_1 = false;
771 bool half_2 = false, sext_2 = false;
772
773 /* Should we swap arguments? */
774 bool flip_src12 = false;
775
776 unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
777 unsigned dst_bitsize = nir_dest_bit_size(*dest);
778
779 switch (instr->op) {
780 ALU_CASE(fadd, fadd);
781 ALU_CASE(fmul, fmul);
782 ALU_CASE(fmin, fmin);
783 ALU_CASE(fmax, fmax);
784 ALU_CASE(imin, imin);
785 ALU_CASE(imax, imax);
786 ALU_CASE(umin, umin);
787 ALU_CASE(umax, umax);
788 ALU_CASE(ffloor, ffloor);
789 ALU_CASE(fround_even, froundeven);
790 ALU_CASE(ftrunc, ftrunc);
791 ALU_CASE(fceil, fceil);
792 ALU_CASE(fdot3, fdot3);
793 ALU_CASE(fdot4, fdot4);
794 ALU_CASE(iadd, iadd);
795 ALU_CASE(isub, isub);
796 ALU_CASE(imul, imul);
797
798 /* Zero shoved as second-arg */
799 ALU_CASE(iabs, iabsdiff);
800
801 ALU_CASE(mov, imov);
802
803 ALU_CASE_CMP(feq32, feq, false);
804 ALU_CASE_CMP(fne32, fne, false);
805 ALU_CASE_CMP(flt32, flt, false);
806 ALU_CASE_CMP(ieq32, ieq, true);
807 ALU_CASE_CMP(ine32, ine, true);
808 ALU_CASE_CMP(ilt32, ilt, true);
809 ALU_CASE_CMP(ult32, ult, false);
810
811 /* We don't have a native b2f32 instruction. Instead, like many
812 * GPUs, we exploit booleans as 0/~0 for false/true, and
813 * correspondingly AND
814 * by 1.0 to do the type conversion. For the moment, prime us
815 * to emit:
816 *
817 * iand [whatever], #0
818 *
819 * At the end of emit_alu (as MIR), we'll fix-up the constant
820 */
821
822 ALU_CASE_CMP(b2f32, iand, true);
823 ALU_CASE_CMP(b2i32, iand, true);
824
825 /* Likewise, we don't have a dedicated f2b32 instruction, but
826 * we can do a "not equal to 0.0" test. */
827
828 ALU_CASE_CMP(f2b32, fne, false);
829 ALU_CASE_CMP(i2b32, ine, true);
830
831 ALU_CASE(frcp, frcp);
832 ALU_CASE(frsq, frsqrt);
833 ALU_CASE(fsqrt, fsqrt);
834 ALU_CASE(fexp2, fexp2);
835 ALU_CASE(flog2, flog2);
836
837 ALU_CASE(f2i64, f2i_rtz);
838 ALU_CASE(f2u64, f2u_rtz);
839 ALU_CASE(i2f64, i2f_rtz);
840 ALU_CASE(u2f64, u2f_rtz);
841
842 ALU_CASE(f2i32, f2i_rtz);
843 ALU_CASE(f2u32, f2u_rtz);
844 ALU_CASE(i2f32, i2f_rtz);
845 ALU_CASE(u2f32, u2f_rtz);
846
847 ALU_CASE(f2i16, f2i_rtz);
848 ALU_CASE(f2u16, f2u_rtz);
849 ALU_CASE(i2f16, i2f_rtz);
850 ALU_CASE(u2f16, u2f_rtz);
851
852 ALU_CASE(fsin, fsin);
853 ALU_CASE(fcos, fcos);
854
855 /* We'll get 0 in the second arg, so:
856 * ~a = ~(a | 0) = nor(a, 0) */
857 ALU_CASE(inot, inor);
858 ALU_CASE(iand, iand);
859 ALU_CASE(ior, ior);
860 ALU_CASE(ixor, ixor);
861 ALU_CASE(ishl, ishl);
862 ALU_CASE(ishr, iasr);
863 ALU_CASE(ushr, ilsr);
864
865 ALU_CASE_BCAST(b32all_fequal2, fball_eq, 2);
866 ALU_CASE_BCAST(b32all_fequal3, fball_eq, 3);
867 ALU_CASE(b32all_fequal4, fball_eq);
868
869 ALU_CASE_BCAST(b32any_fnequal2, fbany_neq, 2);
870 ALU_CASE_BCAST(b32any_fnequal3, fbany_neq, 3);
871 ALU_CASE(b32any_fnequal4, fbany_neq);
872
873 ALU_CASE_BCAST(b32all_iequal2, iball_eq, 2);
874 ALU_CASE_BCAST(b32all_iequal3, iball_eq, 3);
875 ALU_CASE(b32all_iequal4, iball_eq);
876
877 ALU_CASE_BCAST(b32any_inequal2, ibany_neq, 2);
878 ALU_CASE_BCAST(b32any_inequal3, ibany_neq, 3);
879 ALU_CASE(b32any_inequal4, ibany_neq);
880
881 /* Source mods will be shoved in later */
882 ALU_CASE(fabs, fmov);
883 ALU_CASE(fneg, fmov);
884 ALU_CASE(fsat, fmov);
885 ALU_CASE(fsat_signed, fmov);
886 ALU_CASE(fclamp_pos, fmov);
887
888 /* For size conversion, we use a move. Ideally though we would squash
889 * these ops together; maybe that has to happen after in NIR as part of
890 * propagation...? An earlier algebraic pass ensured we step down by
891 * only / exactly one size. If stepping down, we use a dest override to
892 * reduce the size; if stepping up, we use a larger-sized move with a
893 * half source and a sign/zero-extension modifier */
894
895 case nir_op_i2i8:
896 case nir_op_i2i16:
897 case nir_op_i2i32:
898 case nir_op_i2i64:
899 /* If we end up upscale, we'll need a sign-extend on the
900 * operand (the second argument) */
901
902 sext_2 = true;
903 /* fallthrough */
904 case nir_op_u2u8:
905 case nir_op_u2u16:
906 case nir_op_u2u32:
907 case nir_op_u2u64:
908 case nir_op_f2f16:
909 case nir_op_f2f32:
910 case nir_op_f2f64: {
911 if (instr->op == nir_op_f2f16 || instr->op == nir_op_f2f32 ||
912 instr->op == nir_op_f2f64)
913 op = midgard_alu_op_fmov;
914 else
915 op = midgard_alu_op_imov;
916
917 if (dst_bitsize == (src_bitsize * 2)) {
918 /* Converting up */
919 half_2 = true;
920 } else if (src_bitsize == (dst_bitsize * 2)) {
921 /* Converting down */
922 dest_override = midgard_dest_override_lower;
923 }
924
925 break;
926 }
927
928 /* For greater-or-equal, we lower to less-or-equal and flip the
929 * arguments */
930
931 case nir_op_fge:
932 case nir_op_fge32:
933 case nir_op_ige32:
934 case nir_op_uge32: {
935 op =
936 instr->op == nir_op_fge ? midgard_alu_op_fle :
937 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
938 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
939 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
940 0;
941
942 flip_src12 = true;
943 ALU_CHECK_CMP(false);
944 break;
945 }
946
947 case nir_op_b32csel: {
948 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
949 bool is_float = mir_is_bcsel_float(instr);
950 op = is_float ?
951 (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel) :
952 (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
953
954 break;
955 }
956
957 default:
958 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
959 assert(0);
960 return;
961 }
962
963 /* Midgard can perform certain modifiers on output of an ALU op */
964
965 unsigned outmod = 0;
966
967 bool abs[4] = { false };
968 bool neg[4] = { false };
969 bool is_int = midgard_is_integer_op(op);
970
971 if (midgard_is_integer_out_op(op)) {
972 outmod = midgard_outmod_int_wrap;
973 } else if (instr->op == nir_op_fsat) {
974 outmod = midgard_outmod_sat;
975 } else if (instr->op == nir_op_fsat_signed) {
976 outmod = midgard_outmod_sat_signed;
977 } else if (instr->op == nir_op_fclamp_pos) {
978 outmod = midgard_outmod_pos;
979 }
980
981 /* Fetch unit, quirks, etc information */
982 unsigned opcode_props = alu_opcode_props[op].props;
983 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
984
985 /* Look for floating point mods. We have the mods fsat, fsat_signed,
986 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
987 *
988 * fsat_signed(fpos(x)) = fsat(x)
989 * fsat_signed(fsat(x)) = fsat(x)
990 * fpos(fsat_signed(x)) = fsat(x)
991 * fpos(fsat(x)) = fsat(x)
992 * fsat(fsat_signed(x)) = fsat(x)
993 * fsat(fpos(x)) = fsat(x)
994 *
995 * So by cases any composition of output modifiers is equivalent to
996 * fsat alone.
997 */
998
999 if (!is_int && !(opcode_props & OP_TYPE_CONVERT)) {
1000 bool fpos = mir_accept_dest_mod(ctx, &dest, nir_op_fclamp_pos);
1001 bool fsat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat);
1002 bool ssat = mir_accept_dest_mod(ctx, &dest, nir_op_fsat_signed);
1003 bool prior = (outmod != midgard_outmod_none);
1004 int count = (int) prior + (int) fpos + (int) ssat + (int) fsat;
1005
1006 outmod = ((count > 1) || fsat) ? midgard_outmod_sat :
1007 fpos ? midgard_outmod_pos :
1008 ssat ? midgard_outmod_sat_signed :
1009 outmod;
1010 }
1011
1012 midgard_instruction ins = {
1013 .type = TAG_ALU_4,
1014 .dest = nir_dest_index(dest),
1015 .dest_type = nir_op_infos[instr->op].output_type
1016 | nir_dest_bit_size(*dest),
1017 };
1018
1019 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
1020 ins.src[i] = ~0;
1021
1022 if (quirk_flipped_r24) {
1023 ins.src[0] = ~0;
1024 mir_copy_src(&ins, instr, 0, 1, &abs[1], &neg[1], &ins.src_invert[1], is_int, broadcast_swizzle);
1025 } else {
1026 for (unsigned i = 0; i < nr_inputs; ++i) {
1027 unsigned to = i;
1028
1029 if (instr->op == nir_op_b32csel) {
1030 /* The condition is the first argument; move
1031 * the other arguments up one to be a binary
1032 * instruction for Midgard with the condition
1033 * last */
1034
1035 if (i == 0)
1036 to = 2;
1037 else if (flip_src12)
1038 to = 2 - i;
1039 else
1040 to = i - 1;
1041 } else if (flip_src12) {
1042 to = 1 - to;
1043 }
1044
1045 mir_copy_src(&ins, instr, i, to, &abs[to], &neg[to], &ins.src_invert[to], is_int, broadcast_swizzle);
1046
1047 /* (!c) ? a : b = c ? b : a */
1048 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1049 ins.src_invert[2] = false;
1050 flip_src12 ^= true;
1051 }
1052 }
1053 }
1054
1055 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
1056 /* Lowered to move */
1057 if (instr->op == nir_op_fneg)
1058 neg[1] = !neg[1];
1059
1060 if (instr->op == nir_op_fabs)
1061 abs[1] = true;
1062 }
1063
1064 ins.mask = mask_of(nr_components);
1065
1066 midgard_vector_alu alu = {
1067 .op = op,
1068 .reg_mode = reg_mode,
1069 .dest_override = dest_override,
1070 .outmod = outmod,
1071
1072 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[0], neg[0], is_int, half_1, sext_1)),
1073 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(abs[1], neg[1], is_int, half_2, sext_2)),
1074 };
1075
1076 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1077 * components that don't exist. Note modifier => SSA => !reg => no
1078 * writemask, so we don't have to worry about writemasks here.*/
1079
1080 if (!is_ssa)
1081 ins.mask &= instr->dest.write_mask;
1082
1083 ins.alu = alu;
1084
1085 /* Arrange for creation of iandnot/iornot */
1086 if (ins.src_invert[0] && !ins.src_invert[1]) {
1087 mir_flip(&ins);
1088 ins.src_invert[0] = false;
1089 ins.src_invert[1] = true;
1090 }
1091
1092 /* Late fixup for emulated instructions */
1093
1094 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1095 /* Presently, our second argument is an inline #0 constant.
1096 * Switch over to an embedded 1.0 constant (that can't fit
1097 * inline, since we're 32-bit, not 16-bit like the inline
1098 * constants) */
1099
1100 ins.has_inline_constant = false;
1101 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1102 ins.src_types[1] = nir_type_float32;
1103 ins.has_constants = true;
1104
1105 if (instr->op == nir_op_b2f32)
1106 ins.constants.f32[0] = 1.0f;
1107 else
1108 ins.constants.i32[0] = 1;
1109
1110 for (unsigned c = 0; c < 16; ++c)
1111 ins.swizzle[1][c] = 0;
1112 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
1113 /* Lots of instructions need a 0 plonked in */
1114 ins.has_inline_constant = false;
1115 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1116 ins.src_types[1] = nir_type_uint32;
1117 ins.has_constants = true;
1118 ins.constants.u32[0] = 0;
1119
1120 for (unsigned c = 0; c < 16; ++c)
1121 ins.swizzle[1][c] = 0;
1122 }
1123
1124 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1125 /* To avoid duplicating the lookup tables (probably), true LUT
1126 * instructions can only operate as if they were scalars. Lower
1127 * them here by changing the component. */
1128
1129 unsigned orig_mask = ins.mask;
1130
1131 unsigned swizzle_back[MIR_VEC_COMPONENTS];
1132 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1133
1134 for (int i = 0; i < nr_components; ++i) {
1135 /* Mask the associated component, dropping the
1136 * instruction if needed */
1137
1138 ins.mask = 1 << i;
1139 ins.mask &= orig_mask;
1140
1141 if (!ins.mask)
1142 continue;
1143
1144 for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
1145 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1146
1147 emit_mir_instruction(ctx, ins);
1148 }
1149 } else {
1150 emit_mir_instruction(ctx, ins);
1151 }
1152 }
1153
1154 #undef ALU_CASE
1155
1156 static void
1157 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1158 {
1159 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1160 unsigned nir_mask = 0;
1161 unsigned dsize = 0;
1162
1163 if (is_read) {
1164 nir_mask = mask_of(nir_intrinsic_dest_components(intr));
1165 dsize = nir_dest_bit_size(intr->dest);
1166 } else {
1167 nir_mask = nir_intrinsic_write_mask(intr);
1168 dsize = 32;
1169 }
1170
1171 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1172 unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
1173 mir_set_bytemask(ins, bytemask);
1174
1175 if (dsize == 64)
1176 ins->load_64 = true;
1177 }
1178
1179 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1180 * optimized) versions of UBO #0 */
1181
1182 static midgard_instruction *
1183 emit_ubo_read(
1184 compiler_context *ctx,
1185 nir_instr *instr,
1186 unsigned dest,
1187 unsigned offset,
1188 nir_src *indirect_offset,
1189 unsigned indirect_shift,
1190 unsigned index)
1191 {
1192 /* TODO: half-floats */
1193
1194 midgard_instruction ins = m_ld_ubo_int4(dest, 0);
1195 ins.constants.u32[0] = offset;
1196
1197 if (instr->type == nir_instr_type_intrinsic)
1198 mir_set_intr_mask(instr, &ins, true);
1199
1200 if (indirect_offset) {
1201 ins.src[2] = nir_src_index(ctx, indirect_offset);
1202 ins.src_types[2] = nir_type_uint32;
1203 ins.load_store.arg_2 = (indirect_shift << 5);
1204 } else {
1205 ins.load_store.arg_2 = 0x1E;
1206 }
1207
1208 ins.load_store.arg_1 = index;
1209
1210 return emit_mir_instruction(ctx, ins);
1211 }
1212
1213 /* Globals are like UBOs if you squint. And shared memory is like globals if
1214 * you squint even harder */
1215
1216 static void
1217 emit_global(
1218 compiler_context *ctx,
1219 nir_instr *instr,
1220 bool is_read,
1221 unsigned srcdest,
1222 nir_src *offset,
1223 bool is_shared)
1224 {
1225 /* TODO: types */
1226
1227 midgard_instruction ins;
1228
1229 if (is_read)
1230 ins = m_ld_int4(srcdest, 0);
1231 else
1232 ins = m_st_int4(srcdest, 0);
1233
1234 mir_set_offset(ctx, &ins, offset, is_shared);
1235 mir_set_intr_mask(instr, &ins, is_read);
1236
1237 emit_mir_instruction(ctx, ins);
1238 }
1239
1240 static void
1241 emit_varying_read(
1242 compiler_context *ctx,
1243 unsigned dest, unsigned offset,
1244 unsigned nr_comp, unsigned component,
1245 nir_src *indirect_offset, nir_alu_type type, bool flat)
1246 {
1247 /* XXX: Half-floats? */
1248 /* TODO: swizzle, mask */
1249
1250 midgard_instruction ins = m_ld_vary_32(dest, offset);
1251 ins.mask = mask_of(nr_comp);
1252
1253 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1254 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1255
1256 midgard_varying_parameter p = {
1257 .is_varying = 1,
1258 .interpolation = midgard_interp_default,
1259 .flat = flat,
1260 };
1261
1262 unsigned u;
1263 memcpy(&u, &p, sizeof(p));
1264 ins.load_store.varying_parameters = u;
1265
1266 if (indirect_offset) {
1267 ins.src[2] = nir_src_index(ctx, indirect_offset);
1268 ins.src_types[2] = nir_type_uint32;
1269 } else
1270 ins.load_store.arg_2 = 0x1E;
1271
1272 ins.load_store.arg_1 = 0x9E;
1273
1274 /* Use the type appropriate load */
1275 switch (type) {
1276 case nir_type_uint:
1277 case nir_type_bool:
1278 ins.load_store.op = midgard_op_ld_vary_32u;
1279 break;
1280 case nir_type_int:
1281 ins.load_store.op = midgard_op_ld_vary_32i;
1282 break;
1283 case nir_type_float:
1284 ins.load_store.op = midgard_op_ld_vary_32;
1285 break;
1286 default:
1287 unreachable("Attempted to load unknown type");
1288 break;
1289 }
1290
1291 emit_mir_instruction(ctx, ins);
1292 }
1293
1294 static void
1295 emit_attr_read(
1296 compiler_context *ctx,
1297 unsigned dest, unsigned offset,
1298 unsigned nr_comp, nir_alu_type t)
1299 {
1300 midgard_instruction ins = m_ld_attr_32(dest, offset);
1301 ins.load_store.arg_1 = 0x1E;
1302 ins.load_store.arg_2 = 0x1E;
1303 ins.mask = mask_of(nr_comp);
1304
1305 /* Use the type appropriate load */
1306 switch (t) {
1307 case nir_type_uint:
1308 case nir_type_bool:
1309 ins.load_store.op = midgard_op_ld_attr_32u;
1310 break;
1311 case nir_type_int:
1312 ins.load_store.op = midgard_op_ld_attr_32i;
1313 break;
1314 case nir_type_float:
1315 ins.load_store.op = midgard_op_ld_attr_32;
1316 break;
1317 default:
1318 unreachable("Attempted to load unknown type");
1319 break;
1320 }
1321
1322 emit_mir_instruction(ctx, ins);
1323 }
1324
1325 static void
1326 emit_sysval_read(compiler_context *ctx, nir_instr *instr,
1327 unsigned nr_components, unsigned offset)
1328 {
1329 nir_dest nir_dest;
1330
1331 /* Figure out which uniform this is */
1332 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
1333 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
1334
1335 unsigned dest = nir_dest_index(&nir_dest);
1336
1337 /* Sysvals are prefix uniforms */
1338 unsigned uniform = ((uintptr_t) val) - 1;
1339
1340 /* Emit the read itself -- this is never indirect */
1341 midgard_instruction *ins =
1342 emit_ubo_read(ctx, instr, dest, (uniform * 16) + offset, NULL, 0, 0);
1343
1344 ins->mask = mask_of(nr_components);
1345 }
1346
1347 static unsigned
1348 compute_builtin_arg(nir_op op)
1349 {
1350 switch (op) {
1351 case nir_intrinsic_load_work_group_id:
1352 return 0x14;
1353 case nir_intrinsic_load_local_invocation_id:
1354 return 0x10;
1355 default:
1356 unreachable("Invalid compute paramater loaded");
1357 }
1358 }
1359
1360 static void
1361 emit_fragment_store(compiler_context *ctx, unsigned src, enum midgard_rt_id rt)
1362 {
1363 assert(rt < ARRAY_SIZE(ctx->writeout_branch));
1364
1365 midgard_instruction *br = ctx->writeout_branch[rt];
1366
1367 assert(!br);
1368
1369 emit_explicit_constant(ctx, src, src);
1370
1371 struct midgard_instruction ins =
1372 v_branch(false, false);
1373
1374 ins.writeout = true;
1375
1376 /* Add dependencies */
1377 ins.src[0] = src;
1378 ins.src_types[0] = nir_type_uint32;
1379 ins.constants.u32[0] = rt == MIDGARD_ZS_RT ?
1380 0xFF : (rt - MIDGARD_COLOR_RT0) * 0x100;
1381
1382 /* Emit the branch */
1383 br = emit_mir_instruction(ctx, ins);
1384 schedule_barrier(ctx);
1385 ctx->writeout_branch[rt] = br;
1386
1387 /* Push our current location = current block count - 1 = where we'll
1388 * jump to. Maybe a bit too clever for my own good */
1389
1390 br->branch.target_block = ctx->block_count - 1;
1391 }
1392
1393 static void
1394 emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1395 {
1396 unsigned reg = nir_dest_index(&instr->dest);
1397 midgard_instruction ins = m_ld_compute_id(reg, 0);
1398 ins.mask = mask_of(3);
1399 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1400 ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
1401 emit_mir_instruction(ctx, ins);
1402 }
1403
1404 static unsigned
1405 vertex_builtin_arg(nir_op op)
1406 {
1407 switch (op) {
1408 case nir_intrinsic_load_vertex_id:
1409 return PAN_VERTEX_ID;
1410 case nir_intrinsic_load_instance_id:
1411 return PAN_INSTANCE_ID;
1412 default:
1413 unreachable("Invalid vertex builtin");
1414 }
1415 }
1416
1417 static void
1418 emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
1419 {
1420 unsigned reg = nir_dest_index(&instr->dest);
1421 emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
1422 }
1423
1424 static void
1425 emit_control_barrier(compiler_context *ctx)
1426 {
1427 midgard_instruction ins = {
1428 .type = TAG_TEXTURE_4,
1429 .src = { ~0, ~0, ~0, ~0 },
1430 .texture = {
1431 .op = TEXTURE_OP_BARRIER,
1432
1433 /* TODO: optimize */
1434 .barrier_buffer = 1,
1435 .barrier_shared = 1
1436 }
1437 };
1438
1439 emit_mir_instruction(ctx, ins);
1440 }
1441
1442 static const nir_variable *
1443 search_var(struct exec_list *vars, unsigned driver_loc)
1444 {
1445 nir_foreach_variable(var, vars) {
1446 if (var->data.driver_location == driver_loc)
1447 return var;
1448 }
1449
1450 return NULL;
1451 }
1452
1453 static unsigned
1454 mir_get_branch_cond(nir_src *src, bool *invert)
1455 {
1456 /* Wrap it. No swizzle since it's a scalar */
1457
1458 nir_alu_src alu = {
1459 .src = *src
1460 };
1461
1462 *invert = pan_has_source_mod(&alu, nir_op_inot);
1463 return nir_src_index(NULL, &alu.src);
1464 }
1465
1466 static void
1467 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1468 {
1469 unsigned offset = 0, reg;
1470
1471 switch (instr->intrinsic) {
1472 case nir_intrinsic_discard_if:
1473 case nir_intrinsic_discard: {
1474 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1475 struct midgard_instruction discard = v_branch(conditional, false);
1476 discard.branch.target_type = TARGET_DISCARD;
1477
1478 if (conditional) {
1479 discard.src[0] = mir_get_branch_cond(&instr->src[0],
1480 &discard.branch.invert_conditional);
1481 discard.src_types[0] = nir_type_uint32;
1482 }
1483
1484 emit_mir_instruction(ctx, discard);
1485 schedule_barrier(ctx);
1486
1487 break;
1488 }
1489
1490 case nir_intrinsic_load_uniform:
1491 case nir_intrinsic_load_ubo:
1492 case nir_intrinsic_load_global:
1493 case nir_intrinsic_load_shared:
1494 case nir_intrinsic_load_input:
1495 case nir_intrinsic_load_interpolated_input: {
1496 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
1497 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
1498 bool is_global = instr->intrinsic == nir_intrinsic_load_global;
1499 bool is_shared = instr->intrinsic == nir_intrinsic_load_shared;
1500 bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
1501 bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
1502
1503 /* Get the base type of the intrinsic */
1504 /* TODO: Infer type? Does it matter? */
1505 nir_alu_type t =
1506 (is_ubo || is_global || is_shared) ? nir_type_uint :
1507 (is_interp) ? nir_type_float :
1508 nir_intrinsic_type(instr);
1509
1510 t = nir_alu_type_get_base_type(t);
1511
1512 if (!(is_ubo || is_global)) {
1513 offset = nir_intrinsic_base(instr);
1514 }
1515
1516 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1517
1518 nir_src *src_offset = nir_get_io_offset_src(instr);
1519
1520 bool direct = nir_src_is_const(*src_offset);
1521 nir_src *indirect_offset = direct ? NULL : src_offset;
1522
1523 if (direct)
1524 offset += nir_src_as_uint(*src_offset);
1525
1526 /* We may need to apply a fractional offset */
1527 int component = (is_flat || is_interp) ?
1528 nir_intrinsic_component(instr) : 0;
1529 reg = nir_dest_index(&instr->dest);
1530
1531 if (is_uniform && !ctx->is_blend) {
1532 emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0);
1533 } else if (is_ubo) {
1534 nir_src index = instr->src[0];
1535
1536 /* TODO: Is indirect block number possible? */
1537 assert(nir_src_is_const(index));
1538
1539 uint32_t uindex = nir_src_as_uint(index) + 1;
1540 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
1541 } else if (is_global || is_shared) {
1542 emit_global(ctx, &instr->instr, true, reg, src_offset, is_shared);
1543 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1544 emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
1545 } else if (ctx->is_blend) {
1546 /* For blend shaders, load the input color, which is
1547 * preloaded to r0 */
1548
1549 midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
1550 emit_mir_instruction(ctx, move);
1551 schedule_barrier(ctx);
1552 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1553 emit_attr_read(ctx, reg, offset, nr_comp, t);
1554 } else {
1555 DBG("Unknown load\n");
1556 assert(0);
1557 }
1558
1559 break;
1560 }
1561
1562 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1563 case nir_intrinsic_load_barycentric_pixel:
1564 case nir_intrinsic_load_barycentric_centroid:
1565 break;
1566
1567 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1568
1569 case nir_intrinsic_load_raw_output_pan:
1570 case nir_intrinsic_load_output_u8_as_fp16_pan:
1571 reg = nir_dest_index(&instr->dest);
1572 assert(ctx->is_blend);
1573
1574 /* T720 and below use different blend opcodes with slightly
1575 * different semantics than T760 and up */
1576
1577 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
1578 bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
1579
1580 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
1581 ld.load_store.op = old_blend ?
1582 midgard_op_ld_color_buffer_u8_as_fp16_old :
1583 midgard_op_ld_color_buffer_u8_as_fp16;
1584
1585 if (old_blend) {
1586 ld.load_store.address = 1;
1587 ld.load_store.arg_2 = 0x1E;
1588 }
1589
1590 for (unsigned c = 2; c < 16; ++c)
1591 ld.swizzle[0][c] = 0;
1592 }
1593
1594 emit_mir_instruction(ctx, ld);
1595 break;
1596
1597 case nir_intrinsic_load_blend_const_color_rgba: {
1598 assert(ctx->is_blend);
1599 reg = nir_dest_index(&instr->dest);
1600
1601 /* Blend constants are embedded directly in the shader and
1602 * patched in, so we use some magic routing */
1603
1604 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
1605 ins.has_constants = true;
1606 ins.has_blend_constant = true;
1607 emit_mir_instruction(ctx, ins);
1608 break;
1609 }
1610
1611 case nir_intrinsic_store_zs_output_pan: {
1612 assert(ctx->stage == MESA_SHADER_FRAGMENT);
1613 emit_fragment_store(ctx, nir_src_index(ctx, &instr->src[0]),
1614 MIDGARD_ZS_RT);
1615
1616 midgard_instruction *br = ctx->writeout_branch[MIDGARD_ZS_RT];
1617
1618 if (!nir_intrinsic_component(instr))
1619 br->writeout_depth = true;
1620 if (nir_intrinsic_component(instr) ||
1621 instr->num_components)
1622 br->writeout_stencil = true;
1623 assert(br->writeout_depth | br->writeout_stencil);
1624 break;
1625 }
1626
1627 case nir_intrinsic_store_output:
1628 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1629
1630 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1631
1632 reg = nir_src_index(ctx, &instr->src[0]);
1633
1634 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1635 const nir_variable *var;
1636 enum midgard_rt_id rt;
1637
1638 var = search_var(&ctx->nir->outputs,
1639 nir_intrinsic_base(instr));
1640 assert(var);
1641 if (var->data.location == FRAG_RESULT_COLOR)
1642 rt = MIDGARD_COLOR_RT0;
1643 else if (var->data.location >= FRAG_RESULT_DATA0)
1644 rt = MIDGARD_COLOR_RT0 + var->data.location -
1645 FRAG_RESULT_DATA0;
1646 else
1647 assert(0);
1648
1649 emit_fragment_store(ctx, reg, rt);
1650 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1651 /* We should have been vectorized, though we don't
1652 * currently check that st_vary is emitted only once
1653 * per slot (this is relevant, since there's not a mask
1654 * parameter available on the store [set to 0 by the
1655 * blob]). We do respect the component by adjusting the
1656 * swizzle. If this is a constant source, we'll need to
1657 * emit that explicitly. */
1658
1659 emit_explicit_constant(ctx, reg, reg);
1660
1661 unsigned dst_component = nir_intrinsic_component(instr);
1662 unsigned nr_comp = nir_src_num_components(instr->src[0]);
1663
1664 midgard_instruction st = m_st_vary_32(reg, offset);
1665 st.load_store.arg_1 = 0x9E;
1666 st.load_store.arg_2 = 0x1E;
1667
1668 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
1669 case nir_type_uint:
1670 case nir_type_bool:
1671 st.load_store.op = midgard_op_st_vary_32u;
1672 break;
1673 case nir_type_int:
1674 st.load_store.op = midgard_op_st_vary_32i;
1675 break;
1676 case nir_type_float:
1677 st.load_store.op = midgard_op_st_vary_32;
1678 break;
1679 default:
1680 unreachable("Attempted to store unknown type");
1681 break;
1682 }
1683
1684 /* nir_intrinsic_component(store_intr) encodes the
1685 * destination component start. Source component offset
1686 * adjustment is taken care of in
1687 * install_registers_instr(), when offset_swizzle() is
1688 * called.
1689 */
1690 unsigned src_component = COMPONENT_X;
1691
1692 assert(nr_comp > 0);
1693 for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
1694 st.swizzle[0][i] = src_component;
1695 if (i >= dst_component && i < dst_component + nr_comp - 1)
1696 src_component++;
1697 }
1698
1699 emit_mir_instruction(ctx, st);
1700 } else {
1701 DBG("Unknown store\n");
1702 assert(0);
1703 }
1704
1705 break;
1706
1707 /* Special case of store_output for lowered blend shaders */
1708 case nir_intrinsic_store_raw_output_pan:
1709 assert (ctx->stage == MESA_SHADER_FRAGMENT);
1710 reg = nir_src_index(ctx, &instr->src[0]);
1711
1712 if (ctx->quirks & MIDGARD_OLD_BLEND) {
1713 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1714 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1715 * of:
1716 *
1717 * imov r0.xyzw, r0.xxxx
1718 */
1719
1720 unsigned expanded = make_compiler_temp(ctx);
1721
1722 midgard_instruction splatter = v_mov(reg, expanded);
1723
1724 for (unsigned c = 0; c < 16; ++c)
1725 splatter.swizzle[1][c] = 0;
1726
1727 emit_mir_instruction(ctx, splatter);
1728 emit_fragment_store(ctx, expanded, ctx->blend_rt);
1729 } else
1730 emit_fragment_store(ctx, reg, ctx->blend_rt);
1731
1732 break;
1733
1734 case nir_intrinsic_store_global:
1735 case nir_intrinsic_store_shared:
1736 reg = nir_src_index(ctx, &instr->src[0]);
1737 emit_explicit_constant(ctx, reg, reg);
1738
1739 emit_global(ctx, &instr->instr, false, reg, &instr->src[1], instr->intrinsic == nir_intrinsic_store_shared);
1740 break;
1741
1742 case nir_intrinsic_load_ssbo_address:
1743 emit_sysval_read(ctx, &instr->instr, 1, 0);
1744 break;
1745
1746 case nir_intrinsic_get_buffer_size:
1747 emit_sysval_read(ctx, &instr->instr, 1, 8);
1748 break;
1749
1750 case nir_intrinsic_load_viewport_scale:
1751 case nir_intrinsic_load_viewport_offset:
1752 case nir_intrinsic_load_num_work_groups:
1753 case nir_intrinsic_load_sampler_lod_parameters_pan:
1754 emit_sysval_read(ctx, &instr->instr, 3, 0);
1755 break;
1756
1757 case nir_intrinsic_load_work_group_id:
1758 case nir_intrinsic_load_local_invocation_id:
1759 emit_compute_builtin(ctx, instr);
1760 break;
1761
1762 case nir_intrinsic_load_vertex_id:
1763 case nir_intrinsic_load_instance_id:
1764 emit_vertex_builtin(ctx, instr);
1765 break;
1766
1767 case nir_intrinsic_memory_barrier_buffer:
1768 case nir_intrinsic_memory_barrier_shared:
1769 break;
1770
1771 case nir_intrinsic_control_barrier:
1772 schedule_barrier(ctx);
1773 emit_control_barrier(ctx);
1774 schedule_barrier(ctx);
1775 break;
1776
1777 default:
1778 fprintf(stderr, "Unhandled intrinsic %s\n", nir_intrinsic_infos[instr->intrinsic].name);
1779 assert(0);
1780 break;
1781 }
1782 }
1783
1784 static unsigned
1785 midgard_tex_format(enum glsl_sampler_dim dim)
1786 {
1787 switch (dim) {
1788 case GLSL_SAMPLER_DIM_1D:
1789 case GLSL_SAMPLER_DIM_BUF:
1790 return MALI_TEX_1D;
1791
1792 case GLSL_SAMPLER_DIM_2D:
1793 case GLSL_SAMPLER_DIM_EXTERNAL:
1794 case GLSL_SAMPLER_DIM_RECT:
1795 return MALI_TEX_2D;
1796
1797 case GLSL_SAMPLER_DIM_3D:
1798 return MALI_TEX_3D;
1799
1800 case GLSL_SAMPLER_DIM_CUBE:
1801 return MALI_TEX_CUBE;
1802
1803 default:
1804 DBG("Unknown sampler dim type\n");
1805 assert(0);
1806 return 0;
1807 }
1808 }
1809
1810 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1811 * was successful */
1812
1813 static bool
1814 pan_attach_constant_bias(
1815 compiler_context *ctx,
1816 nir_src lod,
1817 midgard_texture_word *word)
1818 {
1819 /* To attach as constant, it has to *be* constant */
1820
1821 if (!nir_src_is_const(lod))
1822 return false;
1823
1824 float f = nir_src_as_float(lod);
1825
1826 /* Break into fixed-point */
1827 signed lod_int = f;
1828 float lod_frac = f - lod_int;
1829
1830 /* Carry over negative fractions */
1831 if (lod_frac < 0.0) {
1832 lod_int--;
1833 lod_frac += 1.0;
1834 }
1835
1836 /* Encode */
1837 word->bias = float_to_ubyte(lod_frac);
1838 word->bias_int = lod_int;
1839
1840 return true;
1841 }
1842
1843 static void
1844 emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
1845 unsigned midgard_texop)
1846 {
1847 /* TODO */
1848 //assert (!instr->sampler);
1849
1850 int texture_index = instr->texture_index;
1851 int sampler_index = texture_index;
1852
1853 nir_alu_type dest_base = nir_alu_type_get_base_type(instr->dest_type);
1854 nir_alu_type dest_type = dest_base | nir_dest_bit_size(instr->dest);
1855
1856 midgard_instruction ins = {
1857 .type = TAG_TEXTURE_4,
1858 .mask = 0xF,
1859 .dest = nir_dest_index(&instr->dest),
1860 .src = { ~0, ~0, ~0, ~0 },
1861 .dest_type = dest_type,
1862 .swizzle = SWIZZLE_IDENTITY_4,
1863 .texture = {
1864 .op = midgard_texop,
1865 .format = midgard_tex_format(instr->sampler_dim),
1866 .texture_handle = texture_index,
1867 .sampler_handle = sampler_index,
1868 .shadow = instr->is_shadow,
1869 }
1870 };
1871
1872 if (instr->is_shadow && !instr->is_new_style_shadow)
1873 for (int i = 0; i < 4; ++i)
1874 ins.swizzle[0][i] = COMPONENT_X;
1875
1876 /* We may need a temporary for the coordinate */
1877
1878 bool needs_temp_coord =
1879 (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
1880 (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
1881 (instr->is_shadow);
1882
1883 unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
1884
1885 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1886 int index = nir_src_index(ctx, &instr->src[i].src);
1887 unsigned nr_components = nir_src_num_components(instr->src[i].src);
1888 unsigned sz = nir_src_bit_size(instr->src[i].src);
1889 nir_alu_type T = nir_tex_instr_src_type(instr, i) | sz;
1890
1891 switch (instr->src[i].src_type) {
1892 case nir_tex_src_coord: {
1893 emit_explicit_constant(ctx, index, index);
1894
1895 unsigned coord_mask = mask_of(instr->coord_components);
1896
1897 bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
1898
1899 if (flip_zw)
1900 coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
1901
1902 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1903 /* texelFetch is undefined on samplerCube */
1904 assert(midgard_texop != TEXTURE_OP_TEXEL_FETCH);
1905
1906 /* For cubemaps, we use a special ld/st op to
1907 * select the face and copy the xy into the
1908 * texture register */
1909
1910 midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
1911 ld.src[1] = index;
1912 ld.src_types[1] = T;
1913 ld.mask = 0x3; /* xy */
1914 ld.load_store.arg_1 = 0x20;
1915 ld.swizzle[1][3] = COMPONENT_X;
1916 emit_mir_instruction(ctx, ld);
1917
1918 /* xyzw -> xyxx */
1919 ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1920 ins.swizzle[1][3] = COMPONENT_X;
1921 } else if (needs_temp_coord) {
1922 /* mov coord_temp, coords */
1923 midgard_instruction mov = v_mov(index, coords);
1924 mov.mask = coord_mask;
1925
1926 if (flip_zw)
1927 mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
1928
1929 emit_mir_instruction(ctx, mov);
1930 } else {
1931 coords = index;
1932 }
1933
1934 ins.src[1] = coords;
1935 ins.src_types[1] = T;
1936
1937 /* Texelfetch coordinates uses all four elements
1938 * (xyz/index) regardless of texture dimensionality,
1939 * which means it's necessary to zero the unused
1940 * components to keep everything happy */
1941
1942 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1943 /* mov index.zw, #0, or generalized */
1944 midgard_instruction mov =
1945 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
1946 mov.has_constants = true;
1947 mov.mask = coord_mask ^ 0xF;
1948 emit_mir_instruction(ctx, mov);
1949 }
1950
1951 if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
1952 /* Array component in w but NIR wants it in z,
1953 * but if we have a temp coord we already fixed
1954 * that up */
1955
1956 if (nr_components == 3) {
1957 ins.swizzle[1][2] = COMPONENT_Z;
1958 ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
1959 } else if (nr_components == 2) {
1960 ins.swizzle[1][2] =
1961 instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
1962 ins.swizzle[1][3] = COMPONENT_X;
1963 } else
1964 unreachable("Invalid texture 2D components");
1965 }
1966
1967 if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
1968 /* We zeroed */
1969 ins.swizzle[1][2] = COMPONENT_Z;
1970 ins.swizzle[1][3] = COMPONENT_W;
1971 }
1972
1973 break;
1974 }
1975
1976 case nir_tex_src_bias:
1977 case nir_tex_src_lod: {
1978 /* Try as a constant if we can */
1979
1980 bool is_txf = midgard_texop == TEXTURE_OP_TEXEL_FETCH;
1981 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
1982 break;
1983
1984 ins.texture.lod_register = true;
1985 ins.src[2] = index;
1986 ins.src_types[2] = T;
1987
1988 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
1989 ins.swizzle[2][c] = COMPONENT_X;
1990
1991 emit_explicit_constant(ctx, index, index);
1992
1993 break;
1994 };
1995
1996 case nir_tex_src_offset: {
1997 ins.texture.offset_register = true;
1998 ins.src[3] = index;
1999 ins.src_types[3] = T;
2000
2001 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
2002 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
2003
2004 emit_explicit_constant(ctx, index, index);
2005 break;
2006 };
2007
2008 case nir_tex_src_comparator: {
2009 unsigned comp = COMPONENT_Z;
2010
2011 /* mov coord_temp.foo, coords */
2012 midgard_instruction mov = v_mov(index, coords);
2013 mov.mask = 1 << comp;
2014
2015 for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
2016 mov.swizzle[1][i] = COMPONENT_X;
2017
2018 emit_mir_instruction(ctx, mov);
2019 break;
2020 }
2021
2022 default: {
2023 fprintf(stderr, "Unknown texture source type: %d\n", instr->src[i].src_type);
2024 assert(0);
2025 }
2026 }
2027 }
2028
2029 emit_mir_instruction(ctx, ins);
2030 }
2031
2032 static void
2033 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
2034 {
2035 switch (instr->op) {
2036 case nir_texop_tex:
2037 case nir_texop_txb:
2038 emit_texop_native(ctx, instr, TEXTURE_OP_NORMAL);
2039 break;
2040 case nir_texop_txl:
2041 emit_texop_native(ctx, instr, TEXTURE_OP_LOD);
2042 break;
2043 case nir_texop_txf:
2044 emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
2045 break;
2046 case nir_texop_txs:
2047 emit_sysval_read(ctx, &instr->instr, 4, 0);
2048 break;
2049 default: {
2050 fprintf(stderr, "Unhandled texture op: %d\n", instr->op);
2051 assert(0);
2052 }
2053 }
2054 }
2055
2056 static void
2057 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
2058 {
2059 switch (instr->type) {
2060 case nir_jump_break: {
2061 /* Emit a branch out of the loop */
2062 struct midgard_instruction br = v_branch(false, false);
2063 br.branch.target_type = TARGET_BREAK;
2064 br.branch.target_break = ctx->current_loop_depth;
2065 emit_mir_instruction(ctx, br);
2066 break;
2067 }
2068
2069 default:
2070 DBG("Unknown jump type %d\n", instr->type);
2071 break;
2072 }
2073 }
2074
2075 static void
2076 emit_instr(compiler_context *ctx, struct nir_instr *instr)
2077 {
2078 switch (instr->type) {
2079 case nir_instr_type_load_const:
2080 emit_load_const(ctx, nir_instr_as_load_const(instr));
2081 break;
2082
2083 case nir_instr_type_intrinsic:
2084 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2085 break;
2086
2087 case nir_instr_type_alu:
2088 emit_alu(ctx, nir_instr_as_alu(instr));
2089 break;
2090
2091 case nir_instr_type_tex:
2092 emit_tex(ctx, nir_instr_as_tex(instr));
2093 break;
2094
2095 case nir_instr_type_jump:
2096 emit_jump(ctx, nir_instr_as_jump(instr));
2097 break;
2098
2099 case nir_instr_type_ssa_undef:
2100 /* Spurious */
2101 break;
2102
2103 default:
2104 DBG("Unhandled instruction type\n");
2105 break;
2106 }
2107 }
2108
2109
2110 /* ALU instructions can inline or embed constants, which decreases register
2111 * pressure and saves space. */
2112
2113 #define CONDITIONAL_ATTACH(idx) { \
2114 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2115 \
2116 if (entry) { \
2117 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2118 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2119 } \
2120 }
2121
2122 static void
2123 inline_alu_constants(compiler_context *ctx, midgard_block *block)
2124 {
2125 mir_foreach_instr_in_block(block, alu) {
2126 /* Other instructions cannot inline constants */
2127 if (alu->type != TAG_ALU_4) continue;
2128 if (alu->compact_branch) continue;
2129
2130 /* If there is already a constant here, we can do nothing */
2131 if (alu->has_constants) continue;
2132
2133 CONDITIONAL_ATTACH(0);
2134
2135 if (!alu->has_constants) {
2136 CONDITIONAL_ATTACH(1)
2137 } else if (!alu->inline_constant) {
2138 /* Corner case: _two_ vec4 constants, for instance with a
2139 * csel. For this case, we can only use a constant
2140 * register for one, we'll have to emit a move for the
2141 * other. */
2142
2143 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
2144 unsigned scratch = make_compiler_temp(ctx);
2145
2146 if (entry) {
2147 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2148 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2149
2150 /* Set the source */
2151 alu->src[1] = scratch;
2152
2153 /* Inject us -before- the last instruction which set r31 */
2154 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2155 }
2156 }
2157 }
2158 }
2159
2160 /* Midgard supports two types of constants, embedded constants (128-bit) and
2161 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2162 * constants can be demoted to inline constants, for space savings and
2163 * sometimes a performance boost */
2164
2165 static void
2166 embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
2167 {
2168 mir_foreach_instr_in_block(block, ins) {
2169 if (!ins->has_constants) continue;
2170 if (ins->has_inline_constant) continue;
2171
2172 /* Blend constants must not be inlined by definition */
2173 if (ins->has_blend_constant) continue;
2174
2175 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2176 bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
2177 bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
2178
2179 if (!(is_16 || is_32))
2180 continue;
2181
2182 /* src1 cannot be an inline constant due to encoding
2183 * restrictions. So, if possible we try to flip the arguments
2184 * in that case */
2185
2186 int op = ins->alu.op;
2187
2188 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2189 alu_opcode_props[op].props & OP_COMMUTES) {
2190 mir_flip(ins);
2191 }
2192
2193 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2194 /* Extract the source information */
2195
2196 midgard_vector_alu_src *src;
2197 int q = ins->alu.src2;
2198 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2199 src = m;
2200
2201 /* Component is from the swizzle. Take a nonzero component */
2202 assert(ins->mask);
2203 unsigned first_comp = ffs(ins->mask) - 1;
2204 unsigned component = ins->swizzle[1][first_comp];
2205
2206 /* Scale constant appropriately, if we can legally */
2207 uint16_t scaled_constant = 0;
2208
2209 if (is_16) {
2210 scaled_constant = ins->constants.u16[component];
2211 } else if (midgard_is_integer_op(op)) {
2212 scaled_constant = ins->constants.u32[component];
2213
2214 /* Constant overflow after resize */
2215 if (scaled_constant != ins->constants.u32[component])
2216 continue;
2217 } else {
2218 float original = ins->constants.f32[component];
2219 scaled_constant = _mesa_float_to_half(original);
2220
2221 /* Check for loss of precision. If this is
2222 * mediump, we don't care, but for a highp
2223 * shader, we need to pay attention. NIR
2224 * doesn't yet tell us which mode we're in!
2225 * Practically this prevents most constants
2226 * from being inlined, sadly. */
2227
2228 float fp32 = _mesa_half_to_float(scaled_constant);
2229
2230 if (fp32 != original)
2231 continue;
2232 }
2233
2234 /* We don't know how to handle these with a constant */
2235
2236 if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
2237 DBG("Bailing inline constant...\n");
2238 continue;
2239 }
2240
2241 /* Make sure that the constant is not itself a vector
2242 * by checking if all accessed values are the same. */
2243
2244 const midgard_constants *cons = &ins->constants;
2245 uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
2246
2247 bool is_vector = false;
2248 unsigned mask = effective_writemask(&ins->alu, ins->mask);
2249
2250 for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
2251 /* We only care if this component is actually used */
2252 if (!(mask & (1 << c)))
2253 continue;
2254
2255 uint32_t test = is_16 ?
2256 cons->u16[ins->swizzle[1][c]] :
2257 cons->u32[ins->swizzle[1][c]];
2258
2259 if (test != value) {
2260 is_vector = true;
2261 break;
2262 }
2263 }
2264
2265 if (is_vector)
2266 continue;
2267
2268 /* Get rid of the embedded constant */
2269 ins->has_constants = false;
2270 ins->src[1] = ~0;
2271 ins->has_inline_constant = true;
2272 ins->inline_constant = scaled_constant;
2273 }
2274 }
2275 }
2276
2277 /* Dead code elimination for branches at the end of a block - only one branch
2278 * per block is legal semantically */
2279
2280 static void
2281 midgard_cull_dead_branch(compiler_context *ctx, midgard_block *block)
2282 {
2283 bool branched = false;
2284
2285 mir_foreach_instr_in_block_safe(block, ins) {
2286 if (!midgard_is_branch_unit(ins->unit)) continue;
2287
2288 if (branched)
2289 mir_remove_instruction(ins);
2290
2291 branched = true;
2292 }
2293 }
2294
2295 static unsigned
2296 emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
2297 {
2298 /* Loop to ourselves */
2299 midgard_instruction *br = ctx->writeout_branch[rt];
2300 struct midgard_instruction ins = v_branch(false, false);
2301 ins.writeout = true;
2302 ins.writeout_depth = br->writeout_depth;
2303 ins.writeout_stencil = br->writeout_stencil;
2304 ins.branch.target_block = ctx->block_count - 1;
2305 ins.constants.u32[0] = br->constants.u32[0];
2306 emit_mir_instruction(ctx, ins);
2307
2308 ctx->current_block->epilogue = true;
2309 schedule_barrier(ctx);
2310 return ins.branch.target_block;
2311 }
2312
2313 static midgard_block *
2314 emit_block(compiler_context *ctx, nir_block *block)
2315 {
2316 midgard_block *this_block = ctx->after_block;
2317 ctx->after_block = NULL;
2318
2319 if (!this_block)
2320 this_block = create_empty_block(ctx);
2321
2322 list_addtail(&this_block->base.link, &ctx->blocks);
2323
2324 this_block->scheduled = false;
2325 ++ctx->block_count;
2326
2327 /* Set up current block */
2328 list_inithead(&this_block->base.instructions);
2329 ctx->current_block = this_block;
2330
2331 nir_foreach_instr(instr, block) {
2332 emit_instr(ctx, instr);
2333 ++ctx->instruction_count;
2334 }
2335
2336 return this_block;
2337 }
2338
2339 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2340
2341 static void
2342 emit_if(struct compiler_context *ctx, nir_if *nif)
2343 {
2344 midgard_block *before_block = ctx->current_block;
2345
2346 /* Speculatively emit the branch, but we can't fill it in until later */
2347 bool inv = false;
2348 EMIT(branch, true, true);
2349 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2350 then_branch->src[0] = mir_get_branch_cond(&nif->condition, &inv);
2351 then_branch->src_types[0] = nir_type_uint32;
2352 then_branch->branch.invert_conditional = !inv;
2353
2354 /* Emit the two subblocks. */
2355 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2356 midgard_block *end_then_block = ctx->current_block;
2357
2358 /* Emit a jump from the end of the then block to the end of the else */
2359 EMIT(branch, false, false);
2360 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2361
2362 /* Emit second block, and check if it's empty */
2363
2364 int else_idx = ctx->block_count;
2365 int count_in = ctx->instruction_count;
2366 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2367 midgard_block *end_else_block = ctx->current_block;
2368 int after_else_idx = ctx->block_count;
2369
2370 /* Now that we have the subblocks emitted, fix up the branches */
2371
2372 assert(then_block);
2373 assert(else_block);
2374
2375 if (ctx->instruction_count == count_in) {
2376 /* The else block is empty, so don't emit an exit jump */
2377 mir_remove_instruction(then_exit);
2378 then_branch->branch.target_block = after_else_idx;
2379 } else {
2380 then_branch->branch.target_block = else_idx;
2381 then_exit->branch.target_block = after_else_idx;
2382 }
2383
2384 /* Wire up the successors */
2385
2386 ctx->after_block = create_empty_block(ctx);
2387
2388 pan_block_add_successor(&before_block->base, &then_block->base);
2389 pan_block_add_successor(&before_block->base, &else_block->base);
2390
2391 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base);
2392 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base);
2393 }
2394
2395 static void
2396 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2397 {
2398 /* Remember where we are */
2399 midgard_block *start_block = ctx->current_block;
2400
2401 /* Allocate a loop number, growing the current inner loop depth */
2402 int loop_idx = ++ctx->current_loop_depth;
2403
2404 /* Get index from before the body so we can loop back later */
2405 int start_idx = ctx->block_count;
2406
2407 /* Emit the body itself */
2408 midgard_block *loop_block = emit_cf_list(ctx, &nloop->body);
2409
2410 /* Branch back to loop back */
2411 struct midgard_instruction br_back = v_branch(false, false);
2412 br_back.branch.target_block = start_idx;
2413 emit_mir_instruction(ctx, br_back);
2414
2415 /* Mark down that branch in the graph. */
2416 pan_block_add_successor(&start_block->base, &loop_block->base);
2417 pan_block_add_successor(&ctx->current_block->base, &loop_block->base);
2418
2419 /* Find the index of the block about to follow us (note: we don't add
2420 * one; blocks are 0-indexed so we get a fencepost problem) */
2421 int break_block_idx = ctx->block_count;
2422
2423 /* Fix up the break statements we emitted to point to the right place,
2424 * now that we can allocate a block number for them */
2425 ctx->after_block = create_empty_block(ctx);
2426
2427 mir_foreach_block_from(ctx, start_block, _block) {
2428 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2429 if (ins->type != TAG_ALU_4) continue;
2430 if (!ins->compact_branch) continue;
2431
2432 /* We found a branch -- check the type to see if we need to do anything */
2433 if (ins->branch.target_type != TARGET_BREAK) continue;
2434
2435 /* It's a break! Check if it's our break */
2436 if (ins->branch.target_break != loop_idx) continue;
2437
2438 /* Okay, cool, we're breaking out of this loop.
2439 * Rewrite from a break to a goto */
2440
2441 ins->branch.target_type = TARGET_GOTO;
2442 ins->branch.target_block = break_block_idx;
2443
2444 pan_block_add_successor(_block, &ctx->after_block->base);
2445 }
2446 }
2447
2448 /* Now that we've finished emitting the loop, free up the depth again
2449 * so we play nice with recursion amid nested loops */
2450 --ctx->current_loop_depth;
2451
2452 /* Dump loop stats */
2453 ++ctx->loop_count;
2454 }
2455
2456 static midgard_block *
2457 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2458 {
2459 midgard_block *start_block = NULL;
2460
2461 foreach_list_typed(nir_cf_node, node, node, list) {
2462 switch (node->type) {
2463 case nir_cf_node_block: {
2464 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2465
2466 if (!start_block)
2467 start_block = block;
2468
2469 break;
2470 }
2471
2472 case nir_cf_node_if:
2473 emit_if(ctx, nir_cf_node_as_if(node));
2474 break;
2475
2476 case nir_cf_node_loop:
2477 emit_loop(ctx, nir_cf_node_as_loop(node));
2478 break;
2479
2480 case nir_cf_node_function:
2481 assert(0);
2482 break;
2483 }
2484 }
2485
2486 return start_block;
2487 }
2488
2489 /* Due to lookahead, we need to report the first tag executed in the command
2490 * stream and in branch targets. An initial block might be empty, so iterate
2491 * until we find one that 'works' */
2492
2493 static unsigned
2494 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2495 {
2496 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2497
2498 mir_foreach_block_from(ctx, initial_block, _v) {
2499 midgard_block *v = (midgard_block *) _v;
2500 if (v->quadword_count) {
2501 midgard_bundle *initial_bundle =
2502 util_dynarray_element(&v->bundles, midgard_bundle, 0);
2503
2504 return initial_bundle->tag;
2505 }
2506 }
2507
2508 /* Default to a tag 1 which will break from the shader, in case we jump
2509 * to the exit block (i.e. `return` in a compute shader) */
2510
2511 return 1;
2512 }
2513
2514 /* For each fragment writeout instruction, generate a writeout loop to
2515 * associate with it */
2516
2517 static void
2518 mir_add_writeout_loops(compiler_context *ctx)
2519 {
2520 for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
2521 midgard_instruction *br = ctx->writeout_branch[rt];
2522 if (!br) continue;
2523
2524 unsigned popped = br->branch.target_block;
2525 pan_block_add_successor(&(mir_get_block(ctx, popped - 1)->base), &ctx->current_block->base);
2526 br->branch.target_block = emit_fragment_epilogue(ctx, rt);
2527 br->branch.target_type = TARGET_GOTO;
2528
2529 /* If we have more RTs, we'll need to restore back after our
2530 * loop terminates */
2531
2532 if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
2533 midgard_instruction uncond = v_branch(false, false);
2534 uncond.branch.target_block = popped;
2535 uncond.branch.target_type = TARGET_GOTO;
2536 emit_mir_instruction(ctx, uncond);
2537 pan_block_add_successor(&ctx->current_block->base, &(mir_get_block(ctx, popped)->base));
2538 schedule_barrier(ctx);
2539 } else {
2540 /* We're last, so we can terminate here */
2541 br->last_writeout = true;
2542 }
2543 }
2544 }
2545
2546 int
2547 midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
2548 {
2549 struct util_dynarray *compiled = &program->compiled;
2550
2551 midgard_debug = debug_get_option_midgard_debug();
2552
2553 /* TODO: Bound against what? */
2554 compiler_context *ctx = rzalloc(NULL, compiler_context);
2555
2556 ctx->nir = nir;
2557 ctx->stage = nir->info.stage;
2558 ctx->is_blend = is_blend;
2559 ctx->alpha_ref = program->alpha_ref;
2560 ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
2561 ctx->quirks = midgard_get_quirks(gpu_id);
2562
2563 /* Start off with a safe cutoff, allowing usage of all 16 work
2564 * registers. Later, we'll promote uniform reads to uniform registers
2565 * if we determine it is beneficial to do so */
2566 ctx->uniform_cutoff = 8;
2567
2568 /* Initialize at a global (not block) level hash tables */
2569
2570 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2571 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2572
2573 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2574 * (so we don't accidentally duplicate the epilogue since mesa/st has
2575 * messed with our I/O quite a bit already) */
2576
2577 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2578
2579 if (ctx->stage == MESA_SHADER_VERTEX) {
2580 NIR_PASS_V(nir, nir_lower_viewport_transform);
2581 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
2582 }
2583
2584 NIR_PASS_V(nir, nir_lower_var_copies);
2585 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2586 NIR_PASS_V(nir, nir_split_var_copies);
2587 NIR_PASS_V(nir, nir_lower_var_copies);
2588 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2589 NIR_PASS_V(nir, nir_lower_var_copies);
2590 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2591
2592 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2593 NIR_PASS_V(nir, nir_lower_ssbo);
2594 NIR_PASS_V(nir, midgard_nir_lower_zs_store);
2595
2596 /* Optimisation passes */
2597
2598 optimise_nir(nir, ctx->quirks);
2599
2600 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2601 nir_print_shader(nir, stdout);
2602 }
2603
2604 /* Assign sysvals and counts, now that we're sure
2605 * (post-optimisation) */
2606
2607 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
2608 program->sysval_count = ctx->sysvals.sysval_count;
2609 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
2610
2611 nir_foreach_function(func, nir) {
2612 if (!func->impl)
2613 continue;
2614
2615 list_inithead(&ctx->blocks);
2616 ctx->block_count = 0;
2617 ctx->func = func;
2618 ctx->already_emitted = calloc(BITSET_WORDS(func->impl->ssa_alloc), sizeof(BITSET_WORD));
2619
2620 emit_cf_list(ctx, &func->impl->body);
2621 free(ctx->already_emitted);
2622 break; /* TODO: Multi-function shaders */
2623 }
2624
2625 util_dynarray_init(compiled, NULL);
2626
2627 /* Per-block lowering before opts */
2628
2629 mir_foreach_block(ctx, _block) {
2630 midgard_block *block = (midgard_block *) _block;
2631 inline_alu_constants(ctx, block);
2632 midgard_opt_promote_fmov(ctx, block);
2633 embedded_to_inline_constant(ctx, block);
2634 }
2635 /* MIR-level optimizations */
2636
2637 bool progress = false;
2638
2639 do {
2640 progress = false;
2641 progress |= midgard_opt_dead_code_eliminate(ctx);
2642
2643 mir_foreach_block(ctx, _block) {
2644 midgard_block *block = (midgard_block *) _block;
2645 progress |= midgard_opt_copy_prop(ctx, block);
2646 progress |= midgard_opt_combine_projection(ctx, block);
2647 progress |= midgard_opt_varying_projection(ctx, block);
2648 }
2649 } while (progress);
2650
2651 mir_foreach_block(ctx, _block) {
2652 midgard_block *block = (midgard_block *) _block;
2653 midgard_lower_derivatives(ctx, block);
2654 midgard_cull_dead_branch(ctx, block);
2655 }
2656
2657 if (ctx->stage == MESA_SHADER_FRAGMENT)
2658 mir_add_writeout_loops(ctx);
2659
2660 /* Analyze now that the code is known but before scheduling creates
2661 * pipeline registers which are harder to track */
2662 mir_analyze_helper_terminate(ctx);
2663 mir_analyze_helper_requirements(ctx);
2664
2665 /* Schedule! */
2666 midgard_schedule_program(ctx);
2667 mir_ra(ctx);
2668
2669 /* Now that all the bundles are scheduled and we can calculate block
2670 * sizes, emit actual branch instructions rather than placeholders */
2671
2672 int br_block_idx = 0;
2673
2674 mir_foreach_block(ctx, _block) {
2675 midgard_block *block = (midgard_block *) _block;
2676 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2677 for (int c = 0; c < bundle->instruction_count; ++c) {
2678 midgard_instruction *ins = bundle->instructions[c];
2679
2680 if (!midgard_is_branch_unit(ins->unit)) continue;
2681
2682 /* Parse some basic branch info */
2683 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2684 bool is_conditional = ins->branch.conditional;
2685 bool is_inverted = ins->branch.invert_conditional;
2686 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2687 bool is_writeout = ins->writeout;
2688
2689 /* Determine the block we're jumping to */
2690 int target_number = ins->branch.target_block;
2691
2692 /* Report the destination tag */
2693 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2694
2695 /* Count up the number of quadwords we're
2696 * jumping over = number of quadwords until
2697 * (br_block_idx, target_number) */
2698
2699 int quadword_offset = 0;
2700
2701 if (is_discard) {
2702 /* Ignored */
2703 } else if (target_number > br_block_idx) {
2704 /* Jump forward */
2705
2706 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2707 midgard_block *blk = mir_get_block(ctx, idx);
2708 assert(blk);
2709
2710 quadword_offset += blk->quadword_count;
2711 }
2712 } else {
2713 /* Jump backwards */
2714
2715 for (int idx = br_block_idx; idx >= target_number; --idx) {
2716 midgard_block *blk = mir_get_block(ctx, idx);
2717 assert(blk);
2718
2719 quadword_offset -= blk->quadword_count;
2720 }
2721 }
2722
2723 /* Unconditional extended branches (far jumps)
2724 * have issues, so we always use a conditional
2725 * branch, setting the condition to always for
2726 * unconditional. For compact unconditional
2727 * branches, cond isn't used so it doesn't
2728 * matter what we pick. */
2729
2730 midgard_condition cond =
2731 !is_conditional ? midgard_condition_always :
2732 is_inverted ? midgard_condition_false :
2733 midgard_condition_true;
2734
2735 midgard_jmp_writeout_op op =
2736 is_discard ? midgard_jmp_writeout_op_discard :
2737 is_writeout ? midgard_jmp_writeout_op_writeout :
2738 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2739 midgard_jmp_writeout_op_branch_cond;
2740
2741 if (!is_compact) {
2742 midgard_branch_extended branch =
2743 midgard_create_branch_extended(
2744 cond, op,
2745 dest_tag,
2746 quadword_offset);
2747
2748 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2749 } else if (is_conditional || is_discard) {
2750 midgard_branch_cond branch = {
2751 .op = op,
2752 .dest_tag = dest_tag,
2753 .offset = quadword_offset,
2754 .cond = cond
2755 };
2756
2757 assert(branch.offset == quadword_offset);
2758
2759 memcpy(&ins->br_compact, &branch, sizeof(branch));
2760 } else {
2761 assert(op == midgard_jmp_writeout_op_branch_uncond);
2762
2763 midgard_branch_uncond branch = {
2764 .op = op,
2765 .dest_tag = dest_tag,
2766 .offset = quadword_offset,
2767 .unknown = 1
2768 };
2769
2770 assert(branch.offset == quadword_offset);
2771
2772 memcpy(&ins->br_compact, &branch, sizeof(branch));
2773 }
2774 }
2775 }
2776
2777 ++br_block_idx;
2778 }
2779
2780 /* Emit flat binary from the instruction arrays. Iterate each block in
2781 * sequence. Save instruction boundaries such that lookahead tags can
2782 * be assigned easily */
2783
2784 /* Cache _all_ bundles in source order for lookahead across failed branches */
2785
2786 int bundle_count = 0;
2787 mir_foreach_block(ctx, _block) {
2788 midgard_block *block = (midgard_block *) _block;
2789 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2790 }
2791 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2792 int bundle_idx = 0;
2793 mir_foreach_block(ctx, _block) {
2794 midgard_block *block = (midgard_block *) _block;
2795 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2796 source_order_bundles[bundle_idx++] = bundle;
2797 }
2798 }
2799
2800 int current_bundle = 0;
2801
2802 /* Midgard prefetches instruction types, so during emission we
2803 * need to lookahead. Unless this is the last instruction, in
2804 * which we return 1. */
2805
2806 mir_foreach_block(ctx, _block) {
2807 midgard_block *block = (midgard_block *) _block;
2808 mir_foreach_bundle_in_block(block, bundle) {
2809 int lookahead = 1;
2810
2811 if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
2812 lookahead = source_order_bundles[current_bundle + 1]->tag;
2813
2814 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2815 ++current_bundle;
2816 }
2817
2818 /* TODO: Free deeper */
2819 //util_dynarray_fini(&block->instructions);
2820 }
2821
2822 free(source_order_bundles);
2823
2824 /* Report the very first tag executed */
2825 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2826
2827 /* Deal with off-by-one related to the fencepost problem */
2828 program->work_register_count = ctx->work_registers + 1;
2829 program->uniform_cutoff = ctx->uniform_cutoff;
2830
2831 program->blend_patch_offset = ctx->blend_constant_offset;
2832 program->tls_size = ctx->tls_size;
2833
2834 if (midgard_debug & MIDGARD_DBG_SHADERS)
2835 disassemble_midgard(stdout, program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
2836
2837 if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
2838 unsigned nr_bundles = 0, nr_ins = 0;
2839
2840 /* Count instructions and bundles */
2841
2842 mir_foreach_block(ctx, _block) {
2843 midgard_block *block = (midgard_block *) _block;
2844 nr_bundles += util_dynarray_num_elements(
2845 &block->bundles, midgard_bundle);
2846
2847 mir_foreach_bundle_in_block(block, bun)
2848 nr_ins += bun->instruction_count;
2849 }
2850
2851 /* Calculate thread count. There are certain cutoffs by
2852 * register count for thread count */
2853
2854 unsigned nr_registers = program->work_register_count;
2855
2856 unsigned nr_threads =
2857 (nr_registers <= 4) ? 4 :
2858 (nr_registers <= 8) ? 2 :
2859 1;
2860
2861 /* Dump stats */
2862
2863 fprintf(stderr, "shader%d - %s shader: "
2864 "%u inst, %u bundles, %u quadwords, "
2865 "%u registers, %u threads, %u loops, "
2866 "%u:%u spills:fills\n",
2867 SHADER_DB_COUNT++,
2868 gl_shader_stage_name(ctx->stage),
2869 nr_ins, nr_bundles, ctx->quadword_count,
2870 nr_registers, nr_threads,
2871 ctx->loop_count,
2872 ctx->spills, ctx->fills);
2873 }
2874
2875 ralloc_free(ctx);
2876
2877 return 0;
2878 }