2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
63 unsigned SHADER_DB_COUNT
= 0;
65 int midgard_debug
= 0;
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
73 midgard_is_branch_unit(unsigned unit
)
75 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
79 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
85 for (unsigned i
= 0; i
< block
->nr_successors
; ++i
) {
86 if (block
->successors
[i
] == successor
)
90 block
->successors
[block
->nr_successors
++] = successor
;
91 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
94 /* Helpers to generate midgard_instruction's using macro magic, since every
95 * driver seems to do it that way */
97 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
99 #define M_LOAD_STORE(name, store) \
100 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
101 midgard_instruction i = { \
102 .type = TAG_LOAD_STORE_4, \
106 .src = { -1, -1, -1 }, \
109 .op = midgard_op_##name, \
110 .swizzle = SWIZZLE_XYZW, \
116 i.ssa_args.src[0] = ssa; \
118 i.ssa_args.dest = ssa; \
123 #define M_LOAD(name) M_LOAD_STORE(name, false)
124 #define M_STORE(name) M_LOAD_STORE(name, true)
126 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
127 * the corresponding Midgard source */
129 static midgard_vector_alu_src
130 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
131 bool half
, bool sext
)
133 if (!src
) return blank_alu_src
;
135 /* Figure out how many components there are so we can adjust the
136 * swizzle. Specifically we want to broadcast the last channel so
137 * things like ball2/3 work
140 if (broadcast_count
) {
141 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
143 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
144 src
->swizzle
[c
] = last_component
;
148 midgard_vector_alu_src alu_src
= {
152 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
156 alu_src
.mod
= midgard_int_normal
;
158 /* Sign/zero-extend if needed */
162 midgard_int_sign_extend
163 : midgard_int_zero_extend
;
166 /* These should have been lowered away */
167 assert(!(src
->abs
|| src
->negate
));
169 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
175 /* load/store instructions have both 32-bit and 16-bit variants, depending on
176 * whether we are using vectors composed of highp or mediump. At the moment, we
177 * don't support half-floats -- this requires changes in other parts of the
178 * compiler -- therefore the 16-bit versions are commented out. */
180 //M_LOAD(ld_attr_16);
182 //M_LOAD(ld_vary_16);
187 M_LOAD(ld_color_buffer_8
);
188 //M_STORE(st_vary_16);
190 M_LOAD(st_cubemap_coords
);
191 M_LOAD(ld_compute_id
);
193 static midgard_instruction
194 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
196 midgard_branch_cond branch
= {
204 memcpy(&compact
, &branch
, sizeof(branch
));
206 midgard_instruction ins
= {
208 .unit
= ALU_ENAB_BR_COMPACT
,
209 .prepacked_branch
= true,
210 .compact_branch
= true,
211 .br_compact
= compact
,
214 .src
= { -1, -1, -1 },
218 if (op
== midgard_jmp_writeout_op_writeout
)
224 static midgard_instruction
225 v_branch(bool conditional
, bool invert
)
227 midgard_instruction ins
= {
229 .unit
= ALU_ENAB_BRANCH
,
230 .compact_branch
= true,
232 .conditional
= conditional
,
233 .invert_conditional
= invert
237 .src
= { -1, -1, -1 },
244 static midgard_branch_extended
245 midgard_create_branch_extended( midgard_condition cond
,
246 midgard_jmp_writeout_op op
,
248 signed quadword_offset
)
250 /* The condition code is actually a LUT describing a function to
251 * combine multiple condition codes. However, we only support a single
252 * condition code at the moment, so we just duplicate over a bunch of
255 uint16_t duplicated_cond
=
265 midgard_branch_extended branch
= {
267 .dest_tag
= dest_tag
,
268 .offset
= quadword_offset
,
269 .cond
= duplicated_cond
276 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
278 ins
->has_constants
= true;
279 memcpy(&ins
->constants
, constants
, 16);
283 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
285 return glsl_count_attribute_slots(type
, false);
288 /* Lower fdot2 to a vector multiplication followed by channel addition */
290 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
292 if (alu
->op
!= nir_op_fdot2
)
295 b
->cursor
= nir_before_instr(&alu
->instr
);
297 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
298 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
300 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
302 nir_ssa_def
*sum
= nir_fadd(b
,
303 nir_channel(b
, product
, 0),
304 nir_channel(b
, product
, 1));
306 /* Replace the fdot2 with this sum */
307 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
311 midgard_sysval_for_ssbo(nir_intrinsic_instr
*instr
)
313 /* This is way too meta */
314 bool is_store
= instr
->intrinsic
== nir_intrinsic_store_ssbo
;
315 unsigned idx_idx
= is_store
? 1 : 0;
317 nir_src index
= instr
->src
[idx_idx
];
318 assert(nir_src_is_const(index
));
319 uint32_t uindex
= nir_src_as_uint(index
);
321 return PAN_SYSVAL(SSBO
, uindex
);
325 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
327 switch (instr
->intrinsic
) {
328 case nir_intrinsic_load_viewport_scale
:
329 return PAN_SYSVAL_VIEWPORT_SCALE
;
330 case nir_intrinsic_load_viewport_offset
:
331 return PAN_SYSVAL_VIEWPORT_OFFSET
;
332 case nir_intrinsic_load_num_work_groups
:
333 return PAN_SYSVAL_NUM_WORK_GROUPS
;
334 case nir_intrinsic_load_ssbo
:
335 case nir_intrinsic_store_ssbo
:
336 return midgard_sysval_for_ssbo(instr
);
342 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
345 nir_intrinsic_instr
*intr
;
346 nir_dest
*dst
= NULL
;
350 bool is_store
= false;
352 switch (instr
->type
) {
353 case nir_instr_type_intrinsic
:
354 intr
= nir_instr_as_intrinsic(instr
);
355 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
357 is_store
|= intr
->intrinsic
== nir_intrinsic_store_ssbo
;
359 case nir_instr_type_tex
:
360 tex
= nir_instr_as_tex(instr
);
361 if (tex
->op
!= nir_texop_txs
)
364 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
365 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
366 nir_tex_instr_dest_size(tex
) -
367 (tex
->is_array
? 1 : 0),
375 if (dest
&& dst
&& !is_store
)
376 *dest
= nir_dest_index(ctx
, dst
);
382 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
386 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
390 /* We have a sysval load; check if it's already been assigned */
392 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
395 /* It hasn't -- so assign it now! */
397 unsigned id
= ctx
->sysval_count
++;
398 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
399 ctx
->sysvals
[id
] = sysval
;
403 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
405 ctx
->sysval_count
= 0;
407 nir_foreach_function(function
, shader
) {
408 if (!function
->impl
) continue;
410 nir_foreach_block(block
, function
->impl
) {
411 nir_foreach_instr_safe(instr
, block
) {
412 midgard_nir_assign_sysval_body(ctx
, instr
);
419 midgard_nir_lower_fdot2(nir_shader
*shader
)
421 bool progress
= false;
423 nir_foreach_function(function
, shader
) {
424 if (!function
->impl
) continue;
427 nir_builder
*b
= &_b
;
428 nir_builder_init(b
, function
->impl
);
430 nir_foreach_block(block
, function
->impl
) {
431 nir_foreach_instr_safe(instr
, block
) {
432 if (instr
->type
!= nir_instr_type_alu
) continue;
434 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
435 midgard_nir_lower_fdot2_body(b
, alu
);
441 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
448 /* Flushes undefined values to zero */
451 optimise_nir(nir_shader
*nir
)
454 unsigned lower_flrp
=
455 (nir
->options
->lower_flrp16
? 16 : 0) |
456 (nir
->options
->lower_flrp32
? 32 : 0) |
457 (nir
->options
->lower_flrp64
? 64 : 0);
459 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
460 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
461 NIR_PASS(progress
, nir
, nir_lower_idiv
);
463 nir_lower_tex_options lower_tex_1st_pass_options
= {
468 nir_lower_tex_options lower_tex_2nd_pass_options
= {
469 .lower_txs_lod
= true,
472 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_1st_pass_options
);
473 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_2nd_pass_options
);
478 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
479 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
481 NIR_PASS(progress
, nir
, nir_copy_prop
);
482 NIR_PASS(progress
, nir
, nir_opt_dce
);
483 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
484 NIR_PASS(progress
, nir
, nir_opt_cse
);
485 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
486 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
487 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
489 if (lower_flrp
!= 0) {
490 bool lower_flrp_progress
= false;
491 NIR_PASS(lower_flrp_progress
,
495 false /* always_precise */,
496 nir
->options
->lower_ffma
);
497 if (lower_flrp_progress
) {
498 NIR_PASS(progress
, nir
,
499 nir_opt_constant_folding
);
503 /* Nothing should rematerialize any flrps, so we only
504 * need to do this lowering once.
509 NIR_PASS(progress
, nir
, nir_opt_undef
);
510 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
512 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
515 nir_var_function_temp
);
517 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
520 /* Must be run at the end to prevent creation of fsin/fcos ops */
521 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
526 NIR_PASS(progress
, nir
, nir_opt_dce
);
527 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
528 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
529 NIR_PASS(progress
, nir
, nir_copy_prop
);
532 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
534 /* We implement booleans as 32-bit 0/~0 */
535 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
537 /* Now that booleans are lowered, we can run out late opts */
538 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
540 /* Lower mods for float ops only. Integer ops don't support modifiers
541 * (saturate doesn't make sense on integers, neg/abs require dedicated
544 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
545 NIR_PASS(progress
, nir
, nir_copy_prop
);
546 NIR_PASS(progress
, nir
, nir_opt_dce
);
548 /* Take us out of SSA */
549 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
550 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
552 /* We are a vector architecture; write combine where possible */
553 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
554 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
556 NIR_PASS(progress
, nir
, nir_opt_dce
);
559 /* Do not actually emit a load; instead, cache the constant for inlining */
562 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
564 nir_ssa_def def
= instr
->def
;
566 float *v
= rzalloc_array(NULL
, float, 4);
567 nir_const_load_to_arr(v
, instr
, f32
);
569 /* Shifted for SSA, +1 for off-by-one */
570 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, v
);
573 /* Normally constants are embedded implicitly, but for I/O and such we have to
574 * explicitly emit a move with the constant source */
577 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
579 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
581 if (constant_value
) {
582 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, to
);
583 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
584 emit_mir_instruction(ctx
, ins
);
589 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
591 unsigned comp
= src
->swizzle
[0];
593 for (unsigned c
= 1; c
< nr_components
; ++c
) {
594 if (src
->swizzle
[c
] != comp
)
601 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
602 * output of a conditional test) into that register */
605 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
607 int condition
= nir_src_index(ctx
, src
);
609 /* Source to swizzle the desired component into w */
611 const midgard_vector_alu_src alu_src
= {
612 .swizzle
= SWIZZLE(component
, component
, component
, component
),
615 /* There is no boolean move instruction. Instead, we simulate a move by
616 * ANDing the condition with itself to get it into r31.w */
618 midgard_instruction ins
= {
621 /* We need to set the conditional as close as possible */
622 .precede_break
= true,
623 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
624 .mask
= 1 << COMPONENT_W
,
627 .src
= { condition
, condition
, -1 },
628 .dest
= SSA_FIXED_REGISTER(31),
632 .op
= midgard_alu_op_iand
,
633 .outmod
= midgard_outmod_int_wrap
,
634 .reg_mode
= midgard_reg_mode_32
,
635 .dest_override
= midgard_dest_override_none
,
636 .src1
= vector_alu_srco_unsigned(alu_src
),
637 .src2
= vector_alu_srco_unsigned(alu_src
)
641 emit_mir_instruction(ctx
, ins
);
644 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
648 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
650 int condition
= nir_src_index(ctx
, &src
->src
);
652 /* Source to swizzle the desired component into w */
654 const midgard_vector_alu_src alu_src
= {
655 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
658 /* There is no boolean move instruction. Instead, we simulate a move by
659 * ANDing the condition with itself to get it into r31.w */
661 midgard_instruction ins
= {
663 .precede_break
= true,
664 .mask
= mask_of(nr_comp
),
666 .src
= { condition
, condition
, -1 },
667 .dest
= SSA_FIXED_REGISTER(31),
670 .op
= midgard_alu_op_iand
,
671 .outmod
= midgard_outmod_int_wrap
,
672 .reg_mode
= midgard_reg_mode_32
,
673 .dest_override
= midgard_dest_override_none
,
674 .src1
= vector_alu_srco_unsigned(alu_src
),
675 .src2
= vector_alu_srco_unsigned(alu_src
)
679 emit_mir_instruction(ctx
, ins
);
682 #define ALU_CASE(nir, _op) \
684 op = midgard_alu_op_##_op; \
685 assert(src_bitsize == dst_bitsize); \
688 #define ALU_CASE_BCAST(nir, _op, count) \
690 op = midgard_alu_op_##_op; \
691 broadcast_swizzle = count; \
692 assert(src_bitsize == dst_bitsize); \
695 nir_is_fzero_constant(nir_src src
)
697 if (!nir_src_is_const(src
))
700 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
701 if (nir_src_comp_as_float(src
, c
) != 0.0)
708 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
709 * special treatment override this anyway. */
711 static midgard_reg_mode
712 reg_mode_for_nir(nir_alu_instr
*instr
)
714 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
716 switch (src_bitsize
) {
718 return midgard_reg_mode_8
;
720 return midgard_reg_mode_16
;
722 return midgard_reg_mode_32
;
724 return midgard_reg_mode_64
;
726 unreachable("Invalid bit size");
731 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
733 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
734 * is handled elsewhere */
736 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
737 midgard_emit_derivatives(ctx
, instr
);
741 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
743 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
744 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
745 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
747 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
748 * supported. A few do not and are commented for now. Also, there are a
749 * number of NIR ops which Midgard does not support and need to be
750 * lowered, also TODO. This switch block emits the opcode and calling
751 * convention of the Midgard instruction; actual packing is done in
756 /* Number of components valid to check for the instruction (the rest
757 * will be forced to the last), or 0 to use as-is. Relevant as
758 * ball-type instructions have a channel count in NIR but are all vec4
761 unsigned broadcast_swizzle
= 0;
763 /* What register mode should we operate in? */
764 midgard_reg_mode reg_mode
=
765 reg_mode_for_nir(instr
);
767 /* Do we need a destination override? Used for inline
770 midgard_dest_override dest_override
=
771 midgard_dest_override_none
;
773 /* Should we use a smaller respective source and sign-extend? */
775 bool half_1
= false, sext_1
= false;
776 bool half_2
= false, sext_2
= false;
778 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
779 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
782 ALU_CASE(fadd
, fadd
);
783 ALU_CASE(fmul
, fmul
);
784 ALU_CASE(fmin
, fmin
);
785 ALU_CASE(fmax
, fmax
);
786 ALU_CASE(imin
, imin
);
787 ALU_CASE(imax
, imax
);
788 ALU_CASE(umin
, umin
);
789 ALU_CASE(umax
, umax
);
790 ALU_CASE(ffloor
, ffloor
);
791 ALU_CASE(fround_even
, froundeven
);
792 ALU_CASE(ftrunc
, ftrunc
);
793 ALU_CASE(fceil
, fceil
);
794 ALU_CASE(fdot3
, fdot3
);
795 ALU_CASE(fdot4
, fdot4
);
796 ALU_CASE(iadd
, iadd
);
797 ALU_CASE(isub
, isub
);
798 ALU_CASE(imul
, imul
);
800 /* Zero shoved as second-arg */
801 ALU_CASE(iabs
, iabsdiff
);
805 ALU_CASE(feq32
, feq
);
806 ALU_CASE(fne32
, fne
);
807 ALU_CASE(flt32
, flt
);
808 ALU_CASE(ieq32
, ieq
);
809 ALU_CASE(ine32
, ine
);
810 ALU_CASE(ilt32
, ilt
);
811 ALU_CASE(ult32
, ult
);
813 /* We don't have a native b2f32 instruction. Instead, like many
814 * GPUs, we exploit booleans as 0/~0 for false/true, and
815 * correspondingly AND
816 * by 1.0 to do the type conversion. For the moment, prime us
819 * iand [whatever], #0
821 * At the end of emit_alu (as MIR), we'll fix-up the constant
824 ALU_CASE(b2f32
, iand
);
825 ALU_CASE(b2i32
, iand
);
827 /* Likewise, we don't have a dedicated f2b32 instruction, but
828 * we can do a "not equal to 0.0" test. */
830 ALU_CASE(f2b32
, fne
);
831 ALU_CASE(i2b32
, ine
);
833 ALU_CASE(frcp
, frcp
);
834 ALU_CASE(frsq
, frsqrt
);
835 ALU_CASE(fsqrt
, fsqrt
);
836 ALU_CASE(fexp2
, fexp2
);
837 ALU_CASE(flog2
, flog2
);
839 ALU_CASE(f2i32
, f2i_rtz
);
840 ALU_CASE(f2u32
, f2u_rtz
);
841 ALU_CASE(i2f32
, i2f_rtz
);
842 ALU_CASE(u2f32
, u2f_rtz
);
844 ALU_CASE(f2i16
, f2i_rtz
);
845 ALU_CASE(f2u16
, f2u_rtz
);
846 ALU_CASE(i2f16
, i2f_rtz
);
847 ALU_CASE(u2f16
, u2f_rtz
);
849 ALU_CASE(fsin
, fsin
);
850 ALU_CASE(fcos
, fcos
);
852 /* We'll set invert */
853 ALU_CASE(inot
, imov
);
854 ALU_CASE(iand
, iand
);
856 ALU_CASE(ixor
, ixor
);
857 ALU_CASE(ishl
, ishl
);
858 ALU_CASE(ishr
, iasr
);
859 ALU_CASE(ushr
, ilsr
);
861 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
862 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
863 ALU_CASE(b32all_fequal4
, fball_eq
);
865 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
866 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
867 ALU_CASE(b32any_fnequal4
, fbany_neq
);
869 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
870 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
871 ALU_CASE(b32all_iequal4
, iball_eq
);
873 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
874 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
875 ALU_CASE(b32any_inequal4
, ibany_neq
);
877 /* Source mods will be shoved in later */
878 ALU_CASE(fabs
, fmov
);
879 ALU_CASE(fneg
, fmov
);
880 ALU_CASE(fsat
, fmov
);
882 /* For size conversion, we use a move. Ideally though we would squash
883 * these ops together; maybe that has to happen after in NIR as part of
884 * propagation...? An earlier algebraic pass ensured we step down by
885 * only / exactly one size. If stepping down, we use a dest override to
886 * reduce the size; if stepping up, we use a larger-sized move with a
887 * half source and a sign/zero-extension modifier */
892 /* If we end up upscale, we'll need a sign-extend on the
893 * operand (the second argument) */
899 op
= midgard_alu_op_imov
;
901 if (dst_bitsize
== (src_bitsize
* 2)) {
905 /* Use a greater register mode */
907 } else if (src_bitsize
== (dst_bitsize
* 2)) {
908 /* Converting down */
909 dest_override
= midgard_dest_override_lower
;
916 assert(src_bitsize
== 32);
918 op
= midgard_alu_op_fmov
;
919 dest_override
= midgard_dest_override_lower
;
924 assert(src_bitsize
== 16);
926 op
= midgard_alu_op_fmov
;
933 /* For greater-or-equal, we lower to less-or-equal and flip the
941 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
942 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
943 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
944 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
947 /* Swap via temporary */
948 nir_alu_src temp
= instr
->src
[1];
949 instr
->src
[1] = instr
->src
[0];
950 instr
->src
[0] = temp
;
955 case nir_op_b32csel
: {
956 /* Midgard features both fcsel and icsel, depending on
957 * the type of the arguments/output. However, as long
958 * as we're careful we can _always_ use icsel and
959 * _never_ need fcsel, since the latter does additional
960 * floating-point-specific processing whereas the
961 * former just moves bits on the wire. It's not obvious
962 * why these are separate opcodes, save for the ability
963 * to do things like sat/pos/abs/neg for free */
965 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
966 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
968 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
971 /* Emit the condition into r31 */
974 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
976 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
978 /* The condition is the first argument; move the other
979 * arguments up one to be a binary instruction for
982 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
987 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
992 /* Midgard can perform certain modifiers on output of an ALU op */
995 if (midgard_is_integer_out_op(op
)) {
996 outmod
= midgard_outmod_int_wrap
;
998 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
999 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
1002 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
1004 if (instr
->op
== nir_op_fmax
) {
1005 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
1006 op
= midgard_alu_op_fmov
;
1008 outmod
= midgard_outmod_pos
;
1009 instr
->src
[0] = instr
->src
[1];
1010 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1011 op
= midgard_alu_op_fmov
;
1013 outmod
= midgard_outmod_pos
;
1017 /* Fetch unit, quirks, etc information */
1018 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1019 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1021 /* src0 will always exist afaik, but src1 will not for 1-argument
1022 * instructions. The latter can only be fetched if the instruction
1023 * needs it, or else we may segfault. */
1025 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1026 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1028 /* Rather than use the instruction generation helpers, we do it
1029 * ourselves here to avoid the mess */
1031 midgard_instruction ins
= {
1035 quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1036 quirk_flipped_r24
? src0
: src1
,
1043 nir_alu_src
*nirmods
[2] = { NULL
};
1045 if (nr_inputs
== 2) {
1046 nirmods
[0] = &instr
->src
[0];
1047 nirmods
[1] = &instr
->src
[1];
1048 } else if (nr_inputs
== 1) {
1049 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1054 /* These were lowered to a move, so apply the corresponding mod */
1056 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1057 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
1059 if (instr
->op
== nir_op_fneg
)
1060 s
->negate
= !s
->negate
;
1062 if (instr
->op
== nir_op_fabs
)
1066 bool is_int
= midgard_is_integer_op(op
);
1068 ins
.mask
= mask_of(nr_components
);
1070 midgard_vector_alu alu
= {
1072 .reg_mode
= reg_mode
,
1073 .dest_override
= dest_override
,
1076 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1077 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1080 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1083 ins
.mask
&= instr
->dest
.write_mask
;
1087 /* Late fixup for emulated instructions */
1089 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1090 /* Presently, our second argument is an inline #0 constant.
1091 * Switch over to an embedded 1.0 constant (that can't fit
1092 * inline, since we're 32-bit, not 16-bit like the inline
1095 ins
.ssa_args
.inline_constant
= false;
1096 ins
.ssa_args
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1097 ins
.has_constants
= true;
1099 if (instr
->op
== nir_op_b2f32
) {
1100 ins
.constants
[0] = 1.0f
;
1102 /* Type pun it into place */
1104 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1107 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1108 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1109 /* Lots of instructions need a 0 plonked in */
1110 ins
.ssa_args
.inline_constant
= false;
1111 ins
.ssa_args
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1112 ins
.has_constants
= true;
1113 ins
.constants
[0] = 0.0f
;
1114 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1115 } else if (instr
->op
== nir_op_inot
) {
1119 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1120 /* To avoid duplicating the lookup tables (probably), true LUT
1121 * instructions can only operate as if they were scalars. Lower
1122 * them here by changing the component. */
1124 uint8_t original_swizzle
[4];
1125 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1126 unsigned orig_mask
= ins
.mask
;
1128 for (int i
= 0; i
< nr_components
; ++i
) {
1129 /* Mask the associated component, dropping the
1130 * instruction if needed */
1133 ins
.mask
&= orig_mask
;
1138 for (int j
= 0; j
< 4; ++j
)
1139 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1141 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, false));
1142 emit_mir_instruction(ctx
, ins
);
1145 emit_mir_instruction(ctx
, ins
);
1151 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1152 * optimized) versions of UBO #0 */
1154 midgard_instruction
*
1156 compiler_context
*ctx
,
1159 nir_src
*indirect_offset
,
1162 /* TODO: half-floats */
1164 midgard_instruction ins
= m_ld_ubo_int4(dest
, offset
);
1166 /* TODO: Don't split */
1167 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1168 ins
.load_store
.address
= offset
>> 3;
1170 if (indirect_offset
) {
1171 ins
.ssa_args
.src
[1] = nir_src_index(ctx
, indirect_offset
);
1172 ins
.load_store
.arg_2
= 0x80;
1174 ins
.load_store
.arg_2
= 0x1E;
1177 ins
.load_store
.arg_1
= index
;
1179 return emit_mir_instruction(ctx
, ins
);
1182 /* SSBO reads are like UBO reads if you squint */
1186 compiler_context
*ctx
,
1191 nir_src
*indirect_offset
,
1196 midgard_instruction ins
;
1199 ins
= m_ld_int4(srcdest
, offset
);
1201 ins
= m_st_int4(srcdest
, offset
);
1203 /* SSBO reads use a generic memory read interface, so we need the
1204 * address of the SSBO as the first argument. This is a sysval. */
1206 unsigned addr
= make_compiler_temp(ctx
);
1207 emit_sysval_read(ctx
, instr
, addr
, 2);
1209 /* The source array is a bit of a leaky abstraction for SSBOs.
1210 * Nevertheless, for loads:
1216 * Whereas for stores:
1222 * We would like arg_1 = the address and
1223 * arg_2 = the offset.
1226 ins
.ssa_args
.src
[is_read
? 0 : 1] = addr
;
1228 /* TODO: What is this? It looks superficially like a shift << 5, but
1229 * arg_1 doesn't take a shift Should it be E0 or A0? */
1230 if (indirect_offset
)
1231 ins
.load_store
.arg_1
|= 0xE0;
1233 /* We also need to emit the indirect offset */
1235 if (indirect_offset
)
1236 ins
.ssa_args
.src
[is_read
? 1 : 2] = nir_src_index(ctx
, indirect_offset
);
1238 ins
.load_store
.arg_2
= 0x7E;
1240 /* TODO: Bounds check */
1242 /* Finally, we emit the direct offset */
1244 ins
.load_store
.varying_parameters
= (offset
& 0x1FF) << 1;
1245 ins
.load_store
.address
= (offset
>> 9);
1247 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1250 ins
.mask
= mask_of(nir_intrinsic_dest_components(intr
));
1252 ins
.mask
= nir_intrinsic_write_mask(intr
);
1254 emit_mir_instruction(ctx
, ins
);
1259 compiler_context
*ctx
,
1260 unsigned dest
, unsigned offset
,
1261 unsigned nr_comp
, unsigned component
,
1262 nir_src
*indirect_offset
, nir_alu_type type
)
1264 /* XXX: Half-floats? */
1265 /* TODO: swizzle, mask */
1267 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1268 ins
.mask
= mask_of(nr_comp
);
1269 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1271 midgard_varying_parameter p
= {
1273 .interpolation
= midgard_interp_default
,
1274 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1278 memcpy(&u
, &p
, sizeof(p
));
1279 ins
.load_store
.varying_parameters
= u
;
1281 if (indirect_offset
)
1282 ins
.ssa_args
.src
[1] = nir_src_index(ctx
, indirect_offset
);
1284 ins
.load_store
.arg_2
= 0x1E;
1286 ins
.load_store
.arg_1
= 0x9E;
1288 /* Use the type appropriate load */
1292 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1295 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1297 case nir_type_float
:
1298 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1301 unreachable("Attempted to load unknown type");
1305 emit_mir_instruction(ctx
, ins
);
1309 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
, signed dest_override
,
1310 unsigned nr_components
)
1314 /* Figure out which uniform this is */
1315 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1316 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1318 if (dest_override
>= 0)
1319 dest
= dest_override
;
1321 /* Sysvals are prefix uniforms */
1322 unsigned uniform
= ((uintptr_t) val
) - 1;
1324 /* Emit the read itself -- this is never indirect */
1325 midgard_instruction
*ins
=
1326 emit_ubo_read(ctx
, dest
, uniform
, NULL
, 0);
1328 ins
->mask
= mask_of(nr_components
);
1332 compute_builtin_arg(nir_op op
)
1335 case nir_intrinsic_load_work_group_id
:
1337 case nir_intrinsic_load_local_invocation_id
:
1340 unreachable("Invalid compute paramater loaded");
1344 /* Emit store for a fragment shader, which is encoded via a fancy branch. TODO:
1345 * Handle MRT here */
1348 emit_fragment_store(compiler_context
*ctx
, unsigned src
, unsigned rt
)
1350 /* First, move in whatever we're outputting */
1351 midgard_instruction move
= v_mov(src
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1353 /* Force a tight schedule. TODO: Make the scheduler MRT aware */
1354 move
.unit
= UNIT_VMUL
;
1355 move
.precede_break
= true;
1356 move
.dont_eliminate
= true;
1359 emit_mir_instruction(ctx
, move
);
1361 /* If we're doing MRT, we need to specify the render target */
1363 midgard_instruction rt_move
= {
1370 /* We'll write to r1.z */
1371 rt_move
= v_mov(-1, blank_alu_src
, SSA_FIXED_REGISTER(1));
1372 rt_move
.mask
= 1 << COMPONENT_Z
;
1373 rt_move
.unit
= UNIT_SADD
;
1375 /* r1.z = (rt * 0x100) */
1376 rt_move
.ssa_args
.inline_constant
= true;
1377 rt_move
.inline_constant
= (rt
* 0x100);
1380 ctx
->work_registers
= MAX2(ctx
->work_registers
, 1);
1383 emit_mir_instruction(ctx
, rt_move
);
1386 /* Next, generate the branch. For R render targets in the writeout, the
1387 * i'th render target jumps to pseudo-offset [2(R-1) + i] */
1389 unsigned offset
= (2 * (ctx
->nir
->num_outputs
- 1)) + rt
;
1391 struct midgard_instruction ins
=
1392 v_alu_br_compact_cond(midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, offset
, midgard_condition_always
);
1394 /* Add dependencies */
1395 ins
.ssa_args
.src
[0] = move
.ssa_args
.dest
;
1396 ins
.ssa_args
.src
[1] = rt_move
.ssa_args
.dest
;
1398 /* Emit the branch */
1399 emit_mir_instruction(ctx
, ins
);
1403 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1405 unsigned reg
= nir_dest_index(ctx
, &instr
->dest
);
1406 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1407 ins
.mask
= mask_of(3);
1408 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1409 emit_mir_instruction(ctx
, ins
);
1412 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1414 unsigned offset
= 0, reg
;
1416 switch (instr
->intrinsic
) {
1417 case nir_intrinsic_discard_if
:
1418 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1422 case nir_intrinsic_discard
: {
1423 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1424 struct midgard_instruction discard
= v_branch(conditional
, false);
1425 discard
.branch
.target_type
= TARGET_DISCARD
;
1426 emit_mir_instruction(ctx
, discard
);
1430 case nir_intrinsic_load_uniform
:
1431 case nir_intrinsic_load_ubo
:
1432 case nir_intrinsic_load_ssbo
:
1433 case nir_intrinsic_load_input
: {
1434 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1435 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1436 bool is_ssbo
= instr
->intrinsic
== nir_intrinsic_load_ssbo
;
1438 /* Get the base type of the intrinsic */
1439 /* TODO: Infer type? Does it matter? */
1441 (is_ubo
|| is_ssbo
) ? nir_type_uint
: nir_intrinsic_type(instr
);
1442 t
= nir_alu_type_get_base_type(t
);
1444 if (!(is_ubo
|| is_ssbo
)) {
1445 offset
= nir_intrinsic_base(instr
);
1448 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1450 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1452 bool direct
= nir_src_is_const(*src_offset
);
1453 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1456 offset
+= nir_src_as_uint(*src_offset
);
1458 /* We may need to apply a fractional offset */
1459 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1460 nir_intrinsic_component(instr
) : 0;
1461 reg
= nir_dest_index(ctx
, &instr
->dest
);
1463 if (is_uniform
&& !ctx
->is_blend
) {
1464 emit_ubo_read(ctx
, reg
, ctx
->sysval_count
+ offset
, indirect_offset
, 0);
1465 } else if (is_ubo
) {
1466 nir_src index
= instr
->src
[0];
1468 /* We don't yet support indirect UBOs. For indirect
1469 * block numbers (if that's possible), we don't know
1470 * enough about the hardware yet. For indirect sources,
1471 * we know what we need but we need to add some NIR
1472 * support for lowering correctly with respect to
1475 assert(nir_src_is_const(index
));
1476 assert(nir_src_is_const(*src_offset
));
1478 /* TODO: Alignment */
1479 assert((offset
& 0xF) == 0);
1481 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1482 emit_ubo_read(ctx
, reg
, offset
/ 16, NULL
, uindex
);
1483 } else if (is_ssbo
) {
1484 nir_src index
= instr
->src
[0];
1485 assert(nir_src_is_const(index
));
1486 uint32_t uindex
= nir_src_as_uint(index
);
1488 emit_ssbo_access(ctx
, &instr
->instr
, true, reg
, offset
, indirect_offset
, uindex
);
1489 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1490 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
, t
);
1491 } else if (ctx
->is_blend
) {
1492 /* For blend shaders, load the input color, which is
1493 * preloaded to r0 */
1495 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), blank_alu_src
, reg
);
1496 emit_mir_instruction(ctx
, move
);
1497 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1498 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1499 ins
.load_store
.arg_1
= 0x1E;
1500 ins
.load_store
.arg_2
= 0x1E;
1501 ins
.mask
= mask_of(nr_comp
);
1503 /* Use the type appropriate load */
1507 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1510 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1512 case nir_type_float
:
1513 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1516 unreachable("Attempted to load unknown type");
1520 emit_mir_instruction(ctx
, ins
);
1522 DBG("Unknown load\n");
1529 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1531 case nir_intrinsic_load_raw_output_pan
:
1532 reg
= nir_dest_index(ctx
, &instr
->dest
);
1533 assert(ctx
->is_blend
);
1535 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1536 emit_mir_instruction(ctx
, ins
);
1539 case nir_intrinsic_load_blend_const_color_rgba
: {
1540 assert(ctx
->is_blend
);
1541 reg
= nir_dest_index(ctx
, &instr
->dest
);
1543 /* Blend constants are embedded directly in the shader and
1544 * patched in, so we use some magic routing */
1546 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1547 ins
.has_constants
= true;
1548 ins
.has_blend_constant
= true;
1549 emit_mir_instruction(ctx
, ins
);
1553 case nir_intrinsic_store_output
:
1554 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1556 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1558 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1560 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1561 /* Determine number of render targets */
1562 emit_fragment_store(ctx
, reg
, offset
);
1563 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1564 /* We should have been vectorized, though we don't
1565 * currently check that st_vary is emitted only once
1566 * per slot (this is relevant, since there's not a mask
1567 * parameter available on the store [set to 0 by the
1568 * blob]). We do respect the component by adjusting the
1569 * swizzle. If this is a constant source, we'll need to
1570 * emit that explicitly. */
1572 emit_explicit_constant(ctx
, reg
, reg
);
1574 unsigned component
= nir_intrinsic_component(instr
);
1576 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1577 st
.load_store
.arg_1
= 0x9E;
1578 st
.load_store
.arg_2
= 0x1E;
1579 st
.load_store
.swizzle
= SWIZZLE_XYZW
<< (2*component
);
1580 emit_mir_instruction(ctx
, st
);
1582 DBG("Unknown store\n");
1588 /* Special case of store_output for lowered blend shaders */
1589 case nir_intrinsic_store_raw_output_pan
:
1590 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1591 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1592 emit_fragment_store(ctx
, reg
, 0);
1596 case nir_intrinsic_store_ssbo
:
1597 assert(nir_src_is_const(instr
->src
[1]));
1599 bool direct_offset
= nir_src_is_const(instr
->src
[2]);
1600 offset
= direct_offset
? nir_src_as_uint(instr
->src
[2]) : 0;
1601 nir_src
*indirect_offset
= direct_offset
? NULL
: &instr
->src
[2];
1602 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1604 uint32_t uindex
= nir_src_as_uint(instr
->src
[1]);
1606 emit_explicit_constant(ctx
, reg
, reg
);
1607 emit_ssbo_access(ctx
, &instr
->instr
, false, reg
, offset
, indirect_offset
, uindex
);
1610 case nir_intrinsic_load_alpha_ref_float
:
1611 assert(instr
->dest
.is_ssa
);
1613 float ref_value
= ctx
->alpha_ref
;
1615 /* See emit_load_const */
1616 float *v
= ralloc_array(NULL
, float, 4);
1617 memcpy(v
, &ref_value
, sizeof(float));
1618 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (instr
->dest
.ssa
.index
<< 1) + 1, v
);
1621 case nir_intrinsic_load_viewport_scale
:
1622 case nir_intrinsic_load_viewport_offset
:
1623 case nir_intrinsic_load_num_work_groups
:
1624 emit_sysval_read(ctx
, &instr
->instr
, -1, 3);
1627 case nir_intrinsic_load_work_group_id
:
1628 case nir_intrinsic_load_local_invocation_id
:
1629 emit_compute_builtin(ctx
, instr
);
1633 printf ("Unhandled intrinsic\n");
1640 midgard_tex_format(enum glsl_sampler_dim dim
)
1643 case GLSL_SAMPLER_DIM_1D
:
1644 case GLSL_SAMPLER_DIM_BUF
:
1647 case GLSL_SAMPLER_DIM_2D
:
1648 case GLSL_SAMPLER_DIM_EXTERNAL
:
1651 case GLSL_SAMPLER_DIM_3D
:
1654 case GLSL_SAMPLER_DIM_CUBE
:
1655 return MALI_TEX_CUBE
;
1658 DBG("Unknown sampler dim type\n");
1664 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1668 pan_attach_constant_bias(
1669 compiler_context
*ctx
,
1671 midgard_texture_word
*word
)
1673 /* To attach as constant, it has to *be* constant */
1675 if (!nir_src_is_const(lod
))
1678 float f
= nir_src_as_float(lod
);
1680 /* Break into fixed-point */
1682 float lod_frac
= f
- lod_int
;
1684 /* Carry over negative fractions */
1685 if (lod_frac
< 0.0) {
1691 word
->bias
= float_to_ubyte(lod_frac
);
1692 word
->bias_int
= lod_int
;
1697 static enum mali_sampler_type
1698 midgard_sampler_type(nir_alu_type t
) {
1699 switch (nir_alu_type_get_base_type(t
))
1701 case nir_type_float
:
1702 return MALI_SAMPLER_FLOAT
;
1704 return MALI_SAMPLER_SIGNED
;
1706 return MALI_SAMPLER_UNSIGNED
;
1708 unreachable("Unknown sampler type");
1713 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1714 unsigned midgard_texop
)
1717 //assert (!instr->sampler);
1718 //assert (!instr->texture_array_size);
1720 int texture_index
= instr
->texture_index
;
1721 int sampler_index
= texture_index
;
1723 /* No helper to build texture words -- we do it all here */
1724 midgard_instruction ins
= {
1725 .type
= TAG_TEXTURE_4
,
1728 .dest
= nir_dest_index(ctx
, &instr
->dest
),
1729 .src
= { -1, -1, -1 },
1732 .op
= midgard_texop
,
1733 .format
= midgard_tex_format(instr
->sampler_dim
),
1734 .texture_handle
= texture_index
,
1735 .sampler_handle
= sampler_index
,
1736 .swizzle
= SWIZZLE_XYZW
,
1737 .in_reg_swizzle
= SWIZZLE_XYZW
,
1743 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1747 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1748 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1749 midgard_vector_alu_src alu_src
= blank_alu_src
;
1751 switch (instr
->src
[i
].src_type
) {
1752 case nir_tex_src_coord
: {
1753 emit_explicit_constant(ctx
, index
, index
);
1755 /* Texelfetch coordinates uses all four elements
1756 * (xyz/index) regardless of texture dimensionality,
1757 * which means it's necessary to zero the unused
1758 * components to keep everything happy */
1760 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1761 unsigned old_index
= index
;
1763 index
= make_compiler_temp(ctx
);
1765 /* mov index, old_index */
1766 midgard_instruction mov
= v_mov(old_index
, blank_alu_src
, index
);
1768 emit_mir_instruction(ctx
, mov
);
1770 /* mov index.zw, #0 */
1771 mov
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
),
1772 blank_alu_src
, index
);
1773 mov
.has_constants
= true;
1774 mov
.mask
= (1 << COMPONENT_Z
) | (1 << COMPONENT_W
);
1775 emit_mir_instruction(ctx
, mov
);
1778 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1779 /* texelFetch is undefined on samplerCube */
1780 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1782 /* For cubemaps, we use a special ld/st op to
1783 * select the face and copy the xy into the
1784 * texture register */
1786 unsigned temp
= make_compiler_temp(ctx
);
1787 midgard_instruction st
= m_st_cubemap_coords(temp
, 0);
1788 st
.ssa_args
.src
[0] = index
;
1789 st
.mask
= 0x3; /* xy */
1790 st
.load_store
.arg_1
= 0x20;
1791 st
.load_store
.swizzle
= alu_src
.swizzle
;
1792 emit_mir_instruction(ctx
, st
);
1794 ins
.ssa_args
.src
[0] = temp
;
1796 ins
.ssa_args
.src
[0] = index
;
1799 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1800 /* Array component in w but NIR wants it in z */
1801 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYZZ
;
1807 case nir_tex_src_bias
:
1808 case nir_tex_src_lod
: {
1809 /* Try as a constant if we can */
1811 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1812 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1815 ins
.texture
.lod_register
= true;
1816 ins
.ssa_args
.src
[1] = index
;
1817 emit_explicit_constant(ctx
, index
, index
);
1823 unreachable("Unknown texture source type\n");
1827 emit_mir_instruction(ctx
, ins
);
1829 /* Used for .cont and .last hinting */
1830 ctx
->texture_op_count
++;
1834 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1836 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1837 * generic tex in some cases (which confuses the hardware) */
1839 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1841 if (is_vertex
&& instr
->op
== nir_texop_tex
)
1842 instr
->op
= nir_texop_txl
;
1844 switch (instr
->op
) {
1847 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1850 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1853 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1856 emit_sysval_read(ctx
, &instr
->instr
, -1, 4);
1859 unreachable("Unhanlded texture op");
1864 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1866 switch (instr
->type
) {
1867 case nir_jump_break
: {
1868 /* Emit a branch out of the loop */
1869 struct midgard_instruction br
= v_branch(false, false);
1870 br
.branch
.target_type
= TARGET_BREAK
;
1871 br
.branch
.target_break
= ctx
->current_loop_depth
;
1872 emit_mir_instruction(ctx
, br
);
1877 DBG("Unknown jump type %d\n", instr
->type
);
1883 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1885 switch (instr
->type
) {
1886 case nir_instr_type_load_const
:
1887 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1890 case nir_instr_type_intrinsic
:
1891 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1894 case nir_instr_type_alu
:
1895 emit_alu(ctx
, nir_instr_as_alu(instr
));
1898 case nir_instr_type_tex
:
1899 emit_tex(ctx
, nir_instr_as_tex(instr
));
1902 case nir_instr_type_jump
:
1903 emit_jump(ctx
, nir_instr_as_jump(instr
));
1906 case nir_instr_type_ssa_undef
:
1911 DBG("Unhandled instruction type\n");
1917 /* ALU instructions can inline or embed constants, which decreases register
1918 * pressure and saves space. */
1920 #define CONDITIONAL_ATTACH(src) { \
1921 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1924 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1925 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1930 inline_alu_constants(compiler_context
*ctx
)
1932 mir_foreach_instr(ctx
, alu
) {
1933 /* Other instructions cannot inline constants */
1934 if (alu
->type
!= TAG_ALU_4
) continue;
1936 /* If there is already a constant here, we can do nothing */
1937 if (alu
->has_constants
) continue;
1939 CONDITIONAL_ATTACH(src
[0]);
1941 if (!alu
->has_constants
) {
1942 CONDITIONAL_ATTACH(src
[1])
1943 } else if (!alu
->inline_constant
) {
1944 /* Corner case: _two_ vec4 constants, for instance with a
1945 * csel. For this case, we can only use a constant
1946 * register for one, we'll have to emit a move for the
1947 * other. Note, if both arguments are constants, then
1948 * necessarily neither argument depends on the value of
1949 * any particular register. As the destination register
1950 * will be wiped, that means we can spill the constant
1951 * to the destination register.
1954 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src
[1] + 1);
1955 unsigned scratch
= alu
->ssa_args
.dest
;
1958 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1959 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src
[1] + 1);
1961 /* Force a break XXX Defer r31 writes */
1962 ins
.unit
= UNIT_VLUT
;
1964 /* Set the source */
1965 alu
->ssa_args
.src
[1] = scratch
;
1967 /* Inject us -before- the last instruction which set r31 */
1968 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1974 /* Being a little silly with the names, but returns the op that is the bitwise
1975 * inverse of the op with the argument switched. I.e. (f and g are
1978 * f(a, b) = ~g(b, a)
1980 * Corollary: if g is the contrapositve of f, f is the contrapositive of g:
1982 * f(a, b) = ~g(b, a)
1983 * ~f(a, b) = g(b, a)
1984 * ~f(a, b) = ~h(a, b) where h is the contrapositive of g
1987 * Thus we define this function in pairs.
1990 static inline midgard_alu_op
1991 mir_contrapositive(midgard_alu_op op
)
1994 case midgard_alu_op_flt
:
1995 return midgard_alu_op_fle
;
1996 case midgard_alu_op_fle
:
1997 return midgard_alu_op_flt
;
1999 case midgard_alu_op_ilt
:
2000 return midgard_alu_op_ile
;
2001 case midgard_alu_op_ile
:
2002 return midgard_alu_op_ilt
;
2005 unreachable("No known contrapositive");
2009 /* Midgard supports two types of constants, embedded constants (128-bit) and
2010 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2011 * constants can be demoted to inline constants, for space savings and
2012 * sometimes a performance boost */
2015 embedded_to_inline_constant(compiler_context
*ctx
)
2017 mir_foreach_instr(ctx
, ins
) {
2018 if (!ins
->has_constants
) continue;
2020 if (ins
->ssa_args
.inline_constant
) continue;
2022 /* Blend constants must not be inlined by definition */
2023 if (ins
->has_blend_constant
) continue;
2025 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2026 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
2027 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
2029 if (!(is_16
|| is_32
))
2032 /* src1 cannot be an inline constant due to encoding
2033 * restrictions. So, if possible we try to flip the arguments
2036 int op
= ins
->alu
.op
;
2038 if (ins
->ssa_args
.src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2039 bool flip
= alu_opcode_props
[op
].props
& OP_COMMUTES
;
2042 /* Conditionals can be inverted */
2043 case midgard_alu_op_flt
:
2044 case midgard_alu_op_ilt
:
2045 case midgard_alu_op_fle
:
2046 case midgard_alu_op_ile
:
2047 ins
->alu
.op
= mir_contrapositive(ins
->alu
.op
);
2052 case midgard_alu_op_fcsel
:
2053 case midgard_alu_op_icsel
:
2054 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
2060 /* Flip the SSA numbers */
2061 ins
->ssa_args
.src
[0] = ins
->ssa_args
.src
[1];
2062 ins
->ssa_args
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2064 /* And flip the modifiers */
2068 src_temp
= ins
->alu
.src2
;
2069 ins
->alu
.src2
= ins
->alu
.src1
;
2070 ins
->alu
.src1
= src_temp
;
2074 if (ins
->ssa_args
.src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2075 /* Extract the source information */
2077 midgard_vector_alu_src
*src
;
2078 int q
= ins
->alu
.src2
;
2079 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2082 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2083 int component
= src
->swizzle
& 3;
2085 /* Scale constant appropriately, if we can legally */
2086 uint16_t scaled_constant
= 0;
2088 if (midgard_is_integer_op(op
) || is_16
) {
2089 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2090 scaled_constant
= (uint16_t) iconstants
[component
];
2092 /* Constant overflow after resize */
2093 if (scaled_constant
!= iconstants
[component
])
2096 float original
= (float) ins
->constants
[component
];
2097 scaled_constant
= _mesa_float_to_half(original
);
2099 /* Check for loss of precision. If this is
2100 * mediump, we don't care, but for a highp
2101 * shader, we need to pay attention. NIR
2102 * doesn't yet tell us which mode we're in!
2103 * Practically this prevents most constants
2104 * from being inlined, sadly. */
2106 float fp32
= _mesa_half_to_float(scaled_constant
);
2108 if (fp32
!= original
)
2112 /* We don't know how to handle these with a constant */
2114 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
2115 DBG("Bailing inline constant...\n");
2119 /* Make sure that the constant is not itself a
2120 * vector by checking if all accessed values
2121 * (by the swizzle) are the same. */
2123 uint32_t *cons
= (uint32_t *) ins
->constants
;
2124 uint32_t value
= cons
[component
];
2126 bool is_vector
= false;
2127 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2129 for (int c
= 1; c
< 4; ++c
) {
2130 /* We only care if this component is actually used */
2131 if (!(mask
& (1 << c
)))
2134 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2136 if (test
!= value
) {
2145 /* Get rid of the embedded constant */
2146 ins
->has_constants
= false;
2147 ins
->ssa_args
.src
[1] = -1;
2148 ins
->ssa_args
.inline_constant
= true;
2149 ins
->inline_constant
= scaled_constant
;
2154 /* Dead code elimination for branches at the end of a block - only one branch
2155 * per block is legal semantically */
2158 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2160 bool branched
= false;
2162 mir_foreach_instr_in_block_safe(block
, ins
) {
2163 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2165 /* We ignore prepacked branches since the fragment epilogue is
2166 * just generally special */
2167 if (ins
->prepacked_branch
) continue;
2169 /* Discards are similarly special and may not correspond to the
2172 if (ins
->branch
.target_type
== TARGET_DISCARD
) continue;
2175 /* We already branched, so this is dead */
2176 mir_remove_instruction(ins
);
2183 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2184 * the move can be propagated away entirely */
2187 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2190 if (comp
== midgard_outmod_none
)
2193 if (*outmod
== midgard_outmod_none
) {
2198 /* TODO: Compose rules */
2203 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2205 bool progress
= false;
2207 mir_foreach_instr_in_block_safe(block
, ins
) {
2208 if (ins
->type
!= TAG_ALU_4
) continue;
2209 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2210 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2212 /* TODO: Registers? */
2213 unsigned src
= ins
->ssa_args
.src
[1];
2214 if (src
& IS_REG
) continue;
2215 assert(!mir_has_multiple_writes(ctx
, src
));
2217 /* There might be a source modifier, too */
2218 if (mir_nontrivial_source2_mod(ins
)) continue;
2220 /* Backpropagate the modifier */
2221 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2222 if (v
->type
!= TAG_ALU_4
) continue;
2223 if (v
->ssa_args
.dest
!= src
) continue;
2225 /* Can we even take a float outmod? */
2226 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2228 midgard_outmod_float temp
= v
->alu
.outmod
;
2229 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2231 /* Throw in the towel.. */
2232 if (!progress
) break;
2234 /* Otherwise, transfer the modifier */
2235 v
->alu
.outmod
= temp
;
2236 ins
->alu
.outmod
= midgard_outmod_none
;
2246 emit_fragment_epilogue(compiler_context
*ctx
)
2248 /* Just emit the last chunk with the branch */
2249 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2252 static midgard_block
*
2253 emit_block(compiler_context
*ctx
, nir_block
*block
)
2255 midgard_block
*this_block
= ctx
->after_block
;
2256 ctx
->after_block
= NULL
;
2259 this_block
= calloc(sizeof(midgard_block
), 1);
2261 list_addtail(&this_block
->link
, &ctx
->blocks
);
2263 this_block
->is_scheduled
= false;
2266 ctx
->texture_index
[0] = -1;
2267 ctx
->texture_index
[1] = -1;
2269 /* Set up current block */
2270 list_inithead(&this_block
->instructions
);
2271 ctx
->current_block
= this_block
;
2273 nir_foreach_instr(instr
, block
) {
2274 emit_instr(ctx
, instr
);
2275 ++ctx
->instruction_count
;
2278 inline_alu_constants(ctx
);
2279 embedded_to_inline_constant(ctx
);
2281 /* Append fragment shader epilogue (value writeout) */
2282 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2283 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2284 emit_fragment_epilogue(ctx
);
2288 /* Allow the next control flow to access us retroactively, for
2290 ctx
->current_block
= this_block
;
2295 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2298 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2300 midgard_block
*before_block
= ctx
->current_block
;
2302 /* Conditional branches expect the condition in r31.w; emit a move for
2303 * that in the _previous_ block (which is the current block). */
2304 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2306 /* Speculatively emit the branch, but we can't fill it in until later */
2307 EMIT(branch
, true, true);
2308 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2310 /* Emit the two subblocks. */
2311 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2312 midgard_block
*end_then_block
= ctx
->current_block
;
2314 /* Emit a jump from the end of the then block to the end of the else */
2315 EMIT(branch
, false, false);
2316 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2318 /* Emit second block, and check if it's empty */
2320 int else_idx
= ctx
->block_count
;
2321 int count_in
= ctx
->instruction_count
;
2322 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2323 midgard_block
*end_else_block
= ctx
->current_block
;
2324 int after_else_idx
= ctx
->block_count
;
2326 /* Now that we have the subblocks emitted, fix up the branches */
2331 if (ctx
->instruction_count
== count_in
) {
2332 /* The else block is empty, so don't emit an exit jump */
2333 mir_remove_instruction(then_exit
);
2334 then_branch
->branch
.target_block
= after_else_idx
;
2336 then_branch
->branch
.target_block
= else_idx
;
2337 then_exit
->branch
.target_block
= after_else_idx
;
2340 /* Wire up the successors */
2342 ctx
->after_block
= calloc(sizeof(midgard_block
), 1);
2344 midgard_block_add_successor(before_block
, then_block
);
2345 midgard_block_add_successor(before_block
, else_block
);
2347 midgard_block_add_successor(end_then_block
, ctx
->after_block
);
2348 midgard_block_add_successor(end_else_block
, ctx
->after_block
);
2352 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2354 /* Remember where we are */
2355 midgard_block
*start_block
= ctx
->current_block
;
2357 /* Allocate a loop number, growing the current inner loop depth */
2358 int loop_idx
= ++ctx
->current_loop_depth
;
2360 /* Get index from before the body so we can loop back later */
2361 int start_idx
= ctx
->block_count
;
2363 /* Emit the body itself */
2364 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2366 /* Branch back to loop back */
2367 struct midgard_instruction br_back
= v_branch(false, false);
2368 br_back
.branch
.target_block
= start_idx
;
2369 emit_mir_instruction(ctx
, br_back
);
2371 /* Mark down that branch in the graph. */
2372 midgard_block_add_successor(start_block
, loop_block
);
2373 midgard_block_add_successor(ctx
->current_block
, loop_block
);
2375 /* Find the index of the block about to follow us (note: we don't add
2376 * one; blocks are 0-indexed so we get a fencepost problem) */
2377 int break_block_idx
= ctx
->block_count
;
2379 /* Fix up the break statements we emitted to point to the right place,
2380 * now that we can allocate a block number for them */
2381 ctx
->after_block
= calloc(sizeof(midgard_block
), 1);
2383 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2384 mir_foreach_instr_in_block(block
, ins
) {
2385 if (ins
->type
!= TAG_ALU_4
) continue;
2386 if (!ins
->compact_branch
) continue;
2387 if (ins
->prepacked_branch
) continue;
2389 /* We found a branch -- check the type to see if we need to do anything */
2390 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2392 /* It's a break! Check if it's our break */
2393 if (ins
->branch
.target_break
!= loop_idx
) continue;
2395 /* Okay, cool, we're breaking out of this loop.
2396 * Rewrite from a break to a goto */
2398 ins
->branch
.target_type
= TARGET_GOTO
;
2399 ins
->branch
.target_block
= break_block_idx
;
2401 midgard_block_add_successor(block
, ctx
->after_block
);
2405 /* Now that we've finished emitting the loop, free up the depth again
2406 * so we play nice with recursion amid nested loops */
2407 --ctx
->current_loop_depth
;
2409 /* Dump loop stats */
2413 static midgard_block
*
2414 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2416 midgard_block
*start_block
= NULL
;
2418 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2419 switch (node
->type
) {
2420 case nir_cf_node_block
: {
2421 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2424 start_block
= block
;
2429 case nir_cf_node_if
:
2430 emit_if(ctx
, nir_cf_node_as_if(node
));
2433 case nir_cf_node_loop
:
2434 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2437 case nir_cf_node_function
:
2446 /* Due to lookahead, we need to report the first tag executed in the command
2447 * stream and in branch targets. An initial block might be empty, so iterate
2448 * until we find one that 'works' */
2451 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2453 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2455 unsigned first_tag
= 0;
2457 mir_foreach_block_from(ctx
, initial_block
, v
) {
2458 midgard_bundle
*initial_bundle
=
2459 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2461 if (initial_bundle
) {
2462 first_tag
= initial_bundle
->tag
;
2471 midgard_compile_shader_nir(struct midgard_screen
*screen
, nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2473 struct util_dynarray
*compiled
= &program
->compiled
;
2475 midgard_debug
= debug_get_option_midgard_debug();
2477 compiler_context ictx
= {
2480 .stage
= nir
->info
.stage
,
2483 .is_blend
= is_blend
,
2484 .blend_constant_offset
= 0,
2486 .alpha_ref
= program
->alpha_ref
2489 compiler_context
*ctx
= &ictx
;
2491 /* Start off with a safe cutoff, allowing usage of all 16 work
2492 * registers. Later, we'll promote uniform reads to uniform registers
2493 * if we determine it is beneficial to do so */
2494 ctx
->uniform_cutoff
= 8;
2496 /* Initialize at a global (not block) level hash tables */
2498 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2499 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2500 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2502 /* Record the varying mapping for the command stream's bookkeeping */
2504 struct exec_list
*varyings
=
2505 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2507 unsigned max_varying
= 0;
2508 nir_foreach_variable(var
, varyings
) {
2509 unsigned loc
= var
->data
.driver_location
;
2510 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2512 for (int c
= 0; c
< sz
; ++c
) {
2513 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2514 max_varying
= MAX2(max_varying
, loc
+ c
);
2518 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2519 * (so we don't accidentally duplicate the epilogue since mesa/st has
2520 * messed with our I/O quite a bit already) */
2522 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2524 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2525 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2526 NIR_PASS_V(nir
, nir_clamp_psiz
, 1.0, 1024.0);
2529 NIR_PASS_V(nir
, nir_lower_var_copies
);
2530 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2531 NIR_PASS_V(nir
, nir_split_var_copies
);
2532 NIR_PASS_V(nir
, nir_lower_var_copies
);
2533 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2534 NIR_PASS_V(nir
, nir_lower_var_copies
);
2535 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2537 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2539 /* Optimisation passes */
2543 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2544 nir_print_shader(nir
, stdout
);
2547 /* Assign sysvals and counts, now that we're sure
2548 * (post-optimisation) */
2550 midgard_nir_assign_sysvals(ctx
, nir
);
2552 program
->uniform_count
= nir
->num_uniforms
;
2553 program
->sysval_count
= ctx
->sysval_count
;
2554 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2556 nir_foreach_function(func
, nir
) {
2560 list_inithead(&ctx
->blocks
);
2561 ctx
->block_count
= 0;
2564 emit_cf_list(ctx
, &func
->impl
->body
);
2565 emit_block(ctx
, func
->impl
->end_block
);
2567 break; /* TODO: Multi-function shaders */
2570 util_dynarray_init(compiled
, NULL
);
2572 /* MIR-level optimizations */
2574 bool progress
= false;
2579 mir_foreach_block(ctx
, block
) {
2580 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2581 progress
|= midgard_opt_copy_prop(ctx
, block
);
2582 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2583 progress
|= midgard_opt_combine_projection(ctx
, block
);
2584 progress
|= midgard_opt_varying_projection(ctx
, block
);
2585 progress
|= midgard_opt_not_propagate(ctx
, block
);
2586 progress
|= midgard_opt_fuse_src_invert(ctx
, block
);
2587 progress
|= midgard_opt_fuse_dest_invert(ctx
, block
);
2591 mir_foreach_block(ctx
, block
) {
2592 midgard_lower_invert(ctx
, block
);
2593 midgard_lower_derivatives(ctx
, block
);
2596 /* Nested control-flow can result in dead branches at the end of the
2597 * block. This messes with our analysis and is just dead code, so cull
2599 mir_foreach_block(ctx
, block
) {
2600 midgard_opt_cull_dead_branch(ctx
, block
);
2603 /* Ensure we were lowered */
2604 mir_foreach_instr_global(ctx
, ins
) {
2605 assert(!ins
->invert
);
2609 schedule_program(ctx
);
2611 /* Now that all the bundles are scheduled and we can calculate block
2612 * sizes, emit actual branch instructions rather than placeholders */
2614 int br_block_idx
= 0;
2616 mir_foreach_block(ctx
, block
) {
2617 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2618 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2619 midgard_instruction
*ins
= bundle
->instructions
[c
];
2621 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2623 if (ins
->prepacked_branch
) continue;
2625 /* Parse some basic branch info */
2626 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2627 bool is_conditional
= ins
->branch
.conditional
;
2628 bool is_inverted
= ins
->branch
.invert_conditional
;
2629 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2631 /* Determine the block we're jumping to */
2632 int target_number
= ins
->branch
.target_block
;
2634 /* Report the destination tag */
2635 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2637 /* Count up the number of quadwords we're
2638 * jumping over = number of quadwords until
2639 * (br_block_idx, target_number) */
2641 int quadword_offset
= 0;
2645 } else if (target_number
> br_block_idx
) {
2648 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2649 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2652 quadword_offset
+= blk
->quadword_count
;
2655 /* Jump backwards */
2657 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2658 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2661 quadword_offset
-= blk
->quadword_count
;
2665 /* Unconditional extended branches (far jumps)
2666 * have issues, so we always use a conditional
2667 * branch, setting the condition to always for
2668 * unconditional. For compact unconditional
2669 * branches, cond isn't used so it doesn't
2670 * matter what we pick. */
2672 midgard_condition cond
=
2673 !is_conditional
? midgard_condition_always
:
2674 is_inverted
? midgard_condition_false
:
2675 midgard_condition_true
;
2677 midgard_jmp_writeout_op op
=
2678 is_discard
? midgard_jmp_writeout_op_discard
:
2679 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2680 midgard_jmp_writeout_op_branch_cond
;
2683 midgard_branch_extended branch
=
2684 midgard_create_branch_extended(
2689 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2690 } else if (is_conditional
|| is_discard
) {
2691 midgard_branch_cond branch
= {
2693 .dest_tag
= dest_tag
,
2694 .offset
= quadword_offset
,
2698 assert(branch
.offset
== quadword_offset
);
2700 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2702 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2704 midgard_branch_uncond branch
= {
2706 .dest_tag
= dest_tag
,
2707 .offset
= quadword_offset
,
2711 assert(branch
.offset
== quadword_offset
);
2713 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2721 /* Emit flat binary from the instruction arrays. Iterate each block in
2722 * sequence. Save instruction boundaries such that lookahead tags can
2723 * be assigned easily */
2725 /* Cache _all_ bundles in source order for lookahead across failed branches */
2727 int bundle_count
= 0;
2728 mir_foreach_block(ctx
, block
) {
2729 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2731 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2733 mir_foreach_block(ctx
, block
) {
2734 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2735 source_order_bundles
[bundle_idx
++] = bundle
;
2739 int current_bundle
= 0;
2741 /* Midgard prefetches instruction types, so during emission we
2742 * need to lookahead. Unless this is the last instruction, in
2743 * which we return 1. Or if this is the second to last and the
2744 * last is an ALU, then it's also 1... */
2746 mir_foreach_block(ctx
, block
) {
2747 mir_foreach_bundle_in_block(block
, bundle
) {
2750 if (current_bundle
+ 1 < bundle_count
) {
2751 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2753 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2760 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2764 /* TODO: Free deeper */
2765 //util_dynarray_fini(&block->instructions);
2768 free(source_order_bundles
);
2770 /* Report the very first tag executed */
2771 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2773 /* Deal with off-by-one related to the fencepost problem */
2774 program
->work_register_count
= ctx
->work_registers
+ 1;
2775 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2777 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2778 program
->tls_size
= ctx
->tls_size
;
2780 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2781 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
, false, 0, "");
2783 if (midgard_debug
& MIDGARD_DBG_SHADERDB
) {
2784 unsigned nr_bundles
= 0, nr_ins
= 0, nr_quadwords
= 0;
2786 /* Count instructions and bundles */
2788 mir_foreach_instr_global(ctx
, ins
) {
2792 mir_foreach_block(ctx
, block
) {
2793 nr_bundles
+= util_dynarray_num_elements(
2794 &block
->bundles
, midgard_bundle
);
2796 nr_quadwords
+= block
->quadword_count
;
2799 /* Calculate thread count. There are certain cutoffs by
2800 * register count for thread count */
2802 unsigned nr_registers
= program
->work_register_count
;
2804 unsigned nr_threads
=
2805 (nr_registers
<= 4) ? 4 :
2806 (nr_registers
<= 8) ? 2 :
2811 fprintf(stderr
, "shader%d - %s shader: "
2812 "%u inst, %u bundles, %u quadwords, "
2813 "%u registers, %u threads, %u loops, "
2814 "%d:%d spills:fills\n",
2816 gl_shader_stage_name(ctx
->stage
),
2817 nr_ins
, nr_bundles
, nr_quadwords
,
2818 nr_registers
, nr_threads
,
2820 ctx
->spills
, ctx
->fills
);