2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/u_math.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
50 #include "midgard_quirks.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
57 {"shaderdb", MIDGARD_DBG_SHADERDB
, "Prints shader-db statistics"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
63 unsigned SHADER_DB_COUNT
= 0;
65 int midgard_debug
= 0;
67 #define DBG(fmt, ...) \
68 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
69 fprintf(stderr, "%s:%d: "fmt, \
70 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
71 static midgard_block
*
72 create_empty_block(compiler_context
*ctx
)
74 midgard_block
*blk
= rzalloc(ctx
, midgard_block
);
76 blk
->base
.predecessors
= _mesa_set_create(blk
,
78 _mesa_key_pointer_equal
);
80 blk
->base
.name
= ctx
->block_source_count
++;
86 schedule_barrier(compiler_context
*ctx
)
88 midgard_block
*temp
= ctx
->after_block
;
89 ctx
->after_block
= create_empty_block(ctx
);
91 list_addtail(&ctx
->after_block
->base
.link
, &ctx
->blocks
);
92 list_inithead(&ctx
->after_block
->base
.instructions
);
93 pan_block_add_successor(&ctx
->current_block
->base
, &ctx
->after_block
->base
);
94 ctx
->current_block
= ctx
->after_block
;
95 ctx
->after_block
= temp
;
98 /* Helpers to generate midgard_instruction's using macro magic, since every
99 * driver seems to do it that way */
101 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
103 #define M_LOAD_STORE(name, store, T) \
104 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
105 midgard_instruction i = { \
106 .type = TAG_LOAD_STORE_4, \
109 .src = { ~0, ~0, ~0, ~0 }, \
110 .swizzle = SWIZZLE_IDENTITY_4, \
112 .op = midgard_op_##name, \
119 i.src_types[0] = T; \
127 #define M_LOAD(name, T) M_LOAD_STORE(name, false, T)
128 #define M_STORE(name, T) M_LOAD_STORE(name, true, T)
130 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
131 * the corresponding Midgard source */
133 static midgard_vector_alu_src
134 vector_alu_modifiers(bool abs
, bool neg
, bool is_int
,
135 bool half
, bool sext
)
137 /* Figure out how many components there are so we can adjust.
138 * Specifically we want to broadcast the last channel so things like
142 midgard_vector_alu_src alu_src
= {
149 alu_src
.mod
= midgard_int_normal
;
151 /* Sign/zero-extend if needed */
155 midgard_int_sign_extend
156 : midgard_int_zero_extend
;
159 /* These should have been lowered away */
160 assert(!(abs
|| neg
));
162 alu_src
.mod
= (abs
<< 0) | (neg
<< 1);
168 M_LOAD(ld_attr_32
, nir_type_uint32
);
169 M_LOAD(ld_vary_32
, nir_type_uint32
);
170 M_LOAD(ld_ubo_int4
, nir_type_uint32
);
171 M_LOAD(ld_int4
, nir_type_uint32
);
172 M_STORE(st_int4
, nir_type_uint32
);
173 M_LOAD(ld_color_buffer_32u
, nir_type_uint32
);
174 M_STORE(st_vary_32
, nir_type_uint32
);
175 M_LOAD(ld_cubemap_coords
, nir_type_uint32
);
176 M_LOAD(ld_compute_id
, nir_type_uint32
);
178 static midgard_instruction
179 v_branch(bool conditional
, bool invert
)
181 midgard_instruction ins
= {
183 .unit
= ALU_ENAB_BRANCH
,
184 .compact_branch
= true,
186 .conditional
= conditional
,
187 .invert_conditional
= invert
190 .src
= { ~0, ~0, ~0, ~0 },
196 static midgard_branch_extended
197 midgard_create_branch_extended( midgard_condition cond
,
198 midgard_jmp_writeout_op op
,
200 signed quadword_offset
)
202 /* The condition code is actually a LUT describing a function to
203 * combine multiple condition codes. However, we only support a single
204 * condition code at the moment, so we just duplicate over a bunch of
207 uint16_t duplicated_cond
=
217 midgard_branch_extended branch
= {
219 .dest_tag
= dest_tag
,
220 .offset
= quadword_offset
,
221 .cond
= duplicated_cond
228 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
230 ins
->has_constants
= true;
231 memcpy(&ins
->constants
, constants
, 16);
235 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
237 return glsl_count_attribute_slots(type
, false);
240 /* Lower fdot2 to a vector multiplication followed by channel addition */
242 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
244 if (alu
->op
!= nir_op_fdot2
)
247 b
->cursor
= nir_before_instr(&alu
->instr
);
249 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
250 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
252 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
254 nir_ssa_def
*sum
= nir_fadd(b
,
255 nir_channel(b
, product
, 0),
256 nir_channel(b
, product
, 1));
258 /* Replace the fdot2 with this sum */
259 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
263 midgard_nir_lower_fdot2(nir_shader
*shader
)
265 bool progress
= false;
267 nir_foreach_function(function
, shader
) {
268 if (!function
->impl
) continue;
271 nir_builder
*b
= &_b
;
272 nir_builder_init(b
, function
->impl
);
274 nir_foreach_block(block
, function
->impl
) {
275 nir_foreach_instr_safe(instr
, block
) {
276 if (instr
->type
!= nir_instr_type_alu
) continue;
278 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
279 midgard_nir_lower_fdot2_body(b
, alu
);
285 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
292 /* Midgard can't write depth and stencil separately. It has to happen in a
293 * single store operation containing both. Let's add a panfrost specific
294 * intrinsic and turn all depth/stencil stores into a packed depth+stencil
298 midgard_nir_lower_zs_store(nir_shader
*nir
)
300 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
303 nir_variable
*z_var
= NULL
, *s_var
= NULL
;
305 nir_foreach_variable(var
, &nir
->outputs
) {
306 if (var
->data
.location
== FRAG_RESULT_DEPTH
)
308 else if (var
->data
.location
== FRAG_RESULT_STENCIL
)
312 if (!z_var
&& !s_var
)
315 bool progress
= false;
317 nir_foreach_function(function
, nir
) {
318 if (!function
->impl
) continue;
320 nir_intrinsic_instr
*z_store
= NULL
, *s_store
= NULL
, *last_store
= NULL
;
322 nir_foreach_block(block
, function
->impl
) {
323 nir_foreach_instr_safe(instr
, block
) {
324 if (instr
->type
!= nir_instr_type_intrinsic
)
327 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
328 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
331 if (z_var
&& nir_intrinsic_base(intr
) == z_var
->data
.driver_location
) {
337 if (s_var
&& nir_intrinsic_base(intr
) == s_var
->data
.driver_location
) {
345 if (!z_store
&& !s_store
) continue;
348 nir_builder_init(&b
, function
->impl
);
350 b
.cursor
= nir_before_instr(&last_store
->instr
);
352 nir_ssa_def
*zs_store_src
;
354 if (z_store
&& s_store
) {
355 nir_ssa_def
*srcs
[2] = {
356 nir_ssa_for_src(&b
, z_store
->src
[0], 1),
357 nir_ssa_for_src(&b
, s_store
->src
[0], 1),
360 zs_store_src
= nir_vec(&b
, srcs
, 2);
362 zs_store_src
= nir_ssa_for_src(&b
, last_store
->src
[0], 1);
365 nir_intrinsic_instr
*zs_store
;
367 zs_store
= nir_intrinsic_instr_create(b
.shader
,
368 nir_intrinsic_store_zs_output_pan
);
369 zs_store
->src
[0] = nir_src_for_ssa(zs_store_src
);
370 zs_store
->num_components
= z_store
&& s_store
? 2 : 1;
371 nir_intrinsic_set_component(zs_store
, z_store
? 0 : 1);
373 /* Replace the Z and S store by a ZS store */
374 nir_builder_instr_insert(&b
, &zs_store
->instr
);
377 nir_instr_remove(&z_store
->instr
);
380 nir_instr_remove(&s_store
->instr
);
382 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
389 /* Flushes undefined values to zero */
392 optimise_nir(nir_shader
*nir
, unsigned quirks
)
395 unsigned lower_flrp
=
396 (nir
->options
->lower_flrp16
? 16 : 0) |
397 (nir
->options
->lower_flrp32
? 32 : 0) |
398 (nir
->options
->lower_flrp64
? 64 : 0);
400 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
401 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
403 nir_lower_tex_options lower_tex_options
= {
404 .lower_txs_lod
= true,
406 .lower_tex_without_implicit_lod
=
407 (quirks
& MIDGARD_EXPLICIT_LOD
),
409 /* TODO: we have native gradient.. */
413 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
415 /* Must lower fdot2 after tex is lowered */
416 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
418 /* T720 is broken. */
420 if (quirks
& MIDGARD_BROKEN_LOD
)
421 NIR_PASS_V(nir
, midgard_nir_lod_errata
);
426 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
427 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
429 NIR_PASS(progress
, nir
, nir_copy_prop
);
430 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
431 NIR_PASS(progress
, nir
, nir_opt_dce
);
432 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
433 NIR_PASS(progress
, nir
, nir_opt_cse
);
434 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
435 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
436 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
438 if (lower_flrp
!= 0) {
439 bool lower_flrp_progress
= false;
440 NIR_PASS(lower_flrp_progress
,
444 false /* always_precise */,
445 nir
->options
->lower_ffma
);
446 if (lower_flrp_progress
) {
447 NIR_PASS(progress
, nir
,
448 nir_opt_constant_folding
);
452 /* Nothing should rematerialize any flrps, so we only
453 * need to do this lowering once.
458 NIR_PASS(progress
, nir
, nir_opt_undef
);
459 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
461 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
464 nir_var_function_temp
);
466 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
469 /* Must be run at the end to prevent creation of fsin/fcos ops */
470 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
475 NIR_PASS(progress
, nir
, nir_opt_dce
);
476 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
477 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
478 NIR_PASS(progress
, nir
, nir_copy_prop
);
481 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
482 NIR_PASS(progress
, nir
, nir_opt_algebraic_distribute_src_mods
);
484 /* We implement booleans as 32-bit 0/~0 */
485 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
487 /* Now that booleans are lowered, we can run out late opts */
488 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
489 NIR_PASS(progress
, nir
, midgard_nir_cancel_inot
);
491 NIR_PASS(progress
, nir
, nir_copy_prop
);
492 NIR_PASS(progress
, nir
, nir_opt_dce
);
494 /* Take us out of SSA */
495 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
496 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
498 /* We are a vector architecture; write combine where possible */
499 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
500 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
502 NIR_PASS(progress
, nir
, nir_opt_dce
);
505 /* Do not actually emit a load; instead, cache the constant for inlining */
508 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
510 nir_ssa_def def
= instr
->def
;
512 midgard_constants
*consts
= rzalloc(NULL
, midgard_constants
);
514 assert(instr
->def
.num_components
* instr
->def
.bit_size
<= sizeof(*consts
) * 8);
516 #define RAW_CONST_COPY(bits) \
517 nir_const_value_to_array(consts->u##bits, instr->value, \
518 instr->def.num_components, u##bits)
520 switch (instr
->def
.bit_size
) {
534 unreachable("Invalid bit_size for load_const instruction\n");
537 /* Shifted for SSA, +1 for off-by-one */
538 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, (def
.index
<< 1) + 1, consts
);
541 /* Normally constants are embedded implicitly, but for I/O and such we have to
542 * explicitly emit a move with the constant source */
545 emit_explicit_constant(compiler_context
*ctx
, unsigned node
, unsigned to
)
547 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, node
+ 1);
549 if (constant_value
) {
550 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), to
);
551 attach_constants(ctx
, &ins
, constant_value
, node
+ 1);
552 emit_mir_instruction(ctx
, ins
);
557 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
559 unsigned comp
= src
->swizzle
[0];
561 for (unsigned c
= 1; c
< nr_components
; ++c
) {
562 if (src
->swizzle
[c
] != comp
)
569 #define ALU_CASE(nir, _op) \
571 op = midgard_alu_op_##_op; \
572 assert(src_bitsize == dst_bitsize); \
575 #define ALU_CASE_BCAST(nir, _op, count) \
577 op = midgard_alu_op_##_op; \
578 broadcast_swizzle = count; \
579 assert(src_bitsize == dst_bitsize); \
581 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
582 * special treatment override this anyway. */
584 static midgard_reg_mode
585 reg_mode_for_nir(nir_alu_instr
*instr
)
587 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
589 switch (src_bitsize
) {
591 return midgard_reg_mode_8
;
593 return midgard_reg_mode_16
;
595 return midgard_reg_mode_32
;
597 return midgard_reg_mode_64
;
599 unreachable("Invalid bit size");
603 /* Compare mir_lower_invert */
605 nir_accepts_inot(nir_op op
, unsigned src
)
613 /* Only the condition */
621 mir_accept_dest_mod(compiler_context
*ctx
, nir_dest
**dest
, nir_op op
)
623 if (pan_has_dest_mod(dest
, op
)) {
624 assert((*dest
)->is_ssa
);
625 BITSET_SET(ctx
->already_emitted
, (*dest
)->ssa
.index
);
633 mir_copy_src(midgard_instruction
*ins
, nir_alu_instr
*instr
, unsigned i
, unsigned to
, bool *abs
, bool *neg
, bool *not, bool is_int
, unsigned bcast_count
)
635 nir_alu_src src
= instr
->src
[i
];
638 if (pan_has_source_mod(&src
, nir_op_fneg
))
641 if (pan_has_source_mod(&src
, nir_op_fabs
))
645 if (nir_accepts_inot(instr
->op
, i
) && pan_has_source_mod(&src
, nir_op_inot
))
648 unsigned bits
= nir_src_bit_size(src
.src
);
650 ins
->src
[to
] = nir_src_index(NULL
, &src
.src
);
651 ins
->src_types
[to
] = nir_op_infos
[instr
->op
].input_types
[i
] | bits
;
653 for (unsigned c
= 0; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
654 ins
->swizzle
[to
][c
] = src
.swizzle
[
655 (!bcast_count
|| c
< bcast_count
) ? c
:
660 /* Midgard features both fcsel and icsel, depending on whether you want int or
661 * float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
662 * we should emit an int or float csel depending on what modifiers could be
663 * placed. In the absense of modifiers, this is probably arbitrary. */
666 mir_is_bcsel_float(nir_alu_instr
*instr
)
669 nir_op_i2i8
, nir_op_i2i16
,
670 nir_op_i2i32
, nir_op_i2i64
673 nir_op floatmods
[] = {
674 nir_op_fabs
, nir_op_fneg
,
675 nir_op_f2f16
, nir_op_f2f32
,
679 nir_op floatdestmods
[] = {
680 nir_op_fsat
, nir_op_fsat_signed
, nir_op_fclamp_pos
,
681 nir_op_f2f16
, nir_op_f2f32
686 for (unsigned i
= 1; i
< 3; ++i
) {
687 nir_alu_src s
= instr
->src
[i
];
688 for (unsigned q
= 0; q
< ARRAY_SIZE(intmods
); ++q
) {
689 if (pan_has_source_mod(&s
, intmods
[q
]))
694 for (unsigned i
= 1; i
< 3; ++i
) {
695 nir_alu_src s
= instr
->src
[i
];
696 for (unsigned q
= 0; q
< ARRAY_SIZE(floatmods
); ++q
) {
697 if (pan_has_source_mod(&s
, floatmods
[q
]))
702 for (unsigned q
= 0; q
< ARRAY_SIZE(floatdestmods
); ++q
) {
703 nir_dest
*dest
= &instr
->dest
.dest
;
704 if (pan_has_dest_mod(&dest
, floatdestmods
[q
]))
712 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
714 nir_dest
*dest
= &instr
->dest
.dest
;
716 if (dest
->is_ssa
&& BITSET_TEST(ctx
->already_emitted
, dest
->ssa
.index
))
719 /* Derivatives end up emitted on the texture pipe, not the ALUs. This
720 * is handled elsewhere */
722 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddy
) {
723 midgard_emit_derivatives(ctx
, instr
);
727 bool is_ssa
= dest
->is_ssa
;
729 unsigned nr_components
= nir_dest_num_components(*dest
);
730 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
733 /* Number of components valid to check for the instruction (the rest
734 * will be forced to the last), or 0 to use as-is. Relevant as
735 * ball-type instructions have a channel count in NIR but are all vec4
738 unsigned broadcast_swizzle
= 0;
740 /* What register mode should we operate in? */
741 midgard_reg_mode reg_mode
=
742 reg_mode_for_nir(instr
);
744 /* Do we need a destination override? Used for inline
747 midgard_dest_override dest_override
=
748 midgard_dest_override_none
;
750 /* Should we use a smaller respective source and sign-extend? */
752 bool half_1
= false, sext_1
= false;
753 bool half_2
= false, sext_2
= false;
755 /* Should we swap arguments? */
756 bool flip_src12
= false;
758 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
759 unsigned dst_bitsize
= nir_dest_bit_size(*dest
);
762 ALU_CASE(fadd
, fadd
);
763 ALU_CASE(fmul
, fmul
);
764 ALU_CASE(fmin
, fmin
);
765 ALU_CASE(fmax
, fmax
);
766 ALU_CASE(imin
, imin
);
767 ALU_CASE(imax
, imax
);
768 ALU_CASE(umin
, umin
);
769 ALU_CASE(umax
, umax
);
770 ALU_CASE(ffloor
, ffloor
);
771 ALU_CASE(fround_even
, froundeven
);
772 ALU_CASE(ftrunc
, ftrunc
);
773 ALU_CASE(fceil
, fceil
);
774 ALU_CASE(fdot3
, fdot3
);
775 ALU_CASE(fdot4
, fdot4
);
776 ALU_CASE(iadd
, iadd
);
777 ALU_CASE(isub
, isub
);
778 ALU_CASE(imul
, imul
);
780 /* Zero shoved as second-arg */
781 ALU_CASE(iabs
, iabsdiff
);
785 ALU_CASE(feq32
, feq
);
786 ALU_CASE(fne32
, fne
);
787 ALU_CASE(flt32
, flt
);
788 ALU_CASE(ieq32
, ieq
);
789 ALU_CASE(ine32
, ine
);
790 ALU_CASE(ilt32
, ilt
);
791 ALU_CASE(ult32
, ult
);
793 /* We don't have a native b2f32 instruction. Instead, like many
794 * GPUs, we exploit booleans as 0/~0 for false/true, and
795 * correspondingly AND
796 * by 1.0 to do the type conversion. For the moment, prime us
799 * iand [whatever], #0
801 * At the end of emit_alu (as MIR), we'll fix-up the constant
804 ALU_CASE(b2f32
, iand
);
805 ALU_CASE(b2i32
, iand
);
807 /* Likewise, we don't have a dedicated f2b32 instruction, but
808 * we can do a "not equal to 0.0" test. */
810 ALU_CASE(f2b32
, fne
);
811 ALU_CASE(i2b32
, ine
);
813 ALU_CASE(frcp
, frcp
);
814 ALU_CASE(frsq
, frsqrt
);
815 ALU_CASE(fsqrt
, fsqrt
);
816 ALU_CASE(fexp2
, fexp2
);
817 ALU_CASE(flog2
, flog2
);
819 ALU_CASE(f2i64
, f2i_rtz
);
820 ALU_CASE(f2u64
, f2u_rtz
);
821 ALU_CASE(i2f64
, i2f_rtz
);
822 ALU_CASE(u2f64
, u2f_rtz
);
824 ALU_CASE(f2i32
, f2i_rtz
);
825 ALU_CASE(f2u32
, f2u_rtz
);
826 ALU_CASE(i2f32
, i2f_rtz
);
827 ALU_CASE(u2f32
, u2f_rtz
);
829 ALU_CASE(f2i16
, f2i_rtz
);
830 ALU_CASE(f2u16
, f2u_rtz
);
831 ALU_CASE(i2f16
, i2f_rtz
);
832 ALU_CASE(u2f16
, u2f_rtz
);
834 ALU_CASE(fsin
, fsin
);
835 ALU_CASE(fcos
, fcos
);
837 /* We'll get 0 in the second arg, so:
838 * ~a = ~(a | 0) = nor(a, 0) */
839 ALU_CASE(inot
, inor
);
840 ALU_CASE(iand
, iand
);
842 ALU_CASE(ixor
, ixor
);
843 ALU_CASE(ishl
, ishl
);
844 ALU_CASE(ishr
, iasr
);
845 ALU_CASE(ushr
, ilsr
);
847 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
848 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
849 ALU_CASE(b32all_fequal4
, fball_eq
);
851 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
852 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
853 ALU_CASE(b32any_fnequal4
, fbany_neq
);
855 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
856 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
857 ALU_CASE(b32all_iequal4
, iball_eq
);
859 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
860 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
861 ALU_CASE(b32any_inequal4
, ibany_neq
);
863 /* Source mods will be shoved in later */
864 ALU_CASE(fabs
, fmov
);
865 ALU_CASE(fneg
, fmov
);
866 ALU_CASE(fsat
, fmov
);
867 ALU_CASE(fsat_signed
, fmov
);
868 ALU_CASE(fclamp_pos
, fmov
);
870 /* For size conversion, we use a move. Ideally though we would squash
871 * these ops together; maybe that has to happen after in NIR as part of
872 * propagation...? An earlier algebraic pass ensured we step down by
873 * only / exactly one size. If stepping down, we use a dest override to
874 * reduce the size; if stepping up, we use a larger-sized move with a
875 * half source and a sign/zero-extension modifier */
881 /* If we end up upscale, we'll need a sign-extend on the
882 * operand (the second argument) */
893 if (instr
->op
== nir_op_f2f16
|| instr
->op
== nir_op_f2f32
||
894 instr
->op
== nir_op_f2f64
)
895 op
= midgard_alu_op_fmov
;
897 op
= midgard_alu_op_imov
;
899 if (dst_bitsize
== (src_bitsize
* 2)) {
903 /* Use a greater register mode */
905 } else if (src_bitsize
== (dst_bitsize
* 2)) {
906 /* Converting down */
907 dest_override
= midgard_dest_override_lower
;
913 /* For greater-or-equal, we lower to less-or-equal and flip the
921 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
922 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
923 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
924 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
931 case nir_op_b32csel
: {
932 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
933 bool is_float
= mir_is_bcsel_float(instr
);
935 (mixed
? midgard_alu_op_fcsel_v
: midgard_alu_op_fcsel
) :
936 (mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
);
942 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
947 /* Midgard can perform certain modifiers on output of an ALU op */
951 bool abs
[4] = { false };
952 bool neg
[4] = { false };
953 bool is_int
= midgard_is_integer_op(op
);
955 if (midgard_is_integer_out_op(op
)) {
956 outmod
= midgard_outmod_int_wrap
;
957 } else if (instr
->op
== nir_op_fsat
) {
958 outmod
= midgard_outmod_sat
;
959 } else if (instr
->op
== nir_op_fsat_signed
) {
960 outmod
= midgard_outmod_sat_signed
;
961 } else if (instr
->op
== nir_op_fclamp_pos
) {
962 outmod
= midgard_outmod_pos
;
965 /* Fetch unit, quirks, etc information */
966 unsigned opcode_props
= alu_opcode_props
[op
].props
;
967 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
969 /* Look for floating point mods. We have the mods fsat, fsat_signed,
970 * and fpos. We also have the relations (note 3 * 2 = 6 cases):
972 * fsat_signed(fpos(x)) = fsat(x)
973 * fsat_signed(fsat(x)) = fsat(x)
974 * fpos(fsat_signed(x)) = fsat(x)
975 * fpos(fsat(x)) = fsat(x)
976 * fsat(fsat_signed(x)) = fsat(x)
977 * fsat(fpos(x)) = fsat(x)
979 * So by cases any composition of output modifiers is equivalent to
983 if (!is_int
&& !(opcode_props
& OP_TYPE_CONVERT
)) {
984 bool fpos
= mir_accept_dest_mod(ctx
, &dest
, nir_op_fclamp_pos
);
985 bool fsat
= mir_accept_dest_mod(ctx
, &dest
, nir_op_fsat
);
986 bool ssat
= mir_accept_dest_mod(ctx
, &dest
, nir_op_fsat_signed
);
987 bool prior
= (outmod
!= midgard_outmod_none
);
988 int count
= (int) prior
+ (int) fpos
+ (int) ssat
+ (int) fsat
;
990 outmod
= ((count
> 1) || fsat
) ? midgard_outmod_sat
:
991 fpos
? midgard_outmod_pos
:
992 ssat
? midgard_outmod_sat_signed
:
996 midgard_instruction ins
= {
998 .dest
= nir_dest_index(dest
),
999 .dest_type
= nir_op_infos
[instr
->op
].output_type
1000 | nir_dest_bit_size(*dest
),
1003 for (unsigned i
= nr_inputs
; i
< ARRAY_SIZE(ins
.src
); ++i
)
1006 if (quirk_flipped_r24
) {
1008 mir_copy_src(&ins
, instr
, 0, 1, &abs
[1], &neg
[1], &ins
.src_invert
[1], is_int
, broadcast_swizzle
);
1010 for (unsigned i
= 0; i
< nr_inputs
; ++i
) {
1013 if (instr
->op
== nir_op_b32csel
) {
1014 /* The condition is the first argument; move
1015 * the other arguments up one to be a binary
1016 * instruction for Midgard with the condition
1021 else if (flip_src12
)
1025 } else if (flip_src12
) {
1029 mir_copy_src(&ins
, instr
, i
, to
, &abs
[to
], &neg
[to
], &ins
.src_invert
[to
], is_int
, broadcast_swizzle
);
1031 /* (!c) ? a : b = c ? b : a */
1032 if (instr
->op
== nir_op_b32csel
&& ins
.src_invert
[2]) {
1033 ins
.src_invert
[2] = false;
1039 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1040 /* Lowered to move */
1041 if (instr
->op
== nir_op_fneg
)
1044 if (instr
->op
== nir_op_fabs
)
1048 ins
.mask
= mask_of(nr_components
);
1050 midgard_vector_alu alu
= {
1052 .reg_mode
= reg_mode
,
1053 .dest_override
= dest_override
,
1056 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(abs
[0], neg
[0], is_int
, half_1
, sext_1
)),
1057 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(abs
[1], neg
[1], is_int
, half_2
, sext_2
)),
1060 /* Apply writemask if non-SSA, keeping in mind that we can't write to
1061 * components that don't exist. Note modifier => SSA => !reg => no
1062 * writemask, so we don't have to worry about writemasks here.*/
1065 ins
.mask
&= instr
->dest
.write_mask
;
1069 /* Arrange for creation of iandnot/iornot */
1070 if (ins
.src_invert
[0] && !ins
.src_invert
[1]) {
1072 ins
.src_invert
[0] = false;
1073 ins
.src_invert
[1] = true;
1076 /* Late fixup for emulated instructions */
1078 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1079 /* Presently, our second argument is an inline #0 constant.
1080 * Switch over to an embedded 1.0 constant (that can't fit
1081 * inline, since we're 32-bit, not 16-bit like the inline
1084 ins
.has_inline_constant
= false;
1085 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1086 ins
.src_types
[1] = nir_type_float32
;
1087 ins
.has_constants
= true;
1089 if (instr
->op
== nir_op_b2f32
)
1090 ins
.constants
.f32
[0] = 1.0f
;
1092 ins
.constants
.i32
[0] = 1;
1094 for (unsigned c
= 0; c
< 16; ++c
)
1095 ins
.swizzle
[1][c
] = 0;
1096 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1097 /* Lots of instructions need a 0 plonked in */
1098 ins
.has_inline_constant
= false;
1099 ins
.src
[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1100 ins
.src_types
[1] = nir_type_uint32
;
1101 ins
.has_constants
= true;
1102 ins
.constants
.u32
[0] = 0;
1104 for (unsigned c
= 0; c
< 16; ++c
)
1105 ins
.swizzle
[1][c
] = 0;
1108 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1109 /* To avoid duplicating the lookup tables (probably), true LUT
1110 * instructions can only operate as if they were scalars. Lower
1111 * them here by changing the component. */
1113 unsigned orig_mask
= ins
.mask
;
1115 unsigned swizzle_back
[MIR_VEC_COMPONENTS
];
1116 memcpy(&swizzle_back
, ins
.swizzle
[0], sizeof(swizzle_back
));
1118 for (int i
= 0; i
< nr_components
; ++i
) {
1119 /* Mask the associated component, dropping the
1120 * instruction if needed */
1123 ins
.mask
&= orig_mask
;
1128 for (unsigned j
= 0; j
< MIR_VEC_COMPONENTS
; ++j
)
1129 ins
.swizzle
[0][j
] = swizzle_back
[i
]; /* Pull from the correct component */
1131 emit_mir_instruction(ctx
, ins
);
1134 emit_mir_instruction(ctx
, ins
);
1141 mir_set_intr_mask(nir_instr
*instr
, midgard_instruction
*ins
, bool is_read
)
1143 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1144 unsigned nir_mask
= 0;
1148 nir_mask
= mask_of(nir_intrinsic_dest_components(intr
));
1149 dsize
= nir_dest_bit_size(intr
->dest
);
1151 nir_mask
= nir_intrinsic_write_mask(intr
);
1155 /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
1156 unsigned bytemask
= pan_to_bytemask(dsize
, nir_mask
);
1157 mir_set_bytemask(ins
, bytemask
);
1160 ins
->load_64
= true;
1163 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1164 * optimized) versions of UBO #0 */
1166 static midgard_instruction
*
1168 compiler_context
*ctx
,
1172 nir_src
*indirect_offset
,
1173 unsigned indirect_shift
,
1176 /* TODO: half-floats */
1178 midgard_instruction ins
= m_ld_ubo_int4(dest
, 0);
1179 ins
.constants
.u32
[0] = offset
;
1181 if (instr
->type
== nir_instr_type_intrinsic
)
1182 mir_set_intr_mask(instr
, &ins
, true);
1184 if (indirect_offset
) {
1185 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1186 ins
.src_types
[2] = nir_type_uint32
;
1187 ins
.load_store
.arg_2
= (indirect_shift
<< 5);
1189 ins
.load_store
.arg_2
= 0x1E;
1192 ins
.load_store
.arg_1
= index
;
1194 return emit_mir_instruction(ctx
, ins
);
1197 /* Globals are like UBOs if you squint. And shared memory is like globals if
1198 * you squint even harder */
1202 compiler_context
*ctx
,
1211 midgard_instruction ins
;
1214 ins
= m_ld_int4(srcdest
, 0);
1216 ins
= m_st_int4(srcdest
, 0);
1218 mir_set_offset(ctx
, &ins
, offset
, is_shared
);
1219 mir_set_intr_mask(instr
, &ins
, is_read
);
1221 emit_mir_instruction(ctx
, ins
);
1226 compiler_context
*ctx
,
1227 unsigned dest
, unsigned offset
,
1228 unsigned nr_comp
, unsigned component
,
1229 nir_src
*indirect_offset
, nir_alu_type type
, bool flat
)
1231 /* XXX: Half-floats? */
1232 /* TODO: swizzle, mask */
1234 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1235 ins
.mask
= mask_of(nr_comp
);
1237 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
.swizzle
[0]); ++i
)
1238 ins
.swizzle
[0][i
] = MIN2(i
+ component
, COMPONENT_W
);
1240 midgard_varying_parameter p
= {
1242 .interpolation
= midgard_interp_default
,
1247 memcpy(&u
, &p
, sizeof(p
));
1248 ins
.load_store
.varying_parameters
= u
;
1250 if (indirect_offset
) {
1251 ins
.src
[2] = nir_src_index(ctx
, indirect_offset
);
1252 ins
.src_types
[2] = nir_type_uint32
;
1254 ins
.load_store
.arg_2
= 0x1E;
1256 ins
.load_store
.arg_1
= 0x9E;
1258 /* Use the type appropriate load */
1262 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1265 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1267 case nir_type_float
:
1268 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1271 unreachable("Attempted to load unknown type");
1275 emit_mir_instruction(ctx
, ins
);
1280 compiler_context
*ctx
,
1281 unsigned dest
, unsigned offset
,
1282 unsigned nr_comp
, nir_alu_type t
)
1284 midgard_instruction ins
= m_ld_attr_32(dest
, offset
);
1285 ins
.load_store
.arg_1
= 0x1E;
1286 ins
.load_store
.arg_2
= 0x1E;
1287 ins
.mask
= mask_of(nr_comp
);
1289 /* Use the type appropriate load */
1293 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1296 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1298 case nir_type_float
:
1299 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1302 unreachable("Attempted to load unknown type");
1306 emit_mir_instruction(ctx
, ins
);
1310 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
,
1311 unsigned nr_components
, unsigned offset
)
1315 /* Figure out which uniform this is */
1316 int sysval
= panfrost_sysval_for_instr(instr
, &nir_dest
);
1317 void *val
= _mesa_hash_table_u64_search(ctx
->sysvals
.sysval_to_id
, sysval
);
1319 unsigned dest
= nir_dest_index(&nir_dest
);
1321 /* Sysvals are prefix uniforms */
1322 unsigned uniform
= ((uintptr_t) val
) - 1;
1324 /* Emit the read itself -- this is never indirect */
1325 midgard_instruction
*ins
=
1326 emit_ubo_read(ctx
, instr
, dest
, (uniform
* 16) + offset
, NULL
, 0, 0);
1328 ins
->mask
= mask_of(nr_components
);
1332 compute_builtin_arg(nir_op op
)
1335 case nir_intrinsic_load_work_group_id
:
1337 case nir_intrinsic_load_local_invocation_id
:
1340 unreachable("Invalid compute paramater loaded");
1345 emit_fragment_store(compiler_context
*ctx
, unsigned src
, enum midgard_rt_id rt
)
1347 assert(rt
< ARRAY_SIZE(ctx
->writeout_branch
));
1349 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
1353 emit_explicit_constant(ctx
, src
, src
);
1355 struct midgard_instruction ins
=
1356 v_branch(false, false);
1358 ins
.writeout
= true;
1360 /* Add dependencies */
1362 ins
.src_types
[0] = nir_type_uint32
;
1363 ins
.constants
.u32
[0] = rt
== MIDGARD_ZS_RT
?
1364 0xFF : (rt
- MIDGARD_COLOR_RT0
) * 0x100;
1366 /* Emit the branch */
1367 br
= emit_mir_instruction(ctx
, ins
);
1368 schedule_barrier(ctx
);
1369 ctx
->writeout_branch
[rt
] = br
;
1371 /* Push our current location = current block count - 1 = where we'll
1372 * jump to. Maybe a bit too clever for my own good */
1374 br
->branch
.target_block
= ctx
->block_count
- 1;
1378 emit_compute_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1380 unsigned reg
= nir_dest_index(&instr
->dest
);
1381 midgard_instruction ins
= m_ld_compute_id(reg
, 0);
1382 ins
.mask
= mask_of(3);
1383 ins
.swizzle
[0][3] = COMPONENT_X
; /* xyzx */
1384 ins
.load_store
.arg_1
= compute_builtin_arg(instr
->intrinsic
);
1385 emit_mir_instruction(ctx
, ins
);
1389 vertex_builtin_arg(nir_op op
)
1392 case nir_intrinsic_load_vertex_id
:
1393 return PAN_VERTEX_ID
;
1394 case nir_intrinsic_load_instance_id
:
1395 return PAN_INSTANCE_ID
;
1397 unreachable("Invalid vertex builtin");
1402 emit_vertex_builtin(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1404 unsigned reg
= nir_dest_index(&instr
->dest
);
1405 emit_attr_read(ctx
, reg
, vertex_builtin_arg(instr
->intrinsic
), 1, nir_type_int
);
1409 emit_control_barrier(compiler_context
*ctx
)
1411 midgard_instruction ins
= {
1412 .type
= TAG_TEXTURE_4
,
1413 .src
= { ~0, ~0, ~0, ~0 },
1415 .op
= TEXTURE_OP_BARRIER
,
1417 /* TODO: optimize */
1418 .barrier_buffer
= 1,
1423 emit_mir_instruction(ctx
, ins
);
1426 static const nir_variable
*
1427 search_var(struct exec_list
*vars
, unsigned driver_loc
)
1429 nir_foreach_variable(var
, vars
) {
1430 if (var
->data
.driver_location
== driver_loc
)
1438 mir_get_branch_cond(nir_src
*src
, bool *invert
)
1440 /* Wrap it. No swizzle since it's a scalar */
1446 *invert
= pan_has_source_mod(&alu
, nir_op_inot
);
1447 return nir_src_index(NULL
, &alu
.src
);
1451 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1453 unsigned offset
= 0, reg
;
1455 switch (instr
->intrinsic
) {
1456 case nir_intrinsic_discard_if
:
1457 case nir_intrinsic_discard
: {
1458 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1459 struct midgard_instruction discard
= v_branch(conditional
, false);
1460 discard
.branch
.target_type
= TARGET_DISCARD
;
1463 discard
.src
[0] = mir_get_branch_cond(&instr
->src
[0],
1464 &discard
.branch
.invert_conditional
);
1465 discard
.src_types
[0] = nir_type_uint32
;
1468 emit_mir_instruction(ctx
, discard
);
1469 schedule_barrier(ctx
);
1474 case nir_intrinsic_load_uniform
:
1475 case nir_intrinsic_load_ubo
:
1476 case nir_intrinsic_load_global
:
1477 case nir_intrinsic_load_shared
:
1478 case nir_intrinsic_load_input
:
1479 case nir_intrinsic_load_interpolated_input
: {
1480 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1481 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1482 bool is_global
= instr
->intrinsic
== nir_intrinsic_load_global
;
1483 bool is_shared
= instr
->intrinsic
== nir_intrinsic_load_shared
;
1484 bool is_flat
= instr
->intrinsic
== nir_intrinsic_load_input
;
1485 bool is_interp
= instr
->intrinsic
== nir_intrinsic_load_interpolated_input
;
1487 /* Get the base type of the intrinsic */
1488 /* TODO: Infer type? Does it matter? */
1490 (is_ubo
|| is_global
|| is_shared
) ? nir_type_uint
:
1491 (is_interp
) ? nir_type_float
:
1492 nir_intrinsic_type(instr
);
1494 t
= nir_alu_type_get_base_type(t
);
1496 if (!(is_ubo
|| is_global
)) {
1497 offset
= nir_intrinsic_base(instr
);
1500 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1502 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1504 bool direct
= nir_src_is_const(*src_offset
);
1505 nir_src
*indirect_offset
= direct
? NULL
: src_offset
;
1508 offset
+= nir_src_as_uint(*src_offset
);
1510 /* We may need to apply a fractional offset */
1511 int component
= (is_flat
|| is_interp
) ?
1512 nir_intrinsic_component(instr
) : 0;
1513 reg
= nir_dest_index(&instr
->dest
);
1515 if (is_uniform
&& !ctx
->is_blend
) {
1516 emit_ubo_read(ctx
, &instr
->instr
, reg
, (ctx
->sysvals
.sysval_count
+ offset
) * 16, indirect_offset
, 4, 0);
1517 } else if (is_ubo
) {
1518 nir_src index
= instr
->src
[0];
1520 /* TODO: Is indirect block number possible? */
1521 assert(nir_src_is_const(index
));
1523 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1524 emit_ubo_read(ctx
, &instr
->instr
, reg
, offset
, indirect_offset
, 0, uindex
);
1525 } else if (is_global
|| is_shared
) {
1526 emit_global(ctx
, &instr
->instr
, true, reg
, src_offset
, is_shared
);
1527 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1528 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, indirect_offset
, t
, is_flat
);
1529 } else if (ctx
->is_blend
) {
1530 /* For blend shaders, load the input color, which is
1531 * preloaded to r0 */
1533 midgard_instruction move
= v_mov(SSA_FIXED_REGISTER(0), reg
);
1534 emit_mir_instruction(ctx
, move
);
1535 schedule_barrier(ctx
);
1536 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1537 emit_attr_read(ctx
, reg
, offset
, nr_comp
, t
);
1539 DBG("Unknown load\n");
1546 /* Artefact of load_interpolated_input. TODO: other barycentric modes */
1547 case nir_intrinsic_load_barycentric_pixel
:
1548 case nir_intrinsic_load_barycentric_centroid
:
1551 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1553 case nir_intrinsic_load_raw_output_pan
:
1554 case nir_intrinsic_load_output_u8_as_fp16_pan
:
1555 reg
= nir_dest_index(&instr
->dest
);
1556 assert(ctx
->is_blend
);
1558 /* T720 and below use different blend opcodes with slightly
1559 * different semantics than T760 and up */
1561 midgard_instruction ld
= m_ld_color_buffer_32u(reg
, 0);
1562 bool old_blend
= ctx
->quirks
& MIDGARD_OLD_BLEND
;
1564 if (instr
->intrinsic
== nir_intrinsic_load_output_u8_as_fp16_pan
) {
1565 ld
.load_store
.op
= old_blend
?
1566 midgard_op_ld_color_buffer_u8_as_fp16_old
:
1567 midgard_op_ld_color_buffer_u8_as_fp16
;
1570 ld
.load_store
.address
= 1;
1571 ld
.load_store
.arg_2
= 0x1E;
1574 for (unsigned c
= 2; c
< 16; ++c
)
1575 ld
.swizzle
[0][c
] = 0;
1578 emit_mir_instruction(ctx
, ld
);
1581 case nir_intrinsic_load_blend_const_color_rgba
: {
1582 assert(ctx
->is_blend
);
1583 reg
= nir_dest_index(&instr
->dest
);
1585 /* Blend constants are embedded directly in the shader and
1586 * patched in, so we use some magic routing */
1588 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), reg
);
1589 ins
.has_constants
= true;
1590 ins
.has_blend_constant
= true;
1591 emit_mir_instruction(ctx
, ins
);
1595 case nir_intrinsic_store_zs_output_pan
: {
1596 assert(ctx
->stage
== MESA_SHADER_FRAGMENT
);
1597 emit_fragment_store(ctx
, nir_src_index(ctx
, &instr
->src
[0]),
1600 midgard_instruction
*br
= ctx
->writeout_branch
[MIDGARD_ZS_RT
];
1602 if (!nir_intrinsic_component(instr
))
1603 br
->writeout_depth
= true;
1604 if (nir_intrinsic_component(instr
) ||
1605 instr
->num_components
)
1606 br
->writeout_stencil
= true;
1607 assert(br
->writeout_depth
| br
->writeout_stencil
);
1611 case nir_intrinsic_store_output
:
1612 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1614 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1616 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1618 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1619 const nir_variable
*var
;
1620 enum midgard_rt_id rt
;
1622 var
= search_var(&ctx
->nir
->outputs
,
1623 nir_intrinsic_base(instr
));
1625 if (var
->data
.location
== FRAG_RESULT_COLOR
)
1626 rt
= MIDGARD_COLOR_RT0
;
1627 else if (var
->data
.location
>= FRAG_RESULT_DATA0
)
1628 rt
= MIDGARD_COLOR_RT0
+ var
->data
.location
-
1633 emit_fragment_store(ctx
, reg
, rt
);
1634 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1635 /* We should have been vectorized, though we don't
1636 * currently check that st_vary is emitted only once
1637 * per slot (this is relevant, since there's not a mask
1638 * parameter available on the store [set to 0 by the
1639 * blob]). We do respect the component by adjusting the
1640 * swizzle. If this is a constant source, we'll need to
1641 * emit that explicitly. */
1643 emit_explicit_constant(ctx
, reg
, reg
);
1645 unsigned dst_component
= nir_intrinsic_component(instr
);
1646 unsigned nr_comp
= nir_src_num_components(instr
->src
[0]);
1648 midgard_instruction st
= m_st_vary_32(reg
, offset
);
1649 st
.load_store
.arg_1
= 0x9E;
1650 st
.load_store
.arg_2
= 0x1E;
1652 switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr
))) {
1655 st
.load_store
.op
= midgard_op_st_vary_32u
;
1658 st
.load_store
.op
= midgard_op_st_vary_32i
;
1660 case nir_type_float
:
1661 st
.load_store
.op
= midgard_op_st_vary_32
;
1664 unreachable("Attempted to store unknown type");
1668 /* nir_intrinsic_component(store_intr) encodes the
1669 * destination component start. Source component offset
1670 * adjustment is taken care of in
1671 * install_registers_instr(), when offset_swizzle() is
1674 unsigned src_component
= COMPONENT_X
;
1676 assert(nr_comp
> 0);
1677 for (unsigned i
= 0; i
< ARRAY_SIZE(st
.swizzle
); ++i
) {
1678 st
.swizzle
[0][i
] = src_component
;
1679 if (i
>= dst_component
&& i
< dst_component
+ nr_comp
- 1)
1683 emit_mir_instruction(ctx
, st
);
1685 DBG("Unknown store\n");
1691 /* Special case of store_output for lowered blend shaders */
1692 case nir_intrinsic_store_raw_output_pan
:
1693 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1694 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1696 if (ctx
->quirks
& MIDGARD_OLD_BLEND
) {
1697 /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
1698 * reg = r0.x. We want to splatter. So we can do a 32-bit move
1701 * imov r0.xyzw, r0.xxxx
1704 unsigned expanded
= make_compiler_temp(ctx
);
1706 midgard_instruction splatter
= v_mov(reg
, expanded
);
1708 for (unsigned c
= 0; c
< 16; ++c
)
1709 splatter
.swizzle
[1][c
] = 0;
1711 emit_mir_instruction(ctx
, splatter
);
1712 emit_fragment_store(ctx
, expanded
, ctx
->blend_rt
);
1714 emit_fragment_store(ctx
, reg
, ctx
->blend_rt
);
1718 case nir_intrinsic_store_global
:
1719 case nir_intrinsic_store_shared
:
1720 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1721 emit_explicit_constant(ctx
, reg
, reg
);
1723 emit_global(ctx
, &instr
->instr
, false, reg
, &instr
->src
[1], instr
->intrinsic
== nir_intrinsic_store_shared
);
1726 case nir_intrinsic_load_ssbo_address
:
1727 emit_sysval_read(ctx
, &instr
->instr
, 1, 0);
1730 case nir_intrinsic_get_buffer_size
:
1731 emit_sysval_read(ctx
, &instr
->instr
, 1, 8);
1734 case nir_intrinsic_load_viewport_scale
:
1735 case nir_intrinsic_load_viewport_offset
:
1736 case nir_intrinsic_load_num_work_groups
:
1737 case nir_intrinsic_load_sampler_lod_parameters_pan
:
1738 emit_sysval_read(ctx
, &instr
->instr
, 3, 0);
1741 case nir_intrinsic_load_work_group_id
:
1742 case nir_intrinsic_load_local_invocation_id
:
1743 emit_compute_builtin(ctx
, instr
);
1746 case nir_intrinsic_load_vertex_id
:
1747 case nir_intrinsic_load_instance_id
:
1748 emit_vertex_builtin(ctx
, instr
);
1751 case nir_intrinsic_memory_barrier_buffer
:
1752 case nir_intrinsic_memory_barrier_shared
:
1755 case nir_intrinsic_control_barrier
:
1756 schedule_barrier(ctx
);
1757 emit_control_barrier(ctx
);
1758 schedule_barrier(ctx
);
1762 fprintf(stderr
, "Unhandled intrinsic %s\n", nir_intrinsic_infos
[instr
->intrinsic
].name
);
1769 midgard_tex_format(enum glsl_sampler_dim dim
)
1772 case GLSL_SAMPLER_DIM_1D
:
1773 case GLSL_SAMPLER_DIM_BUF
:
1776 case GLSL_SAMPLER_DIM_2D
:
1777 case GLSL_SAMPLER_DIM_EXTERNAL
:
1778 case GLSL_SAMPLER_DIM_RECT
:
1781 case GLSL_SAMPLER_DIM_3D
:
1784 case GLSL_SAMPLER_DIM_CUBE
:
1785 return MALI_TEX_CUBE
;
1788 DBG("Unknown sampler dim type\n");
1794 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1798 pan_attach_constant_bias(
1799 compiler_context
*ctx
,
1801 midgard_texture_word
*word
)
1803 /* To attach as constant, it has to *be* constant */
1805 if (!nir_src_is_const(lod
))
1808 float f
= nir_src_as_float(lod
);
1810 /* Break into fixed-point */
1812 float lod_frac
= f
- lod_int
;
1814 /* Carry over negative fractions */
1815 if (lod_frac
< 0.0) {
1821 word
->bias
= float_to_ubyte(lod_frac
);
1822 word
->bias_int
= lod_int
;
1828 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1829 unsigned midgard_texop
)
1832 //assert (!instr->sampler);
1834 int texture_index
= instr
->texture_index
;
1835 int sampler_index
= texture_index
;
1837 nir_alu_type dest_base
= nir_alu_type_get_base_type(instr
->dest_type
);
1838 nir_alu_type dest_type
= dest_base
| nir_dest_bit_size(instr
->dest
);
1840 midgard_instruction ins
= {
1841 .type
= TAG_TEXTURE_4
,
1843 .dest
= nir_dest_index(&instr
->dest
),
1844 .src
= { ~0, ~0, ~0, ~0 },
1845 .dest_type
= dest_type
,
1846 .swizzle
= SWIZZLE_IDENTITY_4
,
1848 .op
= midgard_texop
,
1849 .format
= midgard_tex_format(instr
->sampler_dim
),
1850 .texture_handle
= texture_index
,
1851 .sampler_handle
= sampler_index
,
1852 .shadow
= instr
->is_shadow
,
1856 if (instr
->is_shadow
&& !instr
->is_new_style_shadow
)
1857 for (int i
= 0; i
< 4; ++i
)
1858 ins
.swizzle
[0][i
] = COMPONENT_X
;
1860 /* We may need a temporary for the coordinate */
1862 bool needs_temp_coord
=
1863 (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) ||
1864 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) ||
1867 unsigned coords
= needs_temp_coord
? make_compiler_temp_reg(ctx
) : 0;
1869 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1870 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1871 unsigned nr_components
= nir_src_num_components(instr
->src
[i
].src
);
1872 unsigned sz
= nir_src_bit_size(instr
->src
[i
].src
);
1873 nir_alu_type T
= nir_tex_instr_src_type(instr
, i
) | sz
;
1875 switch (instr
->src
[i
].src_type
) {
1876 case nir_tex_src_coord
: {
1877 emit_explicit_constant(ctx
, index
, index
);
1879 unsigned coord_mask
= mask_of(instr
->coord_components
);
1881 bool flip_zw
= (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) && (coord_mask
& (1 << COMPONENT_Z
));
1884 coord_mask
^= ((1 << COMPONENT_Z
) | (1 << COMPONENT_W
));
1886 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1887 /* texelFetch is undefined on samplerCube */
1888 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1890 /* For cubemaps, we use a special ld/st op to
1891 * select the face and copy the xy into the
1892 * texture register */
1894 midgard_instruction ld
= m_ld_cubemap_coords(coords
, 0);
1896 ld
.src_types
[1] = T
;
1897 ld
.mask
= 0x3; /* xy */
1898 ld
.load_store
.arg_1
= 0x20;
1899 ld
.swizzle
[1][3] = COMPONENT_X
;
1900 emit_mir_instruction(ctx
, ld
);
1903 ins
.swizzle
[1][2] = instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
1904 ins
.swizzle
[1][3] = COMPONENT_X
;
1905 } else if (needs_temp_coord
) {
1906 /* mov coord_temp, coords */
1907 midgard_instruction mov
= v_mov(index
, coords
);
1908 mov
.mask
= coord_mask
;
1911 mov
.swizzle
[1][COMPONENT_W
] = COMPONENT_Z
;
1913 emit_mir_instruction(ctx
, mov
);
1918 ins
.src
[1] = coords
;
1919 ins
.src_types
[1] = T
;
1921 /* Texelfetch coordinates uses all four elements
1922 * (xyz/index) regardless of texture dimensionality,
1923 * which means it's necessary to zero the unused
1924 * components to keep everything happy */
1926 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1927 /* mov index.zw, #0, or generalized */
1928 midgard_instruction mov
=
1929 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), coords
);
1930 mov
.has_constants
= true;
1931 mov
.mask
= coord_mask
^ 0xF;
1932 emit_mir_instruction(ctx
, mov
);
1935 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
) {
1936 /* Array component in w but NIR wants it in z,
1937 * but if we have a temp coord we already fixed
1940 if (nr_components
== 3) {
1941 ins
.swizzle
[1][2] = COMPONENT_Z
;
1942 ins
.swizzle
[1][3] = needs_temp_coord
? COMPONENT_W
: COMPONENT_Z
;
1943 } else if (nr_components
== 2) {
1945 instr
->is_shadow
? COMPONENT_Z
: COMPONENT_X
;
1946 ins
.swizzle
[1][3] = COMPONENT_X
;
1948 unreachable("Invalid texture 2D components");
1951 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1953 ins
.swizzle
[1][2] = COMPONENT_Z
;
1954 ins
.swizzle
[1][3] = COMPONENT_W
;
1960 case nir_tex_src_bias
:
1961 case nir_tex_src_lod
: {
1962 /* Try as a constant if we can */
1964 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1965 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1968 ins
.texture
.lod_register
= true;
1970 ins
.src_types
[2] = T
;
1972 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
1973 ins
.swizzle
[2][c
] = COMPONENT_X
;
1975 emit_explicit_constant(ctx
, index
, index
);
1980 case nir_tex_src_offset
: {
1981 ins
.texture
.offset_register
= true;
1983 ins
.src_types
[3] = T
;
1985 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
)
1986 ins
.swizzle
[3][c
] = (c
> COMPONENT_Z
) ? 0 : c
;
1988 emit_explicit_constant(ctx
, index
, index
);
1992 case nir_tex_src_comparator
: {
1993 unsigned comp
= COMPONENT_Z
;
1995 /* mov coord_temp.foo, coords */
1996 midgard_instruction mov
= v_mov(index
, coords
);
1997 mov
.mask
= 1 << comp
;
1999 for (unsigned i
= 0; i
< MIR_VEC_COMPONENTS
; ++i
)
2000 mov
.swizzle
[1][i
] = COMPONENT_X
;
2002 emit_mir_instruction(ctx
, mov
);
2007 fprintf(stderr
, "Unknown texture source type: %d\n", instr
->src
[i
].src_type
);
2013 emit_mir_instruction(ctx
, ins
);
2017 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
2019 switch (instr
->op
) {
2022 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
2025 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
2028 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
2031 emit_sysval_read(ctx
, &instr
->instr
, 4, 0);
2034 fprintf(stderr
, "Unhandled texture op: %d\n", instr
->op
);
2041 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
2043 switch (instr
->type
) {
2044 case nir_jump_break
: {
2045 /* Emit a branch out of the loop */
2046 struct midgard_instruction br
= v_branch(false, false);
2047 br
.branch
.target_type
= TARGET_BREAK
;
2048 br
.branch
.target_break
= ctx
->current_loop_depth
;
2049 emit_mir_instruction(ctx
, br
);
2054 DBG("Unknown jump type %d\n", instr
->type
);
2060 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
2062 switch (instr
->type
) {
2063 case nir_instr_type_load_const
:
2064 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2067 case nir_instr_type_intrinsic
:
2068 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2071 case nir_instr_type_alu
:
2072 emit_alu(ctx
, nir_instr_as_alu(instr
));
2075 case nir_instr_type_tex
:
2076 emit_tex(ctx
, nir_instr_as_tex(instr
));
2079 case nir_instr_type_jump
:
2080 emit_jump(ctx
, nir_instr_as_jump(instr
));
2083 case nir_instr_type_ssa_undef
:
2088 DBG("Unhandled instruction type\n");
2094 /* ALU instructions can inline or embed constants, which decreases register
2095 * pressure and saves space. */
2097 #define CONDITIONAL_ATTACH(idx) { \
2098 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
2101 attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
2102 alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2107 inline_alu_constants(compiler_context
*ctx
, midgard_block
*block
)
2109 mir_foreach_instr_in_block(block
, alu
) {
2110 /* Other instructions cannot inline constants */
2111 if (alu
->type
!= TAG_ALU_4
) continue;
2112 if (alu
->compact_branch
) continue;
2114 /* If there is already a constant here, we can do nothing */
2115 if (alu
->has_constants
) continue;
2117 CONDITIONAL_ATTACH(0);
2119 if (!alu
->has_constants
) {
2120 CONDITIONAL_ATTACH(1)
2121 } else if (!alu
->inline_constant
) {
2122 /* Corner case: _two_ vec4 constants, for instance with a
2123 * csel. For this case, we can only use a constant
2124 * register for one, we'll have to emit a move for the
2127 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->src
[1] + 1);
2128 unsigned scratch
= make_compiler_temp(ctx
);
2131 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), scratch
);
2132 attach_constants(ctx
, &ins
, entry
, alu
->src
[1] + 1);
2134 /* Set the source */
2135 alu
->src
[1] = scratch
;
2137 /* Inject us -before- the last instruction which set r31 */
2138 mir_insert_instruction_before(ctx
, mir_prev_op(alu
), ins
);
2144 /* Midgard supports two types of constants, embedded constants (128-bit) and
2145 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2146 * constants can be demoted to inline constants, for space savings and
2147 * sometimes a performance boost */
2150 embedded_to_inline_constant(compiler_context
*ctx
, midgard_block
*block
)
2152 mir_foreach_instr_in_block(block
, ins
) {
2153 if (!ins
->has_constants
) continue;
2154 if (ins
->has_inline_constant
) continue;
2156 /* Blend constants must not be inlined by definition */
2157 if (ins
->has_blend_constant
) continue;
2159 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
2160 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
2161 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
2163 if (!(is_16
|| is_32
))
2166 /* src1 cannot be an inline constant due to encoding
2167 * restrictions. So, if possible we try to flip the arguments
2170 int op
= ins
->alu
.op
;
2172 if (ins
->src
[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
) &&
2173 alu_opcode_props
[op
].props
& OP_COMMUTES
) {
2177 if (ins
->src
[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2178 /* Extract the source information */
2180 midgard_vector_alu_src
*src
;
2181 int q
= ins
->alu
.src2
;
2182 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2185 /* Component is from the swizzle. Take a nonzero component */
2187 unsigned first_comp
= ffs(ins
->mask
) - 1;
2188 unsigned component
= ins
->swizzle
[1][first_comp
];
2190 /* Scale constant appropriately, if we can legally */
2191 uint16_t scaled_constant
= 0;
2194 scaled_constant
= ins
->constants
.u16
[component
];
2195 } else if (midgard_is_integer_op(op
)) {
2196 scaled_constant
= ins
->constants
.u32
[component
];
2198 /* Constant overflow after resize */
2199 if (scaled_constant
!= ins
->constants
.u32
[component
])
2202 float original
= ins
->constants
.f32
[component
];
2203 scaled_constant
= _mesa_float_to_half(original
);
2205 /* Check for loss of precision. If this is
2206 * mediump, we don't care, but for a highp
2207 * shader, we need to pay attention. NIR
2208 * doesn't yet tell us which mode we're in!
2209 * Practically this prevents most constants
2210 * from being inlined, sadly. */
2212 float fp32
= _mesa_half_to_float(scaled_constant
);
2214 if (fp32
!= original
)
2218 /* We don't know how to handle these with a constant */
2220 if (mir_nontrivial_source2_mod_simple(ins
) || src
->rep_low
|| src
->rep_high
) {
2221 DBG("Bailing inline constant...\n");
2225 /* Make sure that the constant is not itself a vector
2226 * by checking if all accessed values are the same. */
2228 const midgard_constants
*cons
= &ins
->constants
;
2229 uint32_t value
= is_16
? cons
->u16
[component
] : cons
->u32
[component
];
2231 bool is_vector
= false;
2232 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
2234 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
2235 /* We only care if this component is actually used */
2236 if (!(mask
& (1 << c
)))
2239 uint32_t test
= is_16
?
2240 cons
->u16
[ins
->swizzle
[1][c
]] :
2241 cons
->u32
[ins
->swizzle
[1][c
]];
2243 if (test
!= value
) {
2252 /* Get rid of the embedded constant */
2253 ins
->has_constants
= false;
2255 ins
->has_inline_constant
= true;
2256 ins
->inline_constant
= scaled_constant
;
2261 /* Dead code elimination for branches at the end of a block - only one branch
2262 * per block is legal semantically */
2265 midgard_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2267 bool branched
= false;
2269 mir_foreach_instr_in_block_safe(block
, ins
) {
2270 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2273 mir_remove_instruction(ins
);
2280 emit_fragment_epilogue(compiler_context
*ctx
, unsigned rt
)
2282 /* Loop to ourselves */
2283 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2284 struct midgard_instruction ins
= v_branch(false, false);
2285 ins
.writeout
= true;
2286 ins
.writeout_depth
= br
->writeout_depth
;
2287 ins
.writeout_stencil
= br
->writeout_stencil
;
2288 ins
.branch
.target_block
= ctx
->block_count
- 1;
2289 ins
.constants
.u32
[0] = br
->constants
.u32
[0];
2290 emit_mir_instruction(ctx
, ins
);
2292 ctx
->current_block
->epilogue
= true;
2293 schedule_barrier(ctx
);
2294 return ins
.branch
.target_block
;
2297 static midgard_block
*
2298 emit_block(compiler_context
*ctx
, nir_block
*block
)
2300 midgard_block
*this_block
= ctx
->after_block
;
2301 ctx
->after_block
= NULL
;
2304 this_block
= create_empty_block(ctx
);
2306 list_addtail(&this_block
->base
.link
, &ctx
->blocks
);
2308 this_block
->scheduled
= false;
2311 /* Set up current block */
2312 list_inithead(&this_block
->base
.instructions
);
2313 ctx
->current_block
= this_block
;
2315 nir_foreach_instr(instr
, block
) {
2316 emit_instr(ctx
, instr
);
2317 ++ctx
->instruction_count
;
2323 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2326 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2328 midgard_block
*before_block
= ctx
->current_block
;
2330 /* Speculatively emit the branch, but we can't fill it in until later */
2332 EMIT(branch
, true, true);
2333 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2334 then_branch
->src
[0] = mir_get_branch_cond(&nif
->condition
, &inv
);
2335 then_branch
->src_types
[0] = nir_type_uint32
;
2336 then_branch
->branch
.invert_conditional
= !inv
;
2338 /* Emit the two subblocks. */
2339 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2340 midgard_block
*end_then_block
= ctx
->current_block
;
2342 /* Emit a jump from the end of the then block to the end of the else */
2343 EMIT(branch
, false, false);
2344 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2346 /* Emit second block, and check if it's empty */
2348 int else_idx
= ctx
->block_count
;
2349 int count_in
= ctx
->instruction_count
;
2350 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2351 midgard_block
*end_else_block
= ctx
->current_block
;
2352 int after_else_idx
= ctx
->block_count
;
2354 /* Now that we have the subblocks emitted, fix up the branches */
2359 if (ctx
->instruction_count
== count_in
) {
2360 /* The else block is empty, so don't emit an exit jump */
2361 mir_remove_instruction(then_exit
);
2362 then_branch
->branch
.target_block
= after_else_idx
;
2364 then_branch
->branch
.target_block
= else_idx
;
2365 then_exit
->branch
.target_block
= after_else_idx
;
2368 /* Wire up the successors */
2370 ctx
->after_block
= create_empty_block(ctx
);
2372 pan_block_add_successor(&before_block
->base
, &then_block
->base
);
2373 pan_block_add_successor(&before_block
->base
, &else_block
->base
);
2375 pan_block_add_successor(&end_then_block
->base
, &ctx
->after_block
->base
);
2376 pan_block_add_successor(&end_else_block
->base
, &ctx
->after_block
->base
);
2380 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2382 /* Remember where we are */
2383 midgard_block
*start_block
= ctx
->current_block
;
2385 /* Allocate a loop number, growing the current inner loop depth */
2386 int loop_idx
= ++ctx
->current_loop_depth
;
2388 /* Get index from before the body so we can loop back later */
2389 int start_idx
= ctx
->block_count
;
2391 /* Emit the body itself */
2392 midgard_block
*loop_block
= emit_cf_list(ctx
, &nloop
->body
);
2394 /* Branch back to loop back */
2395 struct midgard_instruction br_back
= v_branch(false, false);
2396 br_back
.branch
.target_block
= start_idx
;
2397 emit_mir_instruction(ctx
, br_back
);
2399 /* Mark down that branch in the graph. */
2400 pan_block_add_successor(&start_block
->base
, &loop_block
->base
);
2401 pan_block_add_successor(&ctx
->current_block
->base
, &loop_block
->base
);
2403 /* Find the index of the block about to follow us (note: we don't add
2404 * one; blocks are 0-indexed so we get a fencepost problem) */
2405 int break_block_idx
= ctx
->block_count
;
2407 /* Fix up the break statements we emitted to point to the right place,
2408 * now that we can allocate a block number for them */
2409 ctx
->after_block
= create_empty_block(ctx
);
2411 mir_foreach_block_from(ctx
, start_block
, _block
) {
2412 mir_foreach_instr_in_block(((midgard_block
*) _block
), ins
) {
2413 if (ins
->type
!= TAG_ALU_4
) continue;
2414 if (!ins
->compact_branch
) continue;
2416 /* We found a branch -- check the type to see if we need to do anything */
2417 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2419 /* It's a break! Check if it's our break */
2420 if (ins
->branch
.target_break
!= loop_idx
) continue;
2422 /* Okay, cool, we're breaking out of this loop.
2423 * Rewrite from a break to a goto */
2425 ins
->branch
.target_type
= TARGET_GOTO
;
2426 ins
->branch
.target_block
= break_block_idx
;
2428 pan_block_add_successor(_block
, &ctx
->after_block
->base
);
2432 /* Now that we've finished emitting the loop, free up the depth again
2433 * so we play nice with recursion amid nested loops */
2434 --ctx
->current_loop_depth
;
2436 /* Dump loop stats */
2440 static midgard_block
*
2441 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2443 midgard_block
*start_block
= NULL
;
2445 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2446 switch (node
->type
) {
2447 case nir_cf_node_block
: {
2448 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2451 start_block
= block
;
2456 case nir_cf_node_if
:
2457 emit_if(ctx
, nir_cf_node_as_if(node
));
2460 case nir_cf_node_loop
:
2461 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2464 case nir_cf_node_function
:
2473 /* Due to lookahead, we need to report the first tag executed in the command
2474 * stream and in branch targets. An initial block might be empty, so iterate
2475 * until we find one that 'works' */
2478 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2480 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2482 mir_foreach_block_from(ctx
, initial_block
, _v
) {
2483 midgard_block
*v
= (midgard_block
*) _v
;
2484 if (v
->quadword_count
) {
2485 midgard_bundle
*initial_bundle
=
2486 util_dynarray_element(&v
->bundles
, midgard_bundle
, 0);
2488 return initial_bundle
->tag
;
2492 /* Default to a tag 1 which will break from the shader, in case we jump
2493 * to the exit block (i.e. `return` in a compute shader) */
2498 /* For each fragment writeout instruction, generate a writeout loop to
2499 * associate with it */
2502 mir_add_writeout_loops(compiler_context
*ctx
)
2504 for (unsigned rt
= 0; rt
< ARRAY_SIZE(ctx
->writeout_branch
); ++rt
) {
2505 midgard_instruction
*br
= ctx
->writeout_branch
[rt
];
2508 unsigned popped
= br
->branch
.target_block
;
2509 pan_block_add_successor(&(mir_get_block(ctx
, popped
- 1)->base
), &ctx
->current_block
->base
);
2510 br
->branch
.target_block
= emit_fragment_epilogue(ctx
, rt
);
2511 br
->branch
.target_type
= TARGET_GOTO
;
2513 /* If we have more RTs, we'll need to restore back after our
2514 * loop terminates */
2516 if ((rt
+ 1) < ARRAY_SIZE(ctx
->writeout_branch
) && ctx
->writeout_branch
[rt
+ 1]) {
2517 midgard_instruction uncond
= v_branch(false, false);
2518 uncond
.branch
.target_block
= popped
;
2519 uncond
.branch
.target_type
= TARGET_GOTO
;
2520 emit_mir_instruction(ctx
, uncond
);
2521 pan_block_add_successor(&ctx
->current_block
->base
, &(mir_get_block(ctx
, popped
)->base
));
2522 schedule_barrier(ctx
);
2524 /* We're last, so we can terminate here */
2525 br
->last_writeout
= true;
2531 midgard_compile_shader_nir(nir_shader
*nir
, panfrost_program
*program
, bool is_blend
, unsigned blend_rt
, unsigned gpu_id
, bool shaderdb
)
2533 struct util_dynarray
*compiled
= &program
->compiled
;
2535 midgard_debug
= debug_get_option_midgard_debug();
2537 /* TODO: Bound against what? */
2538 compiler_context
*ctx
= rzalloc(NULL
, compiler_context
);
2541 ctx
->stage
= nir
->info
.stage
;
2542 ctx
->is_blend
= is_blend
;
2543 ctx
->alpha_ref
= program
->alpha_ref
;
2544 ctx
->blend_rt
= MIDGARD_COLOR_RT0
+ blend_rt
;
2545 ctx
->quirks
= midgard_get_quirks(gpu_id
);
2547 /* Start off with a safe cutoff, allowing usage of all 16 work
2548 * registers. Later, we'll promote uniform reads to uniform registers
2549 * if we determine it is beneficial to do so */
2550 ctx
->uniform_cutoff
= 8;
2552 /* Initialize at a global (not block) level hash tables */
2554 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2555 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2557 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2558 * (so we don't accidentally duplicate the epilogue since mesa/st has
2559 * messed with our I/O quite a bit already) */
2561 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2563 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2564 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2565 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
2568 NIR_PASS_V(nir
, nir_lower_var_copies
);
2569 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2570 NIR_PASS_V(nir
, nir_split_var_copies
);
2571 NIR_PASS_V(nir
, nir_lower_var_copies
);
2572 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2573 NIR_PASS_V(nir
, nir_lower_var_copies
);
2574 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2576 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2577 NIR_PASS_V(nir
, nir_lower_ssbo
);
2578 NIR_PASS_V(nir
, midgard_nir_lower_zs_store
);
2580 /* Optimisation passes */
2582 optimise_nir(nir
, ctx
->quirks
);
2584 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2585 nir_print_shader(nir
, stdout
);
2588 /* Assign sysvals and counts, now that we're sure
2589 * (post-optimisation) */
2591 panfrost_nir_assign_sysvals(&ctx
->sysvals
, nir
);
2592 program
->sysval_count
= ctx
->sysvals
.sysval_count
;
2593 memcpy(program
->sysvals
, ctx
->sysvals
.sysvals
, sizeof(ctx
->sysvals
.sysvals
[0]) * ctx
->sysvals
.sysval_count
);
2595 nir_foreach_function(func
, nir
) {
2599 list_inithead(&ctx
->blocks
);
2600 ctx
->block_count
= 0;
2602 ctx
->already_emitted
= calloc(BITSET_WORDS(func
->impl
->ssa_alloc
), sizeof(BITSET_WORD
));
2604 emit_cf_list(ctx
, &func
->impl
->body
);
2605 free(ctx
->already_emitted
);
2606 break; /* TODO: Multi-function shaders */
2609 util_dynarray_init(compiled
, NULL
);
2611 /* Per-block lowering before opts */
2613 mir_foreach_block(ctx
, _block
) {
2614 midgard_block
*block
= (midgard_block
*) _block
;
2615 inline_alu_constants(ctx
, block
);
2616 midgard_opt_promote_fmov(ctx
, block
);
2617 embedded_to_inline_constant(ctx
, block
);
2619 /* MIR-level optimizations */
2621 bool progress
= false;
2625 progress
|= midgard_opt_dead_code_eliminate(ctx
);
2627 mir_foreach_block(ctx
, _block
) {
2628 midgard_block
*block
= (midgard_block
*) _block
;
2629 progress
|= midgard_opt_copy_prop(ctx
, block
);
2630 progress
|= midgard_opt_combine_projection(ctx
, block
);
2631 progress
|= midgard_opt_varying_projection(ctx
, block
);
2635 mir_foreach_block(ctx
, _block
) {
2636 midgard_block
*block
= (midgard_block
*) _block
;
2637 midgard_lower_derivatives(ctx
, block
);
2638 midgard_cull_dead_branch(ctx
, block
);
2641 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
2642 mir_add_writeout_loops(ctx
);
2644 /* Analyze now that the code is known but before scheduling creates
2645 * pipeline registers which are harder to track */
2646 mir_analyze_helper_terminate(ctx
);
2647 mir_analyze_helper_requirements(ctx
);
2650 midgard_schedule_program(ctx
);
2653 /* Now that all the bundles are scheduled and we can calculate block
2654 * sizes, emit actual branch instructions rather than placeholders */
2656 int br_block_idx
= 0;
2658 mir_foreach_block(ctx
, _block
) {
2659 midgard_block
*block
= (midgard_block
*) _block
;
2660 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2661 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2662 midgard_instruction
*ins
= bundle
->instructions
[c
];
2664 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2666 /* Parse some basic branch info */
2667 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2668 bool is_conditional
= ins
->branch
.conditional
;
2669 bool is_inverted
= ins
->branch
.invert_conditional
;
2670 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2671 bool is_writeout
= ins
->writeout
;
2673 /* Determine the block we're jumping to */
2674 int target_number
= ins
->branch
.target_block
;
2676 /* Report the destination tag */
2677 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2679 /* Count up the number of quadwords we're
2680 * jumping over = number of quadwords until
2681 * (br_block_idx, target_number) */
2683 int quadword_offset
= 0;
2687 } else if (target_number
> br_block_idx
) {
2690 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2691 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2694 quadword_offset
+= blk
->quadword_count
;
2697 /* Jump backwards */
2699 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2700 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2703 quadword_offset
-= blk
->quadword_count
;
2707 /* Unconditional extended branches (far jumps)
2708 * have issues, so we always use a conditional
2709 * branch, setting the condition to always for
2710 * unconditional. For compact unconditional
2711 * branches, cond isn't used so it doesn't
2712 * matter what we pick. */
2714 midgard_condition cond
=
2715 !is_conditional
? midgard_condition_always
:
2716 is_inverted
? midgard_condition_false
:
2717 midgard_condition_true
;
2719 midgard_jmp_writeout_op op
=
2720 is_discard
? midgard_jmp_writeout_op_discard
:
2721 is_writeout
? midgard_jmp_writeout_op_writeout
:
2722 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2723 midgard_jmp_writeout_op_branch_cond
;
2726 midgard_branch_extended branch
=
2727 midgard_create_branch_extended(
2732 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2733 } else if (is_conditional
|| is_discard
) {
2734 midgard_branch_cond branch
= {
2736 .dest_tag
= dest_tag
,
2737 .offset
= quadword_offset
,
2741 assert(branch
.offset
== quadword_offset
);
2743 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2745 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2747 midgard_branch_uncond branch
= {
2749 .dest_tag
= dest_tag
,
2750 .offset
= quadword_offset
,
2754 assert(branch
.offset
== quadword_offset
);
2756 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2764 /* Emit flat binary from the instruction arrays. Iterate each block in
2765 * sequence. Save instruction boundaries such that lookahead tags can
2766 * be assigned easily */
2768 /* Cache _all_ bundles in source order for lookahead across failed branches */
2770 int bundle_count
= 0;
2771 mir_foreach_block(ctx
, _block
) {
2772 midgard_block
*block
= (midgard_block
*) _block
;
2773 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2775 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2777 mir_foreach_block(ctx
, _block
) {
2778 midgard_block
*block
= (midgard_block
*) _block
;
2779 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2780 source_order_bundles
[bundle_idx
++] = bundle
;
2784 int current_bundle
= 0;
2786 /* Midgard prefetches instruction types, so during emission we
2787 * need to lookahead. Unless this is the last instruction, in
2788 * which we return 1. */
2790 mir_foreach_block(ctx
, _block
) {
2791 midgard_block
*block
= (midgard_block
*) _block
;
2792 mir_foreach_bundle_in_block(block
, bundle
) {
2795 if (!bundle
->last_writeout
&& (current_bundle
+ 1 < bundle_count
))
2796 lookahead
= source_order_bundles
[current_bundle
+ 1]->tag
;
2798 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2802 /* TODO: Free deeper */
2803 //util_dynarray_fini(&block->instructions);
2806 free(source_order_bundles
);
2808 /* Report the very first tag executed */
2809 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2811 /* Deal with off-by-one related to the fencepost problem */
2812 program
->work_register_count
= ctx
->work_registers
+ 1;
2813 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2815 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2816 program
->tls_size
= ctx
->tls_size
;
2818 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2819 disassemble_midgard(stdout
, program
->compiled
.data
, program
->compiled
.size
, gpu_id
, ctx
->stage
);
2821 if (midgard_debug
& MIDGARD_DBG_SHADERDB
|| shaderdb
) {
2822 unsigned nr_bundles
= 0, nr_ins
= 0;
2824 /* Count instructions and bundles */
2826 mir_foreach_block(ctx
, _block
) {
2827 midgard_block
*block
= (midgard_block
*) _block
;
2828 nr_bundles
+= util_dynarray_num_elements(
2829 &block
->bundles
, midgard_bundle
);
2831 mir_foreach_bundle_in_block(block
, bun
)
2832 nr_ins
+= bun
->instruction_count
;
2835 /* Calculate thread count. There are certain cutoffs by
2836 * register count for thread count */
2838 unsigned nr_registers
= program
->work_register_count
;
2840 unsigned nr_threads
=
2841 (nr_registers
<= 4) ? 4 :
2842 (nr_registers
<= 8) ? 2 :
2847 fprintf(stderr
, "shader%d - %s shader: "
2848 "%u inst, %u bundles, %u quadwords, "
2849 "%u registers, %u threads, %u loops, "
2850 "%u:%u spills:fills\n",
2852 gl_shader_stage_name(ctx
->stage
),
2853 nr_ins
, nr_bundles
, ctx
->quadword_count
,
2854 nr_registers
, nr_threads
,
2856 ctx
->spills
, ctx
->fills
);