src/panfrost/midgard/midgard_compile.h

   1 /*
   2  * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef __MIDGARD_H_
  25 #define __MIDGARD_H_
  26
  27 #include "compiler/nir/nir.h"
  28 #include "util/u_dynarray.h"
  29 #include "util/register_allocate.h"
  30
  31 /* To be shoved inside panfrost_screen for the Gallium driver, or somewhere
  32  * else for Vulkan/standalone. The single compiler "screen" to be shared across
  33  * all shader compiles, used to store complex initialization (for instance,
  34  * related to register allocation) */
  35
  36 struct midgard_screen {
  37         /* Precomputed register allocation sets for varying numbers of work
  38          * registers.  The zeroeth entry corresponds to 8 work registers. The
  39          * eighth entry corresponds to 16 work registers. NULL if this set has
  40          * not been allocated yet. */
  41
  42         struct ra_regs *regs[9];
  43
  44         /* Work register classes corresponds to the above register sets */
  45         unsigned reg_classes[9][4];
  46 };
  47
  48 /* Define the general compiler entry point */
  49
  50 #define MAX_SYSVAL_COUNT 32
  51
  52 /* Allow 2D of sysval IDs, while allowing nonparametric sysvals to equal
  53  * their class for equal comparison */
  54
  55 #define PAN_SYSVAL(type, no) (((no) << 16) | PAN_SYSVAL_##type)
  56 #define PAN_SYSVAL_TYPE(sysval) ((sysval) & 0xffff)
  57 #define PAN_SYSVAL_ID(sysval) ((sysval) >> 16)
  58
  59 /* Define some common types. We start at one for easy indexing of hash
  60  * tables internal to the compiler */
  61
  62 enum {
  63         PAN_SYSVAL_VIEWPORT_SCALE = 1,
  64         PAN_SYSVAL_VIEWPORT_OFFSET = 2,
  65         PAN_SYSVAL_TEXTURE_SIZE = 3,
  66 } pan_sysval;
  67
  68 #define PAN_TXS_SYSVAL_ID(texidx, dim, is_array)          \
  69         ((texidx) | ((dim) << 7) | ((is_array) ? (1 << 9) : 0))
  70
  71 #define PAN_SYSVAL_ID_TO_TXS_TEX_IDX(id)        ((id) & 0x7f)
  72 #define PAN_SYSVAL_ID_TO_TXS_DIM(id)            (((id) >> 7) & 0x3)
  73 #define PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(id)       !!((id) & (1 << 9))
  74
  75 typedef struct {
  76         int work_register_count;
  77         int uniform_count;
  78         int uniform_cutoff;
  79
  80         int attribute_count;
  81         int varying_count;
  82
  83         /* Prepended before uniforms, mapping to SYSVAL_ names for the
  84          * sysval */
  85
  86         unsigned sysval_count;
  87         unsigned sysvals[MAX_SYSVAL_COUNT];
  88
  89         unsigned varyings[32];
  90
  91         int first_tag;
  92
  93         struct util_dynarray compiled;
  94
  95         /* For a blend shader using a constant color -- patch point. If
  96          * negative, there's no constant. */
  97
  98         int blend_patch_offset;
  99
 100         /* The number of bytes to allocate per-thread for Thread Local Storage
 101          * (register spilling), or zero if no spilling is used */
 102         unsigned tls_size;
 103
 104         /* IN: For a fragment shader with a lowered alpha test, the ref value */
 105         float alpha_ref;
 106 } midgard_program;
 107
 108 int
 109 midgard_compile_shader_nir(struct midgard_screen *screen, nir_shader *nir, midgard_program *program, bool is_blend);
 110
 111 /* NIR options are shared between the standalone compiler and the online
 112  * compiler. Defining it here is the simplest, though maybe not the Right
 113  * solution. */
 114
 115 static const nir_shader_compiler_options midgard_nir_options = {
 116         .lower_ffma = true,
 117         .lower_sub = true,
 118         .lower_scmp = true,
 119         .lower_flrp32 = true,
 120         .lower_flrp64 = true,
 121         .lower_ffract = true,
 122         .lower_fmod = true,
 123         .lower_fdiv = true,
 124         .lower_idiv = true,
 125         .lower_isign = true,
 126         .lower_fpow = true,
 127         .lower_find_lsb = true,
 128
 129         .lower_wpos_pntc = true,
 130
 131         /* TODO: We have native ops to help here, which we'll want to look into
 132          * eventually */
 133         .lower_fsign = true,
 134
 135         .vertex_id_zero_based = true,
 136         .lower_extract_byte = true,
 137         .lower_extract_word = true,
 138         .lower_rotate = true,
 139
 140         .lower_doubles_options = nir_lower_dmod,
 141
 142         .vectorize_io = true,
 143 };
 144
 145 #endif