src/panfrost/midgard/midgard_emit.c

   1 /*
   2  * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "compiler.h"
  25 #include "midgard_ops.h"
  26
  27 static midgard_int_mod
  28 mir_get_imod(bool shift, nir_alu_type T, bool half, bool scalar)
  29 {
  30         if (!half) {
  31                 assert(!shift);
  32                 /* Sign-extension, really... */
  33                 return scalar ? 0 : midgard_int_normal;
  34         }
  35
  36         if (shift)
  37                 return midgard_int_shift;
  38
  39         if (nir_alu_type_get_base_type(T) == nir_type_int)
  40                 return midgard_int_sign_extend;
  41         else
  42                 return midgard_int_zero_extend;
  43 }
  44
  45 static unsigned
  46 mir_pack_mod(midgard_instruction *ins, unsigned i, bool scalar)
  47 {
  48         bool integer = midgard_is_integer_op(ins->alu.op);
  49         unsigned base_size = (8 << ins->alu.reg_mode);
  50         unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
  51         bool half = (sz == (base_size >> 1));
  52
  53         return integer ?
  54                 mir_get_imod(ins->src_shift[i], ins->src_types[i], half, scalar) :
  55                 ((ins->src_abs[i] << 0) |
  56                  ((ins->src_neg[i] << 1)));
  57 }
  58
  59 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
  60  * use scalar ALU instructions, for functional or performance reasons. To do
  61  * this, we just demote vector ALU payloads to scalar. */
  62
  63 static int
  64 component_from_mask(unsigned mask)
  65 {
  66         for (int c = 0; c < 8; ++c) {
  67                 if (mask & (1 << c))
  68                         return c;
  69         }
  70
  71         assert(0);
  72         return 0;
  73 }
  74
  75 static unsigned
  76 mir_pack_scalar_source(unsigned mod, bool is_full, unsigned component)
  77 {
  78         midgard_scalar_alu_src s = {
  79                 .mod = mod,
  80                 .full = is_full,
  81                 .component = component << (is_full ? 1 : 0)
  82         };
  83
  84         unsigned o;
  85         memcpy(&o, &s, sizeof(s));
  86
  87         return o & ((1 << 6) - 1);
  88 }
  89
  90 static midgard_scalar_alu
  91 vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins)
  92 {
  93         bool is_full = nir_alu_type_get_type_size(ins->dest_type) == 32;
  94
  95         bool half_0 = nir_alu_type_get_type_size(ins->src_types[0]) == 16;
  96         bool half_1 = nir_alu_type_get_type_size(ins->src_types[1]) == 16;
  97         unsigned comp = component_from_mask(ins->mask);
  98
  99         unsigned packed_src[2] = {
 100                 mir_pack_scalar_source(mir_pack_mod(ins, 0, true), !half_0, ins->swizzle[0][comp]),
 101                 mir_pack_scalar_source(mir_pack_mod(ins, 1, true), !half_1, ins->swizzle[1][comp])
 102         };
 103
 104         /* The output component is from the mask */
 105         midgard_scalar_alu s = {
 106                 .op = v.op,
 107                 .src1 = packed_src[0],
 108                 .src2 = packed_src[1],
 109                 .unknown = 0,
 110                 .outmod = v.outmod,
 111                 .output_full = is_full,
 112                 .output_component = comp
 113         };
 114
 115         /* Full components are physically spaced out */
 116         if (is_full) {
 117                 assert(s.output_component < 4);
 118                 s.output_component <<= 1;
 119         }
 120
 121         /* Inline constant is passed along rather than trying to extract it
 122          * from v */
 123
 124         if (ins->has_inline_constant) {
 125                 uint16_t imm = 0;
 126                 int lower_11 = ins->inline_constant & ((1 << 12) - 1);
 127                 imm |= (lower_11 >> 9) & 3;
 128                 imm |= (lower_11 >> 6) & 4;
 129                 imm |= (lower_11 >> 2) & 0x38;
 130                 imm |= (lower_11 & 63) << 6;
 131
 132                 s.src2 = imm;
 133         }
 134
 135         return s;
 136 }
 137
 138 /* 64-bit swizzles are super easy since there are 2 components of 2 components
 139  * in an 8-bit field ... lots of duplication to go around!
 140  *
 141  * Swizzles of 32-bit vectors accessed from 64-bit instructions are a little
 142  * funny -- pack them *as if* they were native 64-bit, using rep_* flags to
 143  * flag upper. For instance, xy would become 64-bit XY but that's just xyzw
 144  * native. Likewise, zz would become 64-bit XX with rep* so it would be xyxy
 145  * with rep. Pretty nifty, huh? */
 146
 147 static unsigned
 148 mir_pack_swizzle_64(unsigned *swizzle, unsigned max_component)
 149 {
 150         unsigned packed = 0;
 151
 152         for (unsigned i = 0; i < 2; ++i) {
 153                 assert(swizzle[i] <= max_component);
 154
 155                 unsigned a = (swizzle[i] & 1) ?
 156                         (COMPONENT_W << 2) | COMPONENT_Z :
 157                         (COMPONENT_Y << 2) | COMPONENT_X;
 158
 159                 packed |= a << (i * 4);
 160         }
 161
 162         return packed;
 163 }
 164
 165 static void
 166 mir_pack_mask_alu(midgard_instruction *ins)
 167 {
 168         unsigned effective = ins->mask;
 169
 170         /* If we have a destination override, we need to figure out whether to
 171          * override to the lower or upper half, shifting the effective mask in
 172          * the latter, so AAAA.... becomes AAAA */
 173
 174         unsigned inst_size = 8 << ins->alu.reg_mode;
 175         signed upper_shift = mir_upper_override(ins, inst_size);
 176
 177         if (upper_shift >= 0) {
 178                 effective >>= upper_shift;
 179                 ins->alu.dest_override = upper_shift ?
 180                         midgard_dest_override_upper :
 181                         midgard_dest_override_lower;
 182         } else {
 183                 ins->alu.dest_override = midgard_dest_override_none;
 184         }
 185
 186         if (ins->alu.reg_mode == midgard_reg_mode_32)
 187                 ins->alu.mask = expand_writemask(effective, 4);
 188         else if (ins->alu.reg_mode == midgard_reg_mode_64)
 189                 ins->alu.mask = expand_writemask(effective, 2);
 190         else
 191                 ins->alu.mask = effective;
 192 }
 193
 194 static unsigned
 195 mir_pack_swizzle(unsigned mask, unsigned *swizzle,
 196                 nir_alu_type T, midgard_reg_mode reg_mode,
 197                 bool op_channeled, bool *rep_low, bool *rep_high)
 198 {
 199         unsigned packed = 0;
 200         unsigned sz = nir_alu_type_get_type_size(T);
 201
 202         if (reg_mode == midgard_reg_mode_64) {
 203                 unsigned components = 64 / sz;
 204
 205                 packed = mir_pack_swizzle_64(swizzle, components);
 206
 207                 if (sz == 32) {
 208                         bool lo = swizzle[0] >= COMPONENT_Z;
 209                         bool hi = swizzle[1] >= COMPONENT_Z;
 210
 211                         if (mask & 0x1) {
 212                                 /* We can't mix halves... */
 213                                 if (mask & 2)
 214                                         assert(lo == hi);
 215
 216                                 *rep_low = lo;
 217                         } else {
 218                                 *rep_low = hi;
 219                         }
 220                 } else if (sz < 32) {
 221                         unreachable("Cannot encode 8/16 swizzle in 64-bit");
 222                 }
 223         } else {
 224                 /* For 32-bit, swizzle packing is stupid-simple. For 16-bit,
 225                  * the strategy is to check whether the nibble we're on is
 226                  * upper or lower. We need all components to be on the same
 227                  * "side"; that much is enforced by the ISA and should have
 228                  * been lowered. TODO: 8-bit packing. TODO: vec8 */
 229
 230                 unsigned first = mask ? ffs(mask) - 1 : 0;
 231                 bool upper = swizzle[first] > 3;
 232
 233                 if (upper && mask)
 234                         assert(sz <= 16);
 235
 236                 bool dest_up = !op_channeled && (first >= 4);
 237
 238                 for (unsigned c = (dest_up ? 4 : 0); c < (dest_up ? 8 : 4); ++c) {
 239                         unsigned v = swizzle[c];
 240
 241                         bool t_upper = v > 3;
 242
 243                         /* Ensure we're doing something sane */
 244
 245                         if (mask & (1 << c)) {
 246                                 assert(t_upper == upper);
 247                                 assert(v <= 7);
 248                         }
 249
 250                         /* Use the non upper part */
 251                         v &= 0x3;
 252
 253                         packed |= v << (2 * (c % 4));
 254                 }
 255
 256
 257                 /* Replicate for now.. should really pick a side for
 258                  * dot products */
 259
 260                 if (reg_mode == midgard_reg_mode_16) {
 261                         *rep_low = !upper;
 262                         *rep_high = upper;
 263                 } else if (reg_mode == midgard_reg_mode_32) {
 264                         *rep_low = upper;
 265                 } else {
 266                         unreachable("Unhandled reg mode");
 267                 }
 268         }
 269
 270         return packed;
 271 }
 272
 273 static void
 274 mir_pack_vector_srcs(midgard_instruction *ins)
 275 {
 276         bool channeled = GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props);
 277
 278         midgard_reg_mode mode = ins->alu.reg_mode;
 279         unsigned base_size = (8 << mode);
 280
 281         for (unsigned i = 0; i < 2; ++i) {
 282                 if (ins->has_inline_constant && (i == 1))
 283                         continue;
 284
 285                 if (ins->src[i] == ~0)
 286                         continue;
 287
 288                 bool rep_lo = false, rep_hi = false;
 289                 unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
 290                 bool half = (sz == (base_size >> 1));
 291
 292                 assert((sz == base_size) || half);
 293
 294                 unsigned swizzle = mir_pack_swizzle(ins->mask, ins->swizzle[i],
 295                                 ins->src_types[i], ins->alu.reg_mode,
 296                                 channeled, &rep_lo, &rep_hi);
 297
 298                 midgard_vector_alu_src pack = {
 299                         .mod = mir_pack_mod(ins, i, false),
 300                         .rep_low = rep_lo,
 301                         .rep_high = rep_hi,
 302                         .half = half,
 303                         .swizzle = swizzle
 304                 };
 305
 306                 unsigned p = vector_alu_srco_unsigned(pack);
 307
 308                 if (i == 0)
 309                         ins->alu.src1 = p;
 310                 else
 311                         ins->alu.src2 = p;
 312         }
 313 }
 314
 315 static void
 316 mir_pack_swizzle_ldst(midgard_instruction *ins)
 317 {
 318         /* TODO: non-32-bit, non-vec4 */
 319         for (unsigned c = 0; c < 4; ++c) {
 320                 unsigned v = ins->swizzle[0][c];
 321
 322                 /* Check vec4 */
 323                 assert(v <= 3);
 324
 325                 ins->load_store.swizzle |= v << (2 * c);
 326         }
 327
 328         /* TODO: arg_1/2 */
 329 }
 330
 331 static void
 332 mir_pack_swizzle_tex(midgard_instruction *ins)
 333 {
 334         for (unsigned i = 0; i < 2; ++i) {
 335                 unsigned packed = 0;
 336
 337                 for (unsigned c = 0; c < 4; ++c) {
 338                         unsigned v = ins->swizzle[i][c];
 339
 340                         /* Check vec4 */
 341                         assert(v <= 3);
 342
 343                         packed |= v << (2 * c);
 344                 }
 345
 346                 if (i == 0)
 347                         ins->texture.swizzle = packed;
 348                 else
 349                         ins->texture.in_reg_swizzle = packed;
 350         }
 351
 352         /* TODO: bias component */
 353 }
 354
 355 /* Load store masks are 4-bits. Load/store ops pack for that. vec4 is the
 356  * natural mask width; vec8 is constrained to be in pairs, vec2 is duplicated. TODO: 8-bit?
 357  */
 358
 359 static void
 360 mir_pack_ldst_mask(midgard_instruction *ins)
 361 {
 362         unsigned sz = nir_alu_type_get_type_size(ins->dest_type);
 363         unsigned packed = ins->mask;
 364
 365         if (sz == 64) {
 366                 packed = ((ins->mask & 0x2) ? (0x8 | 0x4) : 0) |
 367                          ((ins->mask & 0x1) ? (0x2 | 0x1) : 0);
 368         } else if (sz == 16) {
 369                 packed = 0;
 370
 371                 for (unsigned i = 0; i < 4; ++i) {
 372                         /* Make sure we're duplicated */
 373                         bool u = (ins->mask & (1 << (2*i + 0))) != 0;
 374                         bool v = (ins->mask & (1 << (2*i + 1))) != 0;
 375                         assert(u == v);
 376
 377                         packed |= (u << i);
 378                 }
 379         } else {
 380                 assert(sz == 32);
 381         }
 382
 383         ins->load_store.mask = packed;
 384 }
 385
 386 static void
 387 mir_lower_inverts(midgard_instruction *ins)
 388 {
 389         bool inv[3] = {
 390                 ins->src_invert[0],
 391                 ins->src_invert[1],
 392                 ins->src_invert[2]
 393         };
 394
 395         switch (ins->alu.op) {
 396         case midgard_alu_op_iand:
 397                 /* a & ~b = iandnot(a, b) */
 398                 /* ~a & ~b = ~(a | b) = inor(a, b) */
 399
 400                 if (inv[0] && inv[1])
 401                         ins->alu.op = midgard_alu_op_inor;
 402                 else if (inv[1])
 403                         ins->alu.op = midgard_alu_op_iandnot;
 404
 405                 break;
 406         case midgard_alu_op_ior:
 407                 /*  a | ~b = iornot(a, b) */
 408                 /* ~a | ~b = ~(a & b) = inand(a, b) */
 409
 410                 if (inv[0] && inv[1])
 411                         ins->alu.op = midgard_alu_op_inand;
 412                 else if (inv[1])
 413                         ins->alu.op = midgard_alu_op_iornot;
 414
 415                 break;
 416
 417         case midgard_alu_op_ixor:
 418                 /* ~a ^ b = a ^ ~b = ~(a ^ b) = inxor(a, b) */
 419                 /* ~a ^ ~b = a ^ b */
 420
 421                 if (inv[0] ^ inv[1])
 422                         ins->alu.op = midgard_alu_op_inxor;
 423
 424                 break;
 425
 426         default:
 427                 break;
 428         }
 429 }
 430
 431 static void
 432 emit_alu_bundle(compiler_context *ctx,
 433                 midgard_bundle *bundle,
 434                 struct util_dynarray *emission,
 435                 unsigned lookahead)
 436 {
 437         /* Emit the control word */
 438         util_dynarray_append(emission, uint32_t, bundle->control | lookahead);
 439
 440         /* Next up, emit register words */
 441         for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 442                 midgard_instruction *ins = bundle->instructions[i];
 443
 444                 /* Check if this instruction has registers */
 445                 if (ins->compact_branch) continue;
 446
 447                 /* Otherwise, just emit the registers */
 448                 uint16_t reg_word = 0;
 449                 memcpy(&reg_word, &ins->registers, sizeof(uint16_t));
 450                 util_dynarray_append(emission, uint16_t, reg_word);
 451         }
 452
 453         /* Now, we emit the body itself */
 454         for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 455                 midgard_instruction *ins = bundle->instructions[i];
 456
 457                 /* Where is this body */
 458                 unsigned size = 0;
 459                 void *source = NULL;
 460
 461                 /* In case we demote to a scalar */
 462                 midgard_scalar_alu scalarized;
 463
 464                 if (!ins->compact_branch)
 465                         mir_lower_inverts(ins);
 466
 467                 if (ins->unit & UNITS_ANY_VECTOR) {
 468                         mir_pack_mask_alu(ins);
 469                         mir_pack_vector_srcs(ins);
 470                         size = sizeof(midgard_vector_alu);
 471                         source = &ins->alu;
 472                 } else if (ins->unit == ALU_ENAB_BR_COMPACT) {
 473                         size = sizeof(midgard_branch_cond);
 474                         source = &ins->br_compact;
 475                 } else if (ins->compact_branch) { /* misnomer */
 476                         size = sizeof(midgard_branch_extended);
 477                         source = &ins->branch_extended;
 478                 } else {
 479                         size = sizeof(midgard_scalar_alu);
 480                         scalarized = vector_to_scalar_alu(ins->alu, ins);
 481                         source = &scalarized;
 482                 }
 483
 484                 memcpy(util_dynarray_grow_bytes(emission, size, 1), source, size);
 485         }
 486
 487         /* Emit padding (all zero) */
 488         memset(util_dynarray_grow_bytes(emission, bundle->padding, 1), 0, bundle->padding);
 489
 490         /* Tack on constants */
 491
 492         if (bundle->has_embedded_constants)
 493                 util_dynarray_append(emission, midgard_constants, bundle->constants);
 494 }
 495
 496 /* Shift applied to the immediate used as an offset. Probably this is papering
 497  * over some other semantic distinction else well, but it unifies things in the
 498  * compiler so I don't mind. */
 499
 500 static unsigned
 501 mir_ldst_imm_shift(midgard_load_store_op op)
 502 {
 503         if (OP_IS_UBO_READ(op))
 504                 return 3;
 505         else
 506                 return 1;
 507 }
 508
 509 static enum mali_sampler_type
 510 midgard_sampler_type(nir_alu_type t) {
 511         switch (nir_alu_type_get_base_type(t))
 512         {
 513         case nir_type_float:
 514                 return MALI_SAMPLER_FLOAT;
 515         case nir_type_int:
 516                 return MALI_SAMPLER_SIGNED;
 517         case nir_type_uint:
 518                 return MALI_SAMPLER_UNSIGNED;
 519         default:
 520                 unreachable("Unknown sampler type");
 521         }
 522 }
 523
 524 /* After everything is scheduled, emit whole bundles at a time */
 525
 526 void
 527 emit_binary_bundle(compiler_context *ctx,
 528                    midgard_bundle *bundle,
 529                    struct util_dynarray *emission,
 530                    int next_tag)
 531 {
 532         int lookahead = next_tag << 4;
 533
 534         switch (bundle->tag) {
 535         case TAG_ALU_4:
 536         case TAG_ALU_8:
 537         case TAG_ALU_12:
 538         case TAG_ALU_16:
 539         case TAG_ALU_4 + 4:
 540         case TAG_ALU_8 + 4:
 541         case TAG_ALU_12 + 4:
 542         case TAG_ALU_16 + 4:
 543                 emit_alu_bundle(ctx, bundle, emission, lookahead);
 544                 break;
 545
 546         case TAG_LOAD_STORE_4: {
 547                 /* One or two composing instructions */
 548
 549                 uint64_t current64, next64 = LDST_NOP;
 550
 551                 /* Copy masks */
 552
 553                 for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 554                         mir_pack_ldst_mask(bundle->instructions[i]);
 555
 556                         mir_pack_swizzle_ldst(bundle->instructions[i]);
 557
 558                         /* Apply a constant offset */
 559                         unsigned offset = bundle->instructions[i]->constants.u32[0];
 560
 561                         if (offset) {
 562                                 unsigned shift = mir_ldst_imm_shift(bundle->instructions[i]->load_store.op);
 563                                 unsigned upper_shift = 10 - shift;
 564
 565                                 bundle->instructions[i]->load_store.varying_parameters |= (offset & ((1 << upper_shift) - 1)) << shift;
 566                                 bundle->instructions[i]->load_store.address |= (offset >> upper_shift);
 567                         }
 568                 }
 569
 570                 memcpy(&current64, &bundle->instructions[0]->load_store, sizeof(current64));
 571
 572                 if (bundle->instruction_count == 2)
 573                         memcpy(&next64, &bundle->instructions[1]->load_store, sizeof(next64));
 574
 575                 midgard_load_store instruction = {
 576                         .type = bundle->tag,
 577                         .next_type = next_tag,
 578                         .word1 = current64,
 579                         .word2 = next64
 580                 };
 581
 582                 util_dynarray_append(emission, midgard_load_store, instruction);
 583
 584                 break;
 585         }
 586
 587         case TAG_TEXTURE_4:
 588         case TAG_TEXTURE_4_VTX:
 589         case TAG_TEXTURE_4_BARRIER: {
 590                 /* Texture instructions are easy, since there is no pipelining
 591                  * nor VLIW to worry about. We may need to set .cont/.last
 592                  * flags. */
 593
 594                 midgard_instruction *ins = bundle->instructions[0];
 595
 596                 ins->texture.type = bundle->tag;
 597                 ins->texture.next_type = next_tag;
 598
 599                 signed override = mir_upper_override(ins, 32);
 600
 601                 ins->texture.mask = override > 0 ?
 602                         ins->mask >> override :
 603                         ins->mask;
 604
 605                 mir_pack_swizzle_tex(ins);
 606
 607                 unsigned osz = nir_alu_type_get_type_size(ins->dest_type);
 608                 unsigned isz = nir_alu_type_get_type_size(ins->src_types[1]);
 609
 610                 assert(osz == 32 || osz == 16);
 611                 assert(isz == 32 || isz == 16);
 612
 613                 ins->texture.out_full = (osz == 32);
 614                 ins->texture.out_upper = override > 0;
 615                 ins->texture.in_reg_full = (isz == 32);
 616                 ins->texture.sampler_type = midgard_sampler_type(ins->dest_type);
 617
 618                 if (mir_op_computes_derivatives(ctx->stage, ins->texture.op)) {
 619                         ins->texture.cont = !ins->helper_terminate;
 620                         ins->texture.last = ins->helper_terminate || ins->helper_execute;
 621                 } else {
 622                         ins->texture.cont = ins->texture.last = 1;
 623                 }
 624
 625                 util_dynarray_append(emission, midgard_texture_word, ins->texture);
 626                 break;
 627         }
 628
 629         default:
 630                 unreachable("Unknown midgard instruction type\n");
 631         }
 632 }