src/panfrost/midgard/midgard_opt_dce.c

   1 /*
   2  * Copyright (C) 2018 Alyssa Rosenzweig
   3  * Copyright (C) 2019 Collabora, Ltd.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 #include "compiler.h"
  26
  27 /* Basic dead code elimination on the MIR itself */
  28
  29 bool
  30 midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block)
  31 {
  32         bool progress = false;
  33
  34         mir_foreach_instr_in_block_safe(block, ins) {
  35                 if (ins->type != TAG_ALU_4) continue;
  36                 if (ins->compact_branch) continue;
  37
  38                 if (ins->ssa_args.dest >= SSA_FIXED_MINIMUM) continue;
  39                 if (mir_is_live_after(ctx, block, ins, ins->ssa_args.dest)) continue;
  40
  41                 mir_remove_instruction(ins);
  42                 progress = true;
  43         }
  44
  45         return progress;
  46 }
  47
  48 /* Removes dead moves, that is, moves with a destination overwritten before
  49  * being read. Normally handled implicitly as part of DCE, but this has to run
  50  * after the out-of-SSA pass */
  51
  52 bool
  53 midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block)
  54 {
  55         bool progress = false;
  56
  57         mir_foreach_instr_in_block_safe(block, ins) {
  58                 if (ins->type != TAG_ALU_4) continue;
  59                 if (ins->compact_branch) continue;
  60                 if (!OP_IS_MOVE(ins->alu.op)) continue;
  61
  62                 /* Check if it's overwritten in this block before being read */
  63                 bool overwritten = false;
  64
  65                 mir_foreach_instr_in_block_from(block, q, mir_next_op(ins)) {
  66                         /* Check if used */
  67                         if (mir_has_arg(q, ins->ssa_args.dest))
  68                                 break;
  69
  70                         /* Check if overwritten */
  71                         if (q->ssa_args.dest == ins->ssa_args.dest) {
  72                                 /* Special case to vec4; component tracking is
  73                                  * harder */
  74
  75                                 overwritten = (q->mask == 0xF);
  76                                 break;
  77                         }
  78                 }
  79
  80                 if (overwritten) {
  81                         mir_remove_instruction(ins);
  82                         progress = true;
  83                 }
  84         }
  85
  86         return progress;
  87 }
  88
  89 /* An even further special case - to be run after RA runs but before
  90  * scheduling, eliminating moves that end up being useless even though they
  91  * appeared meaningful in the SSA. Part #2 of register coalescing. */
  92
  93 void
  94 midgard_opt_post_move_eliminate(compiler_context *ctx, midgard_block *block, struct ra_graph *g)
  95 {
  96         mir_foreach_instr_in_block_safe(block, ins) {
  97                 if (ins->type != TAG_ALU_4) continue;
  98                 if (ins->compact_branch) continue;
  99                 if (!OP_IS_MOVE(ins->alu.op)) continue;
 100                 if (ins->dont_eliminate) continue;
 101
 102                 /* Check we're to the same place post-RA */
 103                 unsigned iA = ins->ssa_args.dest;
 104                 unsigned iB = ins->ssa_args.src[1];
 105
 106                 if ((iA < 0) || (iB < 0)) continue;
 107
 108                 unsigned A = iA >= SSA_FIXED_MINIMUM ?
 109                         SSA_REG_FROM_FIXED(iA) :
 110                         ra_get_node_reg(g, iA);
 111
 112                 unsigned B = iB >= SSA_FIXED_MINIMUM ?
 113                         SSA_REG_FROM_FIXED(iB) :
 114                         ra_get_node_reg(g, iB);
 115
 116                 if (A != B) continue;
 117
 118                 /* Check we're in the work zone. TODO: promoted
 119                  * uniforms? */
 120                 if (A >= 16) continue;
 121
 122                 /* Ensure there aren't side effects */
 123                 if (mir_nontrivial_source2_mod(ins)) continue;
 124                 if (mir_nontrivial_outmod(ins)) continue;
 125                 if (ins->mask != 0xF) continue;
 126
 127                 /* We do need to rewrite to facilitate pipelining/scheduling */
 128                 mir_rewrite_index(ctx, ins->ssa_args.src[1], ins->ssa_args.dest);
 129
 130                 /* We're good to go */
 131                 mir_remove_instruction(ins);
 132
 133         }
 134
 135 }